387 lines
12 KiB
Plaintext
387 lines
12 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: SPINAND FLASH Program script for the J721S2-EVM
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; @Description:
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; The SPINAND flash is connected to the OSPI_CS0 controller.
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; Supported SPINAND flash memories:
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; - W25N01JWxxxG
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; - W35N01JWxxxG
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;
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; SRAM:
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; OSPI(controller) Base: 0x47040000
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; OSPI memory mapped ADDRESS: 0x50000000
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;
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; @Author: CMO, JIM
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; @Chip: TDA4AL88, TDA4VE88, TDA4VL21, AM68AX
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; @Board: J721S2-EVM
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; @Keywords: SPINAND
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: j721s2-spinand.cmm 12107 2023-05-11 13:19:26Z cmorgenstern $
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WinCLEAR
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LOCAL &arg1 &prepateOnly &tmp &isW25
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ENTRY &arg1
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&arg1=STRing.UPpeR("&arg1") // for example "PREPAREONLY", "MEM=W25", "MEM=W35"
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&prepateOnly=(STRing.SCAN("&arg1","PREPAREONLY",0)!=-1)
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&tmp=STRing.SCANAndExtract("&arg1","MEM=","")
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&isW25=FALSE()
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IF ("&tmp"=="W25")
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&isW25=TRUE()
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LOCAL &pdd
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&pdd=OS.PresentDemoDirectory()
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; --------------------------------------------------------------------------------
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LOCAL &OSPI_BASE &OSPI_MEMORY_BASE &flash_algorithm
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&OSPI_BASE=0x47040000
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&OSPI_MEMORY_BASE=0x50000000 ; flash contents memory mapped address
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IF (&isW25)
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&flash_algorithm="~~/demo/arm/flash/byte/spinand2k6_tiospi.bin"
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ELSE
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&flash_algorithm="~~/demo/arm/flash/byte/spinand4k7_tiospi.bin"
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; --------------------------------------------------------------------------------
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; Open the master core(CM4) to configure system
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; Close leftover GUIs
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InterCom OTHERS QUIT
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; Open all SLAVE GUIs
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IF !INTERCOM.PING(CM4)
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TargetSystem.NewInstance CM4 /ARCHitecture ARM
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InterCom CM4 TITLE "TRACE32 for ARM - J721S2-CM4 - SLAVE" ; set GUI title
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InterCom CM4 RESet
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InterCom CM4 SYStem.RESet
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InterCom CM4 SYStem.CPU TDA4VE88-CM4-0
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InterCom CM4 SYStem.CONFIG CORE 2. 1.
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InterCom CM4 SYStem.CONFIG SLAVE OFF
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InterCom CM4 SYStem.Option RESBREAK OFF
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InterCom CM4 SYStem.Option EnReset OFF
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InterCom CM4 SYSTEM.JTAGCLOCK CTCK 10MHz
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IF COMBIPROBE()||UTRACE()
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(
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InterCom CM4 SYStem.CONFIG.CONNECTOR MIPI34 ; because of converter LA-3782
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)
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InterCom CM4 SYStem.Mode Prepare
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InterCom CM4 Data.Set EDBG:0x400003f0 %Long 0x00190000 ; Ensure Power-AP unlocked
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InterCom CM4 Data.Set EDBG:0x400003f0 %Long 0yxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1 ; Soft reset system
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InterCom CM4 WAIT 500.ms ; Wait some time for system to stabilize
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; Basic board setup via CortexM4
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; Disbale CR5-MCU lockstep
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InterCom CM4 Data.Set EZAXI:0x45A50040 %Long 0x00000000
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; Basic board setup via CortexM4
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InterCom CM4 Do "&pdd/hardware/j721s2/scripts/configure_pll.cmm" MAIN
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InterCom.WAIT CM4
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InterCom CM4 Do "&pdd/hardware/j721s2/scripts/configure_pll.cmm" DEBUG
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InterCom.WAIT CM4
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; Enable Power
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InterCom CM4 Do "&pdd/hardware/j721s2/scripts/configure_psc.cmm" 0. 0. 0. 0x1 0x3 ; LPSC_WKUP_ALWAYSON
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InterCom.WAIT CM4
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InterCom CM4 Do "&pdd/hardware/j721s2/scripts/configure_psc.cmm" 0. 0. 1. 0x1 0x3 ; LPSC_DMSC
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InterCom.WAIT CM4
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InterCom CM4 Do "&pdd/hardware/j721s2/scripts/configure_psc.cmm" 0. 0. 2. 0x1 0x3 ; LPSC_DEBUG2DMSC
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InterCom.WAIT CM4
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InterCom CM4 Do "&pdd/hardware/j721s2/scripts/configure_psc.cmm" 0. 0. 7. 0x1 0x3 ; LPSC_MCU_DEBUG
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InterCom.WAIT CM4
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InterCom CM4 DO "&pdd/hardware/j721s2/scripts/configure_psc.cmm" 0. 0. 10. 0x1 0x3 ; LPSC_MCU_OSPI_0
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InterCom.WAIT CM4
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InterCom CM4 DO "&pdd/hardware/j721s2/scripts/configure_psc.cmm" 0. 0. 11. 0x1 0x3 ; LPSC_MCU_OSPI_1
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InterCom.WAIT CM4
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; Close CM4 GUI
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InterCom OTHERS QUIT
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; --------------------------------------------------------------------------------
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; Connect to MCU-CR5 to program flash
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SYStem.CPU TDA4VE88-CR5-MCU
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SYStem.CONFIG.CORE 3. 1.
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CORE.ASSIGN 1.
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SYStem.Option.ResBreak OFF
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SYStem.Option.EnReset OFF
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SYStem.MemAccess DAP ;Enable to use the dualport
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SYStem.Option.TRST OFF
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SYStem.Attach
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Break
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; ------------------------------------------------------------------------------
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; Flash Controller Power & Clock Enable
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GOSUB CLK_INIT
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; ------------------------------------------------------------------------------
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; Flash Pin Mux Configuration
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GOSUB PIN_MUX
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; ------------------------------------------------------------------------------
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; Flash Controller Init
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GOSUB OSPI_INIT
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GOSUB CACHE_MMU_INIT
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; ------------------------------------------------------------------------------
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; Flash Read ID Test
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GOSUB READ_ID_TEST
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; ------------------------------------------------------------------------------
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; Flash declaration
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&pdd=OS.PresentDemoDirectory()
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Break.RESet
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FLASHFILE.RESet
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FLASHFILE.Create 0x0--0x7FFFFFF 0x20000 ; W25N01JWxxxG, 128KB uniform blocks
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//FLASFILE.CONFIG <MCU_FSS0_OSPI0_CTRL>
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FLASHFILE.CONFIG &OSPI_BASE &OSPI_MEMORY_BASE
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FLASHFILE.TARGET 0x41C00000++0x1FFF E:0x41C02000++0x23FF &flash_algorithm /KEEP /DualPort
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// Read FLASH Manufacturer and Device ID
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FLASHFILE.GETID
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;GOSUB FLASHFILE_ONFI_TEST ;Read out the onfi registers in spinand flash
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; ------------------------------------------------------------------------------
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; SPINAND specific function to read memory
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GOSUB FLASHFILE_CHECK_SPINAND_READMODE ;Check BUF flag in the SR-2[3], it changes the spinand read method
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//Unlock SPI NAND FLASH
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FLASHFILE.UNLOCK 0x0--0x7FFFFFF
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//End of the test prepareonly
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IF &prepateOnly
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ENDDO
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; ------------------------------------------------------------------------------
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; Flash programming example
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//Dump window for Serial FLASH
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FLASHFILE.DUMP 0x0
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;FLASHFILE.DUMP 0x0 /SPARE /Track
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//Write Serial FLASH
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;FLASHFILE.ERASE 0x0--0xFFFFF
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//Write Serial FLASH
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;FLASHFILE.LOAD * 0x0
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;FLASHFILE.LOAD * 0x0 /ComPare
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//Reset device
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PRINT "Please power-cycle the board after flash program is complete"
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ENDDO
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READ_ID_TEST:
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(
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; In case of errors you can try to read the ID via:
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; GOSUB READ_ID_TEST
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;
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; Check the output of the AREA window.
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; Expected output ID:
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; 0xFF (Dummy)
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; 0xEF (Manufacture)
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; 0xBC
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; 0x21
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LOCAL &rdata
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&CTRLREG=&OSPI_BASE+0x090
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&RXDATA0=&OSPI_BASE+0x0A0
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&RXDATA1=&OSPI_BASE+0x0A4
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&cmd=0x9f<<24. //cmd
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&rd=0x1<<23. //rd data enable
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&rd_num=0x7<<20. //7+1==8bytes, max
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&cmd_exec=0x1 //cmd execution
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Data.Set EZAXI:&CTRLREG %LE %Long (&cmd|&cmd_exec|&rd_num|&rd) ;write cmd + write data
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WAIT 100.ms
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&rdata=Data.Long(EZAXI:&RXDATA0) ;read lower , 8byte fifo
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PRINT "1st 0x" (&rdata)&0xFF " (Dummy)" ; //RXFIFO0
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PRINT "2nd 0x" (&rdata>>8.)&0xFF " (Manufacture)"
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PRINT "3rd 0x" (&rdata>>16.)&0xFF " (Device ID)[15:8]"
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PRINT "4th 0x" (&rdata>>24.)&0xFF " (Device ID)[7:0]"
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&rdata=Data.Long(EZAXI:&RXDATA1) ;read upper , 8byte fifo
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;PRINT "5th 0x" (&rdata)&0xFF
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;PRINT "6th 0x" (&rdata>>8.)&0xFF
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;PRINT "7th 0x" (&rdata>>16.)&0xFF
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;PRINT "8th 0x" (&rdata>>24.)&0xFF
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RETURN
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)
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FLASHFILE_ONFI_TEST:
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(
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FLASHFILE.GETONFI /VM
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PRINT "A page size: " %Decimal Data.Long(VM:0x50) "./" Data.Long(VM:0x54) ".Bytes (main/spare)"
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PRINT "A block size: 0x" Data.Long(VM:0x50)*Data.Long(VM:0x5C) " (" %Decimal Data.Long(VM:0x5C) ".Pages)"
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PRINT "A device size: 0x" Data.Long(VM:0x50)*Data.Long(VM:0x5C)*Data.Long(VM:0x60) " Bytes"
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RETURN
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)
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FLASHFILE_CHECK_SPINAND_READMODE:
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(
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LOCAL &status
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//The Buffer Read Mode (BUF=1) requires a Column Address to start outputting the existing data inside
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//the Data Buffer, and once it reaches the end of the data buffer (Byte 2,111), DO (IO1) pin will become
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//high-Z state.
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//The Continuous Read Mode (BUF=0) doesn't require the starting Column Address. The device will
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//always start output the data from the first column (Byte 0) of the Data buffer, and once the end of the
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//data buffer (Byte 2,048) is reached, the data output will continue through the next memory page.
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//2048+64, Buffer Read Mode (BUF=1), bcz the OSPI RX buffer is not large enough (Not A nand page size)
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FLASHFILE.SPI.CMD 0x0F 0xB0 /READ 0x4 VM:0
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&status=Data.Byte(VM:0x0)
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//old flash algorithm needs the ecc enable, but new one needs the ecc disable
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IF FLASHFILE.TARGET.BUILD(&flash_algorithm)<11484.
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(
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&status=&status|0x18 ;Set ECC[4]=1, BUF[3]=1 in Status Register-2
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)
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ELSE
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(
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&status=&status|0x8 // Set BUF[3]=1 in Status Register-2
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&status=(&status&~0x10)&0xFF // Set ECC[4]=0, ECC disable
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)
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FLASHFILE.SPI.CMD 0x1F 0xB0 &status
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RETURN
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)
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OSPI_INIT:
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(
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Data.Set EZAXI:&OSPI_BASE+0x0 %LE %Long 0x0
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Data.Set EZAXI:&OSPI_BASE+0x4 %LE %Long 0x00000013 ; 4B Addr Read
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Data.Set EZAXI:&OSPI_BASE+0x8 %LE %Long 0x00000012 ; 4B Addr Write
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Data.Set EZAXI:&OSPI_BASE+0x0 %LE %Long 0x80800000
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Data.Set EZAXI:&OSPI_BASE+0x14 %LE %Long 0x1003; 4B Address mode, 3B Addr: 0x1002
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Data.Set EZAXI:&OSPI_BASE+0x10 %LE %Long 0x21
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Data.Set EZAXI:&OSPI_BASE+0x1C %LE %Long 0xFFFFFFFF
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//Data.Set EZAXI:&OSPI_BASE+0xC %LE %Long (0xFF<<16.)|(0xFF<<8.) ; !!!!! OSPI_DEV_DELAY_REG because of writing !!!!!
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Data.Set EZAXI:&OSPI_BASE+0x0 %LE %Long 0x00000081|(0x1<<19.)|(0xE<<10.) ; 0x1==baudrate_div4, enable usage of OSPI_CS0
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Data.Set EZAXI:&OSPI_BASE+0x1C %LE %Long 0x04000000 ;ospi_setdirectcutoff, end of the flash address
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RETURN
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)
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PIN_MUX:
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(
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;MMR_unlock
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Data.Set EZAXI:0x4301D008 %Long 0x68EF3490 ;CTRLMMR_WKUP_LOCK7_KICK0
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Data.Set EZAXI:0x4301D00C %Long 0xD172BC5A
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Data.Set EZAXI:0x4301C000 %Long 0x00040000 ;CTRLMMR_WKUP_PADCONFIG0
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Data.Set EZAXI:0x4301C004 %Long 0x00040000
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Data.Set EZAXI:0x4301C008 %Long 0x00040000
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Data.Set EZAXI:0x4301C00C %Long 0x00040000
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Data.Set EZAXI:0x4301C010 %Long 0x00040000
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Data.Set EZAXI:0x4301C014 %Long 0x00040000
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Data.Set EZAXI:0x4301C018 %Long 0x00040000
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Data.Set EZAXI:0x4301C01C %Long 0x00040000
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Data.Set EZAXI:0x4301C020 %Long 0x00040000
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Data.Set EZAXI:0x4301C024 %Long 0x00040000
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Data.Set EZAXI:0x4301C028 %Long 0x00040000
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Data.Set EZAXI:0x4301C02C %Long 0x00040000
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Data.Set EZAXI:0x4301C030 %Long 0x00040000
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Data.Set EZAXI:0x4301C038 %Long 0x00040001
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Data.Set EZAXI:0x4301C03C %Long 0x00040001
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RETURN
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)
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CLK_INIT:
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(
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PRIVATE &HSDIV_OPTION
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; If there are flashing issues or if it fails, try to modfy the following value.
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; The valid range is: 0x3 <= &HSDIV_OPTION <= 0x8
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&HSDIV_OPTION=0x5
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; Set clock source
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Data.Set EZAXI:0x40F09008 %Long 0x68EF3490 ; CTRLMMR_MCU_LOCK2_KICK0
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Data.Set EZAXI:0x40F0900C %Long 0xD172BC5A
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Data.Set EZAXI:0x40F08030 %Long 0x1 ; CTRLMMR_MCU_OSPI0_CLKSEL: 0x1 = MCU_PLL2_HSDIV4_CLKOUT
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; Adjust PLL for MCU_PLL2_HSDIV4_CLKOUT
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DO &pdd/hardware/j721e/scripts/configure_pll _CFG_ BYPASS MCU 2.
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DO &pdd/hardware/j721e/scripts/configure_pll _CFG_ DIV MCU 2. 0x2 0x1 0x1 0x68 0x2AAAAB
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DO &pdd/hardware/j721e/scripts/configure_pll _CFG_ HSDIV MCU 2. 4. &HSDIV_OPTION
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DO &pdd/hardware/j721e/scripts/configure_pll _CFG_ ENABLE MCU 2.
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RETURN
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)
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CACHE_MMU_INIT:
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(
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PRIVATE &i &tmpReg
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; Enable MPU and disable I and D caches
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&tmpReg=Data.Long(C15:0x1)
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&tmpReg=&tmpReg|0x1 ; enable MPU
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&tmpReg=(&tmpReg&(~(0x1<<2.))) ; disable D cache
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&tmpReg=(&tmpReg&(~(0x1<<12.))) ; disable I cache
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Data.Set C15:0x1 %Long &tmpReg
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; Configure small region setup for flash programming
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PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x016 %Long 0x00000000 ; set default
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PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x216 %Long 0x0000003F
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PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x416 %Long 0x00001310
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PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x016 %Long 0x50000000 ; setup flash window
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PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x216 %Long 0x00000035
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PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x416 %Long 0x00001301
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PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x016 %Long 0x41C00000 ; setup buffer space
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PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x216 %Long 0x00000027
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PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x416 %Long 0x0000030C
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; Reset all other MPU regions
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&i=3.
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WHILE &i<16.
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(
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PER.Set.SaveIndex C15:0x026 %Long &i C15:0x016 %Long 0x0
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PER.Set.SaveIndex C15:0x026 %Long &i C15:0x216 %Long 0x0
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PER.Set.SaveIndex C15:0x026 %Long &i C15:0x416 %Long 0x0
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&i=&i+1.
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)
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RETURN
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)
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// detect the flash address mode by the internal flash register (0x0080_0003)
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// CR2V : should come 0x08(3B) or 0x88(4B)
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SPI_4B_ADDRMODE_ENABLE:
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(
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SILENT.FLASH.SPI.CMD 1. 0x06
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SILENT.FLASH.SPI.CMD 1. 0x71 0x80 0x00 0x03 0x88 ; write 0x88 to CR2V , switch 3B->4B address mode
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Data.Set VM:0x0--0xFF %Long 0x0
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SILENT.FLASH.SPI.CMD 1. 0x65 0x00 0x80 0x00 0x03 0x0 /READ 0x4 vm:0x0 ;4Bytes Address mode
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®Data=Data.Byte(vm:0x0)
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IF ®Data!=0x88
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(
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PRINT "We expect 0x08 latency(dummy) cycles but we got the dummy cycle 0x" %Hex ®Data
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ENDDO
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)
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RETURN
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)
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