276 lines
9.7 KiB
Plaintext
276 lines
9.7 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: IMX8MMini on X-8MMINILPD4-EVK Board eMMC FLASH Program Template
|
|
; @Description:
|
|
; The Sandisk <tbd> is connected to USDHC3
|
|
;
|
|
; SRAM: 0x900000
|
|
; USDHC(controller) Base: 0x30B60000
|
|
;
|
|
; @Keywords: Flash eMMC
|
|
; @Author: jjeong
|
|
; @Board: X-8MMINILPD4-EVK
|
|
; @Chip: IMX8MM*
|
|
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: imx8mm-emmc.cmm 12049 2023-04-20 12:32:16Z bschroefel $
|
|
|
|
PRIVATE &arg1 &nSdhc
|
|
LOCAL &MMC_BASE
|
|
ENTRY &arg1
|
|
&arg1=STRing.UPpeR("&arg1") // for example "PREPAREONLY"
|
|
|
|
&nSdhc=3.
|
|
|
|
RESet
|
|
SYStem.RESet
|
|
SYStem.CPU IMX8MM
|
|
SYStem.JtagClock 10MHz
|
|
SYStem.MemAccess DAP ;need for dualport
|
|
SYStem.Option ResBreak OFF
|
|
SYStem.Option WaitIDCODE 1.5s
|
|
Trace.DISable
|
|
CORE.ASSIGN 1.
|
|
SYStem.Up
|
|
|
|
//CA53 MMU disable for the cache disable
|
|
Register.Set M 0x5 ;EL1h
|
|
GOSUB MMU_DISABLE
|
|
|
|
// CCM_TARGET_ROOTn : Address: 3038_0000h base + 8000h offset + (128d x i), where i=0d to 124d
|
|
// i=88. USDHC1_CLK_ROOT, i=89. USDHC2_CLK_ROOT, i=121. USDHC3_CLK_ROOT
|
|
IF &nSdhc==1.
|
|
(
|
|
&MMC_BASE=0x30B40000 ;SDHC1
|
|
Data.Set A:0x30384518 %LE %Long 0x3 ;CCM_CCGR81_CLEAR, clock gating register CCM_CCGR81
|
|
Data.Set A:(0x30388000+0x2C00) %LE %Long 0x10000000 ;USDHC1_CLK_ROOT - MUX=24MHz, DIV=1
|
|
Data.Set A:0x30384514 %LE %Long 0x3 ;CCM_CCGR81_SET, clock gating register CCM_CCGR81
|
|
|
|
GOSUB Config_SDHC1
|
|
)
|
|
ELSE IF &nSdhc==2.
|
|
(
|
|
&MMC_BASE=0x30B50000 ;SDHC2
|
|
Data.Set A:0x30384528 %LE %Long 0x3 ;CCM_CCGR82_CLEAR, clock gating register CCM_CCGR82
|
|
Data.Set A:(0x30388000+0x2C80) %LE %Long 0x10000000 ;USDHC2_CLK_ROOT - MUX=24MHz, DIV=1
|
|
Data.Set A:0x30384524 %LE %Long 0x3 ;CCM_CCGR82_SET, clock gating register CCM_CCGR82
|
|
)
|
|
ELSE IF &nSdhc==3.
|
|
(
|
|
&MMC_BASE=0x30B60000 ;SDHC3
|
|
Data.Set A:0x303845E8 %LE %Long 0x3 ;CCM_CCGR94_CLEAR, clock gating register CCM_CCGR94
|
|
Data.Set A:(0x30388000+0x3C80) %LE %Long 0x10000000 ;USDHC3_CLK_ROOT - MUX=24MHz, DIV=1
|
|
Data.Set A:0x303845E4 %LE %Long 0x3 ;CCM_CCGR94_SET, clock gating register CCM_CCGR94
|
|
|
|
GOSUB Config_SDHC3
|
|
)
|
|
|
|
GOSUB READ_ID_TEST
|
|
|
|
LOCAL &pdd
|
|
&pdd=OS.PresentDemoDirectory()
|
|
|
|
FLASHFILE.RESet
|
|
|
|
;FLASHFILE.CONFIG <eMMC controller> <0x0> <0x0>
|
|
FLASHFILE.CONFIG &MMC_BASE 0x0 0x0
|
|
|
|
;FLASHFILE.TARGET <<code range>> <<data range>> <<algorithm file>>
|
|
FLASHFILE.TARGET 0x900000++0x1fff 0x902000++0x27ff &pdd/flash/byte/emmc_imx8.bin /KEEP /STACKSIZE 0x200
|
|
;FLASHFILE.TARGET A:0x900000++0x1fff EAHB:0x902000++0x27ff &pdd/flash/byte/emmc_imx8.bin /KEEP /STACKSIZE 0x200 /DUALPORT
|
|
|
|
FLASHFILE.GETID
|
|
|
|
Data.Set A:&MMC_BASE+0x2C %LE %Long 0x008E0002 ; 24MHz clk
|
|
//Get EXTended CSD registers
|
|
FLASHFILE.GETEXTCSD
|
|
|
|
//End of the test prepareonly
|
|
IF "&arg1"=="PREPAREONLY"
|
|
ENDDO
|
|
|
|
//When you access to the other partition on the flash
|
|
;FLASHFILE.SETEXTCSD 179. 0x00 ; access: partition null, no boot, access: no boot partition
|
|
;FLASHFILE.SETEXTCSD 179. 0x48 ; access: partition null
|
|
;FLASHFILE.SETEXTCSD 179. 0x49 ; access: partition boot 1
|
|
;FLASHFILE.SETEXTCSD 179. 0x4A ; access: partition boot 2
|
|
|
|
FLASHFILE.DUMP 0x0 ; Read NAND
|
|
;FLASHFILE.ERASE 0x0--0xFFFFF ; Erase NAND
|
|
;FLASHFILE.LOAD * 0x0 ; Write NAND
|
|
|
|
ENDDO
|
|
|
|
Config_SDHC1:
|
|
(
|
|
; --------------------------------------------------------------------------------
|
|
; IO Mux for SDHC1
|
|
; --------------------------------------------------------------------------------
|
|
|
|
Data.Set A:0x303300A0 %LE %Long 0x0 ;USDHC1_CLK, IOMUXC_SW_MUX_CTL_PAD_SD1_CLK
|
|
Data.Set A:0x303300A4 %LE %Long 0x0 ;USDHC1_CMD, IOMUXC_SW_MUX_CTL_PAD_SD1_CMD
|
|
Data.Set A:0x303300A8 %LE %Long 0x0 ;USDHC1_DAT0, IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0
|
|
Data.Set A:0x303300AC %LE %Long 0x0 ;USDHC1_DAT0, IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1
|
|
Data.Set A:0x303300B0 %LE %Long 0x0 ;USDHC1_DAT0, IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2
|
|
Data.Set A:0x303300B4 %LE %Long 0x0 ;USDHC1_DAT0, IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3
|
|
|
|
Data.Set A:0x30330308 %LE %Long 0x5F; IOMUXC_SW_PAD_CTL_PAD_SD1_CLK
|
|
Data.Set A:0x3033030C %LE %Long 0x5F; IOMUXC_SW_PAD_CTL_PAD_SD1_CMD
|
|
Data.Set A:0x30330310 %LE %Long 0x5F; IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0
|
|
Data.Set A:0x30330314 %LE %Long 0x5F; IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1
|
|
Data.Set A:0x30330318 %LE %Long 0x5F; IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2
|
|
Data.Set A:0x3033031C %LE %Long 0x5F; IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3
|
|
|
|
; --------------------------------------------------------------------------------
|
|
; Config SDHC
|
|
; --------------------------------------------------------------------------------
|
|
Data.Set A:&MMC_BASE+0x04 %LE %Long 0x00010200 ; blk size,cnt
|
|
Data.Set A:&MMC_BASE+0x28 %LE %Long 0x08800020 ; bus width, endian
|
|
Data.Set A:&MMC_BASE+0x2C %LE %Long 0x008E2008 ; DVS=0, SDCLKFS=0x20 -> 24MHz/64. ~= 400KHz clk
|
|
Data.Set A:&MMC_BASE+0x34 %LE %Long 0x007F0037 ; BRR,BWR, TCI, CCI interrupt enable
|
|
Data.Set A:&MMC_BASE+0x38 %LE %Long 0x007F0037 ; BRR,BWR, TCI, CCI interrupt enable
|
|
Data.Set A:&MMC_BASE+0x44 %LE %Long 0x00100010 ; read/write fifo threshold level 64bytes
|
|
RETURN
|
|
)
|
|
|
|
Config_SDHC2:
|
|
(
|
|
; --------------------------------------------------------------------------------
|
|
; IO Mux for SDHC2
|
|
; --------------------------------------------------------------------------------
|
|
|
|
; <tbd>
|
|
|
|
; --------------------------------------------------------------------------------
|
|
; Config SDHC
|
|
; --------------------------------------------------------------------------------
|
|
Data.Set A:&MMC_BASE+0x04 %LE %Long 0x00010200 ; blk size,cnt
|
|
Data.Set A:&MMC_BASE+0x28 %LE %Long 0x08800020 ; bus width, endian
|
|
Data.Set A:&MMC_BASE+0x2C %LE %Long 0x008E2008 ; DVS=0, SDCLKFS=0x20 -> 24MHz/64. ~= 400KHz clk
|
|
Data.Set A:&MMC_BASE+0x34 %LE %Long 0x007F0037 ; BRR,BWR, TCI, CCI interrupt enable
|
|
Data.Set A:&MMC_BASE+0x38 %LE %Long 0x007F0037 ; BRR,BWR, TCI, CCI interrupt enable
|
|
Data.Set A:&MMC_BASE+0x44 %LE %Long 0x00100010 ;read/write fifo threshold level 64bytes
|
|
RETURN
|
|
)
|
|
|
|
Config_SDHC3:
|
|
(
|
|
; --------------------------------------------------------------------------------
|
|
; IO Mux for SDHC3
|
|
; --------------------------------------------------------------------------------
|
|
|
|
Data.Set A:0x30330138 %LE %Long 0x12 ;USDHC3_CLK, IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B
|
|
Data.Set A:0x3033013C %LE %Long 0x2 ;USDHC3_CMD, IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B
|
|
Data.Set A:0x3033011C %LE %Long 0x2 ;USDHC3_DAT0, IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04
|
|
Data.Set A:0x30330120 %LE %Long 0x2 ;USDHC3_DAT1, IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05
|
|
Data.Set A:0x30330124 %LE %Long 0x2 ;USDHC3_DAT2, IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06
|
|
Data.Set A:0x30330128 %LE %Long 0x2 ;USDHC3_DAT3, IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07
|
|
|
|
Data.Set A:0x303303A0 %LE %Long 0x1DF; IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B
|
|
Data.Set A:0x303303A4 %LE %Long 0x1DF; IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B
|
|
Data.Set A:0x30330384 %LE %Long 0x1DF; IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04
|
|
Data.Set A:0x30330388 %LE %Long 0x1DF; IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05
|
|
Data.Set A:0x3033038C %LE %Long 0x1DF; IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06
|
|
Data.Set A:0x30330390 %LE %Long 0x1DF; IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07
|
|
|
|
; --------------------------------------------------------------------------------
|
|
; Config SDHC
|
|
; --------------------------------------------------------------------------------
|
|
Data.Set A:&MMC_BASE+0x04 %LE %Long 0x00010200 ; blk size,cnt
|
|
Data.Set A:&MMC_BASE+0x28 %LE %Long 0x08800020 ; bus width, endian
|
|
Data.Set A:&MMC_BASE+0x2C %LE %Long 0x008E2008 ; DVS=0, SDCLKFS=0x20 -> 24MHz/64. ~= 400KHz clk
|
|
Data.Set A:&MMC_BASE+0x34 %LE %Long 0x007F0037 ; BRR,BWR, TCI, CCI interrupt enable
|
|
Data.Set A:&MMC_BASE+0x38 %LE %Long 0x007F0037 ; BRR,BWR, TCI, CCI interrupt enable
|
|
Data.Set A:&MMC_BASE+0x44 %LE %Long 0x00100010 ;read/write fifo threshold level 64bytes
|
|
RETURN
|
|
)
|
|
|
|
READ_ID_TEST:
|
|
(
|
|
//CMD0
|
|
RePeaT 2.
|
|
(
|
|
Data.Set &MMC_BASE+0x30 %Long 0xFFFFFFFF ;clear status
|
|
Data.Set &MMC_BASE+0x8 %Long 0x0 ;arg
|
|
Data.Set &MMC_BASE+0xc %Long 0x0 ;cmd
|
|
WAIT 10.ms
|
|
)
|
|
|
|
//CMD1
|
|
RePeaT 10.
|
|
(
|
|
Data.Set &MMC_BASE+0x30 %Long 0xFFFFFFFF ;clear status
|
|
Data.Set &MMC_BASE+0x8 %Long 0x40FF8000 ;arg
|
|
Data.Set &MMC_BASE+0xc %Long 0x01020000 ;cmd1
|
|
WAIT 100.ms
|
|
&resp=Data.Long(A:(&MMC_BASE+0x10))
|
|
//print "CMD1 resp: 0x" &resp
|
|
IF (&resp&0x80000000)==0x80000000
|
|
(
|
|
GOTO jump_cmd2
|
|
)
|
|
)
|
|
|
|
PRINT "CMD1 fail"
|
|
END
|
|
|
|
jump_cmd2:
|
|
//CMD2
|
|
Data.Set &MMC_BASE+0x30 %Long 0xFFFFFFFF ;clear status
|
|
Data.Set &MMC_BASE+0x8 %Long 0x0 ;arg
|
|
Data.Set &MMC_BASE+0xc %Long 0x02010000 ;cmd2
|
|
WAIT 10.ms
|
|
|
|
//CMD3
|
|
Data.Set &MMC_BASE+0x30 %Long 0xFFFFFFFF ;clear status
|
|
Data.Set &MMC_BASE+0x8 %Long 0x00010000 ; arg, MMC RCA is (0x0001<<16.)
|
|
Data.Set &MMC_BASE+0xc %Long 0x03020000 ;cmd3
|
|
WAIT 10.ms
|
|
|
|
//CMD10
|
|
Data.Set &MMC_BASE+0x30 %Long 0xFFFFFFFF ;clear status
|
|
Data.Set &MMC_BASE+0x8 %Long 0x00010000 ; arg, MMC RCA is (0x0001<<16.)
|
|
Data.Set &MMC_BASE+0xc %Long 0x0A010000 ;cmd10
|
|
WAIT 10.ms
|
|
|
|
//Response2
|
|
PRINT "CID register"
|
|
PRINT "[127:104] 0x" Data.Long(A:(&MMC_BASE+0x1c))
|
|
PRINT "[103:72] 0x" Data.Long(A:(&MMC_BASE+0x18))
|
|
PRINT "[71:40] 0x" Data.Long(A:(&MMC_BASE+0x14))
|
|
PRINT "[39:8] 0x" Data.Long(A:(&MMC_BASE+0x10))
|
|
|
|
RETURN
|
|
)
|
|
|
|
MMU_DISABLE:
|
|
(
|
|
LOCAL &sctlr &cpsr &sctlrAddr
|
|
|
|
&cpsr=Register(cpsr)
|
|
|
|
IF (&cpsr&0x10)==0x10
|
|
(
|
|
PRINTS "MMU off not supported for AArch32 in this test scenario"
|
|
ENDDO
|
|
)
|
|
ELSE IF (&cpsr&0x0C)==0xC // EL3h or EL3t
|
|
&sctlrAddr=0x36100
|
|
ELSE IF (&cpsr&0x0C)==0x8 // EL2h or EL2t
|
|
&sctlrAddr=0x34100
|
|
ELSE IF (&cpsr&0x0C)==0x4 // 0x5 ;EL1h or EL1t
|
|
&sctlrAddr=0x30100
|
|
ELSE
|
|
(
|
|
PRINTS "CPU mode unknown"
|
|
ENDDO
|
|
)
|
|
|
|
&sctlr=Data.Quad(SPR:&sctlrAddr)
|
|
|
|
&sctlr=&sctlr&0xFFFFFFFE
|
|
|
|
Data.Set SPR:&sctlrAddr %Quad &sctlr
|
|
|
|
RETURN
|
|
)
|