144 lines
4.7 KiB
Plaintext
144 lines
4.7 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: I.MX28 GPMI NAND FLASH Programming Script
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; @Description:
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; FLASH Type: NAND FLASH(SAMSUNG,K9F4G08) connected to NAND_CS0
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;
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; Internal SRAM : 0x001000
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; APBH-Bridge-DMA Register : 0x80004000
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; GPMIRegister : 0x8000C000
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;
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; @Author: jjeong
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; @Chip: IMX287
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; @Keywords: SAMSUNG K9F4G08
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: imx28-nand2g08.cmm 10516 2022-02-02 11:39:30Z bschroefel $
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LOCAL &arg1
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ENTRY &arg1
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&arg1=STRing.UPpeR("&arg1") // for example "PREPAREONLY"
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&GPMI_BASE=0x8000C000
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&APBHDMA_BASE=0x80004000
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SYStem.RESet
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SYStem.CPU IMX287
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SYStem.JtagClock RTCK
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; If the power supply is used the power button has to be pressed each time after reset.
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;
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; Solution 1: Disable EnReset
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; Solution 2: Use USB power on J82
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SYStem.Option EnReset OFF
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SYStem.Up
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PER.Set.simple C15:0x1 %Long 0x51078 ;MMU disable
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GOSUB CLOCK_SETUP
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GOSUB NAND_SETUP
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Break.RESet
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FLASHFILE.RESet
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//FLASHFILE.config <APBH-Bridge-DMA> <GPMI reg>
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FLASHFILE.CONFIG &APBHDMA_BASE &GPMI_BASE , ,
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//FLASHFILE.TARGET <code range> <data range> <Algorithm file>
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FLASHFILE.TARGET 0x010000++0x2FFF 0x00014000++0x3FFF ~~/demo/arm/flash/byte/nand2g08_gpmimx28.bin /STACKSIZE 0x200 /KEEP
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FLASHFILE.GETID ; Read ID
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//End of the test prepareonly
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IF "&arg1"=="PREPAREONLY"
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ENDDO
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;FLASHFILE.DUMP 0x0 ; Read NAND
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;FLASHFILE.ERASE 0x0--0xFFFFF /EraseBadBlock ; Erase NAND
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;FLASHFILE.LOAD * 0x0 /WriteBadBlock ; Write NAND
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ENDDO
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NAND_SETUP:
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Data.Set A:0x80018108 %Long 0x0000FFFF //HW_PINCTRL_MUXSEL0_CLR
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Data.Set A:0x80018118 %Long 0x03FF0F0F //HW_PINCTRL_MUXSEL1_CLR
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Data.Set A:0x80040000 %Long 0x00060000 //HW_CLKCTRL_PLL0CTRL0
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Data.Set A:0x80040060 %Long 0x2 //HW_CLKCTRL_HBUS
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Data.Set A:0x800400D0 %Long 0x00000010 //HW_CLKCTRL_GPMI
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Data.Set A:0x800401B0 %Long 0x92925a52 //HW_CLKCTRL_FRAC0
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Data.Set A:0x800401D0 %Long 0x0000417E //HW_CLKCTRL_CLKSEQ
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Data.Set A:0x800401D4 %Long 0x00000004 //HW_CLKCTRL_CLKSEQ_SET
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Data.Set A:&GPMI_BASE+0x000 %Long 0xC0000000 //HW_GPMI_CTRL0_WR
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Data.Set A:&GPMI_BASE+0x008 %Long 0xC0000000 //HW_GPMI_CTRL0_CLR
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Data.Set A:&GPMI_BASE+0x028 %Long 0x1000 //HW_GPMI_ECCCTRL_CLR
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Data.Set A:&GPMI_BASE+0x070 %Long 0x00030303 //HW_GPMI_TIMING0_WR
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Data.Set A:&GPMI_BASE+0x080 %Long 0xFFFF0000 //HW_GPMI_TIMING1_WR
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Data.Set A:&GPMI_BASE+0x060 %Long 0xC //GPMI_CTRL1
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Data.Set A:&APBHDMA_BASE+0x08 %Long 0xC0000000 //HW_APBH_CTRL0_CLR
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Data.Set A:&APBHDMA_BASE+0x30 %Long 0x10000 //APBH_CHANNEL_CTRLn
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Data.Set A:&APBHDMA_BASE+0x18 %Long 0x1 //APBH_CTRL1_CLR
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Data.Set A:0x8000A080 %Long 0x030A4200 //HW_BCH_FLASH0LAYOUT0
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Data.Set A:0x8000A090 %Long 0x08404200 //HW_BCH_FLASH0LAYOUT1
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RETURN
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CLOCK_SETUP:
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//=============================================================================
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//init script for MX28 EVK/Armadillo DDR2 CPU board (ddr2-EDE1116)
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//Date: DEC-03 2009
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//Author: Freescale-MAD
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//Version: 0.1
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//=============================================================================
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//****************************
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// VDDD setting
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//****************************
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//set VDDD =1.55V =(0.8v + TRIG x 0.025v), TRIG=0x1e
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//Data.Set ASD:0x80044040 %Long 0x0032071e
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Data.Set ASD:0x80044040 %Long 0x0022071e
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//****************************
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// CLOCK set up
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//****************************
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// Power up PLL0 HW_CLKCTRL_PLL0CTRL0
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Data.Set ASD:0x80040000 %Long 0x00020000
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// Set up fractional dividers for CPU and EMI - HW_CLKCTRL_FRAC0
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// EMI - first set DIV_EMI to div-by-2 before programming frac divider
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Data.Set ASD:0x800400F0 %Long 0x80000002
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// CPU: CPUFRAC=19 480*18/19=454.7MHz, EMI: EMIFRAC=22, (480/2)*18/22=196.4MHz
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//Data.Set ASD:0x800401B0 %Long 0x92921613
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// CPU: CPUFRAC=20 480*18/20=432MHz, EMI: EMIFRAC=22, (480/2)*18/22=196.4MHz
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Data.Set ASD:0x800401B0 %Long 0x92921614
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// CPU: CPUFRAC=28 480*18/28=308.6MHz, EMI: EMIFRAC=22, (480/2)*18/22=196.4MHz
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// IF CLK_H=CLK_P/2, then CLK_H=154.3MHz
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//Data.Set ASD:0x800401B0 %Long 0x9292161C
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// Clear the bypass bits for CPU and EMI clocks in HW_CLKCTRL_CLKSEQ_CLR
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Data.Set ASD:0x800401D8 %Long 0x00040080
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// HCLK = CLK_P/2,HW_CLKCTRL_HBUS DIV =0x2 (unstable)
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//Data.Set ASD:0x80040060 %Long 0x00000002
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// HCLK = CLK_P/3,HW_CLKCTRL_HBUS DIV =0x3
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Data.Set ASD:0x80040060 %Long 0x00000003
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// HCLK = CLK_P/4,HW_CLKCTRL_HBUS DIV =0x4
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//Data.Set ASD:0x80040060 %Long 0x00000004
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RETURN
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