1275 lines
76 KiB
Plaintext
1275 lines
76 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: ZSSC1856 On-Chip Peripherals
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; @Props: Released
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; @Author: STR
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; @Changelog: 2013-11-14 STR
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; @Manufacturer: ZMDI
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; @Doc: ZSSC1856_IBS_ZMDI_Datasheet_rev1_00.pdf (2012.04)
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; @Core: Cortex-M0
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perzssc1856.per 12528 2020-11-12 13:57:39Z bschroefel $
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width 0xb
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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tree.end
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width 6.
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tree "Interrupt Priority Registers"
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group.long 0x400++0x1F
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line.long 0x00 "INT0,Interrupt Priority Register"
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bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
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bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
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bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
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bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
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line.long 0x04 "INT1,Interrupt Priority Register"
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bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
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bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
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bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
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bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
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line.long 0x08 "INT2,Interrupt Priority Register"
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bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
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bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
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bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
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bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
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line.long 0x0C "INT3,Interrupt Priority Register"
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bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
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bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
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bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
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bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
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line.long 0x10 "INT4,Interrupt Priority Register"
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bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
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bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
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bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
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bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
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line.long 0x14 "INT5,Interrupt Priority Register"
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bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
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bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
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bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
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bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
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line.long 0x18 "INT6,Interrupt Priority Register"
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bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
base usr:0x00
|
|
tree "SBC Clock and Reset Logic"
|
|
width 14.
|
|
tree "Clocks"
|
|
group.byte 0xc1++0x01
|
|
line.word 0x00 "IREFOSC,Trim Values for the High-Precision Oscillator"
|
|
hexmask.word 0x00 7.--15. 1. " IREFOSCTRIM ,Trim value for the high-precision oscillator"
|
|
bitfld.word 0x00 0.--4. " IREFTCOSCTRIM ,Trim value to minimize the temperature coefficient of the high-precision oscillator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x7a++0x00
|
|
line.byte 0x00 "IREFLPOSC,Trim Value for the Low-power Oscillator"
|
|
hexmask.byte 0x00 0.--6. 1. " LPOSCTRIMVAL ,Trim value for the low-power oscillator"
|
|
group.byte 0x7b++0x00
|
|
line.byte 0x00 "LPOSCTRIM,Configuration Register for the Low-Power Oscillator Trimming Circuit"
|
|
bitfld.byte 0x00 2.--3. " LPOSCTRIMCFG ,Selects the number of clock periods of the low-power oscillator to be used to determine the frequency" "4,8,16,32"
|
|
bitfld.byte 0x00 1. " LPOSCTRIMUPD ,Update bit for the low-power oscillator trimming circuit" "Not allowed,Allowed"
|
|
bitfld.byte 0x00 0. " LPOSCTRIMENA ,Low-power oscillator trimming circuit enable" "Disabled,Enabled"
|
|
rgroup.byte 0x78++0x01
|
|
line.word 0x00 "LPOSCTRIMCNT,Result Counter of the Low-Power Oscillator Trimming Circuit"
|
|
hexmask.word 0x00 0.--10. 1. " LPOSCTRIMCNT ,Result counter of the low-power oscillator trimming circuit"
|
|
tree.end
|
|
width 9.
|
|
tree "Resets"
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "SWRST,Software Reset"
|
|
group.byte 0x68++0x00
|
|
line.byte 0x00 "CMDEXE,Triggering Command Execution by Software"
|
|
bitfld.byte 0x00 2. " LVFSET ,Strobe register - set the low-voltage flag" "No effect,Set"
|
|
bitfld.byte 0x00 1. " OTPDOWNLOAD ,Strobe register - start the download procedure from the OTP" "No effect,Start"
|
|
bitfld.byte 0x00 0. " WDOGCLR ,Clears the watchdog timer" "Not cleared,Cleared"
|
|
group.byte 0x69++0x00
|
|
line.byte 0x00 "FUNCDIS,Disabling VDDP Reset and STO Output Pin"
|
|
bitfld.byte 0x00 1. " DISSTOOUT ,Disable output driver of the STO pin" "No,Yes"
|
|
bitfld.byte 0x00 0. " DISVDDPRST ,VddpReset does not reset the MCU" "No,Yes"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "SBC Watchdog Timer"
|
|
width 14.
|
|
group.byte 0x72++0x01
|
|
line.word 0x00 "WDOGPRESETVAL,Preset Value for the Watchdog Timer"
|
|
rgroup.byte 0x70++0x01
|
|
line.word 0x00 "WDOGCNT,Current Value of Watchdog Timer"
|
|
group.byte 0x74++0x00
|
|
line.byte 0x00 "WDOGCFG,Watchdog Timer Configuration Register"
|
|
bitfld.byte 0x00 7. " WDOGLOCK ,Locks accesses to the other bits of this register and to the wdogPresetVal registers" "Not locked,Locked"
|
|
bitfld.byte 0x00 3.--4. " WDOGPRESCALECFG ,Prescaler configuration" "No prescaler,Prescaler of 125,Prescaler of 1250,Prescaler of 12500"
|
|
bitfld.byte 0x00 2. " WDOGIRQFUNCENA ,Watchdog reloads the preset value when expiring for the first time and generates an interrupt instead of a reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " WDOGPMDIS ,PMU stops the watchdog during any power-down state" "No,Yes"
|
|
bitfld.byte 0x00 0. " WDOGENA ,Global enable bit for the watchdog timer" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "SBC Sleep Timer"
|
|
width 14.
|
|
group.byte 0x60++0x01
|
|
line.word 0x00 "SLEEPTADCCMP,Compare Value for ADC Trigger Timer"
|
|
group.byte 0x62++0x01
|
|
line.word 0x00 "SLEEPTCMP,Compare Value for Sleep Timer"
|
|
rgroup.byte 0x20++0x01
|
|
line.word 0x00 "SLEEPTCURCNT,Current Value of Sleep Timer"
|
|
width 0xb
|
|
tree.end
|
|
tree "SBC Interrupt Controller"
|
|
width 9.
|
|
hgroup.byte 0x00++0x01
|
|
hide.word 0x00 "IRQSTAT,Interrupt Status Register"
|
|
in
|
|
group.byte 0x54++0x01
|
|
line.word 0x00 "IRQENA,Interrupt Enable Register"
|
|
bitfld.word 0x00 15. " IRQENA[15] ,Voltage/Temperature Over-Range Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " IRQENA[14] ,Current Over-Range Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " IRQENA[13] ,Voltage/Temperature Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " IRQENA[12] ,Current Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " IRQENA[11] ,Current Accumulator Threshold Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " IRQENA[10] ,Temperature Threshold Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " IRQENA[9] ,Voltage Comparator Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " IRQENA[8] ,Current Comparator Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " IRQENA[7] ,Temperature Conversion Result Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " IRQENA[6] ,Current Conversion Result Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " IRQENA[5] ,Current Conversion Result Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " IRQENA[4] ,LIN Wakeup Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IRQENA[3] ,LIN Short Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " IRQENA[2] ,LIN TXD Timeout Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " IRQENA[1] ,Sleep Timer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " IRQENA[0] ,Watchdog Timer Interrupt Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "SBC PMU (SBC Power Management Unit)"
|
|
width 12.
|
|
group.byte 0x53++0x00
|
|
line.byte 0x00 "PWRCFGFP,Power Configuration Register for the FP State"
|
|
bitfld.byte 0x00 5. " PDREFBUFOCFP ,Offset cancellation of the reference buffer is powered down" "Powered up,Powered down"
|
|
bitfld.byte 0x00 4. " ULPENAFP ,Bias current of the analog blocks is reduced to 5% in the FP state" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " LPENAFP ,Bias current of the analog blocks is reduced to 10% in the FP state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " PWRADCV ,Voltage/temperature ADC is powered" "Not powered,Powered"
|
|
bitfld.byte 0x00 0. " PWRADCI ,Current ADC is powered" "Not powered,Powered"
|
|
group.byte 0x64++0x00
|
|
line.byte 0x00 "PWRCFGLP,Power Configuration Register for Power-Down States"
|
|
bitfld.byte 0x00 7. " PWRREFBUFOCLP ,Offset cancellation of the reference buffer is powered in LP/ULP state while performing measurements" "Not powered,Powered"
|
|
bitfld.byte 0x00 6. " ULPENALP ,Bias current of the analog blocks is reduced to 5% in the LP/ULP state" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPENALP ,Bias current of the analog blocks is reduced to 10% in the LP/ULP state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--4. " PDMEAS ,Type of measurements to be performed during the LP or ULP state" "No measurements,Discrete/current,Discrete/current/voltage/internal temperature,Discrete/current/voltage/external temperature,Continuous/current,Continuous/current/voltage,Continuous/current/internal temperature,Continuous/current/external temperature"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " PDSTATE ,Select the power-down state to be entered" "LP state,LP state,ULP state,OFF state"
|
|
wgroup.byte 0x65++0x00
|
|
line.byte 0x00 "GOTOPD,Enter Power-down State"
|
|
group.byte 0x5f++0x00
|
|
line.byte 0x00 "DISCCVTCNT,Configuration Register for Discrete Measurements"
|
|
width 0xb
|
|
tree.end
|
|
tree "SBC ADC Unit"
|
|
width 13.
|
|
tree "Clocks Registers"
|
|
group.byte 0xb0++0x01
|
|
line.word 0x00 "SDMCLKCFGLP,Configuration Register for the SDM Clocks in the LP/ULP State"
|
|
hexmask.word 0x00 0.--9. 1. " SDMCLKDIVLP ,Clock divider value for the SDM clock in the LP and ULP states related to the base clock"
|
|
group.byte 0xb2++0x01
|
|
line.word 0x00 "SDMCLKCFGFP,Configuration Register for the SDM Clocks in the FP State"
|
|
bitfld.word 0x00 14.--15. " SDMPOS ,Position of the SDM clock relative to the base clock" "0,1,2,3"
|
|
bitfld.word 0x00 11.--13. " SDMPOS2 ,Position of the chop clock relative to the base clock" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--9. 1. " SDMCLKDIVFP ,Clock divider value for the SDM clock in FP state related to the base clock"
|
|
tree.end
|
|
width 13.
|
|
tree "Data Path Registers"
|
|
group.byte 0x33++0x02
|
|
line.tbyte 0x00 "ADCCOFF,Offset Correction Value for Current Channel"
|
|
group.byte 0x30++0x02
|
|
line.tbyte 0x00 "ADCCGAN,Gain Correction Value for Current Channel"
|
|
group.byte 0x39++0x02
|
|
line.tbyte 0x00 "ADCVOFF,Offset Correction Value for Voltage Channel"
|
|
group.byte 0x36++0x02
|
|
line.tbyte 0x00 "ADCVGAN,Gain Correction Value for Voltage Channel"
|
|
group.byte 0x3e++0x01
|
|
line.word 0x00 "ADCTOFF,Offset Correction Value for Temperature Channel"
|
|
group.byte 0x3c++0x01
|
|
line.word 0x00 "ADCTGAN,Gain Correction Value for Temperature Channel"
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "ADCPOCOGAIN,Post Correction Gain Configuration"
|
|
bitfld.byte 0x00 4.--5. " TEMPPOCOGAIN ,Post correction gain for the temperature channel" "1,2,4,8"
|
|
bitfld.byte 0x00 2.--3. " VOLTPOCOGAIN ,Post correction gain for the voltage channel" "1,2,4,8"
|
|
bitfld.byte 0x00 0.--1. " CURPOCOGAIN ,Post correction gain for the current channel" "1,2,4,8"
|
|
tree.end
|
|
tree "Operating Modes and Result Registers"
|
|
width 9.
|
|
rgroup.byte 0x02++0x02 "Single Measurement Results"
|
|
line.tbyte 0x00 "ADCCDAT,Single Current Measurement Value"
|
|
rgroup.byte 0x05++0x02
|
|
line.tbyte 0x00 "ADCVDAT,Single Voltage Measurement Value"
|
|
rgroup.byte 0x0a++0x01
|
|
line.word 0x00 "ADCTDAT,Single Temperature Measurement Value"
|
|
rgroup.byte 0x08++0x01
|
|
line.word 0x00 "ADCRDAT,Single External Temperature Measurement Value"
|
|
group.byte 0x52++0x00
|
|
line.byte 0x00 "ADCGAIN,Analog Gain Configuration in the Current Path"
|
|
bitfld.byte 0x00 4. " PGA2 ,Sets the gain of the PGA2 in the analog current path" "4,8"
|
|
bitfld.byte 0x00 2.--3. " PGA1 ,Sets the gain of the PGA1 in the analog current path" "1,2,4,8"
|
|
bitfld.byte 0x00 0.--1. " PGAIFC ,Sets the gain of the IFC in the analog current path" "1,2,4,8"
|
|
width 9.
|
|
group.byte 0x40++0x01 "Result Counter Functionality and Conversion Ready Strobes"
|
|
line.word 0x00 "ADCCRCL,Current Result Count Limit"
|
|
rgroup.byte 0x1b++0x01
|
|
line.word 0x00 "ADCCRCV,Current Result Count Value"
|
|
group.byte 0x45++0x00
|
|
line.byte 0x00 "ADCVRCL,Voltage Result Count Limit"
|
|
bitfld.byte 0x00 0.--3. " ADCVRCL ,Number of voltage measurements before the voltage conversion ready strobe is generated" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0x1e++0x00
|
|
line.byte 0x00 "ADCVRCV,Voltage Result Count Value"
|
|
bitfld.byte 0x00 0.--3. " ADCVRCV ,Present value of the voltage result counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 9.
|
|
group.byte 0x42++0x01 "Current Threshold Comparator Functionality"
|
|
line.word 0x00 "ADCCRTH,Absolute Current Threshold"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "ADCCTCL,Current Threshold Counter Limit"
|
|
rgroup.byte 0x1d++0x00
|
|
line.byte 0x00 "ADCCTCV,Current Threshold Counter Value"
|
|
width 11.
|
|
group.byte 0x48++0x03 "Current Accumulator Functionality"
|
|
line.long 0x00 "ADCCACCTH,Current Accumulator Threshold Value"
|
|
rgroup.byte 0x0c++0x03
|
|
line.long 0x00 "ADCCACCU,Current Accumulator Value"
|
|
width 10.
|
|
group.byte 0x46++0x01 "Voltage Threshold Comparator and Voltage Accumulator Functionality"
|
|
line.word 0x00 "ADCVTH,Voltage Threshold Value"
|
|
rgroup.byte 0x10++0x02
|
|
line.tbyte 0x00 "ADCVACCU,Voltage Accumulator Value"
|
|
width 9.
|
|
rgroup.byte 0x13++0x01 "Minimum and Maximum Values of Current and Voltage"
|
|
line.word 0x00 "ADCCMAX,Maximum Current Value"
|
|
rgroup.byte 0x15++0x01
|
|
line.word 0x00 "ADCCMIN,Minimum Current Value"
|
|
rgroup.byte 0x17++0x01
|
|
line.word 0x00 "ADCVMAX,Maximum Voltage Value"
|
|
rgroup.byte 0x19++0x01
|
|
line.word 0x00 "ADCVMIN,Minimum Voltage Value"
|
|
width 9.
|
|
group.byte 0x4c++0x00 "Temperature Limits"
|
|
line.byte 0x00 "ADCTMAX,Upper Boundary for Temperature Interval"
|
|
group.byte 0x4d++0x00
|
|
line.byte 0x00 "ADCTMIN,Lower Boundary for Temperature Interval"
|
|
width 9.
|
|
group.byte 0x4e++0x01 "Miscellaneous Registers"
|
|
line.word 0x00 "ADCACMP,ADC Function Enable Register"
|
|
bitfld.word 0x00 10. " TWUENA ,Enables the strobe to interrupt the controller for checking the temperature limits" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " VTHSEL ,Value compared to the threshold ADCVTH select" "Single conversion,All conversions"
|
|
bitfld.word 0x00 8. " VTHWUENA ,Enables the strobe to interrupt the controller for the voltage threshold comparator and voltage accumulator functionality" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ACCURSTMODE ,ADCCACCU reset when current result counter is reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CTCVRSTMODE ,ADCCTCV reset when current result counter is reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " VTOVRENA ,Enables the strobes to interrupt the controller when an over-range or overflow has been detected in the voltage/temperature channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " COVRENA ,Enables the strobes to interrupt the controller when an over-range or overflow has been detected in the current channel" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CACCUTHENA ,Enables the strobe to interrupt the controller when the current accumulator exceeds its threshold" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--2. " CTCVMODE ,Current threshold comparator mode" "Disabled,Decrement/Increment,Reset/Increment,Retain/Increment"
|
|
textline " "
|
|
bitfld.word 0x00 0. " ANAGNDSW ,Signal pdExtTemp forced to 1" "Not forced,Forced"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "ADCGOMD,Reference Voltage and SDM Configuration"
|
|
bitfld.byte 0x00 4.--7. " SDMSETUP ,Configuration of the initial setup procedure" "4 cycles,8 cycles,16 cycles,32 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,1024 cycles,1024 cycles,1024 cycles,1024 cycles,1024 cycles,1024 cycles,1024 cycles"
|
|
bitfld.byte 0x00 2.--3. " SDMCHOPCLKDIV ,Clock divider value for the chop clock related to the SDM clock" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " VREFSEL ,Selection of the voltage reference" "VBGH,VBGL,VCM,External"
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "ADCSAMP,Oversampling and Filter Configuration"
|
|
bitfld.byte 0x00 5. " CHOPPAUSE ,Length of pause in chopping mode" "8 cycles,16 cycles"
|
|
bitfld.byte 0x00 3.--4. " AVGFILTCFG ,Configuration of post filter" "No averaging,No averaging,2-stage,3-stage"
|
|
bitfld.byte 0x00 0.--1. " ADCSAMP ,Oversampling rater" "256x,128x,64x,32x"
|
|
tree.end
|
|
width 9.
|
|
tree "ADC Control and Conversion Timing Registers"
|
|
group.byte 0x56++0x00
|
|
line.byte 0x00 "ADCCTRL,ADC Control Register"
|
|
bitfld.byte 0x00 6. " CHOPENA ,Chopping Mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--5. " ADCMODE ,ADC multiplexer configuration (FP state)" "Measure current/voltage,Measure current/external temperature,Measure current/internal temperature,Offset calibration,Gain calibration at maximum,Gain calibration at minimum,Internal test voltage/voltage,Test Mode"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " STOPADC ,Stop signal for both ADCs (FP state)" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " STARTADCV ,Start signal for the voltage ADC (FP state)" "Not started,Started"
|
|
bitfld.byte 0x00 0. " STARTADCC ,Start signal for the current ADC (FP state)" "Not started,Started"
|
|
tree.end
|
|
width 9.
|
|
tree "Diagnostic Features Registers"
|
|
if (((d.b(usr:0x00+0x56))&0x38)==0x38)
|
|
group.byte 0xd0++0x00
|
|
line.byte 0x00 "ADCCHAN,Analog Multiplexer Configuration"
|
|
bitfld.byte 0x00 6. " PARALLELMD ,Parallel Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--5. " CSEL ,Selects the differential sources for the current ADC" "INP/INN,INP/INN,INP/INN,INP/INN,1mV/VSSA,VREF/VSSA,VSSA/VREF,VCM/VCM"
|
|
bitfld.byte 0x00 0.--2. " VTSEL ,Selects the differential sources for the voltage ADC" "VDDA/NTH,NTH/NTL,VPTAT/VREF,Divided VBAT/VSSA,VREF/VSSA,VSSA/VREF,VCM/VCM,Internal test input"
|
|
else
|
|
hgroup.byte 0xd0++0x00
|
|
hide.byte 0x00 "ADCCHAN,Analog Multiplexer Configuration"
|
|
endif
|
|
tree.end
|
|
width 9.
|
|
tree "Digital Features Registers"
|
|
group.byte 0xd1++0x00
|
|
line.byte 0x00 "ADCDIAG,Enable Register for Test and Diagnosis Features"
|
|
bitfld.byte 0x00 7. " CLKCHOPENA ,Enable signal for the chop clock used partially in the analog part" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " STOPCLKCHOP ,Disable signal for the chop clock used partially in the analog part" "No,Yes"
|
|
bitfld.byte 0x00 4.--5. " PULLSRCCFG ,Current/temperature channel pull-up/down current sources configuration (on INP|NTH / on INN|NTL)" "-50uA/-50uA,-50uA/+50uA,+50uA/-50uA,+50uA/+50uA"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CTSRCPULLENA ,Enables the current and temperature measurement path pull-up/down current sources" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ADCIFTESTENA ,Enables the serial ADC test" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RAWENA ,Enables the ADC raw data test" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " BISTENA ,Enables BIST" "Disabled,Enabled"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "SBC LIN Support Logic"
|
|
width 8.
|
|
group.byte 0xb4++0x00
|
|
line.byte 0x00 "LINCFG,LIN Configuration Register"
|
|
bitfld.byte 0x00 5. " CLRLINSHORT ,Clear the detected LIN SHORT flag and to release the protection of the LIN TXD line" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 4. " CLRTXDTIMEOUT ,Clear the detected TXD timeout flag and to release the protection of the LIN TXD line" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 2. " SHORTPROTENA ,Enables the LIN short protection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TXDPROTDIS ,All protection features that force the LIN TXD line to 1 are overwritten" "No,Yes"
|
|
bitfld.byte 0x00 0. " LINFASTENA ,Slew rate control in the LIN PHY transmitter is disabled allowing higher LIN data rates of up to 125 kBaud" "Disabled,Enabled"
|
|
width 16.
|
|
group.byte 0xb5++0x00
|
|
line.byte 0x00 "LINSHORTFILTER,Configuration Register for the LIN Short De-bounce Filter"
|
|
group.byte 0xb6++0x00
|
|
line.byte 0x00 "LINSHORTDELAY,Configuration Register LIN Short TX-RX Delay"
|
|
width 0xb
|
|
tree.end
|
|
tree "SBC OTP"
|
|
width 11.
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "OTP_VALID,OTP_VALID Register"
|
|
bitfld.byte 0x00 0. " OTP_VALID ,OTP content valid" "Not valid,Valid"
|
|
group.byte 0xE1++0x00
|
|
line.byte 0x00 "LIN_TRIM,LIN_TRIM Register"
|
|
bitfld.byte 0x00 0.--3. " IBIAS_LIN_TRIM[3:0] ,IBIAS_LIN_TRIM[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xE2++0x00
|
|
line.byte 0x00 "VDD_TRIM,VDD_TRIM Register"
|
|
bitfld.byte 0x00 2.--3. " VBGH_TRIM[1:0] ,VBGH_TRIM[1:0]" "0,1,2,3"
|
|
bitfld.byte 0x00 1. " VDDP_TRIM ,VDDP trim bit" "0,1"
|
|
bitfld.byte 0x00 0. " VDDC_TRIM ,VDDC trim bit" "0,1"
|
|
group.byte 0xE3++0x00
|
|
line.byte 0x00 "BG_TRIM,BG_TRIM Register"
|
|
bitfld.byte 0x00 0.--3. " VBGH_TRIM[5:2] ,VBGH_TRIM[5:2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xE4++0x03
|
|
line.long 0x00 "IREF_OSC,IREF_OSC Register"
|
|
bitfld.long 0x00 24.--27. " IREF_OSC_TRIM[8:5] ,IREF_OSC_TRIM[8:5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. 16.--19. " IREF_OSC_TRIM[4:0] ,IREF_OSC_TRIM[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,%d..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " IBIAS_LIN_TRIM[4] ,IBIAS_LIN_TRIM[4]" "0,1"
|
|
bitfld.long 0x00 0.--3. 8. " IREF_OSC_TC_TRIM ,IREF_OSC_TC_TRIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "IREF_LP_OSC,Trim value for the low-power oscillator"
|
|
group.byte 0xE9++0x02
|
|
line.tbyte 0x00 "ADCCGAN,Gain for the current measurement"
|
|
group.byte 0xEC++0x02
|
|
line.tbyte 0x00 "ADCCOFF,Offset for the current measurement"
|
|
group.byte 0xEF++0x02
|
|
line.tbyte 0x00 "ADCVGAN,Gain for the voltage measurement"
|
|
group.byte 0xF2++0x02
|
|
line.tbyte 0x00 "ADCVOFF,Offset for the voltage measurement"
|
|
group.byte 0xF5++0x01
|
|
line.word 0x00 "ADCTGAN,Gain for the temperature measurement"
|
|
group.byte 0xF7++0x01
|
|
line.word 0x00 "ADCTOFF,Offset for the temperature measurement"
|
|
group.byte 0xFA++0x01
|
|
line.word 0x00 "LOT_ID,Lot ID number"
|
|
group.byte 0xFC++0x01
|
|
line.word 0x00 "WAFER_NO,Wafer number"
|
|
group.byte 0xFE++0x01
|
|
line.word 0x00 "DIE_POS,Die position"
|
|
width 0xb
|
|
tree.end
|
|
tree "SBC Miscellaneous Registers"
|
|
width 14.
|
|
group.byte 0xb8++0x00
|
|
line.byte 0x00 "PULLRESENA,Pull-down Resistor Control Register"
|
|
bitfld.byte 0x00 7. " PULLRESENADBGEN ,Pull-down resistor in the DBGEN pad is connected to the pad" "Not connected,Connected"
|
|
bitfld.byte 0x00 6. " PULLRESENATMS ,Pull-down resistor in the TMS pad is connected to the pad" "Not connected,Connected"
|
|
bitfld.byte 0x00 5. " PULLRESENATCK ,Pull-down resistor in the TCK pad is connected to the pad" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PULLRESENATRSTN ,Pull-down resistor in the TRSTN pad is connected to the pad" "Not connected,Connected"
|
|
bitfld.byte 0x00 3. " PULLRESENATXD ,Pull-down resistor in the TXD pad is connected to the pad" "Not connected,Connected"
|
|
bitfld.byte 0x00 2. " PULLRESENAMOSI ,Pull-down resistor in the MOSI pad is connected to the pad" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " PULLRESENASPICLK ,Pull-down resistor in the SPI_CLK pad is connected to the pad" "Not connected,Connected"
|
|
bitfld.byte 0x00 0. " PULLRESENACSN ,Pull-down resistor in the CSN pad is connected to the pad" "Not connected,Connected"
|
|
rgroup.byte 0xba++0x01
|
|
line.word 0x00 "VERSIONCODE,Version Code of SBC"
|
|
hexmask.word 0x00 0.--11. 1. " VERSIONCODE ,Version code of the SBC"
|
|
group.byte 0xc0++0x00
|
|
line.byte 0x00 "PWRTRIM,Trim Register for the Voltage Regulators and Bandgap"
|
|
bitfld.byte 0x00 2.--7. " VBGHTRIM ,Trim register for the high-precision bandgap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.byte 0x00 1. " VDDPTRIM ,Trim register for the VDDP regulator" "2.5V,3.3V"
|
|
bitfld.byte 0x00 0. " VDDCTRIM ,Trim register for VDDC regulator" "1.2V,1.8V"
|
|
group.byte 0xc3++0x00
|
|
line.byte 0x00 "IBIASLINTRIM,Trim Register for the Bias Current of the LIN Block"
|
|
bitfld.byte 0x00 0.--4. " IBIASLINTRIM ,Trim register for the bias current of the LIN block" "Smallest value,Largest value,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "System ROM"
|
|
base ad:0xF0000000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ROMTABLER,ROM Table Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " ROMTOFF ,Address offset of next ROM table relative to this ROM table"
|
|
bitfld.long 0x00 1. " 32BITF ,32-bit format ROM table" "Low,High"
|
|
bitfld.long 0x00 0. " ROMTPRES ,ROM table presence" "Not present,Present"
|
|
group.byte 0xfcc++0x00
|
|
line.byte 0x00 "MEMTYPE,Memory Type Register"
|
|
bitfld.byte 0x00 0. " MEMTYPE ,Indicates that the system memory is accessible via the DAP" "Not accessible,Accesible"
|
|
group.byte 0xfd0++0x00
|
|
line.byte 0x00 "PERID4,Peripheral ID4 Register"
|
|
bitfld.byte 0x00 0.--3. " JEP100CC , JEP100 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xfe0++0x00
|
|
line.byte 0x00 "PERID0,Peripheral ID0 Register (Project number [11:4])"
|
|
group.byte 0xfe4++0x00
|
|
line.byte 0x00 "PERID1,Peripheral ID1 Register"
|
|
bitfld.byte 0x00 4.--7. " JEP106IDC[3:0] , JEP106 ID code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 2.--3. " VAR ,Variant" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " PRNUM[13:12] ,Project number [13:12]" "0,1,2,3"
|
|
group.byte 0xfe8++0x00
|
|
line.byte 0x00 "PERID2,Peripheral ID2 Register"
|
|
bitfld.byte 0x00 4.--7. " PRNUM[3:0] ,Project number [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 3. " JEDEC ,JEDEC assigned ID fields" "Low,High"
|
|
bitfld.byte 0x00 0.--2. " JEP106IDC[6:4] ,Project number [6:4]" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xfec++0x00
|
|
line.byte 0x00 "PERID3,Peripheral ID3 Register (Revision number)"
|
|
group.byte 0xff0++0x00
|
|
line.byte 0x00 "CMPID0,Component ID0 Register (Preamble)"
|
|
group.byte 0xff4++0x00
|
|
line.byte 0x00 "CMPID1,Component ID1 Register"
|
|
bitfld.byte 0x00 4.--7. " CMPCLASS ,Component Class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PREAMBLE ,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xff8++0x00
|
|
line.byte 0x00 "CMPID2,Component ID2 Register (Preamble)"
|
|
group.byte 0xffc++0x00
|
|
line.byte 0x00 "CMPID3,Component ID3 Register (Preamble)"
|
|
width 0xb
|
|
tree.end
|
|
tree "SMU (System Management Unit)"
|
|
base ad:0x40000000
|
|
width 16.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SYS_CLKCFG,Clock Configuration"
|
|
bitfld.long 0x00 7. " ENSCLK2 ,Enable bit for ZSYSTEM2 clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CLKDIV ,Clock divider value" "/1,/2,/4,/8"
|
|
line.long 0x04 "SYS_MEMPORTCFG,Memory and Port Configuration"
|
|
bitfld.long 0x04 31. " MEMSWAP ,Memory swap bit" "Flash,RAM"
|
|
bitfld.long 0x04 30. " LINTEST ,Configuration bit for LIN test" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " I2CCFG[2:1] ,Configuration bits for I2C in ZSYSTEM2 - select 1 of 4 port sets to which I2C will be mapped" "0,1,2,3"
|
|
bitfld.long 0x04 21. " I2CCFG[0] ,Configuration bits for I2C in ZSYSTEM2 - enable connection between the GPIOs and I2C" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19.--20. " USARTCFG[2:1] ,Configuration bits for USART in ZSYSTEM2 - select 1 of 4 port sets to which USART will be mapped" "0,1,2,3"
|
|
bitfld.long 0x04 18. " USARTCFG[0] ,Configuration bits for USART in ZSYSTEM2 - enable connection between the GPIOs and USART" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " SPICFG[1] ,Configuration bits for SPI in ZSYSTEM2 - select 1 of 2 port sets to which SPI will be mapped" "0,1"
|
|
bitfld.long 0x04 16. " SPICFG[0] ,Configuration bits for SPI in ZSYSTEM2 - enable connection between the GPIOs and SPI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " PPNOD[15] ,GPIO15 output configuration" "Open-drain,Push-pull"
|
|
bitfld.long 0x04 14. " PPNOD[14] ,GPIO14 output configuration" "Open-drain,Push-pull"
|
|
bitfld.long 0x04 13. " PPNOD[13] ,GPIO13 output configuration" "Open-drain,Push-pull"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PPNOD[12] ,GPIO12 output configuration" "Open-drain,Push-pull"
|
|
bitfld.long 0x04 11. " PPNOD[11] ,GPIO11 output configuration" "Open-drain,Push-pull"
|
|
bitfld.long 0x04 10. " PPNOD[10] ,GPIO10 output configuration" "Open-drain,Push-pull"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PPNOD[9] ,GPIO9 output configuration" "Open-drain,Push-pull"
|
|
bitfld.long 0x04 8. " PPNOD[8] ,GPIO8 output configuration" "Open-drain,Push-pull"
|
|
bitfld.long 0x04 7. " PPNOD[7] ,GPIO7 output configuration" "Open-drain,Push-pull"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PPNOD[6] ,GPIO6 output configuration" "Open-drain,Push-pull"
|
|
bitfld.long 0x04 5. " PPNOD[5] ,GPIO5 output configuration" "Open-drain,Push-pull"
|
|
bitfld.long 0x04 4. " PPNOD[4] ,GPIO4 output configuration" "Open-drain,Push-pull"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PPNOD[3] ,GPIO3 output configuration" "Open-drain,Push-pull"
|
|
bitfld.long 0x04 2. " PPNOD[2] ,GPIO2 output configuration" "Open-drain,Push-pull"
|
|
bitfld.long 0x04 1. " PPNOD[1] ,GPIO1 output configuration" "Open-drain,Push-pull"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PPNOD[0] ,GPIO0 output configuration" "Open-drain,Push-pull"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SYS_MEMINF,Memory Information"
|
|
bitfld.long 0x00 30.--31. " PROTINFO[3:2] ,Memory protection scheme - number of failed unlock attempts" "0,1,2,3"
|
|
bitfld.long 0x00 29. " PROTINFO[1] ,Memory protection scheme - permanent lock" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " PROTINFO[0] ,Memory protection scheme - key based lock" "Not locked,Locked"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--26. 1. " RAMSPLIT ,First RAM word that is accessible by JTAG although the memory is locked"
|
|
hexmask.long.byte 0x00 8.--15. 1. " LOGSTART ,First page where the log section inside the flash starts"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PROGSTART ,First page where the program section inside the flash starts"
|
|
hgroup.long 0x0c++0x03
|
|
hide.long 0x00 "SYS_RSTSTAT,Reset Status"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "FC (Flash Controller)"
|
|
base ad:0x40000800
|
|
width 14.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "FC_RAM_ADDR,RAM Address for Command Execution"
|
|
hexmask.long.word 0x00 0.--10. 1. " ADDRRAM ,RAM word address where data to be written into flash is located"
|
|
line.long 0x04 "FC_FLASH_ADDR,FLASH Address for Command Execution"
|
|
hexmask.long.word 0x04 0.--14. 1. " FLASHADDR ,Flash word address (first address) where data will be written"
|
|
line.long 0x08 "FC_CMD_SIZE,Command Setup and Write Size Configuration"
|
|
bitfld.long 0x08 8.--12. " WRSIZE ,Number of words to be written to the flash" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--3. " CMD ,Command to be executed by the flash controller" "ERASE_MAIN_CMD,Reserved,ERASE_BOOT_PROG_CMD,ERASE_PROG_CMD,ERASE_MAINPAGE_CMD,Reserved,ERASE_KEY_CMD,Reserved,UNLOCK_CMD,GETENV_CMD,WRITE_CMD,Reserved,SET_KEY_CMD,SET_BOUNDARY_CMD,LOCK_PERM_CMD,LOCK_KEY_CMD"
|
|
line.long 0x0c "FC_EXE_CMD,Start Command Execution"
|
|
bitfld.long 0x0c 0. " EXECMD ,Starts the execution of the configured command" "No efect,Execute"
|
|
line.long 0x10 "FC_IRQ_EN,Interrupt Enables"
|
|
bitfld.long 0x10 7. " ENIRQ7 ,Status signal prog1Err is allowed to drive the interrupt line" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " ENIRQ6 ,Status signal data2Err is allowed to drive the interrupt line" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " ENIRQ5 ,Status signal data1Err is allowed to drive the interrupt line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " ENIRQ4 ,Status signal dataAll1 is allowed to drive the interrupt line" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " ENIRQ3 ,Status signal unlockFail is allowed to drive the interrupt line" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " ENIRQ2 ,Status signal invalidArea is allowed to drive the interrupt line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ENIRQ1 ,Status signal invalidCmd is allowed to drive the interrupt line" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " ENIRQ0 ,Status signal cmdRdy is allowed to drive the interrupt line" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FC_STAT_CORE,FLASH Controller Core Status"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "FC_STAT_PROG,FLASH Controller Instruction Fetch Status"
|
|
in
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "FC_STAT_DATA,FLASH Controller Data Load Status"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "GPIO (General Pin Input/Output)"
|
|
base ad:0x40001400
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIO_DIR,GPIO Direction"
|
|
bitfld.long 0x00 4. " GPIODIR[4] ,Direction of GPIO pad 4" "Input,Output"
|
|
bitfld.long 0x00 3. " GPIODIR[3] ,Direction of GPIO pad 3" "Input,Output"
|
|
bitfld.long 0x00 2. " GPIODIR[2] ,Direction of GPIO pad 2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GPIODIR[1] ,Direction of GPIO pad 1" "Input,Output"
|
|
bitfld.long 0x00 0. " GPIODIR[0] ,Direction of GPIO pad 0" "Input,Output"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "GPIO_IN,GPIO Input Value"
|
|
bitfld.long 0x00 4. " GPIOIN[4] ,Synchronized input value of GPIO pad 4" "0,1"
|
|
bitfld.long 0x00 3. " GPIOIN[3] ,Synchronized input value of GPIO pad 3" "0,1"
|
|
bitfld.long 0x00 2. " GPIOIN[2] ,Synchronized input value of GPIO pad 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GPIOIN[1] ,Synchronized input value of GPIO pad 1" "0,1"
|
|
bitfld.long 0x00 0. " GPIOIN[0] ,Synchronized input value of GPIO pad 0" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GPIO_OUT,GPIO Output Value"
|
|
bitfld.long 0x00 4. " GPIOOUT[4] ,Value to be driven out of GPIO pad 4" "0,1"
|
|
bitfld.long 0x00 3. " GPIOOUT[3] ,Value to be driven out of GPIO pad 3" "0,1"
|
|
bitfld.long 0x00 2. " GPIOOUT[2] ,Value to be driven out of GPIO pad 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GPIOOUT[1] ,Value to be driven out of GPIO pad 1" "0,1"
|
|
bitfld.long 0x00 0. " GPIOOUT[0] ,Value to be driven out of GPIO pad 0" "0,1"
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "GPIO_SETCLR,Set and Clear for GPIO Output Value"
|
|
bitfld.long 0x00 20. " GPIOCLEAR[4] ,GPIO pad 4 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 19. " GPIOCLEAR[3] ,GPIO pad 3 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 18. " GPIOCLEAR[2] ,GPIO pad 2 clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPIOCLEAR[1] ,GPIO pad 1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 16. " GPIOCLEAR[0] ,GPIO pad 0 clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GPIOSET[4] ,GPIO pad 4 set bit" "No effect,Set"
|
|
bitfld.long 0x00 3. " GPIOSET[3] ,GPIO pad 3 set bit" "No effect,Set"
|
|
bitfld.long 0x00 2. " GPIOSET[2] ,GPIO pad 2 set bit" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GPIOSET[1] ,GPIO pad 1 set bit" "No effect,Set"
|
|
bitfld.long 0x00 0. " GPIOSET[0] ,GPIO pad 0 set bit" "No effect,Set"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "GPIO_IRQSTAT,Interrupt Status"
|
|
in
|
|
group.long 0x14++0x0b
|
|
line.long 0x00 "GPIO_IRQEN,Interrupt Enable"
|
|
bitfld.long 0x00 4. " IRQSTAT[4] ,GPIO pad 4 interrupt allowed to drive interrupt line" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IRQSTAT[3] ,GPIO pad 3 interrupt allowed to drive interrupt line" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IRQSTAT[2] ,GPIO pad 2 interrupt allowed to drive interrupt line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQSTAT[1] ,GPIO pad 1 interrupt allowed to drive interrupt line" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IRQSTAT[0] ,GPIO pad 0 interrupt allowed to drive interrupt line" "Disabled,Enabled"
|
|
line.long 0x04 "GPIO_IRQEDGE,Selection for Interrupt"
|
|
bitfld.long 0x04 4. " IRQEDGE[4] ,GPIO pad 4 interrupt edge to trigger the interrupt line" "Rising,Falling"
|
|
bitfld.long 0x04 3. " IRQEDGE[3] ,GPIO pad 3 interrupt edge to trigger the interrupt line" "Rising,Falling"
|
|
bitfld.long 0x04 2. " IRQEDGE[2] ,GPIO pad 2 interrupt edge to trigger the interrupt line" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IRQEDGE[1] ,GPIO pad 1 interrupt edge to trigger the interrupt line" "Rising,Falling"
|
|
bitfld.long 0x04 0. " IRQEDGE[0] ,GPIO pad 0 interrupt edge to trigger the interrupt line" "Rising,Falling"
|
|
line.long 0x08 "GPIO_TRIGEN,Trigger Enable"
|
|
bitfld.long 0x08 4. " TRIGEN[4] ,GPIO pad 4 trigger line drive" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TRIGEN[3] ,GPIO pad 3 trigger line drive" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " TRIGEN[2] ,GPIO pad 2 trigger line drive" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TRIGEN[1] ,GPIO pad 1 trigger line drive" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TRIGEN[0] ,GPIO pad 0 trigger line drive" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "T32 (32-Bit Timer)"
|
|
base ad:0x40001000
|
|
width 13.
|
|
if (((d.l(ad:0x40001000))&0x0a)==0x0a)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "T32_CTRL,Timer Control"
|
|
rbitfld.long 0x00 5. " OVERFLOW ,Overflow flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 4. " MODEPN ,Selects between the rising or falling edge active trigger" "Falling,Rising"
|
|
bitfld.long 0x00 3. " MODELE ,Select between level or edge sensitive trigger" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MODESR ,Select between the reload and single-shot modes" "Reload,Single-Shot"
|
|
bitfld.long 0x00 1. " MODETC ,Select between the timer and counter modes" "Timer,Counter"
|
|
bitfld.long 0x00 0. " EN ,Enable bit for timer" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x40001000))&0x0a)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "T32_CTRL,Timer Control"
|
|
rbitfld.long 0x00 5. " OVERFLOW ,Overflow flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 4. " MODEPN ,Selects between high or low level active trigger" "Low,High"
|
|
bitfld.long 0x00 3. " MODELE ,Select between level or edge sensitive trigger" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MODESR ,Select between the reload and single-shot modes" "Reload,Single-Shot"
|
|
bitfld.long 0x00 1. " MODETC ,Select between the timer and counter modes" "Timer,Counter"
|
|
bitfld.long 0x00 0. " EN ,Enable bit for timer" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "T32_CTRL,Timer Control"
|
|
rbitfld.long 0x00 5. " OVERFLOW ,Overflow flag" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MODESR ,Select between the reload and single-shot modes" "Reload,Single-Shot"
|
|
bitfld.long 0x00 1. " MODETC ,Select between the timer and counter modes" "Timer,Counter"
|
|
bitfld.long 0x00 0. " EN ,Enable bit for timer" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x0b
|
|
line.long 0x00 "T32_TRIGSEL,Trigger Selection"
|
|
bitfld.long 0x00 0.--4. " TRIGSEL ,Select signal for the trigger source" "No source,GPIO0,GPIO1,GPIO2,GPIO3,GPIO4,?..."
|
|
line.long 0x04 "T32_CNT,Timer Value"
|
|
line.long 0x08 "T32_REL,Timer Reload Value"
|
|
width 0xb
|
|
tree.end
|
|
tree.open "ZSYSTEM1"
|
|
tree "SW-LIN (Software Controlled LIN Controller)"
|
|
base ad:0x40001800
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "Z1_LINCFG,SW-LIN Configuration"
|
|
rbitfld.long 0x00 6. " TXACTIVE ,Status of the transmitter" "Not active,Active"
|
|
rbitfld.long 0x00 5. " RXACTIVE ,Status of the receiver" "Not active,Active"
|
|
rbitfld.long 0x00 4. " RXEN ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENTOCNT ,Timeout counter for bus inactivity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FASTMODE ,Distinguishes between slow and fast mode" "Slow,Fast"
|
|
bitfld.long 0x00 1. " DISABLERX ,Receiver disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STOPRX ,Receiver stop" "Running,Stopped"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "Z1_LINSTAT,SW-LIN Status"
|
|
in
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "Z1_LINDATA,SW-LIN Data"
|
|
in
|
|
group.long 0x0c++0x0b
|
|
line.long 0x00 "Z1_LINIRQEN,SW-LIN Interrupt Enable"
|
|
bitfld.long 0x00 7. " INACTIVE ,Inactive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXOFF ,TxOff interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WRCOLL ,WrColl interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXOVERFLOW ,RxOverflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CONFLICT ,Conflict interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TXEMPTY ,TxEmpty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXFULL ,RxFull interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SYNCDET ,SyncDet interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "Z1_LINBAUDLOW,Baud Rate Configuration Low Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LINBAUDLOW ,Baud rate for LIN interface"
|
|
line.long 0x08 "Z1_LINBAUDHIGH,Baud Rate Configuration High Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " LINBAUDHIGH ,Baud rate for LIN interface"
|
|
width 0xb
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x40001820
|
|
width 14.
|
|
group.long 0x00++0x0b
|
|
line.long 0x00 "Z1_SPICFG,SW-LIN Configuration"
|
|
bitfld.long 0x00 7. " SPIEN ,Enable for the SPI module" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CSN ,Directly controls the CSN line" "Low,High"
|
|
bitfld.long 0x00 5. " SAMPLEPOS ,MISO sample select" "Sampling edge,Shift edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WRCOLL ,WrColl interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TXEMPTY ,TxEmpty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXFULL ,RxFull interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXOF ,RxOf interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "Z1_SPIDATA,SPI Data Buffers"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SPIDATA ,SPI Data"
|
|
line.long 0x08 "Z1_SPICLKCFG,SPI Clock Configuration"
|
|
bitfld.long 0x08 2.--7. " CDIV ,Clock divider value" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,88,90,92,94,96,98,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128"
|
|
bitfld.long 0x08 1. " CPHA ,Clock phase" "First edge,Second edge"
|
|
bitfld.long 0x08 0. " CPOL ,Clock polarity" "Low,High"
|
|
hgroup.long 0x0c++0x03
|
|
hide.long 0x00 "Z1_SPISTAT,SPI Status"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "ZSYSTEM2"
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x40001C00
|
|
width 14.
|
|
group.long 0x00++0x0b
|
|
line.long 0x00 "Z2_SPICFG,SW-LIN Configuration"
|
|
bitfld.long 0x00 7. " SPIEN ,Enable for the SPI module" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CSN ,Directly controls the CSN line" "Low,High"
|
|
bitfld.long 0x00 5. " SAMPLEPOS ,MISO sample select" "Sampling edge,Shift edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WRCOLL ,WrColl interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TXEMPTY ,TxEmpty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXFULL ,RxFull interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXOF ,RxOf interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "Z2_SPIDATA,SPI Data Buffers"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SPIDATA ,SPI Data"
|
|
line.long 0x08 "Z2_SPICLKCFG,SPI Clock Configuration"
|
|
bitfld.long 0x08 2.--7. " CDIV ,Clock divider value" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,88,90,92,94,96,98,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128"
|
|
bitfld.long 0x08 1. " CPHA ,Clock phase" "First edge,Second edge"
|
|
bitfld.long 0x08 0. " CPOL ,Clock polarity" "Low,High"
|
|
hgroup.long 0x0c++0x03
|
|
hide.long 0x00 "Z2_SPISTAT,SPI Status"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "I2C (SInter-Integrated Circuit)"
|
|
base ad:0x40001C20
|
|
width 16.
|
|
group.long 0x00++0x0f
|
|
line.long 0x00 "Z2_I2CCLKRATE,Baud Rate Configuration"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CRLSB ,Configuration of bit rate for master operation LSB"
|
|
line.long 0x04 "Z2_I2CCLKRATE2,Baud Rate Configuration 2"
|
|
bitfld.long 0x04 0.--5. " CRMSB ,Configuration of bit rate for master operation MSB" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "Z2_I2CADDR,I2C Address"
|
|
hexmask.long.byte 0x08 1.--7. 0x2 " ADDR ,Own I2C slave address"
|
|
bitfld.long 0x08 0. " GC ,General call address enable" "Disabled,Enabled"
|
|
line.long 0x0c "Z2_I2CCTRL,I2C Control"
|
|
bitfld.long 0x0c 5. " START ,Start/restart bit for master mode" "Not started,Started"
|
|
bitfld.long 0x0c 4. " STOP ,Stop bit for master mode" "Not stopped,Stopped"
|
|
bitfld.long 0x0c 3. " IRQ ,Interrupt bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " ACK ,ACK bit generation" "Not generated,Generated"
|
|
bitfld.long 0x0c 1. " MULTI ,Must be set in multi-master applications" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " ENI2C ,Enable bit for the I2C module" "Disabled,Enabled"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "Z2_I2CSTAT,I2C Status"
|
|
bitfld.long 0x00 0.--4. " GC ,Last interrupt reason" "Idle,TxStart,TxWrAddr,TxWrAddrN,MstTxData,MstTxDataN,TxRdAddr,TxRdAddrN,MstRxData,MstRxDataN,RxWrAddr,RxWrAddrL,RxGcAddr,RxGcAddrL,RxWrData,RxWrDataN,RxGcData,RxGcDataN,RxSlvEnd,RxRdAddr,RxRdAddrL,SlvTxData,SlvTxDataN,SlvTxDataL,Conflict,BusError,Reserved,Reserved,Reserved,Reserved,Reserved,HWError"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "Z2_I2CDATA,I2C Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GC ,Data register"
|
|
width 0xb
|
|
tree.end
|
|
tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
|
|
base ad:0x40001C40
|
|
width 15.
|
|
if (((d.l(ad:0x40001C40))&0x0c)==0x0c)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "Z2_USARTCFG,USART Configuration"
|
|
bitfld.long 0x00 7. " TXBIT8 ,Ninth bit to be transmitted" "0,1"
|
|
bitfld.long 0x00 4. " MPCE ,Multiprocessor communication enable - 9th bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODE ,USART mode" "8 bit/synchronous/rising edge,8 bit/synchronous/end of bit period,8 bit/asynchronous,9 bit/asynchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXEN ,Enable for the RX part of the USART" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x40001C40))&0x0c)==0x08)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "Z2_USARTCFG,USART Configuration"
|
|
bitfld.long 0x00 4. " MPCE ,Multiprocessor communication enable - STOP bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODE ,USART mode" "8 bit/synchronous/rising edge,8 bit/synchronous/end of bit period,8 bit/synchronous,9 bit/asynchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXEN ,Enable for the RX part of the USART" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "Z2_USARTCFG,USART Configuration"
|
|
bitfld.long 0x00 2.--3. " MODE ,USART mode" "8 bit/synchronous/rising edge,8 bit/synchronous/end of bit period,8 bit/synchronous,9 bit/asynchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RXEN ,Enable for the RX part of the USART" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "Z2_USARTSTAT,USART Status"
|
|
in
|
|
group.long 0x08++0x0f
|
|
line.long 0x00 "Z2_USARTDATA,USART Data Buffers"
|
|
hexmask.long.byte 0x00 0.--7. 1. " USERDATA ,User Data"
|
|
line.long 0x04 "Z2_USARTIRQEN,Interrupt Enable"
|
|
bitfld.long 0x04 5. " TXSREMPTY ,TxSrEmpty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " STARTERR ,StartErr interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " WRCOLL ,WrColl interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXEMPTY ,TxEmpty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RXFULL ,RxFull interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RXOF ,RxOf interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "Z2_USARTCLK1,Baud Rate Configuration"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CRLSB ,Configuration of baud rate LSB"
|
|
line.long 0x0c "Z2_USARTCLK2,Baud Rate Configuration 2"
|
|
hexmask.long.byte 0x0c 0.--6. 1. " CRMSB ,Configuration of baud rate MSB"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
width 0xb
|