47329 lines
3.3 MiB
47329 lines
3.3 MiB
; --------------------------------------------------------------------------------
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; @Title: XMC72XX On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2023-01-18 NEJ
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; @Manufacturer: INFINEON - Infineon Technologies AG
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; @Doc: SVD generated (SVD2PER 1.8.6), based on: xmc7200_cat1c8m.svd (Ver. 1.0)
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; @Core: Cortex-M7F, Cortex-M0+
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; @Chip: XMC7200DE272K8384-CM0+, XMC7200DE272K8384-CM7-0, XMC7200DE272K8384-CM7-1,
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; XMC7200DF176K8384-CM0+, XMC7200DF176K8384-CM7-0, XMC7200DF176K8384-CM7-1,
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; XMC7200E272K8384-CM0+, XMC7200E272K8384-CM7, XMC7200F176K8384-CM0+,
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; XMC7200F176K8384-CM7
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perxmc72xx.per 15665 2023-01-23 10:04:36Z kwisniewski $
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sif (CORENAME()=="CORTEXM7F")
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tree.close "Core Registers (Cortex-M7F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 28. " DISFPUISSOPT ,DISFPUISSOPT" "No,Yes"
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bitfld.long 0x00 27. " DISCRITAXIRUW ,Disables critical AXI read-under-write" "No,Yes"
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bitfld.long 0x00 26. " DISDYNADD ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 21.--25. " DISISSCH1 ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 16.--20. " DISDI ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 15. " DISCRITAXIRUR ,Disables critical AXI read-under-read" "No,Yes"
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textline " "
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bitfld.long 0x00 14. " DISBTACALLOC ,DISBTACALLOC" "No,Yes"
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bitfld.long 0x00 13. " DISBTACREAD ,DISBTACREAD" "No,Yes"
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bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
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textline " "
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bitfld.long 0x00 11. " DISRAMODE ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes"
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bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
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textline ""
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Patch 0,Patch 1,Patch 2,?..."
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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textline " "
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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textline " "
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,Writing 1 to this bit causes a local system reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,MemManage" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall status" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault status" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage status" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick status" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV status" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor status" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall status" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault status" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault status" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage status" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x13
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line.long 0x00 "HFSR,HardFault Status Register"
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eventfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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eventfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
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eventfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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eventfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred"
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eventfld.long 0x04 3. " VCATCH ,Indicates triggering of a Vector catch" "Not occurred,Occurred"
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eventfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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eventfld.long 0x04 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred"
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eventfld.long 0x04 0. " HALTED ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred"
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line.long 0x08 "MMFAR,MemManage Fault Address Register"
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line.long 0x0C "BFAR,BusFault Address Register"
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line.long 0x10 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,,Full"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Triggered Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,level 2,?..."
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,?..."
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textline " "
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bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
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bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
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bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
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textline " "
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bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
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bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
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bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 29.--31. " FORMAT ,Indicates the implemented CTR format" ",,,,ARMv7,?..."
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification"
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wgroup.long 0xF58++0x1F
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line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU"
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line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)"
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line.long 0x08 "DCISW,Data cache invalidate by set/way"
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line.long 0x0C "DCCMVAU,Data cache by address to PoU"
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line.long 0x10 "DCCMVAC,Data cache clean by address to PoC"
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line.long 0x14 "DCCSW,Data cache clean by set/way"
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line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC"
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line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way"
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group.long 0xF90++0x13
|
|
line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x00 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x04 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x08 "AHBPCR,AHBP control register"
|
|
bitfld.long 0x08 1.--3. " SZ ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..."
|
|
bitfld.long 0x08 0. " EN ,AHBP enable" "Disabled,Enabled"
|
|
line.long 0x0C "CACR,L1 Cache Control Register"
|
|
bitfld.long 0x0C 2. " FORCEWT ,Enables Force Write-through in the data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ECCDIS ,Disables ECC in the instruction and data cache" "No,Yes"
|
|
bitfld.long 0x0C 0. " SIWT ,Enables limited cache coherency usage" "Disabled,Enabled"
|
|
line.long 0x10 "AHBSCR,AHB Slave Control Register"
|
|
bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x10 2.--10. 1. " TPRI ,Threshold execution priority for AHBS traffic demotion"
|
|
bitfld.long 0x10 0.--1. " CTL ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI"
|
|
group.long 0xFA8++0x03
|
|
line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register"
|
|
bitfld.long 0x00 8.--9. " AXIMTYPE ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR"
|
|
bitfld.long 0x00 4. " EPPB ,Asynchronous fault on EPPB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AXIM ,Asynchronous fault on AXIM interface" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AHBP ,Asynchronous fault on AHBP interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " DTCM ,Asynchronous fault on DTCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ITCM ,Asynchronous fault on ITCM interface" "Not occurred,Occurred"
|
|
group.long 0xFB0++0x03
|
|
line.long 0x00 "IEBR0,Instruction Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "IEBR1,Instruction Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB8++0x03
|
|
line.long 0x00 "DEBR0,Data Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFBC++0x03
|
|
line.long 0x00 "DEBR1,Data Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
width 10.
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
width 6.
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM7F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
newline
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
newline
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
newline
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
else
|
|
tree.close "Core Registers (Cortex-M0+)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0x8
|
|
if (CORENAME()=="CORTEXM1")
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
else
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
endif
|
|
if (CORENAME()=="CORTEXM1")
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
|
|
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
|
|
else
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
|
|
endif
|
|
rgroup.long 0xd00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
|
|
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
|
|
group.long 0xd04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
group.long 0xd08++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
else
|
|
textline " "
|
|
endif
|
|
group.long 0xd0c++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
|
|
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
|
|
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
|
|
group.long 0xd10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
rgroup.long 0xd14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
|
|
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
|
|
group.long 0xd1c++0x0b
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
|
|
line.long 0x04 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
|
|
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
|
|
line.long 0x08 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
else
|
|
textline " "
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
autoindent.on center tree
|
|
tree "BACKUP (SRSS Backup Domain)"
|
|
base ad:0x40270000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EN_CHARGE_KEY,When set to 3C the supercap charger circuit is enabled"
|
|
bitfld.long 0x00 19. "VBACKUP_MEAS,Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--18. "VDDBAK_CTL,Controls the behavior of the switch that generates vddbak from vbackup or vddd" "0: automatically select vddd if its brownout,?,?,3: force vddbak and vmax to select vbackup"
|
|
bitfld.long 0x00 16. "WCO_BYPASS,Configures the WCO for different board-level connections to the WCO pins" "0: Watch crystal,1: Clock signal either a square wave or sine wave"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRESCALER,N/A" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CLK_SEL,Clock select for RTC clock" "0: Watch-crystal oscillator input available in..,1: This allows to use the LFCLK selection as an..,2: Internal Low frequency Oscillator available..,3: Low-power external crystal oscillator.."
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|
newline
|
|
bitfld.long 0x00 3. "WCO_EN,Watch-crystal oscillator (WCO) enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_RW,RTC Read Write register"
|
|
bitfld.long 0x00 1. "WRITE,Write bit Only when this bit is set can the RTC registers be written to (otherwise writes are ignored)" "0,1"
|
|
bitfld.long 0x00 0. "READ,Read bit When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CAL_CTL,Oscillator calibration for absolute frequency"
|
|
bitfld.long 0x00 31. "CAL_OUT,Output enable for wave signal for calibration and allow CALIB_VAL to be written" "0,1"
|
|
bitfld.long 0x00 28.--29. "CAL_SEL,Select calibration wave output signal" "0: 512Hz wave not affected by calibration..,1: RSVD,2: 2Hz wave includes the effect of the..,3: 1Hz wave includes the effect of the.."
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|
newline
|
|
bitfld.long 0x00 6. "CALIB_SIGN,Calibration sign" "0: Negative sign,1: Positive sign"
|
|
bitfld.long 0x00 0.--5. "CALIB_VAL,Calibration value for absolute frequency (at a fixed temperature)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "STATUS,Status"
|
|
bitfld.long 0x00 2. "WCO_OK,Indicates that output has transitioned" "0,1"
|
|
bitfld.long 0x00 0. "RTC_BUSY,Pending RTC" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_TIME,Calendar Seconds Minutes Hours Day of Week"
|
|
bitfld.long 0x00 24.--26. "RTC_DAY,Calendar Day of the week 1-7 It is up to the user to define the meaning of the values but" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 22. "CTRL_12HR,Select 12/24HR mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "RTC_HOUR,Calendar hours value depending on 12/24HR mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 8.--13. "RTC_MIN,Calendar minutes 0-59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
|
bitfld.long 0x00 0.--5. "RTC_SEC,Calendar seconds 0-59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RTC_DATE,Calendar Day of Month Month Year"
|
|
hexmask.long.byte 0x00 16.--22. 1. "RTC_YEAR,Calendar year 0-99"
|
|
bitfld.long 0x00 8.--11. "RTC_MON,Calendar Month 1-12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 0.--4. "RTC_DATE,Calendar Day of the Month 1-31 Automatic Leap Year Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALM1_TIME,Alarm 1 Seconds Minute Hours Day of Week"
|
|
bitfld.long 0x00 31. "ALM_DAY_EN,Alarm Day of the Week enable" "0: ignore,1: match"
|
|
bitfld.long 0x00 24.--26. "ALM_DAY,Alarm Day of the week 1-7 It is up to the user to define the meaning of the values but" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x00 23. "ALM_HOUR_EN,Alarm hour enable" "0: ignore,1: match"
|
|
bitfld.long 0x00 16.--20. "ALM_HOUR,Alarm hours value depending on 12/24HR mode 24HR: [4:0]=0-23 12HR: [4]:0=AM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
|
|
bitfld.long 0x00 15. "ALM_MIN_EN,Alarm minutes enable" "0: ignore,1: match"
|
|
bitfld.long 0x00 8.--13. "ALM_MIN,Alarm minutes 0-59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
|
bitfld.long 0x00 7. "ALM_SEC_EN,Alarm second enable" "0: ignore,1: match"
|
|
bitfld.long 0x00 0.--5. "ALM_SEC,Alarm seconds 0-59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALM1_DATE,Alarm 1 Day of Month Month"
|
|
bitfld.long 0x00 31. "ALM_EN,Master enable for alarm 1" "0: Alarm 1 is disabled,1: Alarm 1 is enabled"
|
|
bitfld.long 0x00 15. "ALM_MON_EN,Alarm Month enable" "0: ignore,1: match"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "ALM_MON,Alarm Month 1-12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "ALM_DATE_EN,Alarm Day of the Month enable" "0: ignore,1: match"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ALM_DATE,Alarm Day of the Month 1-31 Leap Year corrected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ALM2_TIME,Alarm 2 Seconds Minute Hours Day of Week"
|
|
bitfld.long 0x00 31. "ALM_DAY_EN,Alarm Day of the Week enable" "0: ignore,1: match"
|
|
bitfld.long 0x00 24.--26. "ALM_DAY,Alarm Day of the week 1-7 It is up to the user to define the meaning of the values but" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. "ALM_HOUR_EN,Alarm hour enable" "0: ignore,1: match"
|
|
bitfld.long 0x00 16.--20. "ALM_HOUR,Alarm hours value depending on 12/24HR mode 24HR: [4:0]=0-23 12HR: [4]:0=AM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. "ALM_MIN_EN,Alarm minutes enable" "0: ignore,1: match"
|
|
bitfld.long 0x00 8.--13. "ALM_MIN,Alarm minutes 0-59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 7. "ALM_SEC_EN,Alarm second enable" "0: ignore,1: match"
|
|
bitfld.long 0x00 0.--5. "ALM_SEC,Alarm seconds 0-59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ALM2_DATE,Alarm 2 Day of Month Month"
|
|
bitfld.long 0x00 31. "ALM_EN,Master enable for alarm 2" "0: Alarm 2 is disabled,1: Alarm 2 is enabled"
|
|
bitfld.long 0x00 15. "ALM_MON_EN,Alarm Month enable" "0: ignore,1: match"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "ALM_MON,Alarm Month 1-12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "ALM_DATE_EN,Alarm Day of the Month enable" "0: ignore,1: match"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ALM_DATE,Alarm Day of the Month 1-31 Leap Year corrected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CENTURY,Century overflow interrupt" "0,1"
|
|
bitfld.long 0x00 1. "ALARM2,Alarm 2 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ALARM1,Alarm 1 Interrupt" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CENTURY,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 1. "ALARM2,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ALARM1,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CENTURY,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 1. "ALARM2,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ALARM1,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CENTURY,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 1. "ALARM2,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ALARM1,Logical and of corresponding request and mask bits" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PMIC_CTL,PMIC control register"
|
|
bitfld.long 0x00 31. "PMIC_EN,Enable for external PMIC that supplies vddd (if present)" "0,1"
|
|
bitfld.long 0x00 30. "PMIC_ALWAYSEN,Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware" "0: Normal operation PMIC_EN and PMIC_OUTEN work as,1: PMIC_EN and PMIC_OUTEN are ignored and the"
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|
newline
|
|
bitfld.long 0x00 29. "PMIC_EN_OUTEN,Output enable for the output driver in the PMIC_EN pad" "0: Output pad is tristate for PMIC_EN pin,1: Output pad is enabled for PMIC_EN pin"
|
|
bitfld.long 0x00 16. "POLARITY,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "UNLOCK,This byte must be set to 0x3A for PMIC to be disabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RESET,Backup reset register"
|
|
bitfld.long 0x00 31. "RESET,Writing 1 to this register resets the backup logic" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "LPECO_CTL,Low-power external crystal oscillator control"
|
|
bitfld.long 0x00 31. "LPECO_EN,Master enable for LPECO oscillator" "0,1"
|
|
bitfld.long 0x00 30. "LPECO_AMPDET_EN,Minimum amplitude detector enable/disable" "0: Initially enabled and then automatically,1: Keep minimum amplitude detector enabled as long"
|
|
newline
|
|
bitfld.long 0x00 28. "LPECO_DIV_ENABLE,LPECO prescaler enable" "0,1"
|
|
bitfld.long 0x00 12. "LPECO_AMP_SEL,Selects the oscillation amplitude" "0: maximum amplitude is 1.35V,1: maximum amplitude is 1.8V"
|
|
newline
|
|
bitfld.long 0x00 8. "LPECO_FRANGE,Specifies the crystal frequency range" "0: Crystal frequency is in range [4 6) MHz,1: Crystal frequency is in range [6 8] MHz"
|
|
bitfld.long 0x00 4.--5. "LPECO_CRANGE,Specifies the load capacitance of the chosen crystal" "0: load is in range [5pF 10pF],1: load is in range (10pF 15pF],2: load is in range (15pF 20pF],3: load is in range (20pF 25pF]"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "LPECO_PRESCALE,Low-power external crystal oscillator prescaler"
|
|
hexmask.long.word 0x00 16.--25. 1. "LPECO_INT_DIV,Integer divide value allows for LPECO frequencies up to 8MHz to generate 32768 Hz"
|
|
hexmask.long.byte 0x00 8.--15. 1. "LPECO_FRAC_DIV,Fractional value sufficient to get prescaler output within the +/-65ppm calibration range"
|
|
newline
|
|
rbitfld.long 0x00 0. "LPECO_DIV_ENABLED,LPECO prescaler enabled" "0,1"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "LPECO_STATUS,Low-power external crystal oscillator status"
|
|
bitfld.long 0x00 1. "LPECO_READY,Indicates the LPECO has had enough time to start" "0,1"
|
|
bitfld.long 0x00 0. "LPECO_AMPDET_OK,Indicates sufficient oscillation amplitude reported by LPECO amplitude detector" "0,1"
|
|
repeat 64. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x1000)++0x03
|
|
line.long 0x00 "BREG[$1],Backup register region $1"
|
|
hexmask.long 0x00 0.--31. 1. "BREG,Backup memory that contains application-specific data"
|
|
repeat.end
|
|
tree.end
|
|
tree "CANFD (CAN Controller)"
|
|
repeat 2. (list 0. 1.) (list ad:0x40520000 ad:0x40540000)
|
|
tree "CANFD$1"
|
|
base $2
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "CTL,Global CAN control register"
|
|
bitfld.long 0x00 31. "MRAM_OFF,MRAM off" "0: Default MRAM on (with MRAM retained in..,1: Switch MRAM off (not retained) to save power"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STOP_REQ,Clock Stop Request for each TTCAN IP"
|
|
rgroup.long 0x1004++0x03
|
|
line.long 0x00 "STATUS,Global CAN status register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STOP_ACK,Clock Stop Acknowledge for each TTCAN IP"
|
|
rgroup.long 0x1010++0x03
|
|
line.long 0x00 "INTR0_CAUSE,Consolidated interrupt0 cause register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INT0,Show pending m_ttcan_int0 of each channel"
|
|
rgroup.long 0x1014++0x03
|
|
line.long 0x00 "INTR1_CAUSE,Consolidated interrupt1 cause register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INT1,Show pending m_ttcan_int1 of each channel"
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "TS_CTL,Time Stamp control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable bit" "0: Count disabled,1: Count enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. "PRESCALE,Time Stamp counter prescale value"
|
|
group.long 0x1024++0x03
|
|
line.long 0x00 "TS_CNT,Time Stamp counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VALUE,The counter value of the Time Stamp Counter"
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "ECC_CTL,ECC control"
|
|
bitfld.long 0x00 16. "ECC_EN,Enable ECC for CANFD SRAM When disabled also all error injection functionality is disabled" "0,1"
|
|
group.long 0x1084++0x03
|
|
line.long 0x00 "ECC_ERR_INJ,ECC error injection"
|
|
hexmask.long.byte 0x00 24.--30. 1. "ERR_PAR,ECC Parity bits to use for ECC error injection at address ERR_ADDR"
|
|
bitfld.long 0x00 20. "ERR_EN,Enable error injection (ECC_EN must be 1)" "0,1"
|
|
hexmask.long.word 0x00 2.--15. 1. "ERR_ADDR,Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed"
|
|
repeat 5. (increment 0 1)(increment 0 0x200)
|
|
tree "CH[$1]"
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "RXFTOP_CTL,Receive FIFO Top control"
|
|
bitfld.long 0x00 1. "F1TPE,FIFO 1 Top Pointer Enable" "0,1"
|
|
bitfld.long 0x00 0. "F0TPE,FIFO 0 Top Pointer Enable" "0,1"
|
|
rgroup.long ($2+0x1A0)++0x03
|
|
line.long 0x00 "RXFTOP0_STAT,Receive FIFO 0 Top Status"
|
|
hexmask.long.word 0x00 0.--15. 1. "F0TA,Current FIFO 0 Top Address"
|
|
rgroup.long ($2+0x1A8)++0x03
|
|
line.long 0x00 "RXFTOP0_DATA,Receive FIFO 0 Top Data"
|
|
hexmask.long 0x00 0.--31. 1. "F0TD,When enabled (F0TPE=1) read data from MRAM at location FnTA"
|
|
rgroup.long ($2+0x1B0)++0x03
|
|
line.long 0x00 "RXFTOP1_STAT,Receive FIFO 1 Top Status"
|
|
hexmask.long.word 0x00 0.--15. 1. "F1TA,See F0TA description"
|
|
rgroup.long ($2+0x1B8)++0x03
|
|
line.long 0x00 "RXFTOP1_DATA,Receive FIFO 1 Top Data"
|
|
hexmask.long 0x00 0.--31. 1. "F1TD,See F0TD description"
|
|
tree "M_TTCAN"
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. "REL,Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "STEP,Step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded"
|
|
rgroup.long ($2+0x04)++0x03
|
|
line.long 0x00 "ENDN,Endian Register"
|
|
hexmask.long 0x00 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 0x87654321"
|
|
group.long ($2+0x0C)++0x03
|
|
line.long 0x00 "DBTP,Data Bit Timing & Prescaler Register"
|
|
bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
|
|
bitfld.long 0x00 16.--20. "DBRP,Data Bit Rate Prescaler 0x00-0x1F The value by which the oscillator frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point 0x00-0x1F Valid values are 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point 0x0-0xF Valid values are 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "DSJW,Data (Re)Synchronization Jump Width 0x0-0xF Valid values are 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long ($2+0x10)++0x03
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line.long 0x00 "TEST,Test Register"
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rbitfld.long 0x00 7. "RX,Receive Pin Monitors the actual value of pin m_ttcan_rx" "0: The CAN bus is dominant (m_ttcan_rx = '0'),1: The CAN bus is recessive (m_ttcan_rx = '1')"
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bitfld.long 0x00 5.--6. "TX,Control of Transmit Pin 00 Reset value m_ttcan_tx controlled by the CAN Core updated at the end of the CAN bit time 01 Sample Point can be monitored at pin m_ttcan_tx 10 Dominant ('0') level at pin m_ttcan_tx 11 Recessive ('1') at pin m_ttcan_tx" "0,1,2,3"
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bitfld.long 0x00 4. "LBCK,Loop Back Mode" "0: Reset value Loop Back Mode is disabled,1: Loop Back Mode is enabled (see Section 3.1.9"
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bitfld.long 0x00 3. "CAT,ASC is not supported by M_TTCAN Check ASC Transmit Control Monitors level at output pin m_ttcan_asct" "0,1"
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bitfld.long 0x00 2. "CAM,ASC is not supported by M_TTCAN Check ASC Multiplexer Control Monitors level at output pin m_ttcan_ascm" "0: Output pin m_ttcan_ascm = '0',1: Output pin m_ttcan_ascm = '1'"
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bitfld.long 0x00 1. "TAT,ASC is not supported by M_TTCAN Test ASC Transmit Control Controls output pin m_ttcan_asct in test mode ORed with the signal from the FSE" "0: Level at pin m_ttcan_asct controlled by FSE,1: Level at pin m_ttcan_asct = '1'"
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bitfld.long 0x00 0. "TAM,ASC is not supported by M_TTCAN Test ASC Multiplexer Control Controls output pin m_ttcan_ascm in test mode ORed with the signal from the FSE" "0: Level at pin m_ttcan_ascm controlled by FSE,1: Level at pin m_ttcan_ascm = '1'"
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group.long ($2+0x14)++0x03
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line.long 0x00 "RWD,RAM Watchdog"
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hexmask.long.byte 0x00 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value"
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hexmask.long.byte 0x00 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter"
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group.long ($2+0x18)++0x03
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line.long 0x00 "CCCR,CC Control Register"
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bitfld.long 0x00 15. "NISO,Non ISO Operation If this bit is set the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0" "0: CAN FD frame format according to ISO..,1: CAN FD frame format according to Bosch CAN FD"
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bitfld.long 0x00 14. "TXP,Transmit Pause If this bit is set the M_TTCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Section 3.5)" "0: Transmit pause disabled,1: Transmit pause enabled"
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bitfld.long 0x00 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect"
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bitfld.long 0x00 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
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bitfld.long 0x00 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
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bitfld.long 0x00 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
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bitfld.long 0x00 7. "TEST,Test Mode Enable" "0: Normal operation register TEST holds reset..,1: Test Mode write access to register TEST enabled"
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bitfld.long 0x00 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not,1: Automatic retransmission disabled"
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bitfld.long 0x00 5. "MON_,Bus Monitoring Mode Bit MON can only be set by the Host when both CCE and INIT are set to '1'" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
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bitfld.long 0x00 4. "CSR,Clock Stop Request not supported by M_TTCAN use CTL.STOP_REQ at the group level instead" "0: No clock stop is requested,1: Clock stop requested"
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bitfld.long 0x00 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_TTCAN may be set in power down by stopping"
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bitfld.long 0x00 2. "ASM,Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to '1'" "0: Normal CAN operation,1: Restricted Operation Mode active"
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bitfld.long 0x00 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected,1: The CPU has write access to the protected"
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bitfld.long 0x00 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started"
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group.long ($2+0x1C)++0x03
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line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register"
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hexmask.long.byte 0x00 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width 0x00-0x7F Valid values are 0 to 127"
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hexmask.long.word 0x00 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler 0x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time quanta"
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hexmask.long.byte 0x00 8.--15. 1. "NTSEG1,Nominal Time segment before sample point 0x01-0xFF Valid values are 1 to 255"
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hexmask.long.byte 0x00 0.--6. 1. "NTSEG2,Nominal Time segment after sample point 0x01-0x7F Valid values are 1 to 127"
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group.long ($2+0x20)++0x03
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line.long 0x00 "TSCC,Timestamp Counter Configuration"
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bitfld.long 0x00 16.--19. "TCP,Timestamp Counter Prescaler (still used for TOCC) 0x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1...16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--1. "TSS,Timestamp Select should always be set to external timestamp counter" "0: Timestamp counter value always,1: Timestamp counter value incremented according..,2: External timestamp counter value used,3: Same as '00'"
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group.long ($2+0x24)++0x03
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line.long 0x00 "TSCV,Timestamp Counter Value"
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hexmask.long.word 0x00 0.--15. 1. "TSC,Timestamp Counter not used for M_TTCAN The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx)"
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group.long ($2+0x28)++0x03
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line.long 0x00 "TOCC,Timeout Counter Configuration"
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hexmask.long.word 0x00 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter)"
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bitfld.long 0x00 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
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bitfld.long 0x00 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled"
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group.long ($2+0x2C)++0x03
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line.long 0x00 "TOCV,Timeout Counter Value"
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hexmask.long.word 0x00 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the configuration of TSCC.TCP"
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rgroup.long ($2+0x40)++0x03
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line.long 0x00 "ECR,Error Counter Register"
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hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented"
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bitfld.long 0x00 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error,1: The Receive Error Counter has reached the error"
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hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127"
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hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255"
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rgroup.long ($2+0x44)++0x03
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line.long 0x00 "PSR,Protocol Status Register"
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hexmask.long.byte 0x00 16.--22. 1. "TDCV,Transmitter Delay Compensation Value 0x00-0x7F Position of the secondary sample point defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO"
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bitfld.long 0x00 14. "PXE,Protocol Exception Event Reset on Read" "0: No protocol exception event occurred since last,1: Protocol exception event occurred"
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bitfld.long 0x00 13. "RFDF,Received a CAN FD Message Reset on Read This bit is set independent of acceptance filtering" "0: Since this bit was reset by the CPU no CAN FD,1: Message in CAN FD format with FDF flag set has"
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bitfld.long 0x00 12. "RBRS,BRS flag of last received CAN FD Message Reset on Read This bit is set together with RFDF independent of acceptance filtering" "0: Last received CAN FD message did not have its,1: Last received CAN FD message had its BRS flag.."
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bitfld.long 0x00 11. "RESI,ESI flag of last received CAN FD Message Reset on Read This bit is set together with RFDF independent of acceptance filtering" "0: Last received CAN FD message did not have its,1: Last received CAN FD message had its ESI flag.."
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bitfld.long 0x00 8.--10. "DLEC,Data Phase Last Error Code Set on Read Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state"
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bitfld.long 0x00 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning,1: At least one of error counter has reached the"
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bitfld.long 0x00 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state,1: The M_CAN is in the Error_Passive state"
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bitfld.long 0x00 3.--4. "ACT,Activity Monitors the module's CAN communication state" "0: Synchronizing - node is synchronizing on CAN,1: Idle - node is neither receiver nor transmitter,2: Receiver - node is operating as receiver,3: Transmitter - node is operating as transmitter"
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bitfld.long 0x00 0.--2. "LEC,Last Error Code Set on Read0 The LEC indicates the type of the last error to occur on the CAN bus" "0: No Error,1: Stuff Error,2: Form Error,3: AckError,4: Bit1Error,5: Bit0Error,6: CRCError,7: NoChange"
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group.long ($2+0x48)++0x03
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line.long 0x00 "TDCR,Transmitter Delay Compensation Register"
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hexmask.long.byte 0x00 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset 0x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to m_ttcan_rx and the secondary sample point"
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hexmask.long.byte 0x00 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length 0x00-0x7F Defines the minimum value for the SSP position dominant edges on m_ttcan_rx that would result in an earlier SSP position are ignored for transmitter delay measurement"
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group.long ($2+0x50)++0x03
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line.long 0x00 "IR,Interrupt Register"
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bitfld.long 0x00 29. "ARA,N/A" "0,1"
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bitfld.long 0x00 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC"
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bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected"
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bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
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bitfld.long 0x00 25. "BO_,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
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bitfld.long 0x00 24. "EW_,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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bitfld.long 0x00 23. "EP_,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
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bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred"
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bitfld.long 0x00 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected" "0: No bit error detected when reading from Message,1: Bit error detected uncorrected (e.g. parity.."
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bitfld.long 0x00 20. "BEC,M_TTCAN reports correctable ECC fault to the generic fault structure this bit always reads as 0" "0: No bit error detected when reading from Message,1: Bit error detected and corrected (e.g. ECC)"
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bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx"
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bitfld.long 0x00 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
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bitfld.long 0x00 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler - has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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bitfld.long 0x00 15. "TEFL_,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write"
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bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
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bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark"
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bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
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bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
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bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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bitfld.long 0x00 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
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bitfld.long 0x00 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
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bitfld.long 0x00 7. "RF1L_,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write"
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bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
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bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark"
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bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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bitfld.long 0x00 3. "RF0L_,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write"
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bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark"
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bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
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group.long ($2+0x54)++0x03
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line.long 0x00 "IE,Interrupt Enable"
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bitfld.long 0x00 29. "ARAE,N/A" "0,1"
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bitfld.long 0x00 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
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bitfld.long 0x00 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
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bitfld.long 0x00 26. "WDIE,Watchdog Interrupt Enable" "0,1"
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bitfld.long 0x00 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
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bitfld.long 0x00 24. "EWE,Warning Status Interrupt Enable" "0,1"
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bitfld.long 0x00 23. "EPE,Error Passive Interrupt Enable" "0,1"
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bitfld.long 0x00 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
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bitfld.long 0x00 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
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bitfld.long 0x00 20. "BECE,Bit Error Corrected Interrupt Enable (not used in M_TTCAN)" "0,1"
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bitfld.long 0x00 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
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bitfld.long 0x00 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
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bitfld.long 0x00 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
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bitfld.long 0x00 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
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bitfld.long 0x00 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
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bitfld.long 0x00 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
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bitfld.long 0x00 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
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bitfld.long 0x00 12. "TEFNE,Tx Event FIDO New Entry Interrupt Enable" "0,1"
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bitfld.long 0x00 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
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bitfld.long 0x00 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
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bitfld.long 0x00 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
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bitfld.long 0x00 8. "HPME,High Priority Message Interrupt Enable" "0,1"
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bitfld.long 0x00 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1"
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bitfld.long 0x00 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
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bitfld.long 0x00 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
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bitfld.long 0x00 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
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bitfld.long 0x00 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
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bitfld.long 0x00 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
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bitfld.long 0x00 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
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bitfld.long 0x00 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
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group.long ($2+0x58)++0x03
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line.long 0x00 "ILS,Interrupt Line Select"
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bitfld.long 0x00 29. "ARAL,N/A" "0,1"
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bitfld.long 0x00 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
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bitfld.long 0x00 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
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bitfld.long 0x00 26. "WDIL,Watchdog Interrupt Line" "0,1"
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bitfld.long 0x00 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
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bitfld.long 0x00 24. "EWL,Warning Status Interrupt Line" "0,1"
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bitfld.long 0x00 23. "EPL,Error Passive Interrupt Line" "0,1"
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bitfld.long 0x00 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
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bitfld.long 0x00 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
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bitfld.long 0x00 20. "BECL,Bit Error Corrected Interrupt Line (not used in M_TTCAN)" "0,1"
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bitfld.long 0x00 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
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bitfld.long 0x00 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
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bitfld.long 0x00 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
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bitfld.long 0x00 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
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bitfld.long 0x00 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
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bitfld.long 0x00 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
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bitfld.long 0x00 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
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bitfld.long 0x00 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
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bitfld.long 0x00 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
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bitfld.long 0x00 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
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bitfld.long 0x00 9. "TCL,Transmission Completed Interrupt Line" "0,1"
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bitfld.long 0x00 8. "HPML,High Priority Message Interrupt Line" "0,1"
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bitfld.long 0x00 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
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bitfld.long 0x00 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
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bitfld.long 0x00 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
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bitfld.long 0x00 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
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bitfld.long 0x00 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
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bitfld.long 0x00 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
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bitfld.long 0x00 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
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|
bitfld.long 0x00 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
|
|
group.long ($2+0x5C)++0x03
|
|
line.long 0x00 "ILE,Interrupt Line Enable"
|
|
bitfld.long 0x00 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_ttcan_int1 disabled,1: Interrupt line m_ttcan_int1 enabled"
|
|
bitfld.long 0x00 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_ttcan_int0 disabled,1: Interrupt line m_ttcan_int0 enabled"
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated" "0: Accept in Rx,1: Accept in Rx,2: Reject,3: Reject"
|
|
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated" "0: Accept in Rx,1: Accept in Rx,2: Reject,3: Reject"
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|
newline
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bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard.."
|
|
bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended.."
|
|
group.long ($2+0x84)++0x03
|
|
line.long 0x00 "SIDFC,Standard ID Filter Configuration"
|
|
abitfld.long 0x00 16.--23. "LSS,List Size Standard" "0x00=0: No standard Message ID filter 1-128=..,0x80=128: Values greater than 128 are.."
|
|
hexmask.long.word 0x00 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see Figure 2)"
|
|
group.long ($2+0x88)++0x03
|
|
line.long 0x00 "XIDFC,Extended ID Filter Configuration"
|
|
abitfld.long 0x00 16.--22. "LSE,List Size Extended" "0x00=0: No extended Message ID filter 1-64=..,0x40=64: Values greater than 64 are interpreted.."
|
|
hexmask.long.word 0x00 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see Figure 2)"
|
|
group.long ($2+0x90)++0x03
|
|
line.long 0x00 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame"
|
|
rgroup.long ($2+0x94)++0x03
|
|
line.long 0x00 "HPMS,High Priority Message Status"
|
|
bitfld.long 0x00 15. "FLST,Filter List Indicates the filter list of the matching filter element" "0: Standard Filter List,1: Extended Filter List"
|
|
hexmask.long.byte 0x00 8.--14. 1. "FIDX,Filter Index Index of matching filter element"
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|
newline
|
|
bitfld.long 0x00 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x00 0.--5. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long ($2+0x98)++0x03
|
|
line.long 0x00 "NDAT1,New Data 1"
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|
abitfld.long 0x00 0.--31. "ND,New Data The register holds the New Data flags of Rx Buffers 0 to 31" "0x00000000=0: Rx Buffer not updated,0x00000001=1: Rx Buffer updated from new message"
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|
group.long ($2+0x9C)++0x03
|
|
line.long 0x00 "NDAT2,New Data 2"
|
|
abitfld.long 0x00 0.--31. "ND,New Data The register holds the New Data flags of Rx Buffers 32 to 63" "0x00000000=0: Rx Buffer not updated,0x00000001=1: Rx Buffer updated from new message"
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|
group.long ($2+0xA0)++0x03
|
|
line.long 0x00 "RXF0C,Rx FIFO 0 Configuration"
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|
bitfld.long 0x00 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2)" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
|
|
abitfld.long 0x00 24.--30. "F0WM,Rx FIFO 0 Watermark" "0x00=0: Watermark interrupt disabled 1-64= Level..,0x40=64: Watermark interrupt disabled"
|
|
newline
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abitfld.long 0x00 16.--22. "F0S,Rx FIFO 0 Size" "0x00=0: No Rx FIFO 0 1-64= Number of Rx FIFO 0..,0x40=64: Values greater than 64 are interpreted.."
|
|
hexmask.long.word 0x00 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see Figure 2)"
|
|
rgroup.long ($2+0xA4)++0x03
|
|
line.long 0x00 "RXF0S,Rx FIFO 0 Status"
|
|
bitfld.long 0x00 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag IR.RF0L" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write"
|
|
bitfld.long 0x00 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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|
newline
|
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bitfld.long 0x00 16.--21. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 8.--13. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
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hexmask.long.byte 0x00 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64"
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|
group.long ($2+0xA8)++0x03
|
|
line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge"
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|
bitfld.long 0x00 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xAC)++0x03
|
|
line.long 0x00 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x00 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address)"
|
|
group.long ($2+0xB0)++0x03
|
|
line.long 0x00 "RXF1C,Rx FIFO 1 Configuration"
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|
bitfld.long 0x00 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2)" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
|
|
abitfld.long 0x00 24.--30. "F1WM,Rx FIFO 1 Watermark" "0x00=0: Watermark interrupt disabled 1-64= Level..,0x40=64: Watermark interrupt disabled"
|
|
newline
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abitfld.long 0x00 16.--22. "F1S,Rx FIFO 1 Size" "0x00=0: No Rx FIFO 1 1-64= Number of Rx FIFO 1..,0x40=64: Values greater than 64 are interpreted.."
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|
hexmask.long.word 0x00 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see Figure 2)"
|
|
rgroup.long ($2+0xB4)++0x03
|
|
line.long 0x00 "RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x00 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is.."
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|
bitfld.long 0x00 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag IR.RF1L" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write"
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|
newline
|
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bitfld.long 0x00 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
bitfld.long 0x00 16.--21. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 8.--13. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
hexmask.long.byte 0x00 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64"
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|
group.long ($2+0xB8)++0x03
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line.long 0x00 "RXF1A,Rx FIFO 1 Acknowledge"
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|
bitfld.long 0x00 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long ($2+0xBC)++0x03
|
|
line.long 0x00 "RXESC,Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x00 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
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bitfld.long 0x00 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
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newline
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bitfld.long 0x00 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
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|
group.long ($2+0xC0)++0x03
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|
line.long 0x00 "TXBC,Tx Buffer Configuration"
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|
bitfld.long 0x00 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
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|
bitfld.long 0x00 24.--29. "TFQS,Transmit FIFO/Queue Size" "0: No Tx FIFO/Queue 1-32= Number of Tx Buffers..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Values greater than 32 are interpreted as 32,?..."
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newline
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bitfld.long 0x00 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0: No Dedicated Tx Buffers 1-32= Number of,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Values greater than 32 are interpreted as 32,?..."
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|
hexmask.long.word 0x00 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Figure 2)"
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rgroup.long ($2+0xC4)++0x03
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line.long 0x00 "TXFQS,Tx FIFO/Queue Status"
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bitfld.long 0x00 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
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bitfld.long 0x00 16.--20. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 8.--12. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--5. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from TFGI range 0 to 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long ($2+0xC8)++0x03
|
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line.long 0x00 "TXESC,Tx Buffer Element Size Configuration"
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bitfld.long 0x00 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
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rgroup.long ($2+0xCC)++0x03
|
|
line.long 0x00 "TXBRP,Tx Buffer Request Pending"
|
|
abitfld.long 0x00 0.--31. "TRP,Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit" "0x00000000=0: No transmission request pending,0x00000001=1: Transmission request pending"
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|
group.long ($2+0xD0)++0x03
|
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line.long 0x00 "TXBAR,Tx Buffer Add Request"
|
|
abitfld.long 0x00 0.--31. "AR,Add Request Each Tx Buffer has its own Add Request bit" "0x00000000=0: No transmission request added,0x00000001=1: Transmission requested added"
|
|
group.long ($2+0xD4)++0x03
|
|
line.long 0x00 "TXBCR,Tx Buffer Cancellation Request"
|
|
abitfld.long 0x00 0.--31. "CR,Cancellation Request Each Tx Buffer has its own Cancellation Request bit" "0x00000000=0: No cancellation pending,0x00000001=1: Cancellation pending"
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|
rgroup.long ($2+0xD8)++0x03
|
|
line.long 0x00 "TXBTO,Tx Buffer Transmission Occurred"
|
|
abitfld.long 0x00 0.--31. "TO,Transmission Occurred Each Tx Buffer has its own Transmission Occurred bit" "0x00000000=0: No transmission occurred,0x00000001=1: Transmission occurred"
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|
rgroup.long ($2+0xDC)++0x03
|
|
line.long 0x00 "TXBCF,Tx Buffer Cancellation Finished"
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abitfld.long 0x00 0.--31. "CF,Cancellation Finished Each Tx Buffer has its own Cancellation Finished bit" "0x00000000=0: No transmit buffer cancellation,0x00000001=1: Transmit buffer cancellation.."
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|
group.long ($2+0xE0)++0x03
|
|
line.long 0x00 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
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|
abitfld.long 0x00 0.--31. "TIE,Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit" "0x00000000=0: Transmission interrupt disabled,0x00000001=1: Transmission interrupt enable"
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group.long ($2+0xE4)++0x03
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|
line.long 0x00 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
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abitfld.long 0x00 0.--31. "CFIE,Cancellation Finished Interrupt Enable Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit" "0x00000000=0: Cancellation finished interrupt..,0x00000001=1: Cancellation finished interrupt.."
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|
group.long ($2+0xF0)++0x03
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|
line.long 0x00 "TXEFC,Tx Event FIFO Configuration"
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bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0: Watermark interrupt disabled 1-32= Level for Tx,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Watermark interrupt disabled,?..."
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bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0: Tx Event FIFO disabled 1-32= Number of Tx Event,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Values greater than 32 are interpreted as 32..,?..."
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newline
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hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see Figure 2)"
|
|
rgroup.long ($2+0xF4)++0x03
|
|
line.long 0x00 "TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x00 25. "TEFL,Tx Event FIFO Element Lost This bit is a copy of interrupt flag IR.TEFL" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write"
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|
bitfld.long 0x00 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
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|
newline
|
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bitfld.long 0x00 16.--20. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 8.--12. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x00 0.--5. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xF8)++0x03
|
|
line.long 0x00 "TXEFA,Tx Event FIFO Acknowledge"
|
|
bitfld.long 0x00 0.--4. "EFAI,Event FIFO Acknowledge Index After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "TTTMC,TT Trigger Memory Configuration"
|
|
abitfld.long 0x00 16.--22. "TME,Trigger Memory Elements" "0x00=0: No Trigger Memory 1-64= Number of..,0x40=64: Values greater than 64 are interpreted.."
|
|
hexmask.long.word 0x00 2.--15. 1. "TMSA,Trigger Memory Start Address Start address of Trigger Memory in Message RAM (32-bit word address see Figure 2)"
|
|
group.long ($2+0x104)++0x03
|
|
line.long 0x00 "TTRMC,TT Reference Message Configuration"
|
|
bitfld.long 0x00 31. "RMPS,Reference Message Payload Select Ignored in case of time slaves" "0: Message Marker MM Event FIFO Control EFC Data,1: bytes 2-8 Level 0"
|
|
bitfld.long 0x00 30. "XTD,Extended Identifier" "0: 11-bit standard identifier,1: 29-bit extended identifier"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. "RID,Reference Identifier Identifier transmitted with reference message and used for reference message filtering"
|
|
group.long ($2+0x108)++0x03
|
|
line.long 0x00 "TTOCF,TT Operation Configuration"
|
|
bitfld.long 0x00 26. "EVTP,Event Trigger Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x00 25. "ECC,Enable Clock Calibration" "0: Automatic clock calibration in TTCAN Level 0 2,1: Automatic clock calibration in TTCAN Level 0 2"
|
|
newline
|
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bitfld.long 0x00 24. "EGTF,Enable Global Time Filtering" "0: Global time filtering in TTCAN Level 0 2 is,1: Global time filtering in TTCAN Level 0 2 is"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AWL,Application Watchdog Limit The application watchdog can be disabled by programming AWL to 0x00"
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|
newline
|
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bitfld.long 0x00 15. "EECS,Enable External Clock Synchronization If enabled TUR configuration (TURCF.NCL only) may be updated during TTCAN operation" "0: External clock synchronization in TTCAN Level 0,1: External clock synchronization in TTCAN Level 0"
|
|
hexmask.long.byte 0x00 8.--14. 1. "IRTO,Initial Reference Trigger Offset 0x00-7F Positive offset range from 0 to 127"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "LDSDL,LD of Synchronization Deviation Limit The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL = 2(LDSDL + 5)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "TM,Time Master" "0: Time Master function disabled,1: Potential Time Master"
|
|
newline
|
|
bitfld.long 0x00 3. "GEN,Gap Enable" "0: Strictly time-triggered operation,1: External event-synchronized time-triggered"
|
|
bitfld.long 0x00 0.--1. "OM,Operation Mode" "0: Event-driven CAN communication default,1: TTCAN level 1,2: TTCAN level 2,3: TTCAN level 0"
|
|
group.long ($2+0x10C)++0x03
|
|
line.long 0x00 "TTMLM,TT Matrix Limits"
|
|
hexmask.long.word 0x00 16.--27. 1. "ENTT,Expected Number of Tx Triggers 0x000-FFF Expected number of Tx Triggers in one Matrix Cycle"
|
|
bitfld.long 0x00 8.--11. "TXEW,Tx Enable Window 0x0-F Length of Tx enable window 1-16 NTU cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 6.--7. "CSS,N/A" "0,1,2,3"
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|
bitfld.long 0x00 0.--5. "CCM,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long ($2+0x110)++0x03
|
|
line.long 0x00 "TURCF,TUR Configuration"
|
|
bitfld.long 0x00 31. "ELT,Enable Local Time" "0: Local time is stopped default,1: Local time is enabled"
|
|
hexmask.long.word 0x00 16.--29. 1. "DC,Denominator Configuration 0x0000 Illegal value 0x0001-3FFF Denominator Configuration"
|
|
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|
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hexmask.long.word 0x00 0.--15. 1. "NCL,Numerator Configuration Low Write access to the TUR Numerator Configuration Low is only possible during configuration with TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set"
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|
group.long ($2+0x114)++0x03
|
|
line.long 0x00 "TTOCN,TT Operation Control"
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|
rbitfld.long 0x00 15. "LCKC,TT Operation Control Register Locked Set by a write access to register TTOCN" "0: Write access to TTOCN enabled,1: Write access to TTOCN locked"
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bitfld.long 0x00 13. "ESCN,External Synchronization Control If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising edge at pin m_ttcan_evt (see Section 4.11)" "0: External synchronization disabled,1: External synchronization enabled"
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bitfld.long 0x00 12. "NIG,Next is Gap This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for external event-synchronized time-triggered operation (TTOCF.GEN = '1')" "0: No action reset by reception of any reference,1: Transmit next reference message with.."
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|
bitfld.long 0x00 11. "TMG,Time Mark Gap" "0: Reset by each reference message,1: Next reference message started when Register"
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|
newline
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bitfld.long 0x00 10. "FGP,Finish Gap Set by the CPU reset by each reference message" "0: No reference message requested,1: Application requested start of reference.."
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|
bitfld.long 0x00 9. "GCS,Gap Control Select" "0: Gap control independent from m_ttcan_evt,1: Gap control by input pin m_ttcan_evt"
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newline
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bitfld.long 0x00 8. "TTIE,Trigger Time Mark Interrupt Pulse Enable External time mark events are configured by trigger memory element TMEX (see Section 2.4.7)" "0: Trigger Time Mark Interrupt output m_ttcan_tmp,1: Trigger Time Mark Interrupt output m_ttcan_tmp"
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bitfld.long 0x00 6.--7. "TMC,Register Time Mark Compare" "0: No Register Time Mark Interrupt generated,1: Register Time Mark Interrupt if Time Mark =,2: Register Time Mark Interrupt if Time Mark =,3: Register Time Mark Interrupt if Time Mark ="
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newline
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bitfld.long 0x00 5. "RTIE,Register Time Mark Interrupt Pulse Enable Register time mark interrupts are configured by register TTTMK" "0: Register Time Mark Interrupt output m_ttcan_rtp,1: Register Time Mark Interrupt output m_ttcan_rtp"
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bitfld.long 0x00 3.--4. "SWS,Stop Watch Source" "0: Stop Watch disabled,1: Actual value of cycle time is copied to..,2: Actual value of local time is copied to..,3: Actual value of global time is copied to.."
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bitfld.long 0x00 2. "SWP,Stop Watch Polarity" "0: Rising edge trigger,1: Falling edge trigger"
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bitfld.long 0x00 1. "ECS,External Clock Synchronization Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master" "0,1"
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bitfld.long 0x00 0. "SGT,Set Global time Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master" "0,1"
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group.long ($2+0x118)++0x03
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line.long 0x00 "TTGTP,TT Global Time Preset"
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|
hexmask.long.word 0x00 16.--31. 1. "CTP,Cycle Time Target Phase CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11)"
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hexmask.long.word 0x00 0.--15. 1. "TP,N/A"
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group.long ($2+0x11C)++0x03
|
|
line.long 0x00 "TTTMK,TT Time Mark"
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rbitfld.long 0x00 31. "LCKM,TT Time Mark Register Locked Always set by a write access to registers TTOCN" "0: Write access to TTTMK enabled,1: Write access to TTTMK locked"
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|
hexmask.long.byte 0x00 16.--22. 1. "TICC,Time Mark Cycle Code Cycle count for which the time mark is valid"
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hexmask.long.word 0x00 0.--15. 1. "TM_,Time Mark 0x0000-FFFF Time Mark"
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|
group.long ($2+0x120)++0x03
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line.long 0x00 "TTIR,TT Interrupt Register"
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|
bitfld.long 0x00 18. "CER,Configuration Error Trigger out of order" "0: No error found in trigger list,1: Error found in trigger list"
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bitfld.long 0x00 17. "AW,Application Watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time"
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bitfld.long 0x00 16. "WT,Watch Trigger" "0: cycle time 0xFF00),1: Missing reference message (Level"
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bitfld.long 0x00 15. "IWT,Initialization Watch Trigger The initialization is restarted by resetting IWT" "0: No missing reference message during system..,1: No system startup due to missing reference.."
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bitfld.long 0x00 14. "ELC,Error Level Changed Not set when error level changed during initialization" "0: No change in error level,1: Error level changed"
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bitfld.long 0x00 13. "SE2,Scheduling Error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred"
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bitfld.long 0x00 12. "SE1,Scheduling Error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred"
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bitfld.long 0x00 11. "TXO,Tx Count Overflow" "0: Number of Tx Trigger as expected,1: More Tx trigger than expected in one matrix.."
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bitfld.long 0x00 10. "TXU,Tx Count Underflow" "0: Number of Tx Trigger as expected,1: Less Tx trigger than expected in one matrix.."
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bitfld.long 0x00 9. "GTE,Global Time Error Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL TTCAN Level 0 2 only" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit"
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newline
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bitfld.long 0x00 8. "GTD,Global Time Discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time"
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|
bitfld.long 0x00 7. "GTW,Global Time Wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred"
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bitfld.long 0x00 6. "SWE,Stop Watch Event" "0: No rising/falling edge at stop watch trigger..,1: Rising/falling edge at stop watch trigger pin"
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bitfld.long 0x00 5. "TTMI,Trigger Time Mark Event Internal Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7)" "0: cycle time TTOCF.IRTO * 0x200),1: Time mark reached (Level"
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bitfld.long 0x00 4. "RTMI,Register Time Mark Interrupt Set when time referenced by TTOCN.TMC (cycle local or global) equals TTTMK.TM independent of the synchronization state" "0: Time mark not reached,1: Time mark reached"
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bitfld.long 0x00 3. "SOG,Start of Gap" "0: No reference message seen with Next_is_Gap..,1: Reference message with Next_is_Gap bit set"
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bitfld.long 0x00 2. "CSM_,Change of Synchronization Mode" "0: No change in master to slave relation or,1: Master to slave relation or schedule"
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|
bitfld.long 0x00 1. "SMC,Start of Matrix Cycle" "0: No Matrix Cycle started since bit has been..,1: Matrix Cycle started"
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newline
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bitfld.long 0x00 0. "SBC,Start of Basic Cycle" "0: No Basic Cycle started since bit has been reset,1: Basic Cycle started"
|
|
group.long ($2+0x124)++0x03
|
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line.long 0x00 "TTIE,TT Interrupt Enable"
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|
bitfld.long 0x00 18. "CERE,Configuration Error Interrupt Enable" "0,1"
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|
bitfld.long 0x00 17. "AWE_,Application Watchdog Interrupt Enable" "0,1"
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newline
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bitfld.long 0x00 16. "WTE,Watch Trigger Interrupt Enable" "0,1"
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|
bitfld.long 0x00 15. "IWTE,Initialization Watch Trigger Interrupt Enable" "0,1"
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newline
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bitfld.long 0x00 14. "ELCE,Change Error Level Interrupt Enable" "0,1"
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|
bitfld.long 0x00 13. "SE2E,Scheduling Error 2 Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x00 12. "SE1E,Scheduling Error 1 Interrupt Enable" "0,1"
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|
bitfld.long 0x00 11. "TXOE,Tx Count Overflow Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x00 10. "TXUE,Tx Count Underflow Interrupt Enable" "0,1"
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|
bitfld.long 0x00 9. "GTEE,Global Time Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x00 8. "GTDE,Global Time Discontinuity Interrupt Enable" "0,1"
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|
bitfld.long 0x00 7. "GTWE,Global Time Wrap Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x00 6. "SWEE,Stop Watch Event Interrupt Enable" "0,1"
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bitfld.long 0x00 5. "TTMIE,Trigger Time Mark Event Internal Enable" "0,1"
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newline
|
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bitfld.long 0x00 4. "RTMIE,Register Time Mark Interrupt Enable" "0,1"
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|
bitfld.long 0x00 3. "SOGE,Start of Gap Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x00 2. "CSME,Change of Synchronization Mode Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 1. "SMCE,Start of Matrix Cycle Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x00 0. "SBCE,Start of Basic Cycle Interrupt Enable" "0,1"
|
|
group.long ($2+0x128)++0x03
|
|
line.long 0x00 "TTILS,TT Interrupt Line Select"
|
|
bitfld.long 0x00 18. "CERL,Configuration Error Interrupt Line" "0,1"
|
|
bitfld.long 0x00 17. "AWL_,Application Watchdog Interrupt Line" "0,1"
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newline
|
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bitfld.long 0x00 16. "WTL,Watch Trigger Interrupt Line" "0,1"
|
|
bitfld.long 0x00 15. "IWTL,Initialization Watch Trigger Interrupt Line" "0,1"
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|
newline
|
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bitfld.long 0x00 14. "ELCL,Change Error Level Interrupt Line" "0,1"
|
|
bitfld.long 0x00 13. "SE2L,Scheduling Error 2 Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x00 12. "SE1L,Scheduling Error 1 Interrupt Line" "0,1"
|
|
bitfld.long 0x00 11. "TXOL,Tx Count Overflow Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "TXUL,Tx Count Underflow Interrupt Line" "0,1"
|
|
bitfld.long 0x00 9. "GTEL,Global Time Error Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "GTDL,Global Time Discontinuity Interrupt Line" "0,1"
|
|
bitfld.long 0x00 7. "GTWL,Global Time Wrap Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SWEL,Stop Watch Event Interrupt Line" "0,1"
|
|
bitfld.long 0x00 5. "TTMIL,Trigger Time Mark Event Internal Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RTMIL,Register Time Mark Interrupt Line" "0,1"
|
|
bitfld.long 0x00 3. "SOGL,Start of Gap Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CSML,Change of Synchronization Mode Interrupt Line" "0,1"
|
|
bitfld.long 0x00 1. "SMCL,Start of Matrix Cycle Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SBCL,Start of Basic Cycle Interrupt Line" "0,1"
|
|
rgroup.long ($2+0x12C)++0x03
|
|
line.long 0x00 "TTOST,TT Operation Status"
|
|
bitfld.long 0x00 31. "SPL,Schedule Phase Lock The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1')" "0: Phase outside range,1: Phase inside range"
|
|
bitfld.long 0x00 30. "WECS,Wait for External Clock Synchronization" "0: No external clock synchronization pending,1: Node waits for external clock synchronization.."
|
|
newline
|
|
bitfld.long 0x00 29. "AWE,Application Watchdog Event The application watchdog is served by reading TTOST" "0: Application Watchdog served in time,1: Failed to serve Application Watchdog in time"
|
|
bitfld.long 0x00 28. "WFE,Wait for Event" "0: No Gap announced reset by a reference message,1: Reference message with Next_is_Gap = '1'.."
|
|
newline
|
|
bitfld.long 0x00 27. "GSI,Gap Started Indicator" "0: No Gap in schedule reset by each reference,1: Gap time after Basic Cycle has started"
|
|
bitfld.long 0x00 24.--26. "TMP,Time Master Priority 0x0-7 Priority of actual Time Master" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 23. "GFI,Gap Finished Indicator Set when the CPU writes TTOCN.FGP or by a time mark interrupt if TMG = '1' or via input pin m_ttcan_evt if TTOCN.GCS = '1'" "0: Reset at the end of each reference message,1: Gap finished by M_TTCAN"
|
|
bitfld.long 0x00 22. "WGTD,Wait for Global Time Discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RTO,Reference Trigger Offset The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F)"
|
|
bitfld.long 0x00 7. "QCS,Quality of Clock Speed Only relevant in TTCAN Level 0 and Level 2 otherwise fixed to '1'" "0: Local clock speed not synchronized to Time,1: Synchronization Deviation <= SDL"
|
|
newline
|
|
bitfld.long 0x00 6. "QGTP,Quality of Global Time Phase Only relevant in TTCAN Level 0 and Level 2 otherwise fixed to '0'" "0: Global time not valid,1: Global time in phase with Time Master"
|
|
bitfld.long 0x00 4.--5. "SYS,Synchronization State" "0: Out of Synchronization,1: Synchronizing to TTCAN communication,2: Schedule suspended by Gap (In_Gap),3: Synchronized to schedule (In_Schedule)"
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|
newline
|
|
bitfld.long 0x00 2.--3. "MS,Master State" "0: Master_Off no master properties relevant,1: Operating as Time Slave,2: Operating as Backup Time Master,3: Operating as current Time Master"
|
|
bitfld.long 0x00 0.--1. "EL,Error Level" "0: No Error,1: Warning,2: Error,3: Severe Error"
|
|
rgroup.long ($2+0x130)++0x03
|
|
line.long 0x00 "TURNA,TUR Numerator Actual"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NAV,N/A"
|
|
rgroup.long ($2+0x134)++0x03
|
|
line.long 0x00 "TTLGT,TT Local & Global Time"
|
|
hexmask.long.word 0x00 16.--31. 1. "GT,Global Time Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5)"
|
|
hexmask.long.word 0x00 0.--15. 1. "LT,Local Time Non-fractional part of local time incremented once each local NTU (see Section 4.5)"
|
|
rgroup.long ($2+0x138)++0x03
|
|
line.long 0x00 "TTCTC,TT Cycle Time & Count"
|
|
bitfld.long 0x00 16.--21. "CC,Cycle Count 0x00-3F Number of actual Basic Cycle in the System Matrix" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "CT,Cycle Time Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5)"
|
|
rgroup.long ($2+0x13C)++0x03
|
|
line.long 0x00 "TTCPT,TT Capture Time"
|
|
hexmask.long.word 0x00 16.--31. 1. "SWV,Stop Watch Value On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt when TTOCN.SWS is != '00' and TTIR.SWE is '0' the actual time value as selected by TTOCN.SWS (cycle local global) is copied to SWV and.."
|
|
bitfld.long 0x00 0.--5. "CCV,Cycle Count Value Cycle count value captured together with SWV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long ($2+0x140)++0x03
|
|
line.long 0x00 "TTCSM,TT Cycle Sync Mark"
|
|
hexmask.long.word 0x00 0.--15. 1. "CSM,Cycle Sync Mark The Cycle Sync Mark is measured"
|
|
tree.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "CPUSS (CPU Subsystem)"
|
|
base ad:0x40200000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IDENTITY,Identity"
|
|
bitfld.long 0x00 8.--11. "MS,This field specifies the bus master identifier of the transfer that reads the register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 4.--7. "PC,This field specifies the protection context of the transfer that reads the register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. "NS,This field specifies the security setting ('0': secure mode '1': non-secure mode) of the transfer that reads the register" "0,1"
|
|
bitfld.long 0x00 0. "P,This field specifies the privileged setting ('0': user mode '1': privileged mode) of the transfer that reads the register" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CM7_0_STATUS,CM7 0 status"
|
|
bitfld.long 0x00 12. "TCMC_AHB_MS,Ongoing AHB transaction" "0,1"
|
|
bitfld.long 0x00 11. "TCMC_EXT_MS_3,Outstanding transactions from external AXI master 3" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "TCMC_EXT_MS_2_TO_0,Outstanding transactions from external AXI masters 2 to 0" "0,1"
|
|
bitfld.long 0x00 9. "TCMC_CM7_1_MS,Outstanding transactions from CM7 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PWR_DONE,After a PWR_MODE change this flag indicates if the new power mode has taken effect or not" "0,1"
|
|
bitfld.long 0x00 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FAST_0_CLOCK_CTL,Fast 0 clock control"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT_DIV,Integer division by (1+INT_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC_DIV,Fractional division by (FRAC_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CM7_0_CTL,CM7 0 control"
|
|
bitfld.long 0x00 31. "IDC_MASK,CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt" "0,1"
|
|
bitfld.long 0x00 28. "IXC_MASK,CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt" "0,1"
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|
newline
|
|
bitfld.long 0x00 27. "UFC_MASK,CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt" "0,1"
|
|
bitfld.long 0x00 26. "OFC_MASK,CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt" "0,1"
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|
newline
|
|
bitfld.long 0x00 25. "DZC_MASK,CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt" "0,1"
|
|
bitfld.long 0x00 24. "IOC_MASK,CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt" "0,1"
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|
newline
|
|
bitfld.long 0x00 23. "TCMC_EN,CM7 TCMC access control: '0': Disable access to the CM7 I/D-TCM slave port (AHBS)" "0,1"
|
|
bitfld.long 0x00 22. "DTCM_READ_WS,DTCM read wait states (writes have no wait states)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "DTCM_ECC_INJ_EN,DTCM ECC error injection enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 20. "DTCM_ECC_EN,DTCM ECC enable: '0': Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "ITCM_ECC_CHECK_DIS,Disable ECC checking and thus fault reports" "0,1"
|
|
bitfld.long 0x00 18. "ITCM_READ_WS,ITCM read wait states (writes have no wait states)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "ITCM_ECC_INJ_EN,ITCM ECC error injection enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 16. "ITCM_ECC_EN,ITCM ECC enable: '0': Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "INIT_RMW_EN,TCM read-modify-write enable initialization after reset: Bit" "0: ITCM,1: DTCM,?..."
|
|
bitfld.long 0x00 8.--9. "INIT_TCM_EN,TCM enable initialization after reset: Bit" "0: ITCM,1: DTCM,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "CPU_WAIT,When this signal is '1' out of reset it forces the CPU into a quiescent state that delays its boot-up sequence and instruction execution until this signal is driven '0'" "0,1"
|
|
bitfld.long 0x00 0.--3. "PPB_LOCK,Write disable for specific CPU registers: Bit" "0: ITCMR register,1: DTCMR register,2: AHBPCR register,3: VTOR register,?..."
|
|
repeat 16. (increment 0 1) (increment 0 0x04)
|
|
rgroup.long ($2+0x100)++0x03
|
|
line.long 0x00 "CM7_0_INT_STATUS[$1],CM7 0 interrupt status $1"
|
|
bitfld.long 0x00 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM7_0 activated system interrupt index for CPU interrupt"
|
|
repeat.end
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CM7_0_VECTOR_TABLE_BASE,CM7 0 vector table base"
|
|
hexmask.long 0x00 7.--31. 1. "ADDR25,The default CM7 vector table base address is 0x0100:0000 (CM7 VTOR and reset exception handler address after reset)"
|
|
repeat 4. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x240)++0x03
|
|
line.long 0x00 "CM7_0_NMI_CTL[$1],CM7 0 NMI control $1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI"
|
|
repeat.end
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "UDB_PWR_CTL,UDB power control"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)"
|
|
bitfld.long 0x00 0.--1. "PWR_MODE,Set Power mode for UDBs" "0: See CM7_0_PWR_CTL,1: See CM7_0_PWR_CTL,2: See CM7_0_PWR_CTL,3: See CM7_0_PWR_CTL"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "UDB_PWR_DELAY_CTL,UDB power control"
|
|
hexmask.long.word 0x00 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "TRC_DBG_CLOCK_CTL,Trace and debug clock control"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT_DIV,Integer division by (1+INT_DIV)"
|
|
rgroup.long 0x404++0x03
|
|
line.long 0x00 "CM7_1_STATUS,CM7 1status"
|
|
bitfld.long 0x00 12. "TCMC_AHB_MS,Refer CM7_0_STATUS description" "0,1"
|
|
bitfld.long 0x00 11. "TCMC_EXT_MS_3,Refer CM7_0_STATUS description" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TCMC_EXT_MS_2_TO_0,Refer CM7_0_STATUS description" "0,1"
|
|
bitfld.long 0x00 8. "TCMC_CM7_0_MS,Outstanding transactions from CM7 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PWR_DONE,After a PWR_MODE change this flag indicates if the new power mode has taken effect or not" "0,1"
|
|
bitfld.long 0x00 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'" "0,1"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "FAST_1_CLOCK_CTL,Fast 1 clock control"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT_DIV,Refer FAST_0_CLOCK_CTL description"
|
|
bitfld.long 0x00 3.--7. "FRAC_DIV,Refer FAST_0_CLOCK_CTL description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "CM7_1_CTL,CM7 1 control"
|
|
bitfld.long 0x00 31. "IDC_MASK,Refer CM7_0_CTL description" "0,1"
|
|
bitfld.long 0x00 28. "IXC_MASK,Refer CM7_0_CTL description" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "UFC_MASK,Refer CM7_0_CTL description" "0,1"
|
|
bitfld.long 0x00 26. "OFC_MASK,Refer CM7_0_CTL description" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DZC_MASK,Refer CM7_0_CTL description" "0,1"
|
|
bitfld.long 0x00 24. "IOC_MASK,Refer CM7_0_CTL description" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "TCMC_EN,Refer CM7_0_CTL description" "0,1"
|
|
bitfld.long 0x00 22. "DTCM_READ_WS,Refer CM7_0_CTL description" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "DTCM_ECC_INJ_EN,Refer CM7_0_CTL description" "0,1"
|
|
bitfld.long 0x00 20. "DTCM_ECC_EN,Refer CM7_0_CTL description" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "ITCM_ECC_CHECK_DIS,Disable ECC checking and thus fault reports" "0,1"
|
|
bitfld.long 0x00 18. "ITCM_READ_WS,Refer CM7_0_CTL description" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "ITCM_ECC_INJ_EN,Refer CM7_0_CTL description" "0,1"
|
|
bitfld.long 0x00 16. "ITCM_ECC_EN,Refer CM7_0_CTL description" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "INIT_RMW_EN,Refer CM7_0_CTL description" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "INIT_TCM_EN,Refer CM7_0_CTL description" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4. "CPU_WAIT,Refer CM7_0_CTL description" "0,1"
|
|
bitfld.long 0x00 0.--3. "PPB_LOCK,Refer CM7_0_CTL description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 16. (increment 0 1) (increment 0 0x04)
|
|
rgroup.long ($2+0x500)++0x03
|
|
line.long 0x00 "CM7_1_INT_STATUS[$1],CM7 1 interrupt status $1"
|
|
bitfld.long 0x00 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM7_1 activated system interrupt index for CPU interrupt 0"
|
|
repeat.end
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "CM7_1_VECTOR_TABLE_BASE,CM7 1 vector table base"
|
|
hexmask.long 0x00 7.--31. 1. "ADDR25,The default CM7 vector table base address is 0x0100:0000 (CM7 VTOR and reset exception handler address after reset)"
|
|
repeat 4. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x640)++0x03
|
|
line.long 0x00 "CM7_1_NMI_CTL[$1],CM7 1 NMI control $1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,Refer CM7_0_NMI_CTL description"
|
|
repeat.end
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "CM0_CTL,CM0+ control"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)"
|
|
bitfld.long 0x00 1. "ENABLED,Processor enable: '0': Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SLV_STALL,Processor debug access control: '0': Access" "0,1"
|
|
rgroup.long 0x1004++0x03
|
|
line.long 0x00 "CM0_STATUS,CM0+ status"
|
|
bitfld.long 0x00 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode" "0,1"
|
|
bitfld.long 0x00 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'" "0,1"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "SLOW_CLOCK_CTL,Slow clock control"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT_DIV,Specifies the slow clock divider (from the memory/AXI clock 'clk_mem' to the slow clock 'clk_slow')"
|
|
group.long 0x100C++0x03
|
|
line.long 0x00 "PERI_CLOCK_CTL,Peripheral interconnect clock control"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT_DIV,Integer division by (1+INT_DIV)"
|
|
group.long 0x1010++0x03
|
|
line.long 0x00 "MEM_CLOCK_CTL,Memory clock control"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT_DIV,Integer division by (1+INT_DIV)"
|
|
rgroup.long 0x1100++0x03
|
|
line.long 0x00 "CM0_INT0_STATUS,CM0+ interrupt 0 status"
|
|
bitfld.long 0x00 31. "SYSTEM_INT_VALID,Valid indication for SYSTEM_INT_IDX" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 0"
|
|
rgroup.long 0x1104++0x03
|
|
line.long 0x00 "CM0_INT1_STATUS,CM0+ interrupt 1 status"
|
|
bitfld.long 0x00 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 1"
|
|
rgroup.long 0x1108++0x03
|
|
line.long 0x00 "CM0_INT2_STATUS,CM0+ interrupt 2 status"
|
|
bitfld.long 0x00 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 2"
|
|
rgroup.long 0x110C++0x03
|
|
line.long 0x00 "CM0_INT3_STATUS,CM0+ interrupt 3 status"
|
|
bitfld.long 0x00 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 3"
|
|
rgroup.long 0x1110++0x03
|
|
line.long 0x00 "CM0_INT4_STATUS,CM0+ interrupt 4 status"
|
|
bitfld.long 0x00 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 4"
|
|
rgroup.long 0x1114++0x03
|
|
line.long 0x00 "CM0_INT5_STATUS,CM0+ interrupt 5 status"
|
|
bitfld.long 0x00 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 5"
|
|
rgroup.long 0x1118++0x03
|
|
line.long 0x00 "CM0_INT6_STATUS,CM0+ interrupt 6 status"
|
|
bitfld.long 0x00 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 6"
|
|
rgroup.long 0x111C++0x03
|
|
line.long 0x00 "CM0_INT7_STATUS,CM0+ interrupt 7 status"
|
|
bitfld.long 0x00 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 7"
|
|
group.long 0x1120++0x03
|
|
line.long 0x00 "CM0_VECTOR_TABLE_BASE,CM0+ vector table base"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ADDR24,The default CM0+ vector table base address is 0x0000:0000 (CM0+ VTOR and reset exception handler address after reset)"
|
|
repeat 4. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x1140)++0x03
|
|
line.long 0x00 "CM0_NMI_CTL[$1],CM0+ NMI control $1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI"
|
|
repeat.end
|
|
group.long 0x1200++0x03
|
|
line.long 0x00 "CM7_0_PWR_CTL,CM7 0 power control"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)"
|
|
bitfld.long 0x00 0.--1. "PWR_MODE,Power mode" "0: Switch CM7_0 off Power off clock off isolate..,1: Reset CM7_0 Clock off no isolated no retain..,2: Put CM7_0 in Retained mode This can only..,3: Switch CM7_0 on"
|
|
group.long 0x1204++0x03
|
|
line.long 0x00 "CM7_0_PWR_DELAY_CTL,CM7 0 power delay control"
|
|
hexmask.long.word 0x00 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1210++0x03
|
|
line.long 0x00 "CM7_1_PWR_CTL,CM7 1 power control"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTKEYSTAT,Refer CM7_0_PWR_CTL description"
|
|
bitfld.long 0x00 0.--1. "PWR_MODE,Refer CM7_0_PWR_CTL description" "0: Refer CM7_0_PWR_CTL description,1: Refer CM7_0_PWR_CTL description,2: Refer CM7_0_PWR_CTL description,3: Refer CM7_0_PWR_CTL description"
|
|
group.long 0x1214++0x03
|
|
line.long 0x00 "CM7_1_PWR_DELAY_CTL,CM7 1 power delay control"
|
|
hexmask.long.word 0x00 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1300++0x03
|
|
line.long 0x00 "RAM0_CTL0,RAM 0 control"
|
|
bitfld.long 0x00 19. "ECC_CHECK_DIS,Disable ECC checking and thus fault reports" "0,1"
|
|
bitfld.long 0x00 18. "ECC_INJ_EN,Enable ECC parity injection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "ECC_AUTO_CORRECT,HW ECC autocorrect functionality: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 16. "ECC_EN,Enable ECC checking: '0': Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast_0/1') interface" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow') intefrace" "0,1,2,3"
|
|
rgroup.long 0x1304++0x03
|
|
line.long 0x00 "RAM0_STATUS,RAM 0 status"
|
|
bitfld.long 0x00 0. "WB_EMPTY,Write buffer empty" "0,1"
|
|
repeat 16. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x1340)++0x03
|
|
line.long 0x00 "RAM0_PWR_MACRO_CTL[$1],RAM 0 power control $1"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)"
|
|
bitfld.long 0x00 0.--1. "PWR_MODE,Power mode" "0: Turn OFF the SRAM,1: undefined,2: Keep SRAM in Retained mode,3: Enable SRAM for regular operation"
|
|
repeat.end
|
|
group.long 0x1380++0x03
|
|
line.long 0x00 "RAM1_CTL0,RAM 1 control"
|
|
bitfld.long 0x00 19. "ECC_CHECK_DIS,Disable ECC checking and thus fault reports" "0,1"
|
|
bitfld.long 0x00 18. "ECC_INJ_EN,Enable ECC parity injection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "ECC_AUTO_CORRECT,Refer RAM0_CTL0 descriotion" "0,1"
|
|
bitfld.long 0x00 16. "ECC_EN,Refer RAM0_CTL0 descriotion" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "FAST_WS,Refer RAM0_CTL0 descriotion" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SLOW_WS,Refer RAM0_CTL0 descriotion" "0,1,2,3"
|
|
rgroup.long 0x1384++0x03
|
|
line.long 0x00 "RAM1_STATUS,RAM 1 status"
|
|
bitfld.long 0x00 0. "WB_EMPTY,Refer RAM0_STATUS description" "0,1"
|
|
group.long 0x1388++0x03
|
|
line.long 0x00 "RAM1_PWR_CTL,RAM 1 power control"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTKEYSTAT,Refer RAM0_PWR_MACRO_CTL description"
|
|
bitfld.long 0x00 0.--1. "PWR_MODE,Power mode" "0: Refer RAM0_PWR_MACRO_CTL description,1: Undefined,2: Refer RAM0_PWR_MACRO_CTL description,3: Refer RAM0_PWR_MACRO_CTL description"
|
|
group.long 0x13A0++0x03
|
|
line.long 0x00 "RAM2_CTL0,RAM 2 control"
|
|
bitfld.long 0x00 19. "ECC_CHECK_DIS,Disable ECC checking and thus fault reports" "0,1"
|
|
bitfld.long 0x00 18. "ECC_INJ_EN,Enable ECC parity injection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "ECC_AUTO_CORRECT,Refer RAM0_CTL0 descriotion" "0,1"
|
|
bitfld.long 0x00 16. "ECC_EN,Refer RAM0_CTL0 descriotion" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "FAST_WS,Refer RAM0_CTL0 descriotion" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SLOW_WS,Refer RAM0_CTL0 descriotion" "0,1,2,3"
|
|
rgroup.long 0x13A4++0x03
|
|
line.long 0x00 "RAM2_STATUS,RAM 2 status"
|
|
bitfld.long 0x00 0. "WB_EMPTY,Refer RAM0_STATUS description" "0,1"
|
|
group.long 0x13A8++0x03
|
|
line.long 0x00 "RAM2_PWR_CTL,RAM 2 power control"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTKEYSTAT,Refer RAM0_PWR_MACRO_CTL description"
|
|
bitfld.long 0x00 0.--1. "PWR_MODE,Power mode" "0: Refer RAM0_PWR_MACRO_CTL description,1: Undefined,2: Refer RAM0_PWR_MACRO_CTL description,3: Refer RAM0_PWR_MACRO_CTL description"
|
|
group.long 0x13C0++0x03
|
|
line.long 0x00 "RAM_PWR_DELAY_CTL,Power up delay used for all SRAM power domains"
|
|
hexmask.long.word 0x00 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x13C4++0x03
|
|
line.long 0x00 "ROM_CTL,ROM control"
|
|
bitfld.long 0x00 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast')" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow')" "0,1,2,3"
|
|
group.long 0x13C8++0x03
|
|
line.long 0x00 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "WORD_ADDR,Specifies the word address where an error will be injected"
|
|
rgroup.long 0x1400++0x03
|
|
line.long 0x00 "PRODUCT_ID,Product identifier and version (same as CoreSight RomTables)"
|
|
bitfld.long 0x00 20.--23. "MINOR_REV,Minir Revision starts with 1 increments with metal layer only tape-out (implemented with metal ECO-able tie-off)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "MAJOR_REV,Major Revision starts with 1 increments with all layer tape-out (implemented with metal ECO-able tie-off)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "FAMILY_ID,Family ID"
|
|
rgroup.long 0x1410++0x03
|
|
line.long 0x00 "DP_STATUS,Debug port status"
|
|
bitfld.long 0x00 2. "SWJ_JTAG_SEL,Specifies if the JTAG or SWD interface is selected" "0,1"
|
|
bitfld.long 0x00 1. "SWJ_DEBUG_EN,Specifies if SWJ debug is enabled i.e" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SWJ_CONNECTED,Specifies if the SWJ debug port is connected i.e" "0,1"
|
|
group.long 0x1414++0x03
|
|
line.long 0x00 "AP_CTL,Access port control"
|
|
bitfld.long 0x00 18. "SYS_DISABLE,Disables the system AP interface: '0': Enabled" "0,1"
|
|
bitfld.long 0x00 17. "CM7_DISABLE,Disables the CM7_0 and CM7_1 AP interface: '0': Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CM0_DISABLE,Disables the CM0 AP interface: '0': Enabled" "0,1"
|
|
bitfld.long 0x00 2. "SYS_ENABLE,Enables the system AP interface: '0': Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CM7_ENABLE,Enables the CM7_0 and CM7_1 AP interface: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 0. "CM0_ENABLE,Enables the CM0 AP interface: '0': Disabled" "0,1"
|
|
group.long 0x1500++0x03
|
|
line.long 0x00 "BUFF_CTL,Buffer control"
|
|
bitfld.long 0x00 0. "WRITE_BUFF,Specifies if write transfer can be buffered in the bus infrastructure bridges: '0': Write transfers are not buffered independent of the transfer's bufferable attribute" "0,1"
|
|
group.long 0x1600++0x03
|
|
line.long 0x00 "SYSTICK_CTL,SysTick timer control"
|
|
bitfld.long 0x00 31. "NOREF,Specifies if an external clock source is provided: '0': An external clock source is provided" "0,1"
|
|
bitfld.long 0x00 30. "SKEW,Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "CLOCK_SOURCE,Specifies an external clock source: '0': The low frequency clock 'clk_lf' is selected" "0,1,2,3"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,Specifies the number of clock source cycles (minus 1) that make up 10 ms"
|
|
rgroup.long 0x1704++0x03
|
|
line.long 0x00 "MBIST_STAT,Memory BIST status"
|
|
bitfld.long 0x00 1. "SFP_FAIL,Report status of the BIST run only valid if SFP_READY=1" "0,1"
|
|
bitfld.long 0x00 0. "SFP_READY,Flag indicating the BIST run is done" "0,1"
|
|
group.long 0x1800++0x03
|
|
line.long 0x00 "CAL_SUP_SET,Calibration support set and read"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Read without side effect write 1 to set"
|
|
group.long 0x1804++0x03
|
|
line.long 0x00 "CAL_SUP_CLR,Calibration support clear and reset"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Read side effect: when read all bits are cleared write 1 to clear a specific bit Note: no exception for the debug host it also causes the read side effect"
|
|
group.long 0x2000++0x03
|
|
line.long 0x00 "CM0_PC_CTL,CM0+ protection context control"
|
|
bitfld.long 0x00 0.--3. "VALID,Valid fields for the protection context handler CM0_PCi_HANDLER registers: Bit" "0: Valid field for CM0_PC0_HANDLER,1: Valid field for CM0_PC1_HANDLER,2: Valid field for CM0_PC2_HANDLER,3: Valid field for CM0_PC3_HANDLER,?..."
|
|
group.long 0x2040++0x03
|
|
line.long 0x00 "CM0_PC0_HANDLER,CM0+ protection context 0 handler"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Address of the protection context 0 handler"
|
|
group.long 0x2044++0x03
|
|
line.long 0x00 "CM0_PC1_HANDLER,CM0+ protection context 1 handler"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Address of the protection context 1 handler"
|
|
group.long 0x2048++0x03
|
|
line.long 0x00 "CM0_PC2_HANDLER,CM0+ protection context 2 handler"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Address of the protection context 2 handler"
|
|
group.long 0x204C++0x03
|
|
line.long 0x00 "CM0_PC3_HANDLER,CM0+ protection context 3 handler"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Address of the protection context 3 handler"
|
|
group.long 0x20C4++0x03
|
|
line.long 0x00 "PROTECTION,Protection status"
|
|
bitfld.long 0x00 0.--2. "STATE,Protection state: '0': UNKNOWN" "0: UNKNOWN,1: VIRGIN,2: NORMAL,3: SECURE,4: DEAD,?..."
|
|
group.long 0x2100++0x03
|
|
line.long 0x00 "TRIM_ROM_CTL,ROM trim control"
|
|
hexmask.long 0x00 0.--31. 1. "TRIM,N/A"
|
|
group.long 0x2104++0x03
|
|
line.long 0x00 "TRIM_RAM_CTL,RAM trim control for less than 100MHz SRAMs"
|
|
hexmask.long 0x00 0.--31. 1. "TRIM,N/A"
|
|
group.long 0x2108++0x03
|
|
line.long 0x00 "TRIM_RAM200_CTL,RAM trim control for 100MHz - 200MHz SRAMs"
|
|
hexmask.long 0x00 0.--31. 1. "TRIM,See TRIM_RAM_CTL for description"
|
|
group.long 0x210C++0x03
|
|
line.long 0x00 "TRIM_RAM350_CTL,RAM trim control for more than 200MHz SRAMs"
|
|
hexmask.long 0x00 0.--31. 1. "TRIM,See TRIM_RAM_CTL for description"
|
|
repeat 1023. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x8000)++0x03
|
|
line.long 0x00 "CM0_SYSTEM_INT_CTL[$1],CM0+ system interrupt control $1"
|
|
bitfld.long 0x00 31. "CPU_INT_VALID,Interrupt enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 0.--2. "CM0_CPU_INT_IDX,CPU interrupt index (legal range [0 7])" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 1023. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0xA000)++0x03
|
|
line.long 0x00 "CM7_0_SYSTEM_INT_CTL[$1],CM7 0 system interrupt control $1"
|
|
bitfld.long 0x00 31. "CPU_INT_VALID,Interrupt enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 0.--3. "CPU_INT_IDX,CPU interrupt index (legal range [0 15])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
repeat 1023. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0xC000)++0x03
|
|
line.long 0x00 "CM7_1_SYSTEM_INT_CTL[$1],CM7 1 system interrupt control $1"
|
|
bitfld.long 0x00 31. "CPU_INT_VALID,Refer CM7_0_SYSTEM_INT_CTL description" "0,1"
|
|
bitfld.long 0x00 0.--3. "CPU_INT_IDX,Refer CM7_0_SYSTEM_INT_CTL description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
tree.end
|
|
tree "DMAC"
|
|
base ad:0x402A0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control"
|
|
bitfld.long 0x00 31. "ENABLED,IP enable: '0': Disabled" "0: DISABLED,1: ENABLED"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ACTIVE,Active channels"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ACTIVE,Specifies active channels i.e"
|
|
repeat 8. (increment 0 1)(increment 0 0x100)
|
|
tree "CH[$1]"
|
|
group.long ($2+0x1000)++0x03
|
|
line.long 0x00 "CTL,Channel control"
|
|
bitfld.long 0x00 31. "ENABLED,Channel enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,Channel priority: '0': highest priority" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "PC,Protection context" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2. "B,Non-bufferable/bufferable access control: '0': non-bufferable" "0,1"
|
|
bitfld.long 0x00 1. "NS,Secure/on-secure access control: '0': secure" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "P,User/privileged access control: '0': user mode" "0,1"
|
|
rgroup.long ($2+0x1010)++0x03
|
|
line.long 0x00 "IDX,Channel current indices"
|
|
hexmask.long.word 0x00 16.--31. 1. "Y,Specifies the Y loop index with Y_COUNT taken from the current descriptor"
|
|
hexmask.long.word 0x00 0.--15. 1. "X,Specifies the X loop index"
|
|
rgroup.long ($2+0x1014)++0x03
|
|
line.long 0x00 "SRC,Channel current source address"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Current address of source location"
|
|
rgroup.long ($2+0x1018)++0x03
|
|
line.long 0x00 "DST,Channel current destination address"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Current address of destination location"
|
|
group.long ($2+0x1020)++0x03
|
|
line.long 0x00 "CURR,Channel current descriptor pointer"
|
|
hexmask.long 0x00 2.--31. 1. "PTR,Address of current descriptor"
|
|
group.long ($2+0x1028)++0x03
|
|
line.long 0x00 "TR_CMD,Channle software trigger"
|
|
bitfld.long 0x00 0. "ACTIVATE,Software trigger" "0,1"
|
|
rgroup.long ($2+0x1040)++0x03
|
|
line.long 0x00 "DESCR_STATUS,Channel descriptor status"
|
|
bitfld.long 0x00 31. "VALID,Indicates whether the descriptor information present in DESCR_CTL DESCR_SRC DESCR_DST DESCR_X_SIZE DESCR_X_INCR DESCR_Y_SIZE DESCR_Y_INCR DESCR_NEXT status registers is valid or not" "0,1"
|
|
rgroup.long ($2+0x1060)++0x03
|
|
line.long 0x00 "DESCR_CTL,Channel descriptor control"
|
|
bitfld.long 0x00 28.--30. "DESCR_TYPE,Specifies the descriptor type (not to be confused with the trigger type): '0': Single transfer" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 27. "DST_TRANSFER_SIZE,Specifies the bus transfer size to the destination location: '0': As specified by DATA_SIZE" "0,1"
|
|
bitfld.long 0x00 26. "SRC_TRANSFER_SIZE,Specifies the bus transfer size to the source location: '0': As specified by DATA_SIZE" "0,1"
|
|
bitfld.long 0x00 24. "CH_DISABLE,Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value): '0': Channel is not disabled" "0,1"
|
|
bitfld.long 0x00 16.--17. "DATA_SIZE,Specifies the data element size: '0': Byte (8 bits)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8. "DATA_PREFETCH,Source data prefetch: '0': No source data prefetch" "0,1"
|
|
bitfld.long 0x00 6.--7. "TR_IN_TYPE,Specifies the input trigger type (not to be confused with the descriptor type): '0': A trigger results in the execution of a single transfer" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "TR_OUT_TYPE,Specifies when an output trigger is generated: '0': An output trigger is generated after a single transfer" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "INTR_TYPE,Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION): '0': An interrupt is generated after a single transfer" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "WAIT_FOR_DEACT,Specifies whether the controller should wait for the input trigger to be deactivated i.e" "0,1,2,3"
|
|
rgroup.long ($2+0x1064)++0x03
|
|
line.long 0x00 "DESCR_SRC,Channel descriptor source"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Base address of source location"
|
|
rgroup.long ($2+0x1068)++0x03
|
|
line.long 0x00 "DESCR_DST,Channel descriptor destination"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Base address of destination location"
|
|
rgroup.long ($2+0x106C)++0x03
|
|
line.long 0x00 "DESCR_X_SIZE,Channel descriptor X size"
|
|
hexmask.long.word 0x00 0.--15. 1. "X_COUNT,Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer)"
|
|
rgroup.long ($2+0x1070)++0x03
|
|
line.long 0x00 "DESCR_X_INCR,Channel descriptor X increment"
|
|
hexmask.long.word 0x00 16.--31. 1. "DST_X,Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE)"
|
|
hexmask.long.word 0x00 0.--15. 1. "SRC_X,Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE)"
|
|
rgroup.long ($2+0x1074)++0x03
|
|
line.long 0x00 "DESCR_Y_SIZE,Channel descriptor Y size"
|
|
hexmask.long.word 0x00 0.--15. 1. "Y_COUNT,Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0 65535] representing 1 through 65536 iterations"
|
|
rgroup.long ($2+0x1078)++0x03
|
|
line.long 0x00 "DESCR_Y_INCR,Channel descriptor Y increment"
|
|
hexmask.long.word 0x00 16.--31. 1. "DST_Y,Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE)"
|
|
hexmask.long.word 0x00 0.--15. 1. "SRC_Y,Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE)"
|
|
rgroup.long ($2+0x107C)++0x03
|
|
line.long 0x00 "DESCR_NEXT,Channel descriptor next pointer"
|
|
hexmask.long 0x00 2.--31. 1. "PTR,Address of next descriptor in descriptor list"
|
|
group.long ($2+0x1080)++0x03
|
|
line.long 0x00 "INTR,Interrupt"
|
|
bitfld.long 0x00 7. "DESCR_BUS_ERROR,Activated (set to '1') on a bus error for a load of the descriptor" "0,1"
|
|
bitfld.long 0x00 6. "ACTIVE_CH_DISABLED,Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy" "0,1"
|
|
bitfld.long 0x00 5. "CURR_PTR_NULL,Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'" "0,1"
|
|
bitfld.long 0x00 4. "DST_MISAL,Activated (set to '1') on a misalignment of the destination address" "0,1"
|
|
bitfld.long 0x00 3. "SRC_MISAL,Activated (set to '1') on a misalignment of the source address" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DST_BUS_ERROR,Activated (set to '1') on a bus error for a store to the destination" "0,1"
|
|
bitfld.long 0x00 1. "SRC_BUS_ERROR,Activated (set to '1') on a bus error for a load from the source" "0,1"
|
|
bitfld.long 0x00 0. "COMPLETION,Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE" "0,1"
|
|
group.long ($2+0x1084)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x00 7. "DESCR_BUS_ERROR,Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 6. "ACTIVE_CH_DISABLED,Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 5. "CURR_PTR_NULL,Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 4. "DST_MISAL,Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 3. "SRC_MISAL,Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DST_BUS_ERROR,Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 1. "SRC_BUS_ERROR,Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 0. "COMPLETION,Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect)" "0,1"
|
|
group.long ($2+0x1088)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x00 7. "DESCR_BUS_ERROR,Mask for INTR.DESCR_BUS_ERROR interrupt" "0,1"
|
|
bitfld.long 0x00 6. "ACTIVE_CH_DISABLED,Mask for INTR.ACTIVE_CH_DISABLED interrupt" "0,1"
|
|
bitfld.long 0x00 5. "CURR_PTR_NULL,Mask for INTR.CURR_PTR_NULL interrupt" "0,1"
|
|
bitfld.long 0x00 4. "DST_MISAL,Mask for INTR.DST_MISAL interrupt" "0,1"
|
|
bitfld.long 0x00 3. "SRC_MISAL,Mask for INTR.SRC_MISAL interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DST_BUS_ERROR,Mask for INTR.DST_BUS_ERROR interrupt" "0,1"
|
|
bitfld.long 0x00 1. "SRC_BUS_ERROR,Mask for INTR.SRC_BUS_ERROR interrupt" "0,1"
|
|
bitfld.long 0x00 0. "COMPLETION,Mask for INTR.COMPLETION interrupt" "0,1"
|
|
rgroup.long ($2+0x108C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x00 7. "DESCR_BUS_ERROR,Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields" "0,1"
|
|
bitfld.long 0x00 6. "ACTIVE_CH_DISABLED,Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields" "0,1"
|
|
bitfld.long 0x00 5. "CURR_PTR_NULL,Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields" "0,1"
|
|
bitfld.long 0x00 4. "DST_MISAL,Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields" "0,1"
|
|
bitfld.long 0x00 3. "SRC_MISAL,Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DST_BUS_ERROR,Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields" "0,1"
|
|
bitfld.long 0x00 1. "SRC_BUS_ERROR,Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields" "0,1"
|
|
bitfld.long 0x00 0. "COMPLETION,Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "DW (Datawire Controller)"
|
|
repeat 2. (list 0. 1.) (list ad:0x40280000 ad:0x40290000)
|
|
tree "DW$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control"
|
|
bitfld.long 0x00 31. "ENABLED,IP enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 1. "ECC_INJ_EN,Enable parity injection for SRAM" "0,1"
|
|
bitfld.long 0x00 0. "ECC_EN,Enable ECC checking: '0': Disabled" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Status"
|
|
bitfld.long 0x00 31. "ACTIVE,Active channel present: '0': No" "0,1"
|
|
bitfld.long 0x00 28.--30. "STATE,State of the DW controller" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--24. 1. "CH_IDX,Active channel index"
|
|
bitfld.long 0x00 11. "PREEMPTABLE,Active channel preemptable" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,Active channel priority" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "PC,Active channel protection context" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2. "B,Active channel non-bufferable/bufferable access control: '0': non-bufferable '1': bufferable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "NS,Active channel secure/non-secure access control: '0': secure" "0,1"
|
|
bitfld.long 0x00 0. "P,Active channel user/privileged access control: '0': user mode" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,N/A"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x00 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ACT_SRC,Active source"
|
|
hexmask.long 0x00 0.--31. 1. "SRC_ADDR,Current address of source location"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "ACT_DST,Active destination"
|
|
hexmask.long 0x00 0.--31. 1. "DST_ADDR,Current address of destination location"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x00 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR"
|
|
hexmask.long.word 0x00 0.--9. 1. "WORD_ADDR,Specifies the word address where an error will be injected"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CRC_CTL,CRC control"
|
|
bitfld.long 0x00 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing): '0': No" "0,1"
|
|
bitfld.long 0x00 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): '0': Most significant bit (bit 1) first" "0,1"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x00 0.--31. 1. "POLYNOMIAL,CRC polynomial"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CRC_LFSR_CTL,CRC LFSR control"
|
|
hexmask.long 0x00 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x00 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder"
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x00 0.--31. 1. "REM,Remainder value"
|
|
repeat 143. (increment 0 1)(increment 0 0x40)
|
|
tree "CH_STRUCT[$1]"
|
|
group.long ($2+0x8000)++0x03
|
|
line.long 0x00 "CH_CTL,Channel control"
|
|
bitfld.long 0x00 31. "ENABLED,Channel enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 11. "PREEMPTABLE,Specifies if the channel is preemptable" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,Channel priority: '0': highest priority" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "PC,Protection context" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2. "B,Non-bufferable/bufferable access control: '0': non-bufferable" "0,1"
|
|
bitfld.long 0x00 1. "NS,Secure/on-secure access control: '0': secure" "0,1"
|
|
bitfld.long 0x00 0. "P,User/privileged access control: '0': user mode" "0,1"
|
|
rgroup.long ($2+0x8004)++0x03
|
|
line.long 0x00 "CH_STATUS,Channel status"
|
|
bitfld.long 0x00 31. "PENDING,Specifies pending DW channels i.e" "0,1"
|
|
bitfld.long 0x00 0.--3. "INTR_CAUSE,Specifies the source of the interrupt cause: '0': No interrupt generated '1': Interrupt based on transfer complettion configuration based on INTR_TYPE '2': Source transfer bus error '3': Destination transfer bus error '4': Source address.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long ($2+0x8008)++0x03
|
|
line.long 0x00 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor"
|
|
hexmask.long.byte 0x00 0.--7. 1. "X_IDX,Specifies the X loop index"
|
|
group.long ($2+0x800C)++0x03
|
|
line.long 0x00 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x00 2.--31. 1. "ADDR,Address of current descriptor"
|
|
group.long ($2+0x8010)++0x03
|
|
line.long 0x00 "INTR,Interrupt"
|
|
bitfld.long 0x00 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected" "0,1"
|
|
group.long ($2+0x8014)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x00 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)" "0,1"
|
|
group.long ($2+0x8018)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x00 0. "CH,Mask for corresponding field in INTR register" "0,1"
|
|
rgroup.long ($2+0x801C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x00 0. "CH,Logical and of corresponding INTR and INTR_MASK fields" "0,1"
|
|
group.long ($2+0x8020)++0x03
|
|
line.long 0x00 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,N/A"
|
|
group.long ($2+0x8024)++0x03
|
|
line.long 0x00 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,N/A"
|
|
group.long ($2+0x8028)++0x03
|
|
line.long 0x00 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x00 0. "ACTIVATE,Software trigger" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "EFUSE (EFUSE MXS40)"
|
|
base ad:0x402C0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control"
|
|
bitfld.long 0x00 31. "ENABLED,IP enable: '0': Disabled" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TEST,Test"
|
|
bitfld.long 0x00 0.--1. "MARG_READ,Margin" "0: Low Resistance,1: Nominal resistance (Default read condition),2: High Resistance,3: Higher Resistance"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CMD,Command"
|
|
bitfld.long 0x00 31. "START,FW sets this field to '1' to start a program operation" "0,1"
|
|
bitfld.long 0x00 16.--19. "MACRO_ADDR,Macro address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--12. "BYTE_ADDR,Byte address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--6. "BIT_ADDR,Bit address" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "BIT_DATA,Bit data" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SEQ_DEFAULT,Sequencer Default value"
|
|
bitfld.long 0x00 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x00 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x00 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x00 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x00 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x00 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "SEQ_READ_CTL_$1,Sequencer read control $1"
|
|
bitfld.long 0x00 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0" "0,1"
|
|
bitfld.long 0x00 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x00 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x00 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x00 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x00 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x00 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1)"
|
|
repeat.end
|
|
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "SEQ_PROGRAM_CTL_$1,Sequencer program control $1"
|
|
bitfld.long 0x00 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0" "0,1"
|
|
bitfld.long 0x00 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x00 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x00 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x00 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x00 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x00 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1)"
|
|
repeat.end
|
|
tree.end
|
|
tree "ETH (Ethernet Interface)"
|
|
repeat 2. (list 0. 1.) (list ad:0x40480000 ad:0x40490000)
|
|
tree "ETH$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,MXETH Control Register"
|
|
bitfld.long 0x00 31. "ENABLED,MXETH enable: '0': Disabled" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "REFCLK_DIV,Specify the ref_clk divider"
|
|
newline
|
|
bitfld.long 0x00 2. "REFCLK_SRC_SEL,Select the source for ref_clk" "0: Ref_clk comes from REF_CLK_IN input port (HSIO),1: Ref_clk comes from REF_CLK_INT_IN input port.."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "ETH_MODE,Set ethernet mode" "0: MII mode (10/100MHz speed is determined by..,1: GMII mode (network_config[10] must be set to..,2: RGMII mode (10M/100M/1G speed is determined..,3: RMII mode (10M/100M speed is determined by.."
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,MXETH Status Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RX_PFC_PAUSED,Each bit corresponds to a priority indicated within the PFC priority based pause frame"
|
|
newline
|
|
bitfld.long 0x00 0. "PFC_NEGOTIATE,Identifies that PFC priority based pause flow control has been negotiated" "0: No PFC priority based pause frames have yet..,1: At least one PFC priority based pause frames.."
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "NETWORK_CONTROL,The network control register contains general MAC control functions for both receiver and transmitter"
|
|
rbitfld.long 0x00 31. "EXT_RXQ_RSVD_31,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "IFG_EATS_QAV_CREDIT,Setting this bit high modifies the CBS algorithm so the IFG/IPG associated with a transmit frame counts towards its 802.1Qav credit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TWO_PT_FIVE_GIG,2.5G operation selected - setting this bit high drives the speed_mode[3] top level output pin high and also adjusts the link timer in the PCS auto-negotiation block to ensure it delivers 10ms for 2500BASE-X and 1.6ms in SGMII mode and.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "SEL_MII_ON_RGMII,If the RGMII interface being used set this bit high to configure the interface for MII operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "OSS_CORRECTION_FIELD,1588 One Step Correction Field Update" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "EXT_RXQ_SEL_EN,Enable external selection of receive queue" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "PFC_CTRL,'Enable multiple PFC pause quantums one per pause priority'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "ONE_STEP_SYNC_MODE,1588 One Step Sync Mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23. "EXT_TSU_PORT_ENABLE,Write ignore read 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "STORE_UDP_OFFSET,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ALT_SGMII_MODE,Alternative sgmii mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "PTP_UNICAST_ENA,Enable detection of unicast PTP unicast frames" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "TX_LPI_EN,Enable LPI transmission when set LPI (low power idle) is immediately transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "FLUSH_RX_PKT_PCLK,Flush the next packet from the external RX DPRAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME,Write a one to transmit PFC priority based pause frame" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PFC_ENABLE,Enable PFC Priority Based Pause Reception capabilities" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "STORE_RX_TS,Store receive time stamp to memory" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 14. "REMOVED_14,Write ignore read 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 13. "REMOVED_13,Write ignore read 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "TX_PAUSE_FRAME_ZERO,Transmit zero quantum pause frame - writing one to this bit causes a pause frame with zero quantum to be transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "TX_PAUSE_FRAME_REQ,Transmit pause frame - writing one to this bit causes a pause frame to be transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TX_HALT_PCLK,Transmit halt - writing one to this bit halts transmission as soon as any ongoing frame transmission ends" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TX_START_PCLK,Start transmission - writing one to this bit starts transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "BACK_PRESSURE,Back pressure if set in 10M or 100M half duplex mode will force collisions on all received frames" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "STATS_WRITE_EN,Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "INC_ALL_STATS_REGS,Incremental statistics registers - this bit is write only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CLEAR_ALL_STATS_REGS,Clear statistics registers - this bit is write only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MAN_PORT_EN,Management port enable - set to one to enable the management port" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ENABLE_TRANSMIT,Transmit enable - when set it enables the GEM transmitter to send data" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENABLE_RECEIVE,Receive enable - when set it enables the GEM to receive data" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOOPBACK_LOCAL,Loopback local - asserts the loopback_local signal to the system clock generator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "LOOPBACK,Loopback - controls the loopback output pin" "0,1"
|
|
group.long 0x1004++0x03
|
|
line.long 0x00 "NETWORK_CONFIG,The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC"
|
|
bitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "IGNORE_IPG_RX_ER,Ignore IPG rx_er" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "NSP_CHANGE,Receive bad preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "IPG_STRETCH_ENABLE,IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "SGMII_MODE_ENABLE,SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "IGNORE_RX_FCS,Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "EN_HALF_DUPLEX_RX,Enable frames to be received in half-duplex mode while transmitting" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RECEIVE_CHECKSUM_OFFLOAD_ENABLE,Receive checksum offload enable - when set the receive checksum engine is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "DISABLE_COPY_OF_PAUSE_FRAMES,Disable copy of pause frames - set to one to prevent pause frames being copied to memory" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "DATA_BUS_WIDTH,Data bus width - set according to AMBA (AXI) or external FIFO data bus width" "0: 32 bit data bus width,1: 64 bit AMBA (AXI) data bus width,2: 128 bit AMBA (AXI) data bus width,3: 128 bit AMBA (AXI) data bus width"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "MDC_CLOCK_DIVISION,MDC clock division - set according to pclk speed" "0: divide pclk by 8 (pclk up to 20 MHz),1: divide pclk by 16 (pclk up to 40 MHz),2: divide pclk by 32 (pclk up to 80 MHz),3: divide pclk by 48 (pclk up to 120MHz),4: divide pclk by 64 (pclk up to 160 MHz),5: divide pclk by 96 (pclk up to 240 MHz),6: divide pclk by 128 (pclk up to 320 MHz),7: divide pclk by 224 (pclk up to 540 MHz)"
|
|
newline
|
|
bitfld.long 0x00 17. "FCS_REMOVE,FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "LENGTH_FIELD_ERROR_FRAME_DISCARD,Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RECEIVE_BUFFER_OFFSET,Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 13. "PAUSE_ENABLE,Pause enable - when set transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "RETRY_TEST,Retry test - must be set to zero for normal operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "PCS_SELECT,PCS select - selects between MII/GMII and TBI" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "GIGABIT_MODE_ENABLE,Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation" "0: 10/100 operation using MII interface,1: Gigabit operation using GMI interface"
|
|
newline
|
|
bitfld.long 0x00 9. "EXTERNAL_ADDRESS_MATCH_ENABLE,External address match enable - when set the external address match interface can be used to copy frames to memory" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RECEIVE_1536_BYTE_FRAMES,Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "UNICAST_HASH_ENABLE,Unicast hash enable - when set unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register" "0,1"
|
|
newline
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bitfld.long 0x00 6. "MULTICAST_HASH_ENABLE,Multicast hash enable - when set multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register" "0,1"
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bitfld.long 0x00 5. "NO_BROADCAST,No broadcast - when set to logic one frames addressed to the broadcast address of all ones will not be accepted" "0,1"
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bitfld.long 0x00 4. "COPY_ALL_FRAMES,Copy all frames - when set to logic one all valid frames will be accepted" "0,1"
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bitfld.long 0x00 3. "JUMBO_FRAMES,Jumbo frames - set to one to enable jumbo frames up to `gem_jumbo_max_length bytes to be accepted" "0,1"
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bitfld.long 0x00 2. "DISCARD_NON_VLAN_FRAMES,Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic" "0,1"
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bitfld.long 0x00 1. "FULL_DUPLEX,Full duplex - if set to logic one the transmit block ignores the state of collision and carrier sense and allows receive while transmitting" "0,1"
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bitfld.long 0x00 0. "SPEED,Speed - set to logic one to indicate 100Mbps operation logic zero for 10Mbps" "0,1"
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rgroup.long 0x1008++0x03
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line.long 0x00 "NETWORK_STATUS,The network status register returns status information with respect to the PHY management interface"
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bitfld.long 0x00 7. "LPI_INDICATE_PCLK,LPI Indication - Low power idle has been detected on receive" "0,1"
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bitfld.long 0x00 6. "PFC_NEGOTIATE_PCLK,Set when PFC Priority Based Pause has been negotiated" "0,1"
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bitfld.long 0x00 4.--5. "REMOVED_5_4,N/A" "0,1,2,3"
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bitfld.long 0x00 3. "MAC_FULL_DUPLEX,PCS auto-negotiation duplex resolution" "0,1"
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bitfld.long 0x00 2. "MAN_DONE,The PHY management logic is idle (i.e. has completed)" "0,1"
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bitfld.long 0x00 1. "MDIO_IN,Returns status of the mdio_in pin" "0,1"
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bitfld.long 0x00 0. "PCS_LINK_STATE,Returns status of PCS link state" "0,1"
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rgroup.long 0x100C++0x03
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line.long 0x00 "USER_IO_REGISTER,Not presents"
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hexmask.long 0x00 0.--31. 1. "RSVD_31_0,Write ignore read 0"
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group.long 0x1010++0x03
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line.long 0x00 "DMA_CONFIG,DMA Configuration Register"
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bitfld.long 0x00 30. "DMA_ADDR_BUS_WIDTH_1,DMA address bus width" "0: 32b,1: 64b"
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bitfld.long 0x00 29. "TX_BD_EXTENDED_MODE_EN,Enable TX extended BD mode" "0,1"
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bitfld.long 0x00 28. "RX_BD_EXTENDED_MODE_EN,Enable RX extended BD mode" "0,1"
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bitfld.long 0x00 26. "FORCE_MAX_AMBA_BURST_TX,Force max length bursts on TX" "0,1"
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bitfld.long 0x00 25. "FORCE_MAX_AMBA_BURST_RX,Force max length bursts on RX" "0,1"
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bitfld.long 0x00 24. "FORCE_DISCARD_ON_ERR,Auto Discard RX pkts during lack of resource" "0,1"
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abitfld.long 0x00 16.--23. "RX_BUF_SIZE,DMA receive buffer size in external AMBA (AXI) system memory" "0x02=2: 128 byte,0x18=24: 1536 byte (1*max length frame/buffer),0xA0=160: 10240 byte (1*10K jumbo frame/buffer).."
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bitfld.long 0x00 13. "CRC_ERROR_REPORT,When the bit is set bit 16 of the receive buffer descriptor will represent FCS/CRC error (only if frames with FCS are copied to memory as enabled by bit 26 in the network config register)" "0,1"
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bitfld.long 0x00 12. "INFINITE_LAST_DBUF_SIZE_EN,Forces the DMA to consider the data buffer pointed to by last descriptor in the descriptor list to be of infinite size" "0,1"
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bitfld.long 0x00 11. "TX_PBUF_TCP_EN,N/A" "0,1"
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bitfld.long 0x00 10. "TX_PBUF_SIZE,N/A" "0,1"
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bitfld.long 0x00 8.--9. "RX_PBUF_SIZE,N/A" "0,1,2,3"
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bitfld.long 0x00 7. "ENDIAN_SWAP_PACKET,endian swap mode enable for packet data accesses" "0,1"
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bitfld.long 0x00 6. "ENDIAN_SWAP_MANAGEMENT,endian swap mode enable for management descriptor accesses" "0,1"
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bitfld.long 0x00 5. "HDR_DATA_SPLITTING_EN,Enable header data Splitting" "0,1"
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bitfld.long 0x00 0.--4. "AMBA_BURST_LENGTH,Selects the burst length to use on the AMBA (AHB/AXI) when transferring frame data" "0: Attempt to use bursts of up to 256,1: Always use SINGLE bursts,?..."
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group.long 0x1014++0x03
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line.long 0x00 "TRANSMIT_STATUS,This register when read provides details of the status of a transmit"
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bitfld.long 0x00 8. "RESP_NOT_OK123,bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK" "0,1"
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bitfld.long 0x00 7. "LATE_COLLISION_OCCURRED,Late collision occurred - only set if the condition occurs in gigabit mode as retry is not attempted" "0,1"
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newline
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bitfld.long 0x00 6. "TRANSMIT_UNDER_RUN123,Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable" "0,1"
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bitfld.long 0x00 5. "TRANSMIT_COMPLETE123,Transmit complete - set when a frame has been transmitted" "0,1"
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bitfld.long 0x00 4. "AMBA_ERROR123,Transmit frame corruption due to AMBA (AXI) errors" "0,1"
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rbitfld.long 0x00 3. "TRANSMIT_GO,Transmit go - if high transmit is active" "0,1"
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bitfld.long 0x00 2. "RETRY_LIMIT_EXCEEDED,Retry limit exceeded - cleared by writing a one to this bit" "0,1"
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bitfld.long 0x00 1. "COLLISION_OCCURRED,Collision occurred - set by the assertion of collision" "0,1"
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bitfld.long 0x00 0. "USED_BIT_READ,Used bit read - set when a transmit buffer descriptor is read with its used bit set" "0,1"
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group.long 0x1018++0x03
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line.long 0x00 "RECEIVE_Q_PTR,This register holds the start address of the receive buffer queue (receive buffers descriptor list)"
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hexmask.long 0x00 2.--31. 1. "DMA_RX_Q_PTR,Receive buffer queue base address - written with the address of the start of the receive queue"
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bitfld.long 0x00 0. "DMA_RX_DIS_Q,Disable queue if set to 1" "0,1"
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group.long 0x101C++0x03
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line.long 0x00 "TRANSMIT_Q_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list)"
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hexmask.long 0x00 2.--31. 1. "DMA_TX_Q_PTR,Transmit buffer queue base address - written with the address of the start of the transmit queue"
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bitfld.long 0x00 0. "DMA_TX_DIS_Q,Disable queue if set to 1" "0,1"
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group.long 0x1020++0x03
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line.long 0x00 "RECEIVE_STATUS,This register when read provides details of the status of a receive"
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bitfld.long 0x00 3. "RESP_NOT_OK1234,bresp not OK - set when the DMA block sees bresp/hresp not OK" "0,1"
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newline
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bitfld.long 0x00 2. "RECEIVE_OVERRUN123,Receive overrun - this bit is set if either the gem_dma RX FIFO or external RX FIFO were unable to store the receive frame due to a FIFO overflow or if the receive status reported by the gem_rx module to the gem_dma was not taken at.." "0,1"
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bitfld.long 0x00 1. "FRAME_RECEIVED,Frame received - one or more frames have been received and placed in memory" "0,1"
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bitfld.long 0x00 0. "BUFFER_NOT_AVAILABLE,Buffer not available - an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor" "0,1"
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group.long 0x1024++0x03
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line.long 0x00 "INT_STATUS,If not configured for priority queueing the GEM generates a single interrupt"
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bitfld.long 0x00 29. "TSU_TIMER_COMPARISON_INTERRUPT,TSU timer comparison interrupt" "0,1"
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rbitfld.long 0x00 28. "REMOVED_28,Write ignore read 0" "0,1"
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bitfld.long 0x00 27. "RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE,Receive LPI indication status bit change" "0,1"
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bitfld.long 0x00 26. "TSU_SECONDS_REGISTER_INCREMENT,TSU seconds register increment indicates the register has incremented" "0,1"
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bitfld.long 0x00 25. "PTP_PDELAY_RESP_FRAME_TRANSMITTED,PTP pdelay_resp frame transmitted indicates a PTP pdelay_resp frame has been transmitted" "0,1"
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newline
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bitfld.long 0x00 24. "PTP_PDELAY_REQ_FRAME_TRANSMITTED,PTP pdelay_req frame transmitted indicates a PTP pdelay_req frame has been transmitted" "0,1"
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newline
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bitfld.long 0x00 23. "PTP_PDELAY_RESP_FRAME_RECEIVED,PTP pdelay_resp frame received indicates a PTP pdelay_resp frame has been received" "0,1"
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newline
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bitfld.long 0x00 22. "PTP_PDELAY_REQ_FRAME_RECEIVED,PTP pdelay_req frame received indicates a PTP pdelay_req frame has been received" "0,1"
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bitfld.long 0x00 21. "PTP_SYNC_FRAME_TRANSMITTED,PTP sync frame transmitted indicates a PTP sync frame has been transmitted" "0,1"
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bitfld.long 0x00 20. "PTP_DELAY_REQ_FRAME_TRANSMITTED,PTP delay_req frame transmitted indicates a PTP delay_req frame has been transmitted" "0,1"
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bitfld.long 0x00 19. "PTP_SYNC_FRAME_RECEIVED,PTP sync frame received indicates a PTP sync frame has been received" "0,1"
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newline
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bitfld.long 0x00 18. "PTP_DELAY_REQ_FRAME_RECEIVED,PTP delay_req frame received indicates a PTP delay_req frame has been received" "0,1"
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rbitfld.long 0x00 17. "REMOVED_17,Write ignore read 0" "0,1"
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rbitfld.long 0x00 16. "REMOVED_16,Write ignore read 0" "0,1"
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rbitfld.long 0x00 15. "REMOVED_15,Write ignore read 0" "0,1"
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bitfld.long 0x00 14. "PAUSE_FRAME_TRANSMITTED,Pause frame transmitted - indicates a pause frame has been successfully transmitted after being initiated from the network control register or from the tx_pause control pin" "0,1"
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newline
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bitfld.long 0x00 13. "PAUSE_TIME_ELAPSED,Pause Time elapsed" "0,1"
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bitfld.long 0x00 12. "PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED,Pause frame with non-zero pause quantum received - indicates a valid pause has been received that has a non-zero pause quantum field" "0,1"
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bitfld.long 0x00 11. "RESP_NOT_OK,bresp not OK - set when the DMA block sees bresp not OK" "0,1"
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bitfld.long 0x00 10. "RECEIVE_OVERRUN,Receive overrun - set when the receive overrun status bit gets set" "0,1"
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rbitfld.long 0x00 9. "REMOVED_9,Write ignore read 0" "0,1"
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bitfld.long 0x00 7. "TRANSMIT_COMPLETE,Transmit complete - set when a frame has been transmitted" "0,1"
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bitfld.long 0x00 6. "AMBA_ERROR,Transmit frame corruption due to AMBA (AXI) error" "0,1"
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newline
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bitfld.long 0x00 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION,Retry limit exceeded or late collision - transmit error" "0,1"
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newline
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bitfld.long 0x00 4. "TRANSMIT_UNDER_RUN,Transmit under run - this interrupt is set if the transmitter was forced to terminate a frame that it has already began transmitting due to further data being unavailable" "0,1"
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newline
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bitfld.long 0x00 3. "TX_USED_BIT_READ,TX used bit read - set when a transmit buffer descriptor is read with its used bit set" "0,1"
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newline
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bitfld.long 0x00 2. "RX_USED_BIT_READ,RX used bit read - set when a receive buffer descriptor is read with its used bit set" "0,1"
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newline
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bitfld.long 0x00 1. "RECEIVE_COMPLETE,Receive complete - a frame has been stored in memory" "0,1"
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newline
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bitfld.long 0x00 0. "MANAGEMENT_FRAME_SENT,Management frame sent - the PHY maintenance register has completed its operation" "0,1"
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wgroup.long 0x1028++0x03
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line.long 0x00 "INT_ENABLE,At reset all interrupts are disabled"
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bitfld.long 0x00 29. "ENABLE_TSU_TIMER_COMPARISON_INTERRUPT,Enable TSU timer comparison interrupt" "0,1"
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bitfld.long 0x00 28. "UNUSED_28,Not used" "0,1"
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bitfld.long 0x00 27. "ENABLE_RX_LPI_INDICATION_INTERRUPT,Enable RX LPI indication interrupt" "0,1"
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newline
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bitfld.long 0x00 26. "ENABLE_TSU_SECONDS_REGISTER_INCREMENT,Enable TSU seconds register increment" "0,1"
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newline
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bitfld.long 0x00 25. "ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED,Enable PTP pdelay_resp frame transmitted" "0,1"
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newline
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bitfld.long 0x00 24. "ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED,Enable PTP pdelay_req frame transmitted" "0,1"
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newline
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bitfld.long 0x00 23. "ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED,Enable PTP pdelay_resp frame received" "0,1"
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newline
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bitfld.long 0x00 22. "ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED,Enable PTP pdelay_req frame received" "0,1"
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newline
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bitfld.long 0x00 21. "ENABLE_PTP_SYNC_FRAME_TRANSMITTED,Enable PTP sync frame transmitted" "0,1"
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newline
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bitfld.long 0x00 20. "ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED,Enable PTP delay_req frame transmitted" "0,1"
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newline
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bitfld.long 0x00 19. "ENABLE_PTP_SYNC_FRAME_RECEIVED,Enable PTP sync frame received" "0,1"
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newline
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bitfld.long 0x00 18. "ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED,Enable PTP delay_req frame received" "0,1"
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bitfld.long 0x00 17. "UNUSED_17,Not used" "0,1"
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bitfld.long 0x00 16. "UNUSED_16,Not used" "0,1"
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bitfld.long 0x00 15. "UNUSED_15,Not used" "0,1"
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bitfld.long 0x00 14. "ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT,Enable pause frame transmitted interrupt" "0,1"
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bitfld.long 0x00 13. "ENABLE_PAUSE_TIME_ZERO_INTERRUPT,Enable pause time zero interrupt" "0,1"
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newline
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bitfld.long 0x00 12. "ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT,Enable pause frame with non-zero pause quantum interrupt" "0,1"
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newline
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bitfld.long 0x00 11. "ENABLE_RESP_NOT_OK_INTERRUPT,Enable bresp not OK interrupt" "0,1"
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newline
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bitfld.long 0x00 10. "ENABLE_RECEIVE_OVERRUN_INTERRUPT,Enable receive overrun interrupt" "0,1"
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newline
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bitfld.long 0x00 9. "UNUSED_9,Not used" "0,1"
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bitfld.long 0x00 8. "UNUSED_8,Not used" "0,1"
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newline
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bitfld.long 0x00 7. "ENABLE_TRANSMIT_COMPLETE_INTERRUPT,Enable transmit complete interrupt" "0,1"
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newline
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bitfld.long 0x00 6. "ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Enable transmit frame corruption due to AMBA (AXI) error interrupt" "0,1"
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newline
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bitfld.long 0x00 5. "ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Enable retry limit exceeded or late collision interrupt" "0,1"
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newline
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bitfld.long 0x00 4. "ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT,Enable transmit buffer under run interrupt" "0,1"
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newline
|
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bitfld.long 0x00 3. "ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT,Enable transmit used bit read interrupt" "0,1"
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newline
|
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bitfld.long 0x00 2. "ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT,Enable receive used bit read interrupt" "0,1"
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newline
|
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bitfld.long 0x00 1. "ENABLE_RECEIVE_COMPLETE_INTERRUPT,Enable receive complete interrupt" "0,1"
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newline
|
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bitfld.long 0x00 0. "ENABLE_MANAGEMENT_DONE_INTERRUPT,Enable management done interrupt" "0,1"
|
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group.long 0x102C++0x03
|
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line.long 0x00 "INT_DISABLE,Writing a 1 to the relevant bit location disables that particular interrupt"
|
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rbitfld.long 0x00 31. "RSVD_31_31,N/A" "0,1"
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newline
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rbitfld.long 0x00 30. "RSVD_30_30,N/A" "0,1"
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newline
|
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bitfld.long 0x00 29. "DISABLE_TSU_TIMER_COMPARISON_INTERRUPT,'Disable TSU timer comparison interrupt.'" "0,1"
|
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newline
|
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bitfld.long 0x00 28. "UNUSED_28,Not used" "0,1"
|
|
newline
|
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bitfld.long 0x00 27. "DISABLE_RX_LPI_INDICATION_INTERRUPT,'Disable RX LPI indication interrupt'" "0,1"
|
|
newline
|
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bitfld.long 0x00 26. "DISABLE_TSU_SECONDS_REGISTER_INCREMENT,'Disable TSU seconds register increment'" "0,1"
|
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newline
|
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bitfld.long 0x00 25. "DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED,'Disable PTP pdelay_resp frame transmitted'" "0,1"
|
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newline
|
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bitfld.long 0x00 24. "DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED,'Disable PTP pdelay_req frame transmitted'" "0,1"
|
|
newline
|
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bitfld.long 0x00 23. "DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED,'Disable PTP pdelay_resp frame received'" "0,1"
|
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newline
|
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bitfld.long 0x00 22. "DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED,'Disable PTP pdelay_req frame received'" "0,1"
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newline
|
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bitfld.long 0x00 21. "DISABLE_PTP_SYNC_FRAME_TRANSMITTED,'Disable PTP sync frame transmitted '" "0,1"
|
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newline
|
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bitfld.long 0x00 20. "DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED,'Disable PTP delay_req frame transmitted '" "0,1"
|
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newline
|
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bitfld.long 0x00 19. "DISABLE_PTP_SYNC_FRAME_RECEIVED,'Disable PTP sync frame received'" "0,1"
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newline
|
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bitfld.long 0x00 18. "DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED,'Disable PTP delay_req frame received'" "0,1"
|
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|
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bitfld.long 0x00 17. "UNUSED_17,Not used" "0,1"
|
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|
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bitfld.long 0x00 16. "UNUSED_16,Not used" "0,1"
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|
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bitfld.long 0x00 15. "UNUSED_15,Not used" "0,1"
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|
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bitfld.long 0x00 14. "DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT,'Disable pause frame transmitted interrupt'" "0,1"
|
|
newline
|
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bitfld.long 0x00 13. "DISABLE_PAUSE_TIME_ZERO_INTERRUPT,'Disable pause time zero interrupt'" "0,1"
|
|
newline
|
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bitfld.long 0x00 12. "DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT,'Disable pause frame with non-zero pause quantum interrupt'" "0,1"
|
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newline
|
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bitfld.long 0x00 11. "DISABLE_RESP_NOT_OK_INTERRUPT,'Disable bresp/hresp not OK interrupt'" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "DISABLE_RECEIVE_OVERRUN_INTERRUPT,'Disable receive overrun interrupt'" "0,1"
|
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newline
|
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bitfld.long 0x00 9. "UNUSED_9,Not used" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "UNUSED_8,Not used" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "DISABLE_TRANSMIT_COMPLETE_INTERRUPT,'Disable transmit complete interrupt'" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,'Disable transmit frame corruption due to AMBA (AHB/AXI) error interrupt'" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,'Disable retry limit exceeded or late collision interrupt'" "0,1"
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bitfld.long 0x00 4. "DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT,'Disable transmit buffer under run interrupt'" "0,1"
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bitfld.long 0x00 3. "DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT,'Disable transmit used bit read interrupt'" "0,1"
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|
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bitfld.long 0x00 2. "DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT,'Disable receive used bit read interrupt'" "0,1"
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|
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bitfld.long 0x00 1. "DISABLE_RECEIVE_COMPLETE_INTERRUPT,'Disable receive complete interrupt'" "0,1"
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|
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bitfld.long 0x00 0. "DISABLE_MANAGEMENT_DONE_INTERRUPT,'Disable management done interrupt'" "0,1"
|
|
rgroup.long 0x1030++0x03
|
|
line.long 0x00 "INT_MASK,The interrupt mask register is a read only register indicating which interrupts are masked"
|
|
bitfld.long 0x00 29. "TSU_TIMER_COMPARISON_MASK,Enable TSU timer comparison interrupt mask" "0,1"
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|
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bitfld.long 0x00 28. "UNUSED_28,unused" "0,1"
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bitfld.long 0x00 27. "RX_LPI_INDICATION_MASK,A read of this register returns the value of the RX LPI indication mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 26. "TSU_SECONDS_REGISTER_INCREMENT_MASK,A read of this register returns the value of the TSU seconds register increment mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 25. "PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK,A read of this register returns the value of the PTP pdelay_resp frame transmitted mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 24. "PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK,A read of this register returns the value of the PTP pdelay_req frame transmitted mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 23. "PTP_PDELAY_RESP_FRAME_RECEIVED_MASK,A read of this register returns the value of the PTP pdelay_resp frame received mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 22. "PTP_PDELAY_REQ_FRAME_RECEIVED_MASK,A read of this register returns the value of the PTP pdelay_req frame received mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 21. "PTP_SYNC_FRAME_TRANSMITTED_MASK,A read of this register returns the value of the PTP sync frame transmitted mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 20. "PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK,A read of this register returns the value of the PTP delay_req frame transmitted mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 19. "PTP_SYNC_FRAME_RECEIVED_MASK,A read of this register returns the value of the PTP sync frame received mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 18. "PTP_DELAY_REQ_FRAME_RECEIVED_MASK,A read of this register returns the value of the PTP delay_req frame received mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 17. "UNUSED_17,Not used" "0,1"
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bitfld.long 0x00 16. "UNUSED_16,Not used" "0,1"
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bitfld.long 0x00 15. "UNUSED_15,Not used" "0,1"
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bitfld.long 0x00 14. "PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK,pause frame transmitted interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 13. "PAUSE_TIME_ZERO_INTERRUPT_MASK,pause time zero interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 12. "PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK,pause frame with non-zero pause quantum interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 11. "RESP_NOT_OK_INTERRUPT_MASK,bresp not OK interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 10. "RECEIVE_OVERRUN_INTERRUPT_MASK,receive overrun interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 9. "UNUSED_9,Not used" "0,1"
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bitfld.long 0x00 8. "UNUSED_8,Not used" "0,1"
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bitfld.long 0x00 7. "TRANSMIT_COMPLETE_INTERRUPT_MASK,transmit complete interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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|
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|
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bitfld.long 0x00 6. "AMBA_ERROR_INTERRUPT_MASK,transmit frame corruption due to AMBA (AXI) error interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK,A read of this register returns the value of the retry limit exceeded or late collision (gigabit mode only) interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 4. "TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK,transmit buffer under run interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 3. "TRANSMIT_USED_BIT_READ_INTERRUPT_MASK,transmit used bit read interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 2. "RECEIVE_USED_BIT_READ_INTERRUPT_MASK,receive used bit read interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x00 1. "RECEIVE_COMPLETE_INTERRUPT_MASK,receive complete interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
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|
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bitfld.long 0x00 0. "MANAGEMENT_DONE_INTERRUPT_MASK,management done interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
group.long 0x1034++0x03
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line.long 0x00 "PHY_MANAGEMENT,The PHY maintenance register is implemented as a shift register"
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bitfld.long 0x00 31. "WRITE0,Must be written with 0" "0,1"
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bitfld.long 0x00 30. "WRITE1,Must be written to 1 for a valid Clause 22 frame and to 0 for a valid Clause 45 frame" "0,1"
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bitfld.long 0x00 28.--29. "OPERATION,Operation" "0,1,2,3"
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bitfld.long 0x00 23.--27. "PHY_ADDRESS,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 18.--22. "REGISTER_ADDRESS,Register address - specifies the register in the PHY to access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--17. "WRITE10,Must be written with 10" "0,1,2,3"
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hexmask.long.word 0x00 0.--15. 1. "PHY_WRITE_READ_DATA,For a write operation this is written with the data to be written to the PHY"
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|
rgroup.long 0x1038++0x03
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line.long 0x00 "PAUSE_TIME,Received Pause Quantum Register"
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hexmask.long.word 0x00 0.--15. 1. "QUANTUM,Received pause quantum - stores the current value of the received pause quantum register which is decremented every 512 bit times"
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group.long 0x103C++0x03
|
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line.long 0x00 "TX_PAUSE_QUANTUM,Transmit Pause Quantum Register"
|
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hexmask.long.word 0x00 16.--31. 1. "QUANTUM_P1,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 1"
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|
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|
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hexmask.long.word 0x00 0.--15. 1. "QUANTUM,Transmit pause quantum - written with the pause quantum value for pause frame transmission"
|
|
group.long 0x1040++0x03
|
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line.long 0x00 "PBUF_TXCUTTHRU,Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode"
|
|
bitfld.long 0x00 31. "DMA_TX_CUTTHRU,Enable TX partial store and forward operation" "0,1"
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hexmask.long.word 0x00 0.--8. 1. "DMA_TX_CUTTHRU_THRESHOLD,Watermark value"
|
|
group.long 0x1044++0x03
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line.long 0x00 "PBUF_RXCUTTHRU,RX Partial Store and Forward"
|
|
bitfld.long 0x00 31. "DMA_RX_CUTTHRU,Enable RX partial store and forward operation" "0,1"
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|
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|
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hexmask.long.byte 0x00 0.--7. 1. "DMA_RX_CUTTHRU_THRESHOLD,Watermark value"
|
|
group.long 0x1048++0x03
|
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line.long 0x00 "JUMBO_MAX_LENGTH,Maximum Jumbo Frame Size"
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hexmask.long.word 0x00 0.--13. 1. "JUMBO_MAX_LENGTH,Maximum Jumbo Frame Size - resets to the gem_jumbo_max_length define value"
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|
rgroup.long 0x104C++0x03
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line.long 0x00 "EXTERNAL_FIFO_INTERFACE,Not presents"
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hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
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|
group.long 0x1054++0x03
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line.long 0x00 "AXI_MAX_PIPELINE,Used to set the maximum amount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels"
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bitfld.long 0x00 16. "USE_AW2B_FILL,For the write issuing capability as defined in bits 15:8 of this register select whether the max number of transactions operates between the AW to W AXI channel or the AW to B channel" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "AW2W_MAX_PIPELINE,Defines the maximum number of outstanding AXI write requests that can be issued by the DMA via the AW channel"
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hexmask.long.byte 0x00 0.--7. 1. "AR2R_MAX_PIPELINE,Defines the maximum number of outstanding AXI read requests that can be issued by the DMA via the AR channel"
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rgroup.long 0x1058++0x03
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line.long 0x00 "RSC_CONTROL,Not presents"
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hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
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group.long 0x105C++0x03
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line.long 0x00 "INT_MODERATION,Used to moderate the number of transmit and receive complete interrupts issued"
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hexmask.long.byte 0x00 16.--23. 1. "TX_INT_MODERATION,Count of 800ns periods before bit 7 is set in the interrupt status register after a frame is transmitted"
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hexmask.long.byte 0x00 0.--7. 1. "RX_INT_MODERATION,Count of 800ns periods before bit 1 is set in the interrupt status register after a frame is received"
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group.long 0x1060++0x03
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line.long 0x00 "SYS_WAKE_TIME,Used to pause transmission after deassertion of tx_lpi_en"
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hexmask.long.word 0x00 0.--15. 1. "SYS_WAKE_TIME,Count of 64ns 320ns or 3200ns intervals before transmission starts after deassertion of tx_lpi_en (each interval is equivalent to eight tx_clk periods and so varies with data rate)"
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group.long 0x1080++0x03
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line.long 0x00 "HASH_BOTTOM,The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames"
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hexmask.long 0x00 0.--31. 1. "ADDRESS_HASH_B,The first 32 bits of the hash address register"
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group.long 0x1084++0x03
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line.long 0x00 "HASH_TOP,Hash Register Top (63 to 32 bits)"
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hexmask.long 0x00 0.--31. 1. "ADDRESS_HASH_T,The remaining 32 bits of the hash address register"
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group.long 0x1088++0x03
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line.long 0x00 "SPEC_ADD1_BOTTOM,The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written"
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hexmask.long 0x00 0.--31. 1. "ADDRESS_ADD1_B,'Least significant 32 bits of the destination address that is bits 31:0"
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group.long 0x108C++0x03
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line.long 0x00 "SPEC_ADD1_TOP,Specific Address Top"
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bitfld.long 0x00 16. "FILTER_TYPE,This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame" "0,1"
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hexmask.long.word 0x00 0.--15. 1. "ADDRESS_TOP,Specific address 1"
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group.long 0x1090++0x03
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line.long 0x00 "SPEC_ADD2_BOTTOM,The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written"
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hexmask.long 0x00 0.--31. 1. "ADDRESS_BOTTOM,Least significant 32 bits of the destination address that is bits 31:0"
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group.long 0x1094++0x03
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line.long 0x00 "SPEC_ADD2_TOP,Specific Address Top"
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bitfld.long 0x00 24.--29. "FILTER_BYTE_MASK,When high the associated byte of the specific address will not be compared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16. "FILTER_TYPE,This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame" "0,1"
|
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newline
|
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hexmask.long.word 0x00 0.--15. 1. "ADDRESS_TOP,Specific address 1"
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group.long 0x1098++0x03
|
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line.long 0x00 "SPEC_ADD3_BOTTOM,The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written"
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hexmask.long 0x00 0.--31. 1. "ADDRESS_BOTTOM,Least significant 32 bits of the destination address that is bits 31:0"
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group.long 0x109C++0x03
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line.long 0x00 "SPEC_ADD3_TOP,Specific Address Top"
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bitfld.long 0x00 24.--29. "FILTER_BYTE_MASK,When high the associated byte of the specific address will not be compared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
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bitfld.long 0x00 16. "FILTER_TYPE,This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame" "0,1"
|
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newline
|
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hexmask.long.word 0x00 0.--15. 1. "ADDRESS_TOP,Specific address 1"
|
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group.long 0x10A0++0x03
|
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line.long 0x00 "SPEC_ADD4_BOTTOM,The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written"
|
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hexmask.long 0x00 0.--31. 1. "ADDRESS_BOTTOM,Least significant 32 bits of the destination address that is bits 31:0"
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group.long 0x10A4++0x03
|
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line.long 0x00 "SPEC_ADD4_TOP,Specific Address Top"
|
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bitfld.long 0x00 24.--29. "FILTER_BYTE_MASK,When high the associated byte of the specific address will not be compared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
|
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bitfld.long 0x00 16. "FILTER_TYPE,This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame" "0,1"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "ADDRESS_TOP,Specific address 1"
|
|
group.long 0x10A8++0x03
|
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line.long 0x00 "SPEC_TYPE1,Type ID Match 1"
|
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bitfld.long 0x00 31. "ENABLE_COPY,Enable copying of type ID match 1 matched frames" "0,1"
|
|
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|
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hexmask.long.word 0x00 0.--15. 1. "MATCH,Type ID match 1"
|
|
group.long 0x10AC++0x03
|
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line.long 0x00 "SPEC_TYPE2,Type ID Match 2"
|
|
bitfld.long 0x00 31. "ENABLE_COPY,Enable copying of type ID match 2 matched frames" "0,1"
|
|
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|
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hexmask.long.word 0x00 0.--15. 1. "MATCH,Type ID match 2"
|
|
group.long 0x10B0++0x03
|
|
line.long 0x00 "SPEC_TYPE3,Type ID Match 3"
|
|
bitfld.long 0x00 31. "ENABLE_COPY,Enable copying of type ID match 3 matched frames" "0,1"
|
|
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|
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hexmask.long.word 0x00 0.--15. 1. "MATCH,Type ID match 3"
|
|
group.long 0x10B4++0x03
|
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line.long 0x00 "SPEC_TYPE4,Type ID Match 4"
|
|
bitfld.long 0x00 31. "ENABLE_COPY,Enable copying of type ID match 4 matched frames" "0,1"
|
|
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|
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hexmask.long.word 0x00 0.--15. 1. "MATCH,Type ID match 4"
|
|
group.long 0x10B8++0x03
|
|
line.long 0x00 "WOL_REGISTER,Wake on LAN Register"
|
|
bitfld.long 0x00 19. "WOL_MASK_3,Wake on LAN multicast hash event enable" "0,1"
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|
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|
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bitfld.long 0x00 18. "WOL_MASK_2,Wake on LAN specific address register 1 event enable" "0,1"
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|
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|
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bitfld.long 0x00 17. "WOL_MASK_1,Wake on LAN ARP request event enable" "0,1"
|
|
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|
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bitfld.long 0x00 16. "WOL_MASK_0,Wake on LAN magic packet event enable" "0,1"
|
|
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|
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hexmask.long.word 0x00 0.--15. 1. "ADDR,Wake on LAN ARP request IP address"
|
|
group.long 0x10BC++0x03
|
|
line.long 0x00 "STRETCH_RATIO,IPG stretch register"
|
|
hexmask.long.word 0x00 0.--15. 1. "IPG_STRETCH,IPG Stretch"
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "STACKED_VLAN,Stacked VLAN Register"
|
|
bitfld.long 0x00 31. "ENABLE_PROCESSING,Enable stacked VLAN processing mode" "0,1"
|
|
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|
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hexmask.long.word 0x00 0.--15. 1. "MATCH,User defined VLAN_TYPE field"
|
|
group.long 0x10C4++0x03
|
|
line.long 0x00 "TX_PFC_PAUSE,Transmit PFC Pause Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "VECTOR,Priority Vector Pause Size"
|
|
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|
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hexmask.long.byte 0x00 0.--7. 1. "VECTOR_ENABLE,Priority Vector Enable"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "MASK_ADD1_BOTTOM,Specific Address Mask 1 Bottom (31 to 0 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS_MASK_BOTTOM,Specific Address Mask"
|
|
group.long 0x10CC++0x03
|
|
line.long 0x00 "MASK_ADD1_TOP,Specific Address Mask 1 Top (47 to 32 bits)"
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRESS_MASK_TOP,Specific Address Mask"
|
|
group.long 0x10D0++0x03
|
|
line.long 0x00 "DMA_ADDR_OR_MASK,Receive DMA Data Buffer Address Mask"
|
|
bitfld.long 0x00 28.--31. "MASK_VALUE_DA,Data Buffer Address Mask Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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bitfld.long 0x00 0.--3. "MASK_ENABLE,Data Buffer Address Mask Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10D4++0x03
|
|
line.long 0x00 "RX_PTP_UNICAST,PTP RX unicast IP destination address"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS_UNICAST,Unicast IP destination address"
|
|
group.long 0x10D8++0x03
|
|
line.long 0x00 "TX_PTP_UNICAST,PTP TX unicast IP destination address"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS_UNICAST,Unicast IP destination address"
|
|
group.long 0x10DC++0x03
|
|
line.long 0x00 "TSU_NSEC_CMP,TSU timer comparison value nanoseconds"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. "COMPARISON_NSEC,TSU timer comparison value (ns)"
|
|
group.long 0x10E0++0x03
|
|
line.long 0x00 "TSU_SEC_CMP,TSU timer comparison value seconds (31 to 0 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "COMPARISON_SEC,TSU timer comparison value (s)"
|
|
group.long 0x10E4++0x03
|
|
line.long 0x00 "TSU_MSB_SEC_CMP,TSU timer comparison value seconds (47 to 32 bits)"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMPARISON_MSB_SEC,TSU timer comparison value (s)"
|
|
rgroup.long 0x10E8++0x03
|
|
line.long 0x00 "TSU_PTP_TX_MSB_SEC,PTP Event Frame Transmitted Seconds Register (47 to 32 bits)"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMER_SECONDS,PTP Event Frame TX Seconds"
|
|
rgroup.long 0x10EC++0x03
|
|
line.long 0x00 "TSU_PTP_RX_MSB_SEC,PTP Event Frame Received Seconds Register (47 to 32 bits)"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMER_SECONDS,PTP Event Frame TX Seconds"
|
|
rgroup.long 0x10F0++0x03
|
|
line.long 0x00 "TSU_PEER_TX_MSB_SEC,PTP Peer Event Frame Transmitted Seconds Register (47 to 32 bits)"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMER_SECONDS,PTP Peer Event Frame TX Seconds"
|
|
rgroup.long 0x10F4++0x03
|
|
line.long 0x00 "TSU_PEER_RX_MSB_SEC,PTP Peer Event Frame Received Seconds Register (47 to 32 bits)"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMER_SECONDS,PTP Peer Event Frame RX Seconds"
|
|
group.long 0x10F8++0x03
|
|
line.long 0x00 "DPRAM_FILL_DBG,The fill levels for the TX & RX packet buffers can be read using this register including the fill level for each queue in the TX direction"
|
|
hexmask.long.word 0x00 16.--31. 1. "DMA_TX_RX_FILL_LEVEL,Fill Level - TX or RX packet buffer fill level selected by the tx_q_fill_level_select and tx_rx_fill_level_select registers"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DMA_TX_Q_FILL_LEVEL_SELECT,TX queue fill level select - select what TX queue to report fill levels for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA_TX_RX_FILL_LEVEL_SELECT,TX/RX Fill Level select - report the fill level for the TX or RX packet buffer" "0,1"
|
|
rgroup.long 0x10FC++0x03
|
|
line.long 0x00 "REVISION_REG,This register indicates a Cadence module identification number and module revision"
|
|
bitfld.long 0x00 28.--31. "FIX_NUMBER,Fix number - incremented for fix releases" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "MODULE_IDENTIFICATION_NUMBER,Module identification number - for the GEM this value is fixed"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MODULE_REVISION,Module revision - fixed value specific to the revision of the design which is incremented for each non-fix release of the IP"
|
|
rgroup.long 0x1100++0x03
|
|
line.long 0x00 "OCTETS_TXED_BOTTOM,Octets Transmitted lower bits (31 to 0 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_BOTTOM,Transmitted octets in frame without errors [31:0]"
|
|
rgroup.long 0x1104++0x03
|
|
line.long 0x00 "OCTETS_TXED_TOP,Octets Transmitted higher bits (47 to 32 bits)"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT_TOP,Transmitted octets in frame without errors [47:32]"
|
|
rgroup.long 0x1108++0x03
|
|
line.long 0x00 "FRAMES_TXED_OK,Frames Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_OK,Frames transmitted without error"
|
|
rgroup.long 0x110C++0x03
|
|
line.long 0x00 "BROADCAST_TXED,Broadcast Frames Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_BROADCAST,Broadcast frames transmitted without error"
|
|
rgroup.long 0x1110++0x03
|
|
line.long 0x00 "MULTICAST_TXED,Multicast Frames Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_MULTICAST,Multicast frames transmitted without error"
|
|
rgroup.long 0x1114++0x03
|
|
line.long 0x00 "PAUSE_FRAMES_TXED,Pause Frames Transmitted"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT_PAUSE,Transmitted pause frames - a 16 bit register counting the number of pause frames transmitted"
|
|
rgroup.long 0x1118++0x03
|
|
line.long 0x00 "FRAMES_TXED_64,64 Byte Frames Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_64,64 byte frames transmitted without error"
|
|
rgroup.long 0x111C++0x03
|
|
line.long 0x00 "FRAMES_TXED_65,65 to 127 Byte Frames Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_65,65 to127 byte frames transmitted without error"
|
|
rgroup.long 0x1120++0x03
|
|
line.long 0x00 "FRAMES_TXED_128,128 to 255 Byte Frames Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_128,128 to 255 byte frames transmitted without error"
|
|
rgroup.long 0x1124++0x03
|
|
line.long 0x00 "FRAMES_TXED_256,256 to 511 Byte Frames Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_256,256 to 511 byte frames transmitted without error"
|
|
rgroup.long 0x1128++0x03
|
|
line.long 0x00 "FRAMES_TXED_512,512 to 1023 Byte Frames Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_512,512 to 1023 byte frames transmitted without error"
|
|
rgroup.long 0x112C++0x03
|
|
line.long 0x00 "FRAMES_TXED_1024,1024 to 1518 Byte Frames Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_1024,1024 to 1518 byte frames transmitted without error"
|
|
rgroup.long 0x1130++0x03
|
|
line.long 0x00 "FRAMES_TXED_1519,Greater Than 1518 Byte Frames Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_1519,Greater than 1518 byte frames transmitted without error"
|
|
rgroup.long 0x1134++0x03
|
|
line.long 0x00 "TX_UNDERRUNS,Transmit Under Runs"
|
|
hexmask.long.word 0x00 0.--9. 1. "COUNT_UN,Transmit under runs - a 10 bit register counting the number of frames not transmitted due to a transmit under run"
|
|
rgroup.long 0x1138++0x03
|
|
line.long 0x00 "SINGLE_COLLISIONS,Single Collision Frames"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "COUNT14,Single collision frames - an 18 bit register counting the number of frames experiencing a single collision before being successfully transmitted i.e"
|
|
rgroup.long 0x113C++0x03
|
|
line.long 0x00 "MULTIPLE_COLLISIONS,Multiple Collision Frames"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "COUNT15,Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted i.e"
|
|
rgroup.long 0x1140++0x03
|
|
line.long 0x00 "EXCESSIVE_COLLISIONS,Excessive Collisions"
|
|
hexmask.long.word 0x00 0.--9. 1. "COUNT16,Excessive collisions - a 10 bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions"
|
|
rgroup.long 0x1144++0x03
|
|
line.long 0x00 "LATE_COLLISIONS,Late Collisions"
|
|
hexmask.long.word 0x00 0.--9. 1. "COUNT17,Late collisions - a 10 bit register counting the number of late collision occurring after the slot time (512 bits) has expired"
|
|
rgroup.long 0x1148++0x03
|
|
line.long 0x00 "DEFERRED_FRAMES,Deferred Transmission Frames"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "COUNT18,Deferred transmission frames - an 18 bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission"
|
|
rgroup.long 0x114C++0x03
|
|
line.long 0x00 "CRS_ERRORS,Carrier Sense Errors"
|
|
hexmask.long.word 0x00 0.--9. 1. "COUNT19,Carrier sense errors - a 10 bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no under run)"
|
|
rgroup.long 0x1150++0x03
|
|
line.long 0x00 "OCTETS_RXED_BOTTOM,Octets Received (31 to 0 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_BOTTOM,Received octets in frame without errors [31:0]"
|
|
rgroup.long 0x1154++0x03
|
|
line.long 0x00 "OCTETS_RXED_TOP,Octets Received (47 to 32 bits)"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT_TOP,Received octets in frame without errors [47:32]"
|
|
rgroup.long 0x1158++0x03
|
|
line.long 0x00 "FRAMES_RXED_OK,Frames Received"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_OK,Frames received without error"
|
|
rgroup.long 0x115C++0x03
|
|
line.long 0x00 "BROADCAST_RXED,Broadcast Frames Received"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_BROADCAST,Broadcast frames received without error"
|
|
rgroup.long 0x1160++0x03
|
|
line.long 0x00 "MULTICAST_RXED,Multicast Frames Received"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_MULTICAST,Multicast frames received without error"
|
|
rgroup.long 0x1164++0x03
|
|
line.long 0x00 "PAUSE_FRAMES_RXED,Pause Frames Received"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT_PAUSE,Received pause frames - a 16 bit register counting the number of pause frames received without error"
|
|
rgroup.long 0x1168++0x03
|
|
line.long 0x00 "FRAMES_RXED_64,64 Byte Frames Received"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_64,64 byte frames received without error"
|
|
rgroup.long 0x116C++0x03
|
|
line.long 0x00 "FRAMES_RXED_65,65 to 127 Byte Frames Received"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_65,65 to 127 byte frames received without error"
|
|
rgroup.long 0x1170++0x03
|
|
line.long 0x00 "FRAMES_RXED_128,128 to 255 Byte Frames Received"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_128,128 to 255 byte frames received without error"
|
|
rgroup.long 0x1174++0x03
|
|
line.long 0x00 "FRAMES_RXED_256,256 to 511 Byte Frames Received"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_256,256 to 511 byte frames received without error"
|
|
rgroup.long 0x1178++0x03
|
|
line.long 0x00 "FRAMES_RXED_512,512 to 1023 Byte Frames Received"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_512,512 to 1023 byte frames received without error"
|
|
rgroup.long 0x117C++0x03
|
|
line.long 0x00 "FRAMES_RXED_1024,1024 to 1518 Byte Frames Received"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_1024,1024 to 1518 byte frames received without error"
|
|
rgroup.long 0x1180++0x03
|
|
line.long 0x00 "FRAMES_RXED_1519,1519 to maximum Byte Frames Received"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT_1519,1519 to maximum byte frames received without error"
|
|
rgroup.long 0x1184++0x03
|
|
line.long 0x00 "UNDERSIZE_FRAMES,Undersized Frames Received"
|
|
hexmask.long.word 0x00 0.--9. 1. "COUNT_UNDERSIZE,Undersize frames received - a 10 bit register counting the number of frames received less than 64 bytes in length (10/100 mode or gigabit mode full duplex) that do not have either a CRC error or an alignment error"
|
|
rgroup.long 0x1188++0x03
|
|
line.long 0x00 "EXCESSIVE_RX_LENGTH,Oversize Frames Received"
|
|
hexmask.long.word 0x00 0.--9. 1. "COUNT_OVERSIZE,Oversize frames received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 bytes if bit 8 is set in network configuration register 10 240 bytes if bit 3 is set in the network configuration register) in.."
|
|
rgroup.long 0x118C++0x03
|
|
line.long 0x00 "RX_JABBERS,Jabbers Received"
|
|
hexmask.long.word 0x00 0.--9. 1. "COUNT_JABBERS,Jabbers received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register 10 240 bytes if bit 3 is set in the network configuration register) in length and have.."
|
|
rgroup.long 0x1190++0x03
|
|
line.long 0x00 "FCS_ERRORS,Frame Check Sequence Errors"
|
|
hexmask.long.word 0x00 0.--9. 1. "COUNT_FCS_ERR,Frame check sequence errors - a 10 bit register counting frames that are an integral number of bytes have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register 10 240 bytes if bit 3 is set.."
|
|
rgroup.long 0x1194++0x03
|
|
line.long 0x00 "RX_LENGTH_ERRORS,Length Field Frame Errors"
|
|
hexmask.long.word 0x00 0.--9. 1. "COUNT_LENGTH_ERR,Length field frame errors - this 10-bit register counts the number of frames received that have a measured length shorter than that extracted from the length field (bytes 13 and 14)"
|
|
rgroup.long 0x1198++0x03
|
|
line.long 0x00 "RX_SYMBOL_ERRORS,Receive Symbol Errors"
|
|
hexmask.long.word 0x00 0.--9. 1. "COUNT_SYMBOL_ERR,Receive symbol errors - a 10-bit register counting the number of frames that had rx_er asserted during reception"
|
|
rgroup.long 0x119C++0x03
|
|
line.long 0x00 "ALIGNMENT_ERRORS,Alignment Errors"
|
|
hexmask.long.word 0x00 0.--9. 1. "COUNT_ALIGNMENT_ERROR,Alignment errors - a 10 bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if.."
|
|
rgroup.long 0x11A0++0x03
|
|
line.long 0x00 "RX_RESOURCE_ERRORS,Receive Resource Errors"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "COUNT_RESOURCE_ERR,Receive resource errors - an 18 bit register counting the number of frames that were successfully received by the MAC (correct address matched frame and adequate slot time) but could not be copied to memory because no receive buffer.."
|
|
rgroup.long 0x11A4++0x03
|
|
line.long 0x00 "RX_OVERRUNS,Receive Overruns"
|
|
hexmask.long.word 0x00 0.--9. 1. "COUNT_OVERRUN,Receive overruns - a 10 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive overrun"
|
|
rgroup.long 0x11A8++0x03
|
|
line.long 0x00 "RX_IP_CK_ERRORS,IP Header Checksum Errors"
|
|
hexmask.long.byte 0x00 0.--7. 1. "COUNT_IPCK_ERR,IP header checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect IP header checksum but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240.."
|
|
rgroup.long 0x11AC++0x03
|
|
line.long 0x00 "RX_TCP_CK_ERRORS,TCP Checksum Errors"
|
|
hexmask.long.byte 0x00 0.--7. 1. "COUNT_TCPCK_ERR,TCP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect TCP checksum but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3.."
|
|
rgroup.long 0x11B0++0x03
|
|
line.long 0x00 "RX_UDP_CK_ERRORS,UDP Checksum Errors"
|
|
hexmask.long.byte 0x00 0.--7. 1. "COUNT_UDPCK_ERR,UDP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect UDP checksum but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3.."
|
|
rgroup.long 0x11B4++0x03
|
|
line.long 0x00 "AUTO_FLUSHED_PKTS,Receive DMA Flushed Packets"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT_FLUSHED,Flushed RX packets counter"
|
|
group.long 0x11BC++0x03
|
|
line.long 0x00 "TSU_TIMER_INCR_SUB_NSEC,1588 Timer Increment Register sub nsec"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SUB_NS_INCR_LSB,These are the least significant bits [7:0] of the sub-ns value by which the 1588 timer will be incremented each clock cycle"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "SUB_NS_INCR,These are the most significant bits [23:8] of the sub-ns value by which the 1588 timer will be incremented each clock cycle"
|
|
group.long 0x11C0++0x03
|
|
line.long 0x00 "TSU_TIMER_MSB_SEC,1588 Timer Seconds Register (47 to 32 bits)"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMER_MSB_SEC,TSU timer value (s)"
|
|
rgroup.long 0x11C4++0x03
|
|
line.long 0x00 "TSU_STROBE_MSB_SEC,1588 Timer Sync Strobe Seconds Register (47 to 32 bits)"
|
|
hexmask.long.word 0x00 0.--15. 1. "STROBE_MSB_SEC,1588 Timer Sync Strobe Seconds"
|
|
rgroup.long 0x11C8++0x03
|
|
line.long 0x00 "TSU_STROBE_SEC,1588 Timer Sync Strobe Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "STROBE_SEC,1588 Timer Sync Strobe Seconds"
|
|
rgroup.long 0x11CC++0x03
|
|
line.long 0x00 "TSU_STROBE_NSEC,1588 Timer Sync Strobe Nanoseconds Register"
|
|
hexmask.long 0x00 0.--29. 1. "STROBE_NSEC,1588 Timer Sync Strobe Nanoseconds"
|
|
group.long 0x11D0++0x03
|
|
line.long 0x00 "TSU_TIMER_SEC,1588 Timer Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "TIMER_SEC,1588 Timer Seconds Register"
|
|
group.long 0x11D4++0x03
|
|
line.long 0x00 "TSU_TIMER_NSEC,1588 Timer Nanoseconds Register"
|
|
hexmask.long 0x00 0.--29. 1. "TIMER_NSEC,Timer count in nanoseconds"
|
|
wgroup.long 0x11D8++0x03
|
|
line.long 0x00 "TSU_TIMER_ADJUST,This register is used to adjust the value of the timer in the TSU"
|
|
bitfld.long 0x00 31. "ADD_SUBTRACT,Write as one to subtract from the 1588 timer" "0,1"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "INCREMENT_VALUE,Timer increment value"
|
|
group.long 0x11DC++0x03
|
|
line.long 0x00 "TSU_TIMER_INCR,1588 Timer Increment Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "NUM_INCS,Number of incs before alt inc"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "ALT_NS_INCR,Alternative nanoseconds count"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "NS_INCREMENT,A count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle"
|
|
rgroup.long 0x11E0++0x03
|
|
line.long 0x00 "TSU_PTP_TX_SEC,PTP Event Frame Transmitted Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "TIMER_PTP_SEC,PTP Event Frame Transmitted Seconds"
|
|
rgroup.long 0x11E4++0x03
|
|
line.long 0x00 "TSU_PTP_TX_NSEC,PTP Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x00 0.--29. 1. "TIMER_PTP_NSEC,PTP Event Frame Transmitted Nanoseconds"
|
|
rgroup.long 0x11E8++0x03
|
|
line.long 0x00 "TSU_PTP_RX_SEC,PTP Event Frame Received Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "TIMER_PTP_SEC,PTP Event Frame Received Seconds"
|
|
rgroup.long 0x11EC++0x03
|
|
line.long 0x00 "TSU_PTP_RX_NSEC,PTP Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x00 0.--29. 1. "TIMER_PTP_NSEC,PTP Event Frame Received Nanoseconds"
|
|
rgroup.long 0x11F0++0x03
|
|
line.long 0x00 "TSU_PEER_TX_SEC,PTP Peer Event Frame Transmitted Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "TIMER_PEER_SEC,PTP Peer Event Frame Received Seconds"
|
|
rgroup.long 0x11F4++0x03
|
|
line.long 0x00 "TSU_PEER_TX_NSEC,PTP Peer Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x00 0.--29. 1. "TIMER_PEER_NSEC,PTP Peer Event Frame Transmitted Nanoseconds"
|
|
rgroup.long 0x11F8++0x03
|
|
line.long 0x00 "TSU_PEER_RX_SEC,PTP Peer Event Frame Received Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x00 0.--31. 1. "TIMER_PEER_SEC,PTP Peer Event Frame Received Seconds"
|
|
rgroup.long 0x11FC++0x03
|
|
line.long 0x00 "TSU_PEER_RX_NSEC,PTP Peer Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x00 0.--29. 1. "TIMER_PEER_NSEC,PTP Peer Event Frame Received Nanoseconds"
|
|
rgroup.long 0x1200++0x03
|
|
line.long 0x00 "PCS_CONTROL,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1204++0x03
|
|
line.long 0x00 "PCS_STATUS,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1210++0x03
|
|
line.long 0x00 "PCS_AN_ADV,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1214++0x03
|
|
line.long 0x00 "PCS_AN_LP_BASE,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1218++0x03
|
|
line.long 0x00 "PCS_AN_EXP,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x121C++0x03
|
|
line.long 0x00 "PCS_AN_NP_TX,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1220++0x03
|
|
line.long 0x00 "PCS_AN_LP_NP,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x123C++0x03
|
|
line.long 0x00 "PCS_AN_EXT_STATUS,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x1260++0x03
|
|
line.long 0x00 "TX_PAUSE_QUANTUM1,Transmit Pause Quantum Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "QUANTUM_P3,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "QUANTUM_P2,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 2"
|
|
group.long 0x1264++0x03
|
|
line.long 0x00 "TX_PAUSE_QUANTUM2,Transmit Pause Quantum Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "QUANTUM_P5,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 5"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "QUANTUM_P4,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 4"
|
|
group.long 0x1268++0x03
|
|
line.long 0x00 "TX_PAUSE_QUANTUM3,Transmit Pause Quantum Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "QUANTUM_P7,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 7"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "QUANTUM_P6,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 6"
|
|
rgroup.long 0x1270++0x03
|
|
line.long 0x00 "RX_LPI,Received LPI transitions"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT_LPI,Count of RX LPI transitions"
|
|
rgroup.long 0x1274++0x03
|
|
line.long 0x00 "RX_LPI_TIME,Received LPI time"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "LPI_TIME,Time in LPI"
|
|
rgroup.long 0x1278++0x03
|
|
line.long 0x00 "TX_LPI,Transmit LPI transitions"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT_LPI,Count of LPI transmissions"
|
|
rgroup.long 0x127C++0x03
|
|
line.long 0x00 "TX_LPI_TIME,Transmit LPI time"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "LPI_TIME,Time in LPI"
|
|
rgroup.long 0x1280++0x03
|
|
line.long 0x00 "DESIGNCFG_DEBUG1,The GEM_GXL(3PIP) has many parameterisation options to configure the IP during compilation stage"
|
|
bitfld.long 0x00 28.--31. "AXI_CACHE_VALUE,Takes the value of the `gem_axi_awcache_value DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 25.--27. "DMA_BUS_WIDTH,Takes the value of bits 7:5 of the `gem_dma_bus_width DEFINE" "0,1,2,3,4,5,6,7"
|
|
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bitfld.long 0x00 24. "EXCLUDE_CBS,Takes the value of the `gem_exclude_cbs DEFINE" "0,1"
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|
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|
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bitfld.long 0x00 23. "IRQ_READ_CLEAR,Takes the value of the `gem_irq_read_clear DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 22. "NO_SNAPSHOT,Takes the value of the `gem_no_snapshot DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 21. "NO_STATS,Takes the value of the `gem_no_stats DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 20. "RSVD_20,N/A" "0,1"
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|
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|
|
bitfld.long 0x00 15.--19. "USER_IN_WIDTH,Takes the value of the `gem_user_in_width DEFINE `gem_user_io" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
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bitfld.long 0x00 10.--14. "USER_OUT_WIDTH,Takes the value of the `gem_user_out_width DEFINE if `gem_user_io is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 9. "USER_IO,Takes the value of the `gem_user_io DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 8. "RSVD_8,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 6. "EXT_FIFO_INTERFACE,Takes the value of the `gem_ext_fifo_interface DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 5. "RSVD_5,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4. "INT_LOOPBACK,Takes the value of the `gem_int_loopback DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 2.--3. "RSVD_2,N/A" "0,1,2,3"
|
|
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|
|
bitfld.long 0x00 1. "EXCLUDE_QBV,Takes the value of the `gem_exclude_qbv DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 0. "NO_PCS,Takes the value of the `gem_no_pcs DEFINE" "0,1"
|
|
rgroup.long 0x1284++0x03
|
|
line.long 0x00 "DESIGNCFG_DEBUG2,Design Configuration Register 2"
|
|
bitfld.long 0x00 31. "SPRAM,Takes the value of the `gem_spram DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 30. "AXI,Takes the value of the `gem_axi DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 26.--29. "TX_PBUF_ADDR,Takes the value of the `gem_tx_pbuf_addr DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x00 22.--25. "RX_PBUF_ADDR,Takes the value of the `gem_rx_pbuf_addr DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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bitfld.long 0x00 21. "TX_PKT_BUFFER,Takes the value of the `gem_tx_pkt_buffer DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 20. "RX_PKT_BUFFER,Takes the value of the `gem_rx_pkt_buffer DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 16.--19. "HPROT_VALUE,Takes the value of the `gem_hprot_value DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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hexmask.long.word 0x00 0.--13. 1. "JUMBO_MAX_LENGTH,Takes the value of the `gem_jumbo_max_length DEFINE"
|
|
rgroup.long 0x1288++0x03
|
|
line.long 0x00 "DESIGNCFG_DEBUG3,Design Configuration Register 3"
|
|
bitfld.long 0x00 24.--29. "NUM_SPEC_ADD_FILTERS,Takes the value of the `num_spec_add_filters DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x128C++0x03
|
|
line.long 0x00 "DESIGNCFG_DEBUG4,Design Configuration Register 4"
|
|
hexmask.long 0x00 0.--31. 1. "RSVD_31_0,N/A"
|
|
rgroup.long 0x1290++0x03
|
|
line.long 0x00 "DESIGNCFG_DEBUG5,Design Configuration Register 5"
|
|
bitfld.long 0x00 29.--31. "AXI_PROT_VALUE,Takes the value of the `gem_axi_prot_value DEFINE" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 28. "TSU_CLK,Takes the value of the `gem_tsu_clk DEFINE" "0,1"
|
|
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|
|
hexmask.long.byte 0x00 20.--27. 1. "RX_BUFFER_LENGTH_DEF,Takes the value of the `gem_rx_buffer_length_def DEFINE"
|
|
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|
|
bitfld.long 0x00 19. "TX_PBUF_SIZE_DEF,Takes the value of the `gem_tx_pbuf_size_def DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 17.--18. "RX_PBUF_SIZE_DEF,Takes the value of the `gem_rx_pbuf_size_def DEFINE" "0,1,2,3"
|
|
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|
|
bitfld.long 0x00 15.--16. "ENDIAN_SWAP_DEF,Takes the value of the `gem_endian_swap_def DEFINE" "0,1,2,3"
|
|
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|
|
bitfld.long 0x00 12.--14. "MDC_CLOCK_DIV,Takes the value of the `gem_mdc_clock_div DEFINE" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x00 10.--11. "DMA_BUS_WIDTH_DEF,Takes the value of the `gem_dma_bus_width_def DEFINE" "0,1,2,3"
|
|
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|
|
bitfld.long 0x00 9. "PHY_IDENT,Takes the value of the `gem_phy_ident DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 8. "TSU,Takes the value of the `gem_tsu DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--7. "TX_FIFO_CNT_WIDTH,Takes the value of the `gem_tx_fifo_cnt_width DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
|
bitfld.long 0x00 0.--3. "RX_FIFO_CNT_WIDTH,Takes the value of the `gem_rx_fifo_cnt_width DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1294++0x03
|
|
line.long 0x00 "DESIGNCFG_DEBUG6,Design Configuration Register 6"
|
|
bitfld.long 0x00 27. "PBUF_LSO,Takes the value of the `gem_pbuf_lso DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 26. "PBUF_RSC,Takes the value of the `gem_pbuf_rsc DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 25. "PBUF_CUTTHRU,Takes the value of the `gem_pbuf_cutthru DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 24. "PFC_MULTI_QUANTUM,Takes the value of the `gem_pfc_multi_quantum DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 23. "DMA_ADDR_WIDTH_IS_64B,Takes the value of the `gem_dma_addr_width_is_64b DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 22. "HOST_IF_SOFT_SELECT,Takes the value of the `gem_host_if_soft_select DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 21. "TX_ADD_FIFO_IF,Takes the value of the `gem_tx_add_fifo_if DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 20. "EXT_TSU_TIMER,Takes the value of the `gem_ext_tsu_timer DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 16.--19. "TX_PBUF_QUEUE_SEGMENT_SIZE,Takes the value of the `gem_tx_pbuf_queue_segment_size DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
|
bitfld.long 0x00 15. "DMA_PRIORITY_QUEUE15,Takes the value of the `dma_priority_queue15 DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 14. "DMA_PRIORITY_QUEUE14,Takes the value of the `dma_priority_queue14 DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 13. "DMA_PRIORITY_QUEUE13,Takes the value of the `dma_priority_queue13 DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 12. "DMA_PRIORITY_QUEUE12,Takes the value of the `dma_priority_queue12 DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 11. "DMA_PRIORITY_QUEUE11,Takes the value of the `dma_priority_queue11 DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 10. "DMA_PRIORITY_QUEUE10,Takes the value of the `dma_priority_queue10 DEFINE" "0,1"
|
|
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|
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bitfld.long 0x00 9. "DMA_PRIORITY_QUEUE9,Takes the value of the `dma_priority_queue9 DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 8. "DMA_PRIORITY_QUEUE8,Takes the value of the `dma_priority_queue8 DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 7. "DMA_PRIORITY_QUEUE7,Takes the value of the `dma_priority_queue7 DEFINE" "0,1"
|
|
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|
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bitfld.long 0x00 6. "DMA_PRIORITY_QUEUE6,Takes the value of the `dma_priority_queue6 DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 5. "DMA_PRIORITY_QUEUE5,Takes the value of the `dma_priority_queue5 DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 4. "DMA_PRIORITY_QUEUE4,Takes the value of the `dma_priority_queue4 DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 3. "DMA_PRIORITY_QUEUE3,Takes the value of the `dma_priority_queue3 DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 2. "DMA_PRIORITY_QUEUE2,Takes the value of the `dma_priority_queue2 DEFINE" "0,1"
|
|
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|
|
bitfld.long 0x00 1. "DMA_PRIORITY_QUEUE1,Takes the value of the `dma_priority_queue1 DEFINE" "0,1"
|
|
rgroup.long 0x1298++0x03
|
|
line.long 0x00 "DESIGNCFG_DEBUG7,Design Configuration Register 7"
|
|
bitfld.long 0x00 28.--31. "X_PBUF_NUM_SEGMENTS_Q7,Takes the value of the `gem_tx_pbuf_num_segments_q7 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
|
bitfld.long 0x00 24.--27. "X_PBUF_NUM_SEGMENTS_Q6,Takes the value of the `gem_tx_pbuf_num_segments_q6 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x00 20.--23. "X_PBUF_NUM_SEGMENTS_Q5,Takes the value of the `gem_tx_pbuf_num_segments_q5 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x00 16.--19. "X_PBUF_NUM_SEGMENTS_Q4,Takes the value of the `gem_tx_pbuf_num_segments_q4 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x00 12.--15. "X_PBUF_NUM_SEGMENTS_Q3,Takes the value of the `gem_tx_pbuf_num_segments_q3 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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bitfld.long 0x00 8.--11. "X_PBUF_NUM_SEGMENTS_Q2,Takes the value of the `gem_tx_pbuf_num_segments_q2 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x00 4.--7. "X_PBUF_NUM_SEGMENTS_Q1,Takes the value of the `gem_tx_pbuf_num_segments_q1 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 0.--3. "X_PBUF_NUM_SEGMENTS_Q0,Takes the value of the `gem_tx_pbuf_num_segments_q0 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x129C++0x03
|
|
line.long 0x00 "DESIGNCFG_DEBUG8,Design Configuration Register 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NUM_TYPE1_SCREENERS,Takes the value of the `num_type1_screeners DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "NUM_TYPE2_SCREENERS,Takes the value of the `num_type2_screeners DEFINE"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "NUM_SCR2_ETHTYPE_REGS,Takes the value of the `num_scr2_ethtype_regs DEFINE"
|
|
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|
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hexmask.long.byte 0x00 0.--7. 1. "NUM_SCR2_COMPARE_REGS,Takes the value of the `num_scr2_compare_regs DEFINE"
|
|
rgroup.long 0x12A0++0x03
|
|
line.long 0x00 "DESIGNCFG_DEBUG9,Design Configuration Register 9"
|
|
bitfld.long 0x00 28.--31. "TX_PBUF_NUM_SEGMENTS_Q15,Takes the value of the `gem_tx_pbuf_num_segments_q15 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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bitfld.long 0x00 24.--27. "TX_PBUF_NUM_SEGMENTS_Q14,Takes the value of the `gem_tx_pbuf_num_segments_q14 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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bitfld.long 0x00 20.--23. "TX_PBUF_NUM_SEGMENTS_Q13,Takes the value of the `gem_tx_pbuf_num_segments_q13 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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bitfld.long 0x00 16.--19. "TX_PBUF_NUM_SEGMENTS_Q12,Takes the value of the `gem_tx_pbuf_num_segments_q12 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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bitfld.long 0x00 12.--15. "TX_PBUF_NUM_SEGMENTS_Q11,Takes the value of the `gem_tx_pbuf_num_segments_q11 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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bitfld.long 0x00 8.--11. "TX_PBUF_NUM_SEGMENTS_Q10,Takes the value of the `gem_tx_pbuf_num_segments_q10 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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bitfld.long 0x00 4.--7. "TX_PBUF_NUM_SEGMENTS_Q9,Takes the value of the `gem_tx_pbuf_num_segments_q9 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x00 0.--3. "TX_PBUF_NUM_SEGMENTS_Q8,Takes the value of the `gem_tx_pbuf_num_segments_q8 DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x12A4++0x03
|
|
line.long 0x00 "DESIGNCFG_DEBUG10,Design Configuration Register 10"
|
|
bitfld.long 0x00 28.--31. "EMAC_BUS_WIDTH,Takes the value of the `gem_emac_bus_width DEFINE" "?,1: The MAC has a datawidth of 32bits,2: The MAC has a datawidth of 64bits,?,4: The MAC has a datawidth of 128bits,?..."
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|
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|
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bitfld.long 0x00 24.--27. "TX_PBUF_DATA,Takes the value of the `gem_tx_pbuf_data DEFINE" "?,1: The TX DPRAM has a datawidth of 32bits,2: The TX DPRAM has a datawidth of 64bits,?,4: The TX DPRAM has a datawidth of 128bits,?..."
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|
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bitfld.long 0x00 20.--23. "RX_PBUF_DATA,Takes the value of the `gem_rx_pbuf_data DEFINE" "?,1: The RX DPRAM has a datawidth of 32bits,2: The RX DPRAM has a datawidth of 64bits,?,4: RX The DPRAM has a datawidth of 128bits,?..."
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|
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bitfld.long 0x00 16.--19. "AXI_ACCESS_PIPELINE_BITS,Takes the value of the `gem_axi_access_pipeline_bits DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 12.--15. "AXI_TX_DESCR_RD_BUFF_BITS,Takes the value of the `gem_axi_tx_descr_rd_buff_bits DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x00 8.--11. "AXI_RX_DESCR_RD_BUFF_BITS,Takes the value of the `gem_axi_rx_descr_rd_buff_bits DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x00 4.--7. "AXI_TX_DESCR_WR_BUFF_BITS,Takes the value of the `gem_axi_tx_descr_wr_buff_bits DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x00 0.--3. "AXI_RX_DESCR_WR_BUFF_BITS,Takes the value of the `gem_axi_rx_descr_wr_buff_bits DEFINE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1300++0x03
|
|
line.long 0x00 "SPEC_ADD5_BOTTOM,Specific address registers 5 ~ 36 doesn't present"
|
|
hexmask.long 0x00 0.--31. 1. "RSVD_31_0,Write ignore read 0"
|
|
rgroup.long 0x1304++0x03
|
|
line.long 0x00 "SPEC_ADD5_TOP,Specific address registers 5 ~ 36 doesn't present"
|
|
hexmask.long 0x00 0.--31. 1. "RSVD_31_0,Write ignore read 0"
|
|
rgroup.long 0x13F8++0x03
|
|
line.long 0x00 "SPEC_ADD36_BOTTOM,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "RSVD_31_0,Write ignore read 0"
|
|
rgroup.long 0x13FC++0x03
|
|
line.long 0x00 "SPEC_ADD36_TOP,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "RSVD_31_0,Write ignore read 0"
|
|
rgroup.long 0x1400++0x03
|
|
line.long 0x00 "INT_Q1_STATUS,Priority queue Interrupt Status Register"
|
|
bitfld.long 0x00 11. "RESP_NOT_OK,bresp not OK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "TRANSMIT_COMPLETE,Transmit complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "AMBA_ERROR,Transmit frame corruption due to AMBA (AXI) error set if an error occurs whilst midway through reading transmit frame from the external memory including RRESP and BRESP errors (AXI) and buffers exhausted mid frame" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION,Retry limit exceeded or late collision" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RX_USED_BIT_READ,RX used bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RECEIVE_COMPLETE,Receive complete" "0,1"
|
|
rgroup.long 0x1404++0x03
|
|
line.long 0x00 "INT_Q2_STATUS,Priority queue Interrupt Status Register"
|
|
bitfld.long 0x00 11. "RESP_NOT_OK,bresp not OK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "TRANSMIT_COMPLETE,Transmit complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "AMBA_ERROR,Transmit frame corruption due to AMBA (AXI) error set if an error occurs whilst midway through reading transmit frame from the external memory including RRESP and BRESP errors (AXI) and buffers exhausted mid frame" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION,Retry limit exceeded or late collision" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RX_USED_BIT_READ,RX used bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RECEIVE_COMPLETE,Receive complete" "0,1"
|
|
rgroup.long 0x1408++0x03
|
|
line.long 0x00 "INT_Q3_STATUS,int_q3_status to int_q15_status doesn't present"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1438++0x03
|
|
line.long 0x00 "INT_Q15_STATUS,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x1440++0x03
|
|
line.long 0x00 "TRANSMIT_Q1_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list)"
|
|
hexmask.long 0x00 2.--31. 1. "DMA_TX_Q_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list)"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA_TX_DIS_Q,Disable queue if set to 1" "0,1"
|
|
group.long 0x1444++0x03
|
|
line.long 0x00 "TRANSMIT_Q2_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list)"
|
|
hexmask.long 0x00 2.--31. 1. "DMA_TX_Q_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list)"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA_TX_DIS_Q,Disable queue if set to 1" "0,1"
|
|
rgroup.long 0x1448++0x03
|
|
line.long 0x00 "TRANSMIT_Q3_PTR,transmit_q3_ptr to transmit_q15_ptr doesn't present"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Disable queue if set to 1"
|
|
rgroup.long 0x1478++0x03
|
|
line.long 0x00 "TRANSMIT_Q15_PTR,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x1480++0x03
|
|
line.long 0x00 "RECEIVE_Q1_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list)"
|
|
hexmask.long 0x00 2.--31. 1. "DMA_RX_Q_PTR,Receive buffer queue base address - written with the address of the start of the receive queue"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA_RX_DIS_Q,Disable queue if set to 1" "0,1"
|
|
group.long 0x1484++0x03
|
|
line.long 0x00 "RECEIVE_Q2_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list)"
|
|
hexmask.long 0x00 2.--31. 1. "DMA_RX_Q_PTR,Receive buffer queue base address - written with the address of the start of the receive queue"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA_RX_DIS_Q,Disable queue if set to 1" "0,1"
|
|
rgroup.long 0x1488++0x03
|
|
line.long 0x00 "RECEIVE_Q3_PTR,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1498++0x03
|
|
line.long 0x00 "RECEIVE_Q7_PTR,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x14A0++0x03
|
|
line.long 0x00 "DMA_RXBUF_SIZE_Q1,Receive Buffer queue 1 Size"
|
|
abitfld.long 0x00 0.--7. "DMA_RX_Q_BUF_SIZE,DMA receive buffer size in system memory" "0x02=2: 128 byte,0x18=24: 1536 byte (1*max length frame/buffer),0xA0=160: 10240 byte (1*10K jumbo frame/buffer).."
|
|
group.long 0x14A4++0x03
|
|
line.long 0x00 "DMA_RXBUF_SIZE_Q2,Receive Buffer queue 2 Size"
|
|
abitfld.long 0x00 0.--7. "DMA_RX_Q_BUF_SIZE,DMA receive buffer size in system memory" "0x02=2: 128 byte,0x18=24: 1536 byte (1*max length frame/buffer),0xA0=160: 10240 byte (1*10K jumbo frame/buffer).."
|
|
rgroup.long 0x14A8++0x03
|
|
line.long 0x00 "DMA_RXBUF_SIZE_Q3,dma_rxbuf_size_q3 to dma_rxbuf_size_q7 doesn't present"
|
|
abitfld.long 0x00 0.--31. "REMOVED_31_0,DMA receive buffer size in system memory" "0x00000002=2: 128 byte,0x00000018=24: 1536 byte (1*max length..,0x000000A0=160: 10240 byte (1*10K jumbo.."
|
|
rgroup.long 0x14B8++0x03
|
|
line.long 0x00 "DMA_RXBUF_SIZE_Q7,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x14BC++0x03
|
|
line.long 0x00 "CBS_CONTROL,The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent"
|
|
bitfld.long 0x00 1. "CBS_ENABLE_QUEUE_B,Enable Credit-Based shaping on the 2nd highest priority queue (queue B)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CBS_ENABLE_QUEUE_A,Enable Credit-Based Shaping on the highest priority queue (queue A)" "0,1"
|
|
group.long 0x14C0++0x03
|
|
line.long 0x00 "CBS_IDLESLOPE_Q_A,queue A is the highest priority queue"
|
|
hexmask.long 0x00 0.--31. 1. "IDLESLOPE_A,IdleSlope value for queue A in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation"
|
|
group.long 0x14C4++0x03
|
|
line.long 0x00 "CBS_IDLESLOPE_Q_B,queue B is the 2nd highest priority queue"
|
|
hexmask.long 0x00 0.--31. 1. "IDLESLOPE_B,IdleSlope value for queue B in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation"
|
|
group.long 0x14C8++0x03
|
|
line.long 0x00 "UPPER_TX_Q_BASE_ADDR,Upper 32 bits of transmit buffer descriptor queue base address"
|
|
hexmask.long 0x00 0.--31. 1. "UPPER_TX_Q_BASE_ADDR,Upper 32 bits of transmit buffer descriptor queue base address"
|
|
group.long 0x14CC++0x03
|
|
line.long 0x00 "TX_BD_CONTROL,TX BD control register"
|
|
bitfld.long 0x00 4.--5. "TX_BD_TS_MODE,TX Descriptor Timestamp Insertion mode" "0: TS insertion disable,1: TS inserted for PTP Event Frames only,2: TS inserted for All PTP Frames only,3: TS insertion for All Frames"
|
|
group.long 0x14D0++0x03
|
|
line.long 0x00 "RX_BD_CONTROL,RX BD control register"
|
|
bitfld.long 0x00 4.--5. "RX_BD_TS_MODE,RX Descriptor Timestamp Insertion mode" "0: TS insertion disable,1: TS inserted for PTP Event Frames only,2: TS inserted for All PTP Frames only,3: TS insertion for All Frames"
|
|
group.long 0x14D4++0x03
|
|
line.long 0x00 "UPPER_RX_Q_BASE_ADDR,Upper 32 bits of receive buffer descriptor queue base address"
|
|
hexmask.long 0x00 0.--31. 1. "UPPER_RX_Q_BASE_ADDR,Upper 32 bits of receive buffer descriptor queue base address"
|
|
group.long 0x14E0++0x03
|
|
line.long 0x00 "HIDDEN_REG0,Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_10m 12'h4e0 // 10M Port TX Rate *** HIDDEN Register ***'"
|
|
hexmask.long 0x00 0.--31. 1. "HIDDEN0_FIELD,default value is defined per description of register cbs_control"
|
|
group.long 0x14E4++0x03
|
|
line.long 0x00 "HIDDEN_REG1,Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_100m 12'h4e4 // 100M Port TX Rate *** HIDDEN Register ***'"
|
|
hexmask.long 0x00 0.--31. 1. "HIDDEN1_FIELD,default value is defined per description of register cbs_control"
|
|
group.long 0x14E8++0x03
|
|
line.long 0x00 "HIDDEN_REG2,Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_1g 12'h4e8 // 1G Port TX Rate *** HIDDEN Register ***'"
|
|
hexmask.long 0x00 0.--31. 1. "HIDDEN2_FIELD,default value is defined per description of register cbs_control"
|
|
group.long 0x14EC++0x03
|
|
line.long 0x00 "HIDDEN_REG3,Hidden registers defined in edma_defs.v '`define gem_wd_counter 12'h4ec // *** HIDDEN Register ***'"
|
|
bitfld.long 0x00 0.--3. "HIDDEN3_FIELD,default value is defined per description of register cbs_control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14F8++0x03
|
|
line.long 0x00 "HIDDEN_REG4,Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold0 12'h4f8 // AXI full threshold setting *** HIDDEN Register ***'"
|
|
hexmask.long.word 0x00 16.--24. 1. "HIDDEN4_FIELD_H,The valid bits is defined by `gem_tx_pbuf_addr"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "HIDDEN4_FIELD_L,The valid bits is defined by `gem_tx_pbuf_addr"
|
|
group.long 0x14FC++0x03
|
|
line.long 0x00 "HIDDEN_REG5,Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold1 12'h4fc // AXI full threshold setting *** HIDDEN Register ***'"
|
|
hexmask.long.word 0x00 16.--24. 1. "HIDDEN5_FIELD_H,The valid bits is defined by `gem_tx_pbuf_addr"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "HIDDEN5_FIELD_L,The valid bits is defined by `gem_tx_pbuf_addr"
|
|
group.long 0x1500++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_0,Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1504++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_1,screening type 1 register 1 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1508++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_2,screening type 1 register 2 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x150C++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_3,screening type 1 register 3 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1510++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_4,screening type 1 register 4 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1514++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_5,screening type 1 register 5 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1518++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_6,screening type 1 register 6 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x151C++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_7,screening type 1 register 7 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1520++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_8,screening type 1 register 8 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1524++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_9,screening type 1 register 9 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1528++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_10,screening type 1 register 10 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x152C++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_11,screening type 1 register 11 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1530++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_12,screening type 1 register 12 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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|
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hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
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bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1534++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_13,screening type 1 register 13 same as screening_type_1_register_0"
|
|
bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
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|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
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newline
|
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hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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newline
|
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hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
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|
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bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1538++0x03
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line.long 0x00 "SCREENING_TYPE_1_REGISTER_14,screening type 1 register 14 same as screening_type_1_register_0"
|
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bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
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|
|
bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
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|
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hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
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hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
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|
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bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x153C++0x03
|
|
line.long 0x00 "SCREENING_TYPE_1_REGISTER_15,screening type 1 register 15 same as screening_type_1_register_0"
|
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bitfld.long 0x00 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
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|
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bitfld.long 0x00 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
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|
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hexmask.long.word 0x00 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x00 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
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bitfld.long 0x00 0.--3. "QUEUE_NUMBER,Queue Number (0 to 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1540++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_0,Screener Type 2 match registers operate independently of screener type 1 registers and offer additional match capabilities extending the capabilities into vendor specific protocols"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
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bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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|
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bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1544++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_1,screening type 2 register 1 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
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|
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bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1548++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_2,screening type 2 register 2 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x154C++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_3,screening type 2 register 3 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1550++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_4,screening type 2 register 4 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1554++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_5,screening type 2 register 5 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1558++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_6,screening type 2 register 6 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x155C++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_7,screening type 2 register 7 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1560++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_8,screening type 2 register 8 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1564++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_9,screening type 2 register 9 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
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|
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bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
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bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1568++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_10,screening type 2 register 10 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
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|
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bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
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bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
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bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
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bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
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|
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bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
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bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x156C++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_11,screening type 2 register 11 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
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|
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bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
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bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1570++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_12,screening type 2 register 12 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
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|
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bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
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bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
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|
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bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1574++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_13,screening type 2 register 13 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
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|
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bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
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bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1578++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_14,screening type 2 register 14 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
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|
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bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x157C++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_REGISTER_15,screening type 2 register 15 same as screening_type_2_register_0"
|
|
rbitfld.long 0x00 31. "RSVD_31,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 25.--29. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 19.--23. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 13.--17. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x00 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
|
bitfld.long 0x00 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x00 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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|
|
bitfld.long 0x00 0.--3. "QUEUE_NUMBER,'Queue Number (0 to 15)'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1580++0x03
|
|
line.long 0x00 "TX_SCHED_CTRL,This register controls the transmit scheduling algorithm the user can select for each active transmit queue"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "REMOVED_31_8,Write ignore read 0"
|
|
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|
|
rbitfld.long 0x00 6.--7. "TX_SCHED_Q3,Write ignore read 0" "0,1,2,3"
|
|
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|
|
bitfld.long 0x00 4.--5. "TX_SCHED_Q2,'Queue 2 selection" "0: Fixed Priority,1: CBS Enabled only valid for top two,2: DWRR Enabled,3: ETS Enabled"
|
|
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|
|
bitfld.long 0x00 2.--3. "TX_SCHED_Q1,'Queue 1 selection" "0: Fixed Priority,1: CBS Enabled only valid for top two,2: DWRR Enabled,3: ETS Enabled'"
|
|
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|
|
bitfld.long 0x00 0.--1. "TX_SCHED_Q0,'Queue 0 selection" "0: Fixed Priority,1: CBS Enabled only valid for top two,2: DWRR Enabled,3: ETS Enabled'"
|
|
group.long 0x1590++0x03
|
|
line.long 0x00 "BW_RATE_LIMIT_Q0TO3,This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 0 to 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DWRR_ETS_WEIGHT_Q3,Write ignore read 0"
|
|
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|
|
hexmask.long.byte 0x00 16.--23. 1. "DWRR_ETS_WEIGHT_Q2,'DWRR Weighting / ETS Bandwidth Allocation for queue 2'"
|
|
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|
|
hexmask.long.byte 0x00 8.--15. 1. "DWRR_ETS_WEIGHT_Q1,'DWRR Weighting / ETS Bandwidth Allocation for queue 1'"
|
|
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|
|
hexmask.long.byte 0x00 0.--7. 1. "DWRR_ETS_WEIGHT_Q0,'DWRR Weighting / ETS Bandwidth Allocation for queue 0'"
|
|
group.long 0x1594++0x03
|
|
line.long 0x00 "BW_RATE_LIMIT_Q4TO7,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,'DWRR Weighting / ETS Bandwidth Allocation for queue 0'"
|
|
rgroup.long 0x1598++0x03
|
|
line.long 0x00 "BW_RATE_LIMIT_Q8TO11,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x159C++0x03
|
|
line.long 0x00 "BW_RATE_LIMIT_Q12TO15,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x15A0++0x03
|
|
line.long 0x00 "TX_Q_SEG_ALLOC_Q0TO7,This register allows the user to distribute the Transmit SRAM used by the DMA across the priority queues for queues 0 to 7"
|
|
rbitfld.long 0x00 31. "RSVD_31_31,Write ignore read 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 28.--30. "REMOVED_30_28,Write ignore read 0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 27. "RSVD_27_27,Write ignore read 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 24.--26. "REMOVED_26_24,Write ignore read 0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 23. "RSVD_23,Write ignore read 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20.--22. "REMOVED_22_20,Write ignore read 0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 19. "RSVD_19_19,Write ignore read 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16.--18. "REMOVED_18_16,Write ignore read 0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 15. "RSVD_15_15,Write ignore read 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 12.--14. "REMOVED_14_12,Write ignore read 0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 11. "RSVD_11_11,Write ignore read 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "SEGMENT_ALLOC_Q2,Number of segments allocated to q2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 7. "RSVD_7_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "SEGMENT_ALLOC_Q1,Number of segments allocated to q1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 3. "RSVD_3_3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEGMENT_ALLOC_Q0,Number of segments allocated to q0" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x15A4++0x03
|
|
line.long 0x00 "TX_Q_SEG_ALLOC_Q8TO15,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x15C0++0x03
|
|
line.long 0x00 "RECEIVE_Q8_PTR,receive_q8_ptr to receive_q15_ptr doesn't present"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x15DC++0x03
|
|
line.long 0x00 "RECEIVE_Q15_PTR,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x15E0++0x03
|
|
line.long 0x00 "DMA_RXBUF_SIZE_Q8,dma_rxbuf_size_q8 to dma_rxbuf_size_q15 doesn't present"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x15FC++0x03
|
|
line.long 0x00 "DMA_RXBUF_SIZE_Q15,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
wgroup.long 0x1600++0x03
|
|
line.long 0x00 "INT_Q1_ENABLE,At reset all interrupts are disabled"
|
|
bitfld.long 0x00 11. "ENABLE_RESP_NOT_OK_INTERRUPT,Enable bresp not OK interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ENABLE_TRANSMIT_COMPLETE_INTERRUPT,Enable Transmit complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Enable Transmit frame corruption due to AMBA (AXI) error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Enable Retry limit exceeded or late collision interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENABLE_RX_USED_BIT_READ_INTERRUPT,Enable RX used bit read interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE_RECEIVE_COMPLETE_INTERRUPT,Enable Receive complete interrupt" "0,1"
|
|
wgroup.long 0x1604++0x03
|
|
line.long 0x00 "INT_Q2_ENABLE,At reset all interrupts are disabled"
|
|
bitfld.long 0x00 11. "ENABLE_RESP_NOT_OK_INTERRUPT,Enable bresp not OK interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ENABLE_TRANSMIT_COMPLETE_INTERRUPT,Enable Transmit complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Enable Transmit frame corruption due to AMBA (AXI) error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Enable Retry limit exceeded or late collision interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENABLE_RX_USED_BIT_READ_INTERRUPT,Enable RX used bit read interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENABLE_RECEIVE_COMPLETE_INTERRUPT,Enable Receive complete interrupt" "0,1"
|
|
rgroup.long 0x1608++0x03
|
|
line.long 0x00 "INT_Q3_ENABLE,int_q3_enable to int_q7_enable doesn't present"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1618++0x03
|
|
line.long 0x00 "INT_Q7_ENABLE,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
wgroup.long 0x1620++0x03
|
|
line.long 0x00 "INT_Q1_DISABLE,Writing a 1 to the relevant bit location disables that particular interrupt"
|
|
bitfld.long 0x00 11. "DISABLE_RESP_NOT_OK_INTERRUPT,Disable bresp not OK interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "DISABLE_TRANSMIT_COMPLETE_INTERRUPT,Disable Transmit complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Disable Transmit frame corruption due to AMBA (AXI) error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Disable Retry limit exceeded or late collision interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DISABLE_RX_USED_BIT_READ_INTERRUPT,Disable RX used bit read interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DISABLE_RECEIVE_COMPLETE_INTERRUPT,Disable Receive complete interrupt" "0,1"
|
|
wgroup.long 0x1624++0x03
|
|
line.long 0x00 "INT_Q2_DISABLE,Writing a 1 to the relevant bit location disables that particular interrupt"
|
|
bitfld.long 0x00 11. "DISABLE_RESP_NOT_OK_INTERRUPT,Disable bresp not OK interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "DISABLE_TRANSMIT_COMPLETE_INTERRUPT,Disable Transmit complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Disable Transmit frame corruption due to AMBA (AXI) error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Disable Retry limit exceeded or late collision interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DISABLE_RX_USED_BIT_READ_INTERRUPT,Disable RX used bit read interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DISABLE_RECEIVE_COMPLETE_INTERRUPT,Disable Receive complete interrupt" "0,1"
|
|
rgroup.long 0x1628++0x03
|
|
line.long 0x00 "INT_Q3_DISABLE,int_q3_disable to int_q7_disable doesn't present"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1638++0x03
|
|
line.long 0x00 "INT_Q7_DISABLE,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1640++0x03
|
|
line.long 0x00 "INT_Q1_MASK,The interrupt mask register is a read only register indicating which interrupts are masked"
|
|
bitfld.long 0x00 11. "RESP_NOT_OK_INTERRUPT_MASK,bresp not OK interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x00 7. "TRANSMIT_COMPLETE_INTERRUPT_MASK,transmit complete interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x00 6. "AMBA_ERROR_INTERRUPT_MASK,A read of this register returns the value of the AMBA (AXI) error interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x00 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK,retry limit exceeded or late collision interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x00 2. "RX_USED_INTERRUPT_MASK,A read of this register returns the value of the RX Used interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RECEIVE_COMPLETE_INTERRUPT_MASK,receive complete interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
rgroup.long 0x1644++0x03
|
|
line.long 0x00 "INT_Q2_MASK,The interrupt mask register is a read only register indicating which interrupts are masked"
|
|
bitfld.long 0x00 11. "RESP_NOT_OK_INTERRUPT_MASK,bresp not OK interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x00 7. "TRANSMIT_COMPLETE_INTERRUPT_MASK,transmit complete interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x00 6. "AMBA_ERROR_INTERRUPT_MASK,A read of this register returns the value of the AMBA (AXI) error interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x00 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK,retry limit exceeded or late collision interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x00 2. "RX_USED_INTERRUPT_MASK,A read of this register returns the value of the RX Used interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RECEIVE_COMPLETE_INTERRUPT_MASK,receive complete interrupt mask" "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
rgroup.long 0x1648++0x03
|
|
line.long 0x00 "INT_Q3_MASK,int_q3_mask to int_q7_mask doesn't present"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1658++0x03
|
|
line.long 0x00 "INT_Q7_MASK,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1660++0x03
|
|
line.long 0x00 "INT_Q8_ENABLE,int_q8_enable to int_q15_enable doesn't present"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x167C++0x03
|
|
line.long 0x00 "INT_Q15_ENABLE,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1680++0x03
|
|
line.long 0x00 "INT_Q8_DISABLE,int_q8_disable to int_q15_disable doesn't present"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x169C++0x03
|
|
line.long 0x00 "INT_Q15_DISABLE,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x16A0++0x03
|
|
line.long 0x00 "INT_Q8_MASK,int_q8_mask to int_q15_mask doesn't present"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x16BC++0x03
|
|
line.long 0x00 "INT_Q15_MASK,Not presents"
|
|
hexmask.long 0x00 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x16E0)++0x03
|
|
line.long 0x00 "SCREENING_TYPE_2_ETHERTYPE_REG_$1,Ethertype Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
repeat.end
|
|
group.long 0x1700++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_0_WORD_0,'Compare A B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x1704++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_0_WORD_1,'Type2 Compare Word 1'"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1708++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_1_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x170C++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_1_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1710++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_2_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x1714++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_2_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1718++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_3_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x171C++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_3_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1720++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_4_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x1724++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_4_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1728++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_5_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x172C++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_5_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1730++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_6_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x1734++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_6_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1738++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_7_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x173C++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_7_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1740++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_8_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x1744++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_8_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1748++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_9_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x174C++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_9_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1750++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_10_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x1754++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_10_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1758++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_11_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x175C++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_11_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1760++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_12_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x1764++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_12_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1768++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_13_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x176C++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_13_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1770++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_14_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x1774++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_14_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1778++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_15_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x177C++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_15_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1780++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_16_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x1784++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_16_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1788++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_17_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x178C++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_17_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1790++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_18_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x1794++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_18_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x1798++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_19_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x179C++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_19_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x17A0++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_20_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x17A4++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_20_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x17A8++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_21_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x17AC++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_21_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x17B0++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_22_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x17B4++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_22_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x17B8++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_23_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x17BC++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_23_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x17C0++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_24_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x17C4++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_24_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x17C8++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_25_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x17CC++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_25_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x17D0++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_26_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x17D4++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_26_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x17D8++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_27_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x17DC++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_27_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x17E0++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_28_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x17E4++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_28_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x17E8++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_29_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x17EC++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_29_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x17F0++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_30_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x17F4++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_30_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
group.long 0x17F8++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_31_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x00 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value"
|
|
group.long 0x17FC++0x03
|
|
line.long 0x00 "TYPE2_COMPARE_31_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x00 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "COMPARE_OFFSET,'Compare byte offset" "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,2: Offset from byte following end of IP header,3: Offset from byte following end of TCP/UDP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "EVTGEN0 (Event Generator)"
|
|
base ad:0x403F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control"
|
|
bitfld.long 0x00 31. "ENABLED,IP enable: '0': Disabled" "0: DISABLED,1: ENABLED"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "COMP0_STATUS,Comparator structures comparator 0 status"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMP0_OUT,Active comparator 'comp0_out[]' outputs"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COMP1_STATUS,Comparator structures comparator 1 status"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMP1_OUT,DeepSleep comparator 'comp1_out_lf[]' outputs (synchronized from clk_lf to the IP clock)"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "COUNTER_STATUS,Counter status"
|
|
bitfld.long 0x00 31. "VALID,Active counter validity: '0': Invalid" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "COUNTER,Counter"
|
|
hexmask.long 0x00 0.--31. 1. "INT32,Active counter 'counter_int[31:0]' on clk_ref_div"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RATIO_CTL,Ratio control"
|
|
bitfld.long 0x00 31. "VALID,Ratio value valid: '0': Invalid" "0,1"
|
|
bitfld.long 0x00 30. "DYNAMIC,Specifies if RATIO_CTL.VALID and RATIO are under SW or HW control: '0': SW control" "0,1"
|
|
bitfld.long 0x00 16.--18. "DYNAMIC_MODE,Weighted average calculation (only used when DYNAMIC is '1'): '0': new RATIO value = (RATIO + measurement + 1) / 2" "0,1,2,3,4,5,6,7"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RATIO,Ratio"
|
|
hexmask.long.word 0x00 16.--31. 1. "INT16,Integer component of ratio value"
|
|
hexmask.long.byte 0x00 8.--15. 1. "FRAC8,Fractional component of ratio value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "REF_CLOCK_CTL,Reference clock control"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INT_DIV,Divider control for clk_ref_div: '0': Divide by 1"
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "INTR,Interrupt"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMP0,This interrupt cause field is activated (HW sets the field to '1') when a comparator 0 event is generated (Active counter 'counter_int[31:0]' becomes greater or equal to COMP0.INT[31:0])"
|
|
group.long 0x704++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMP0,SW writes a '1' to this field to set the corresponding field in the INTR register"
|
|
group.long 0x708++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMP0,Mask bit for corresponding field in the INTR register"
|
|
rgroup.long 0x70C++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMP0,Logical and of corresponding INTR and INTR_MASK fields"
|
|
group.long 0x710++0x03
|
|
line.long 0x00 "INTR_DPSLP,DeepSleep interrupt"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMP1,This interrupt cause field is activated (HW sets the field to '1') when a comparator 1 event is generated (DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1.INT[31:0])"
|
|
group.long 0x714++0x03
|
|
line.long 0x00 "INTR_DPSLP_SET,DeepSleep interrupt set"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMP1,SW writes a '1' to this field to set the corresponding field in the INTR register"
|
|
group.long 0x718++0x03
|
|
line.long 0x00 "INTR_DPSLP_MASK,DeepSleep interrupt mask"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMP1,Mask bit for corresponding field in the INTR register"
|
|
rgroup.long 0x71C++0x03
|
|
line.long 0x00 "INTR_DPSLP_MASKED,DeepSleep interrupt masked"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMP1,Logical and of corresponding INTR and INTR_MASK fields"
|
|
repeat 16. (increment 0 1)(increment 0 0x20)
|
|
tree "COMP_STRUCT[$1]"
|
|
group.long ($2+0x800)++0x03
|
|
line.long 0x00 "COMP_CTL,Comparator control"
|
|
bitfld.long 0x00 31. "ENABLED,Comparator structure enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 16. "TR_OUT_EDGE,Specifies the 'tr_out' output trigger: '0': The trigger is a level sensitive trigger" "0,1"
|
|
bitfld.long 0x00 1. "COMP1_EN,DeepSleep comparator (COMP1) enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 0. "COMP0_EN,Active comparator (COMP0) enable: '0': Disabled" "0,1"
|
|
group.long ($2+0x804)++0x03
|
|
line.long 0x00 "COMP0,Comparator 0 (Active functionality)"
|
|
hexmask.long 0x00 0.--31. 1. "INT32,This value is a 32-bit unsigned integer in the range [0 2^32-1]"
|
|
group.long ($2+0x808)++0x03
|
|
line.long 0x00 "COMP1,Comparator 1 (DeepSleep functionality)"
|
|
hexmask.long 0x00 0.--31. 1. "INT32,This value is a 32-bit unsigned integer in the range [0 2^32-1]"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "FAULT (Fault Structures)"
|
|
base ad:0x40210000
|
|
repeat 4. (increment 0 1)(increment 0 0x100)
|
|
tree "STRUCT[$1]"
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "CTL,Fault control"
|
|
bitfld.long 0x00 2. "RESET_REQ_EN,Reset request enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 1. "OUT_EN,IO output signal enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 0. "TR_EN,Trigger output enable: '0': Disabled" "0,1"
|
|
group.long ($2+0x0C)++0x03
|
|
line.long 0x00 "STATUS,Fault status"
|
|
bitfld.long 0x00 31. "VALID,Valid indication: '0': Invalid" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "IDX,The fault source index for which fault information is captured in DATA0 through DATA3"
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "DATA[0],Fault data"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Captured fault source data"
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "DATA[1],Fault data"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Captured fault source data"
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "DATA[2],Fault data"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Captured fault source data"
|
|
group.long ($2+0x1C)++0x03
|
|
line.long 0x00 "DATA[3],Fault data"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Captured fault source data"
|
|
rgroup.long ($2+0x40)++0x03
|
|
line.long 0x00 "PENDING0,Fault pending 0"
|
|
abitfld.long 0x00 0.--31. "SOURCE,This field specifies the following sources: Bit" "0x00000000=0: CM0 MPU,0x00000001=1: CRYPTO MPU,0x00000002=2: DW 0 MPU,0x00000003=3: DW 1 MPU,0x00000004=4: DMA controller MPU,0x0000000F=15: DAP MPU,0x00000010=16: CM4 system bus MPU,0x00000011=17: CM4 code bus MPU (for non FLASH..,0x00000012=18: CM4 code bus MPU (for FLASH.."
|
|
rgroup.long ($2+0x44)++0x03
|
|
line.long 0x00 "PENDING1,Fault pending 1"
|
|
abitfld.long 0x00 0.--31. "SOURCE,This field specifies the following sources: Bit" "0x00000000=0: Peripheral group 0 PPU,0x00000001=1: Peripheral group 1 PPU,0x00000002=2: Peripheral group 2 PPU,0x00000003=3: Peripheral group 3 PPU,0x00000004=4: Peripheral group 4 PPU,0x00000005=5: Peripheral group 5 PPU,0x00000006=6: Peripheral group 6 PPU,0x00000007=7: Peripheral group 7 PPU,0x0000000F=15: Peripheral group 15 PPU,0x0000001F=31: See STATUS register"
|
|
rgroup.long ($2+0x48)++0x03
|
|
line.long 0x00 "PENDING2,Fault pending 2"
|
|
hexmask.long 0x00 0.--31. 1. "SOURCE,This field specifies the following sources: Bit"
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "MASK0,Fault mask 0"
|
|
hexmask.long 0x00 0.--31. 1. "SOURCE,Fault source enables: Bits 31-0"
|
|
group.long ($2+0x54)++0x03
|
|
line.long 0x00 "MASK1,Fault mask 1"
|
|
hexmask.long 0x00 0.--31. 1. "SOURCE,Fault source enables: Bits 31-0"
|
|
group.long ($2+0x58)++0x03
|
|
line.long 0x00 "MASK2,Fault mask 2"
|
|
hexmask.long 0x00 0.--31. 1. "SOURCE,Fault source enables: Bits 31-0"
|
|
group.long ($2+0xC0)++0x03
|
|
line.long 0x00 "INTR,Interrupt"
|
|
bitfld.long 0x00 0. "FAULT,This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: - STATUS.VALID is set to '1'" "0,1"
|
|
group.long ($2+0xC4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x00 0. "FAULT,SW writes a '1' to this field to set the corresponding field in the INTR register" "0,1"
|
|
group.long ($2+0xC8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x00 0. "FAULT,Mask bit for corresponding field in the INTR register" "0,1"
|
|
rgroup.long ($2+0xCC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x00 0. "FAULT,Logical and of corresponding INTR and INTR_MASK fields" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "FLASHC (Flash Controller)"
|
|
base ad:0x40240000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FLASH_CTL,Control"
|
|
bitfld.long 0x00 24. "WORK_SEQ_RD_EN,Enable sequential read mode for Work Flash for read accesses on the AXI port" "0: Sequential read mode for Work Flash is disabled,1: Sequential read mode for Work Flash is enabled"
|
|
bitfld.long 0x00 22. "WORK_ERR_SILENT,Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error or a FLASH macro work interface internal error)" "0: Bus transfer has a bus error,1: Bus transfer does NOT have a bus error i.e"
|
|
newline
|
|
bitfld.long 0x00 21. "WORK_ECC_INJ_EN,N/A" "0,1"
|
|
bitfld.long 0x00 20. "WORK_ECC_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "MAIN_ERR_SILENT,Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error or a FLASH macro main interface internal error)" "0: Bus transfer has a bus error,1: Bus transfer does NOT have a bus error i.e"
|
|
bitfld.long 0x00 17. "MAIN_ECC_INJ_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "MAIN_ECC_EN,N/A" "0,1"
|
|
bitfld.long 0x00 13. "WORK_BANK_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "MAIN_BANK_MODE,N/A" "0,1"
|
|
bitfld.long 0x00 9. "WORK_MAP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "MAIN_MAP,N/A" "0,1"
|
|
bitfld.long 0x00 0.--3. "WS,FLASH macro wait states (same for main and work interfaces): '0': 0 wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "FLASH_PWR_CTL,Flash power control"
|
|
bitfld.long 0x00 1. "ENABLE_HV,Controls 'enable_hv' pin of the Flash memory" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE,Controls 'enable' pin of the Flash memory" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FLASH_CMD,Command"
|
|
bitfld.long 0x00 1. "BUFF_INV,Invalidation of ALL buffers (does not invalidate the caches)" "0,1"
|
|
bitfld.long 0x00 0. "INV,Invalidation of ALL caches (for CM0+) and ALL buffers" "0,1"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PARITY,N/A"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "WORD_ADDR,N/A"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "FM_SRAM_ECC_CTL0,eCT Flash SRAM ECC control 0"
|
|
hexmask.long 0x00 0.--31. 1. "ECC_INJ_DATA,32-bit data for ECC error injection test of eCT Flash SRAM ECC logic"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "FM_SRAM_ECC_CTL1,eCT Flash SRAM ECC control 1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "ECC_INJ_PARITY,7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic"
|
|
rgroup.long 0x2B8++0x03
|
|
line.long 0x00 "FM_SRAM_ECC_CTL2,eCT Flash SRAM ECC control 2"
|
|
hexmask.long 0x00 0.--31. 1. "CORRECTED_DATA,32-bit corrected data output of the ECC syndrome logic"
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "FM_SRAM_ECC_CTL3,eCT Flash SRAM ECC control 3"
|
|
rbitfld.long 0x00 8. "ECC_TEST_FAIL,Status of ECC test" "0: ECC was performed,1: ECC test failed because eCT Flash macro is busy"
|
|
bitfld.long 0x00 4. "ECC_INJ_EN,eCT Flash SRAM ECC error injection test enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ECC_ENABLE,ECC generation/check enable for eCT Flash SRAM memory" "0,1"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "CM0_CA_CTL0,CM0+ cache control"
|
|
bitfld.long 0x00 31. "CA_EN,Cache enable" "0: Disabled,1: Enabled.G269"
|
|
bitfld.long 0x00 30. "PREF_EN,Prefetch enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "SET_ADDR,Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. "WAY,Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "RAM_ECC_INJ_EN,Enable error injection for cache" "0,1"
|
|
bitfld.long 0x00 0. "RAM_ECC_EN,Enable ECC checking for cache accesses" "0: Disabled,1: Enabled"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "CM0_CA_CTL1,CM0+ cache control"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)"
|
|
bitfld.long 0x00 0.--1. "PWR_MODE,Specifies power mode for CM0 cache" "0: Power OFF the CM0 cache SRAM,1: Undefined,2: Put CM0 cache SRAM in retained mode,3: Enable/Turn ON the CM0 cache SRAM"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "CM0_CA_CTL2,CM0+ cache control"
|
|
hexmask.long.word 0x00 0.--9. 1. "PWRUP_DELAY,Number clock cycles delay needed after power domain power up"
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "CM0_CA_STATUS0,CM0+ cache status 0"
|
|
hexmask.long 0x00 0.--31. 1. "VALID32,Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR"
|
|
rgroup.long 0x444++0x03
|
|
line.long 0x00 "CM0_CA_STATUS1,CM0+ cache status 1"
|
|
hexmask.long 0x00 0.--31. 1. "TAG,Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR"
|
|
rgroup.long 0x448++0x03
|
|
line.long 0x00 "CM0_CA_STATUS2,CM0+ cache status 2"
|
|
bitfld.long 0x00 0.--5. "LRU,Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR" "0: 2_LRU_3,1: 1_LRU_3,2: 1_LRU_2,3: 0_LRU_3,4: 0_LRU_2,5: 0_LRU_1,?..."
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "CM0_STATUS,CM0+ interface status"
|
|
bitfld.long 0x00 1. "WORK_INTERNAL_ERR,See CM0_STATUS.MAIN_INTERNAL_ERROR" "0,1"
|
|
bitfld.long 0x00 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ (or debug access via SYS_AP/CM0_AP) access" "0,1"
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "CM7_0_STATUS,CM7 #0 interface status"
|
|
bitfld.long 0x00 1. "WORK_INTERNAL_ERR,See CM7_0_STATUS.MAIN_INTERNAL_ERROR" "0,1"
|
|
bitfld.long 0x00 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_0 (or debug access via SYS_AP/CM7_0_AP) access" "0,1"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "CM7_1_STATUS,CM7 #1 interface status"
|
|
bitfld.long 0x00 1. "WORK_INTERNAL_ERR,See CM7_1_STATUS.MAIN_INTERNAL_ERROR" "0,1"
|
|
bitfld.long 0x00 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_1 (or debug access via SYS_AP/CM7_1_AP) access" "0,1"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "CRYPTO_BUFF_CTL,Cryptography buffer control"
|
|
bitfld.long 0x00 30. "PREF_EN,Prefetch enable" "0: Disabled,1: Enabled"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "DW0_BUFF_CTL,Datawire 0 buffer control"
|
|
bitfld.long 0x00 30. "PREF_EN,See CRYPTO_BUFF_CTL" "0,1"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "DW1_BUFF_CTL,Datawire 1 buffer control"
|
|
bitfld.long 0x00 30. "PREF_EN,See CRYPTO_BUFF_CTL" "0,1"
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "DMAC_BUFF_CTL,DMA controller buffer control"
|
|
bitfld.long 0x00 30. "PREF_EN,See CRYPTO_BUFF_CTL" "0,1"
|
|
group.long 0x780++0x03
|
|
line.long 0x00 "SLOW0_MS_BUFF_CTL,Slow external master 0 buffer control"
|
|
bitfld.long 0x00 30. "PREF_EN,See CRYPTO_BUFF_CTL" "0,1"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SLOW1_MS_BUFF_CTL,Slow external master 1 buffer control"
|
|
bitfld.long 0x00 30. "PREF_EN,See CRYPTO_BUFF_CTL" "0,1"
|
|
tree "FM_CTL_ECT"
|
|
group.long 0xF000++0x03
|
|
line.long 0x00 "FM_CTL,Flash Macro Control"
|
|
bitfld.long 0x00 31. "EMB_START,'0': not active '1': starts the actual embedded operation" "0,1"
|
|
bitfld.long 0x00 0.--4. "FM_MODE,Flash macro mode selection: d0: Read/Idle - Normal mode read array enabled d1: Not Used - the 1st analog POR is done by enable/enable_hv d2 - POR FUR Download - Downloads critical Flash initialization data from OTP (BG rd redu etc....) d3 - POR.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF004++0x03
|
|
line.long 0x00 "FM_CODE_MARGIN,Flash Macro Margin Mode on Code Flash"
|
|
bitfld.long 0x00 31. "MARGIN_MODE_EN,when set puts the s40ect Flash IP In Margin mode" "0,1"
|
|
bitfld.long 0x00 30. "MARGIN_MODE_RDREG_CHNG_EN,when set will also use the MARGIN_RDREG_TRIM from above" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "MARGIN_PGM_ERS_B," "0,1"
|
|
bitfld.long 0x00 10.--15. "MARGIN_RDREG_TRIM,rdreg_c trim to be used in Margin mode if enabled by MARGIN_MODE_RDREG_CHNG_EN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 9. "MARGIN_DCS_TRIM_EN," "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "MARGIN_DCS_TRIM,see above table to set the DCS reference current value to be used during Margin mode"
|
|
wgroup.long 0xF008++0x03
|
|
line.long 0x00 "FM_ADDR,Flash Macro Address"
|
|
hexmask.long 0x00 0.--31. 1. "FM_ADDR,Code or Work Flash Address to be used during write operations (PGM/ERS)"
|
|
group.long 0xF020++0x03
|
|
line.long 0x00 "INTR,Interrupt"
|
|
bitfld.long 0x00 0. "INTR,Set to '1' when event is detected" "0,1"
|
|
group.long 0xF024++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt Set"
|
|
bitfld.long 0x00 0. "INTR_SET,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
group.long 0xF028++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt Mask"
|
|
bitfld.long 0x00 0. "INTR_MASK,Mask for corresponding field in the INTR register" "0,1"
|
|
rgroup.long 0xF02C++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt Masked"
|
|
bitfld.long 0x00 0. "INTR_MASKED,Logical and of corresponding request and mask fields" "0,1"
|
|
wgroup.long 0xF030++0x03
|
|
line.long 0x00 "ECC_OVERRIDE,ECC Data In override information and control bits"
|
|
bitfld.long 0x00 31. "ECC_OVERRIDE_CODE," "0,1"
|
|
bitfld.long 0x00 30. "ECC_OVERRIDE_WORK," "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "ECC_OVERRIDE_SYNDROME,The override syndrome itself to be used in case one of the enables are set"
|
|
wgroup.long 0xF040++0x03
|
|
line.long 0x00 "FM_DATA,Flash macro data_in[31 to 0] both Code and Work Flash"
|
|
hexmask.long 0x00 0.--31. 1. "FM_DATA,Pgm command data in going to the internal write buffer (WBUF)"
|
|
group.long 0xF064++0x03
|
|
line.long 0x00 "BOOKMARK,Bookmark register - keeps the current FW HV seq"
|
|
hexmask.long 0x00 0.--31. 1. "BOOKMARK,Used by FW"
|
|
group.long 0xF400++0x03
|
|
line.long 0x00 "MAIN_FLASH_SAFETY,Main (Code) Flash Security enable"
|
|
bitfld.long 0x00 0. "MAINFLASHWRITEENABLE,'0': Main Flash embedded operations are blocked '1': Main Flash embedded operations are enabled" "0,1"
|
|
rgroup.long 0xF404++0x03
|
|
line.long 0x00 "STATUS,Status read from Flash Macro"
|
|
bitfld.long 0x00 31. "BUSY,Whenever the device is in embedded mode the RDY goes low" "0: rdy (high also in erase suspend),1: busy in embedded"
|
|
bitfld.long 0x00 30. "HANG,After embedded operation (pgm/erase) this flag will tell if it was successful or failed" "0: PASS,1: FAIL"
|
|
newline
|
|
bitfld.long 0x00 29. "NATIVE_POR,Indicates a Native Flash state (UV) or sorted one" "0: SORTED DEVICE,1: NATIVE"
|
|
bitfld.long 0x00 28. "POR_2B_ECC_ERROR,Indicates an internal ECC error of 2b while downloading info in POR from NVM to VM" "0: No error,1: ECC 2b Error in POR"
|
|
newline
|
|
bitfld.long 0x00 27. "POR_1B_ECC_CORRECTED,Indicates internal ECC found 1b error while downloading info in POR from NVM to VM and fixed it" "0: No error,1: 1b ECC Error corrected"
|
|
bitfld.long 0x00 6. "BLANK_CHCEK_PASS,Indicates the Blank check command result is PASS (Blank)" "0: Not Blank,1: Blank (PASS)"
|
|
newline
|
|
bitfld.long 0x00 5. "BLANK_CHECK_WORK,Indicates if Blank Check mode is currently running on the work flash" "0: not running,1: running"
|
|
bitfld.long 0x00 4. "ERS_SUSPEND,Indicates if Erase operation (Code/Work) is currently being suspended" "0: not suspended,1: suspended"
|
|
newline
|
|
bitfld.long 0x00 3. "ERASE_WORK,Indicates if active Erase operation to the Work flash is taking place" "0: not running,1: running"
|
|
bitfld.long 0x00 2. "ERASE_CODE,Indicates if active Erase operation to the Code flash is taking place" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x00 1. "PGM_WORK,Indicates if active PGM operation to the Work flash is taking place" "0: not running,1: running"
|
|
bitfld.long 0x00 0. "PGM_CODE,Indicates if active PGM operation to the Code flash is taking place" "0: not running,1: running"
|
|
group.long 0xF500++0x03
|
|
line.long 0x00 "WORK_FLASH_SAFETY,Work Flash Security enable"
|
|
bitfld.long 0x00 0. "WORKFLASHWRITEENABLE," "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "FLEXRAY0 (FlexRay Bus Interface)"
|
|
base ad:0x40560000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 31. "ENABLED,This bit enables the operation of this IP" "0: DISABLE,1: ENABLE"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DMA_CTL,DMA Control Register"
|
|
bitfld.long 0x00 2. "ODMAFFE,OBF DMA FIFO enable '0' : Disable: tr_obf_out is postponed until OBF is not busy" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x00 1. "ODMATOE,OBF DMA trigger output enable '0' : Disable: tr_obf_out = '0'" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x00 0. "IDMATOE,IBF DMA trigger output enable '0' : Disable: tr_ibf_out = '0'" "0: DISABLE,1: ENABLE"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TEST1,Test Register 1"
|
|
rbitfld.long 0x00 28.--31. "CERB,N/A" "0: NO_CODING_ERR,1: HEADER_CRC_ERR,2: FRAME_CRC_ERR,3: FRAME_START_SEQ_FSS_LONG,4: FIRST_BIT_OF_BSS_LOW,5: SECOND_BIT_OF_BSS_HIGH,6: FIRST_BIT_OF_FES_HIGH,7: SECOND_BIT_OF_FES_LOW,8: CAS_MTS_SYMBOL_SHORT,9: CAS_MTS_SYMBOL_LONG,?..."
|
|
rbitfld.long 0x00 24.--27. "CERA,N/A" "0: NO_CODING_ERR,1: HEADER_CRC_ERR,2: FRAME_CRC_ERR,3: FRAME_START_SEQ_FSS_LONG,4: FIRST_BIT_OF_BSS_LOW,5: SECOND_BIT_OF_BSS_HIGH,6: FIRST_BIT_OF_FES_HIGH,7: SECOND_BIT_OF_FES_LOW,8: CAS_MTS_SYMBOL_SHORT,9: CAS_MTS_SYMBOL_LONG,?..."
|
|
newline
|
|
bitfld.long 0x00 21. "TXENB,Control of Channel B Transmit Enable Pin This is used to test the interface to the physical layer (connectivity test) by driving the pin" "0: ERAY_TXEN2_N_0,1: ERAY_TXEN2_N_1"
|
|
bitfld.long 0x00 20. "TXENA,Control of Channel A Transmit Enable Pin This is used to test the interface to the physical layer (connectivity test) by driving the pin" "0: ERAY_TXEN1_N_0,1: ERAY_TXEN1_N_1"
|
|
newline
|
|
bitfld.long 0x00 19. "TXB,Control of Channel B Transmit Pin This is used to test the interface to the physical layer (connectivity test) by driving the pin" "0: ERAY_TXD2_0,1: ERAY_TXD2_1"
|
|
bitfld.long 0x00 18. "TXA,Control of Channel A Transmit Pin This is used to test the interface to the physical layer (connectivity test) by driving the pin" "0: ERAY_TXD1_0,1: ERAY_TXD1_1"
|
|
newline
|
|
rbitfld.long 0x00 17. "RXB,Monitor Channel B Receive Pin This is used to test the interface to the physical layer (connectivity test) by reading the pin" "0: ERAY_RXD2_0,1: ERAY_RXD2_1"
|
|
rbitfld.long 0x00 16. "RXA,Monitor Channel A Receive Pin This is used to test the interface to the physical layer (connectivity test) by reading the pin" "0: ERAY_RXD1_0,1: ERAY_RXD1_1"
|
|
newline
|
|
rbitfld.long 0x00 9. "AOB,Activity on B AOB is set when there is activity on channel B" "0: NOACT_DETECT_CH_B_IDLE,1: ACT_DETECT_CH_B_NOT_IDLE"
|
|
rbitfld.long 0x00 8. "AOA,Activity on A AOA is set when there is activity on channel A" "0: NOACT_DETECT_CH_A_IDLE,1: ACT_DETECT_CH_A_NOT_IDLE"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "TMC,Test Multiplexer Control 00" "0: NORMAL_SIGNAL_PATH,1: RAM_TEST_MODE,2: IO_TEST_MODE,3: NORMAL_SIGNAL_PATH_MIRROR"
|
|
bitfld.long 0x00 1. "ELBE,External Loop Back Enable There are two possibilities to perform a Loop Back test" "0: INTERNAL_LOOP_BACK,1: EXTERNAL_LOOP_BACK"
|
|
newline
|
|
bitfld.long 0x00 0. "WRTEN,Write Test Register Enable Enables write access to the test registers" "0: TEST_REG_WR_DISABLED,1: TEST_REG_WR_ENABLED"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TEST2,Test Register 2"
|
|
rbitfld.long 0x00 15. "RDPB,Read Parity Bit Value of parity bit read from bit 32 of the addressed RAM word" "0,1"
|
|
bitfld.long 0x00 14. "WRPB,Write Parity Bit Value of parity bit to be written to bit 32 of the addressed RAM word" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "SSEL,Segment Select To enable access to the complete Message RAM (8192 byte addresses) the Message RAM is segmented" "0: ADDR_0000_TO_03FF_ENABLED,1: ADDR_0400_TO_07FF_ENABLED,2: ADDR_0800_TO_0BFF_ENABLED,3: ADDR_0C00_TO_0FFF_ENABLED,4: ADDR_1000_TO_13FF_ENABLED,5: ADDR_1400_TO_17FF_ENABLED,6: ADDR_1800_TO_1BFF_ENABLED,7: ADDR_1C00_TO_1FFF_ENABLED"
|
|
bitfld.long 0x00 0.--2. "RS,RAM Select In RAM Test mode the RAM blocks selected by RS[2:0] are mapped to module address 0x400 to 7FF (1024 byte addresses)" "0: IBF1,1: IBF2,2: OBF1,3: OBF2,4: TBF1,5: TBF2,6: MBF,?..."
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "LCK,Lock Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TMK,Test Mode Key To write bit TEST1.WRTEN the write operation has to be directly preceded by two consecutive write accesses to the Test Mode Key (unlock sequence)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLK,Configuration Lock Key To leave CONFIG state by writing SUCC1.CMD[3:0] (commands READY MONITOR_MODE ATM LOOP_BACK) the write operation has to be directly preceded by two write accesses to the Configuration Lock Key (unlock sequence)"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EIR,Error Interrupt Register"
|
|
bitfld.long 0x00 26. "TABB,Transmission Across Boundary Channel B The flag signals to the Host that a transmission across a slot boundary occurred for channel B" "0: NO_CH_B_TX_ACROSS_SLOT_BOUND_DETECTED,1: CH_B_TX_ACROSS_SLOT_BOUND_DETECTED"
|
|
bitfld.long 0x00 25. "LTVB,Latest Transmit Violation Channel B The flag signals a latest transmit violation on channel B to the Host" "0: NO_CH_B_LATEST_TX_VIOLATION_DETECTED,1: CH_B_LATEST_TX_VIOLATION_DETECTED"
|
|
newline
|
|
bitfld.long 0x00 24. "EDB,Error Detected on Channel B This bit is set whenever one of the flags ACS.SEDB ACS.CEDB ACS.CIB ACS.SBVB changes from '0' to '1'" "0: NO_CH_B_ERR_DETECTED,1: CH_B_ERR_DETECTED"
|
|
bitfld.long 0x00 18. "TABA,Transmission Across Boundary Channel A The flag signals to the Host that a transmission across a slot boundary occurred for channel A" "0: NO_CH_A_TX_ACROSS_SLOT_BOUND_DETECTED,1: CH_A_TX_ACROSS_SLOT_BOUND_DETECTED"
|
|
newline
|
|
bitfld.long 0x00 17. "LTVA,Latest Transmit Violation Channel A The flag signals a latest transmit violation on channel A to the Host" "0: NO_CH_A_LATEST_TX_VIOLATION_DETECTED,1: CH_A_LATEST_TX_VIOLATION_DETECTED"
|
|
bitfld.long 0x00 16. "EDA,Error Detected on Channel A This bit is set whenever one of the flags ACS.SEDA ACS.CEDA ACS.CIA ACS.SBVA changes from '0' to '1'" "0: NO_CH_A_ERR_DETECTED,1: CH_A_ERR_DETECTED"
|
|
newline
|
|
bitfld.long 0x00 11. "MHF,Message Handler Constraints Flag The flag signals a Message Handler constraints violation condition" "0: NO_MSG_HANDLER_FAIL_DETECT,1: MSG_HANDLER_FAIL_DETECT"
|
|
bitfld.long 0x00 10. "IOBA,Illegal Output buffer Access This flag is set by the CC when the Host requests the transfer of a message buffer from the Message RAM to the Output Buffer while OBCR.OBSYS is set to '1'" "0: NO_ILLEGAL_OBF_ACCESS,1: ILLEGAL_OBF_ACCESS"
|
|
newline
|
|
bitfld.long 0x00 9. "IIBA,Illegal Input Buffer Access This flag is set by the CC when the Host wants to modify a message buffer via Input Buffer and one of the following conditions applies: 1) The CC is not in CONFIG or DEFAULT_CONFIG state and the Host writes to the Input.." "0: NO_ILLEGAL_IBF_ACCESS,1: ILLEGAL_IBF_ACCESS"
|
|
bitfld.long 0x00 8. "EFA,Empty FIFO Access This flag is set by the CC when the Host requests the transfer of a message from the receive FIFO via Output Buffer while the receive FIFO is empty" "0: NO_EMPTY_FIFO_ACCESS,1: EMPTY_FIFO_ACCESS"
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bitfld.long 0x00 7. "RFO,Receive FIFO Overrun The flag is set by the CC when a receive FIFO overrun is detected" "0: NO_RECEIVE_FIFO_OVERRUN,1: RECEIVE_FIFO_OVERRUN"
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bitfld.long 0x00 6. "PERR,Parity Error The flag signals a parity error to the Host" "0: NO_PARITY_ERR,1: PARITY_ERR"
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bitfld.long 0x00 5. "CCL,CHI Command Locked The flag signals that the write access to the CHI command vector SUCC1.CMD[3:0] was not successful because the execution of the previous CHI command has not yet completed" "0: CHI_CMD_ACCEPTED,1: CHI_CMD_NOT_ACCEPTED"
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bitfld.long 0x00 4. "CCF,Clock Correction Failure This flag is set at the end of the cycle whenever one of the following errors occurred: Missing offset and / or rate correction Clock correction limit reached The clock correction status is monitored in registers CCEV and SFS" "0: NO_CLK_CORRECTION_ERR,1: CLK_CORRECTION_ERR"
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bitfld.long 0x00 3. "SFO,Sync Frame Overflow Set when either the number of sync frames received during the last communication cycle or the total number of different sync frame IDs received during the last double cycle exceeds the maximum number of sync frames as defined by.." "0: NO_SYNC_FRAME_OVERFLOW,1: SYNC_FRAME_OVERFLOW"
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bitfld.long 0x00 2. "SFBM,Sync Frames Below Minimum This flag signals that the number of sync frames received during the last communication cycle was below the limit required by the FlexRay protocol" "0: SYNC_FRAMES_NOT_BELOW_MIN,1: SYNC_FRAMES_BELOW_MIN"
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bitfld.long 0x00 1. "CNA,Command Not Accepted The flag signals that the write access to the CHI command vector SUCC1.CMD[3:0] was not successful because the requested command was not valid in the actual POC state or because the CHI command was locked (CCL = '1')" "0: CHI_CMD_ACCEPTED,1: CHI_CMD_NOT_ACCEPTED"
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bitfld.long 0x00 0. "PEMC,POC Error Mode Changed This flag is set whenever the error mode signalled by CCEV.ERRM[1:0] has changed" "0: POC_ERR_MODE_UNCHANGED,1: POC_ERR_MODE_CHANGED"
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group.long 0x24++0x03
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line.long 0x00 "SIR,Status Interrupt Register"
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bitfld.long 0x00 25. "MTSB,MTS Received on Channel B (vSS!ValidMTSB) Media Access Test symbol received on channel B during the preceding symbol window" "0: NO_MTS_SYMBOL_RXD_ON_CH_B,1: MTS_SYMBOL_RXD_ON_CH_B"
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bitfld.long 0x00 24. "WUPB,Wakeup Pattern Channel B This flag is set by the CC when a wakeup pattern was received on channel B" "0: NO_WAKEUP_PATTERN_RXD_ON_CH_B,1: WAKEUP_PATTERN_RXD_ON_CH_B"
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bitfld.long 0x00 17. "MTSA,MTS Received on Channel A (vSS!ValidMTSA) Media Access Test symbol received on channel A during the preceding symbol window" "0: NO_MTS_SYMBOL_RXD_ON_CH_A,1: MTS_SYMBOL_RXD_ON_CH_A"
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bitfld.long 0x00 16. "WUPA,Wakeup Pattern Channel A This flag is set by the CC when a wakeup pattern was received on channel A" "0: NO_WAKEUP_PATTERN_RXD_ON_CH_A,1: WAKEUP_PATTERN_RXD_ON_CH_A"
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bitfld.long 0x00 15. "SDS,Start of Dynamic Segment This flag is set by the CC when the dynamic segment starts" "0: DYNAMIC_SEGMENT_NOT_STARTED,1: DYNAMIC_SEGMENT_STARTED"
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bitfld.long 0x00 14. "MBSI,Message Buffer Status Interrupt This flag is set by the CC when the message buffer status MBS has changed and if bit MBI of that message buffer is set (see Table 17)" "0: NO_MSG_BUFF_STATUS_CHANGED,1: MSG_BUFF_STATUS_CHANGED"
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bitfld.long 0x00 13. "SUCS,Startup Completed Successfully This flag is set whenever a startup completed successfully and the CC entered NORMAL_ACTIVE state" "0: NO_STARTUP_COMPLETED,1: STARTUP_COMPLETED"
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bitfld.long 0x00 12. "SWE,Stop Watch Event This flag is set after a stop watch activation when the actual cycle counter and macrotick value are stored in the Stop Watch register (see [01]Section 4.4.10 Stop Watch Register 1 (STPW1))" "0: NO_STOP_WATCH_EVENT,1: STOP_WATCH_EVENT_OCCURRED"
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bitfld.long 0x00 11. "TOBC,Transfer Output Buffer Completed This flag is set whenever a transfer from the Message RAM to the Output Buffer has completed and OBCR.OBSYS has been reset by the Message Handler" "0: NO_TRANSFER_COMPLETED,1: MSGRAM_TO_OBF_TRANSFER_COMPLETED"
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bitfld.long 0x00 10. "TIBC,Transfer Input Buffer Completed This flag is set whenever a transfer from Input Buffer to the Message RAM has completed and IBCR.IBSYS has been reset by the Message Handler" "0: NO_TRANSFER_COMPLETED,1: IBF_TO_MSGRAM_TRANSFER_COMPLETED"
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bitfld.long 0x00 9. "TI1,Timer Interrupt 1 This flag is set whenever timer 1 matches the conditions configured in register T1C" "0: NO_TIMER_INTERRUPT_1,1: TIMER_INTERRUPT_1_OCCURED"
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bitfld.long 0x00 8. "TI0,Timer Interrupt 0 This flag is set whenever timer 0 matches the conditions configured in register T0C" "0: NO_TIMER_INTERRUPT_0,1: TIMER_INTERRUPT_0_OCCURED"
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bitfld.long 0x00 7. "NMVC,Network Management Vector Changed This interrupt flag signals a change in the Network Management Vector visible to the Host" "0: NTWK_MGMT_VECTOR_UNCHANGED,1: NTWK_MGMT_VECTOR_CHANGED"
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bitfld.long 0x00 6. "RFCL,Receive FIFO Critical Level This flag is set when the receive FIFO fill level FSR.RFFL[7:0] is equal or greater than the critical level as configured by FCL.CL[7:0]" "0: RX_FIFO_BELOW_CRITICAL_LEVEL,1: RX_FIFO_NOT_BELOW_CRITICAL_LEVEL"
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bitfld.long 0x00 5. "RFNE,Receive FIFO Not Empty This flag is set by the CC when a received valid frame was stored into the empty receive FIFO" "0: RX_FIFO_EMPTY,1: RX_FIFO_NOT_EMPTY"
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bitfld.long 0x00 4. "RXI,Receive Interrupt This flag is set by the CC whenever the set condition of a message buffers ND flag is fulfilled see 4.8.6 New Data 1/2/3/4 (NDAT1/2/3/4)) and if bit MBI of that message buffer is set to '1' see Table 17). 1 = At least one ND flag.." "0: NO_ND_FLAG_OF_RX_MBI_BUFF_SET,1: ND_FLAG_OF_RX_MBI_BUFF_SET"
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bitfld.long 0x00 3. "TXI,Transmit Interrupt This flag is set by the CC at the end of frame transmission if bit MBI in the respective message buffer is set to '1' (see Table 17)" "0: NO_FRAME_TXED_FROM_TX_MBI_BUFF,1: FRAME_TXED_FROM_TX_MBI_BUFF"
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bitfld.long 0x00 2. "CYCS,Cycle Start Interrupt This flag is set by the CC when a communication cycle starts" "0: NO_COMM_CYCLE_STARTED,1: COMM_CYCLE_STARTED"
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bitfld.long 0x00 1. "CAS,Collision Avoidance Symbol This flag is set by the CC during STARTUP state when a CAS or a potential CAS was received" "0: NO_CAS_BIT_PATTERN_MATCH,1: CAS_BIT_PATTERN_MATCH"
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bitfld.long 0x00 0. "WST,Wakeup Status This flag is set when CCSV.WSV[2:0] changes to a value other than UNDEFINED" "0: WAKEUP_STATUS_UNCHANGED,1: WAKEUP_STATUS_CHANGED"
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group.long 0x28++0x03
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line.long 0x00 "EILS,Error Interrupt Line Select"
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bitfld.long 0x00 26. "TABBL,Transmission Across Boundary Channel B Interrupt Line" "0,1"
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bitfld.long 0x00 25. "LTVBL,Latest Transmit Violation Channel B Interrupt Line" "0,1"
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bitfld.long 0x00 24. "EDBL,Error Detected on Channel B Interrupt Line" "0,1"
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bitfld.long 0x00 18. "TABAL,Transmission Across Boundary Channel A Interrupt Line" "0,1"
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bitfld.long 0x00 17. "LTVAL,Latest Transmit Violation Channel A Interrupt Line" "0,1"
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bitfld.long 0x00 16. "EDAL,Error Detected on Channel A Interrupt Line" "0,1"
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bitfld.long 0x00 11. "MHFL,Message Handler Constraints Flag Interrupt Line" "0,1"
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bitfld.long 0x00 10. "IOBAL,Illegal Output Buffer Access Interrupt Line" "0,1"
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bitfld.long 0x00 9. "IIBAL,Illegal Input Buffer Access Interrupt Line" "0,1"
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bitfld.long 0x00 8. "EFAL,Empty FIFO Access Interrupt Line" "0,1"
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bitfld.long 0x00 7. "RFOL,Receive FIFO Overrun Interrupt Line" "0,1"
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bitfld.long 0x00 6. "PERRL,Parity Error Interrupt Line" "0,1"
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bitfld.long 0x00 5. "CCLL,CHI Command Locked Interrupt Line" "0,1"
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bitfld.long 0x00 4. "CCFL,Clock Correction Failure Interrupt Line" "0,1"
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bitfld.long 0x00 3. "SFOL,Sync Frame Overflow Interrupt Line" "0,1"
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bitfld.long 0x00 2. "SFBML,Sync Frames Below Minimum Interrupt Line" "0,1"
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bitfld.long 0x00 1. "CNAL,Command Not Accepted Interrupt Line" "0,1"
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bitfld.long 0x00 0. "PEMCL,POC Error Mode Changed Interrupt Line" "0,1"
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group.long 0x2C++0x03
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line.long 0x00 "SILS,Status Interrupt Line Select"
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bitfld.long 0x00 25. "MTSBL,Media Access Test Symbol Channel B Interrupt Line" "0,1"
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bitfld.long 0x00 24. "WUPBL,Wakeup Pattern Channel B Interrupt Line" "0,1"
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bitfld.long 0x00 17. "MTSAL,Media Access Test Symbol Channel A Interrupt Line" "0,1"
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bitfld.long 0x00 16. "WUPAL,Wakeup Pattern Channel A Interrupt Line" "0,1"
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bitfld.long 0x00 15. "SDSL,Start of Dynamic Segment Interrupt Line" "0,1"
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bitfld.long 0x00 14. "MBSIL,Message Buffer Status Interrupt Line" "0,1"
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bitfld.long 0x00 13. "SUCSL,Startup Completed Successfully Interrupt Line" "0,1"
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bitfld.long 0x00 12. "SWEL,Stop Watch Event Interrupt Line" "0,1"
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bitfld.long 0x00 11. "TOBCL,Transfer Output Buffer Completed Interrupt Line" "0,1"
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bitfld.long 0x00 10. "TIBCL,Transfer Input Buffer Completed Interrupt Line" "0,1"
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bitfld.long 0x00 9. "TI1L,Timer Interrupt 1 Line" "0,1"
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bitfld.long 0x00 8. "TI0L,Timer Interrupt 0 Line" "0,1"
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bitfld.long 0x00 7. "NMVCL,Network Management Vector Changed Interrupt Line" "0,1"
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bitfld.long 0x00 6. "RFCLL,Receive FIFO Critical Level Interrupt Line" "0,1"
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bitfld.long 0x00 5. "RFNEL,Receive FIFO Not Empty Interrupt Line" "0,1"
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bitfld.long 0x00 4. "RXIL,Receive Interrupt Line" "0,1"
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bitfld.long 0x00 3. "TXIL,Transmit Interrupt Line" "0,1"
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bitfld.long 0x00 2. "CYCSL,Cycle Start Interrupt Line" "0,1"
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bitfld.long 0x00 1. "CASL,Collision Avoidance Symbol Interrupt Line" "0,1"
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bitfld.long 0x00 0. "WSTL,Wakeup Status Interrupt Line" "0,1"
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group.long 0x30++0x03
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line.long 0x00 "EIES,Error Interrupt Enable Set"
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bitfld.long 0x00 26. "TABBE,Transmission Across Boundary Channel B Interrupt Enable" "0,1"
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bitfld.long 0x00 25. "LTVBE,Latest Transmit Violation Channel B Interrupt Enable" "0,1"
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bitfld.long 0x00 24. "EDBE,Error Detected on Channel B Interrupt Enable" "0,1"
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bitfld.long 0x00 18. "TABAE,Transmission Across Boundary Channel A Interrupt Enable" "0,1"
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bitfld.long 0x00 17. "LTVAE,Latest Transmit Violation Channel A Interrupt Enable" "0,1"
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bitfld.long 0x00 16. "EDAE,Error Detected on Channel A Interrupt Enable" "0,1"
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bitfld.long 0x00 11. "MHFE,Message Handler Constraints Flag Interrupt Enable" "0,1"
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bitfld.long 0x00 10. "IOBAE,Illegal Output Buffer Access Interrupt Enable" "0,1"
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bitfld.long 0x00 9. "IIBAE,Illegal Input Buffer Access Interrupt Enable" "0,1"
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bitfld.long 0x00 8. "EFAE,Empty FIFO Access Interrupt Enable" "0,1"
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bitfld.long 0x00 7. "RFOE,Receive FIFO Overrun Interrupt Enable" "0,1"
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bitfld.long 0x00 6. "PERRE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x00 5. "CCLE,CHI Command Locked Interrupt Enable" "0,1"
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bitfld.long 0x00 4. "CCFE,Clock Correction Failure Interrupt Enable" "0,1"
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bitfld.long 0x00 3. "SFOE,Sync Frame Overflow Interrupt Enable" "0,1"
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bitfld.long 0x00 2. "SFBME,Sync Frames Below Minimum Interrupt Enable" "0,1"
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bitfld.long 0x00 1. "CNAE,Command Not Accepted Interrupt Enable" "0,1"
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bitfld.long 0x00 0. "PEMCE,POC Error Mode Changed Interrupt Enable" "0,1"
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group.long 0x34++0x03
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line.long 0x00 "EIER,Error Interrupt Enable Reset"
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bitfld.long 0x00 26. "TABBE,Transmission Across Boundary Channel B Interrupt Enable" "0,1"
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bitfld.long 0x00 25. "LTVBE,Latest Transmit Violation Channel B Interrupt Enable" "0,1"
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bitfld.long 0x00 24. "EDBE,Error Detected on Channel B Interrupt Enable" "0,1"
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bitfld.long 0x00 18. "TABAE,Transmission Across Boundary Channel A Interrupt Enable" "0,1"
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bitfld.long 0x00 17. "LTVAE,Latest Transmit Violation Channel A Interrupt Enable" "0,1"
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bitfld.long 0x00 16. "EDAE,Error Detected on Channel A Interrupt Enable" "0,1"
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bitfld.long 0x00 11. "MHFE,Message Handler Constraints Flag Interrupt Enable" "0,1"
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bitfld.long 0x00 10. "IOBAE,Illegal Output Buffer Access Interrupt Enable" "0,1"
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bitfld.long 0x00 9. "IIBAE,Illegal Input Buffer Access Interrupt Enable" "0,1"
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bitfld.long 0x00 8. "EFAE,Empty FIFO Access Interrupt Enable" "0,1"
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bitfld.long 0x00 7. "RFOE,Receive FIFO Overrun Interrupt Enable" "0,1"
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bitfld.long 0x00 6. "PERRE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x00 5. "CCLE,CHI Command Locked Interrupt Enable" "0,1"
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bitfld.long 0x00 4. "CCFE,Clock Correction Failure Interrupt Enable" "0,1"
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bitfld.long 0x00 3. "SFOE,Sync Frame Overflow Interrupt Enable" "0,1"
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bitfld.long 0x00 2. "SFBME,Sync Frames Below Minimum Interrupt Enable" "0,1"
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bitfld.long 0x00 1. "CNAE,Command Not Accepted Interrupt Enable" "0,1"
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bitfld.long 0x00 0. "PEMCE,POC Error Mode Changed Interrupt Enable" "0,1"
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group.long 0x38++0x03
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line.long 0x00 "SIES,Status Interrupt Enable Set"
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bitfld.long 0x00 25. "MTSBE,MTS Received on Channel B Interrupt Enable" "0,1"
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bitfld.long 0x00 24. "WUPBE,Wakeup Pattern Channel B Interrupt Enable" "0,1"
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bitfld.long 0x00 17. "MTSAE,MTS Received on Channel A Interrupt Enable" "0,1"
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bitfld.long 0x00 16. "WUPAE,Wakeup Pattern Channel A Interrupt Enable" "0,1"
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bitfld.long 0x00 15. "SDSE,Start of Dynamic Segment Interrupt Enable" "0,1"
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bitfld.long 0x00 14. "MBSIE,Message Buffer Status Interrupt Enable" "0,1"
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bitfld.long 0x00 13. "SUCSE,Startup Completed Successfully Interrupt Enable" "0,1"
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bitfld.long 0x00 12. "SWEE,Stop Watch Event Interrupt Enable" "0,1"
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bitfld.long 0x00 11. "TOBCE,Transfer Output Buffer Completed Interrupt Enable" "0,1"
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bitfld.long 0x00 10. "TIBCE,Transfer Input Buffer Completed Interrupt Enable" "0,1"
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bitfld.long 0x00 9. "TI1E,Timer Interrupt 1 Enable" "0,1"
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bitfld.long 0x00 8. "TI0E,Timer Interrupt 0 Enable" "0,1"
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bitfld.long 0x00 7. "NMVCE,Network Management Vector Changed Interrupt Enable" "0,1"
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bitfld.long 0x00 6. "RFCLE,Receive FIFO Critical Level Interrupt Enable" "0,1"
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bitfld.long 0x00 5. "RFNEE,Receive FIFO Not Empty Interrupt Enable" "0,1"
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bitfld.long 0x00 4. "RXIE,Receive Interrupt Enable" "0,1"
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bitfld.long 0x00 3. "TXIE,Transmit Interrupt Enable" "0,1"
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bitfld.long 0x00 2. "CYCSE,Cycle Start Interrupt Enable" "0,1"
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bitfld.long 0x00 1. "CASE,Collision Avoidance Symbol Interrupt Enable" "0,1"
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bitfld.long 0x00 0. "WSTE,Wakeup Status Interrupt Enable" "0,1"
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group.long 0x3C++0x03
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line.long 0x00 "SIER,Status Interrupt Enable Reset"
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bitfld.long 0x00 25. "MTSBE,MTS Received on Channel B Interrupt Enable" "0,1"
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bitfld.long 0x00 24. "WUPBE,Wakeup Pattern Channel B Interrupt Enable" "0,1"
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bitfld.long 0x00 17. "MTSAE,MTS Received on Channel A Interrupt Enable" "0,1"
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bitfld.long 0x00 16. "WUPAE,Wakeup Pattern Channel A Interrupt Enable" "0,1"
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bitfld.long 0x00 15. "SDSE,Start of Dynamic Segment Interrupt Enable" "0,1"
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bitfld.long 0x00 14. "MBSIE,Message Buffer Status Interrupt Enable" "0,1"
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bitfld.long 0x00 13. "SUCSE,Startup Completed Successfully Interrupt Enable" "0,1"
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bitfld.long 0x00 12. "SWEE,Stop Watch Event Interrupt Enable" "0,1"
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bitfld.long 0x00 11. "TOBCE,Transfer Output Buffer Completed Interrupt Enable" "0,1"
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bitfld.long 0x00 10. "TIBCE,Transfer Input Buffer Completed Interrupt Enable" "0,1"
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newline
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bitfld.long 0x00 9. "TI1E,Timer Interrupt 1 Enable" "0,1"
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bitfld.long 0x00 8. "TI0E,Timer Interrupt 0 Enable" "0,1"
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bitfld.long 0x00 7. "NMVCE,Network Management Vector Changed Interrupt Enable" "0,1"
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bitfld.long 0x00 6. "RFCLE,Receive FIFO Critical Level Interrupt Enable" "0,1"
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bitfld.long 0x00 5. "RFNEE,Receive FIFO Not Empty Interrupt Enable" "0,1"
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bitfld.long 0x00 4. "RXIE,Receive Interrupt Enable" "0,1"
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bitfld.long 0x00 3. "TXIE,Transmit Interrupt Enable" "0,1"
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bitfld.long 0x00 2. "CYCSE,Cycle Start Interrupt Enable" "0,1"
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bitfld.long 0x00 1. "CASE,Collision Avoidance Symbol Interrupt Enable" "0,1"
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bitfld.long 0x00 0. "WSTE,Wakeup Status Interrupt Enable" "0,1"
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group.long 0x40++0x03
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line.long 0x00 "ILE,Interrupt Line Enable"
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bitfld.long 0x00 1. "EINT1_,Enable Interrupt Line 1" "0: ERAY_INT1_DISABLED,1: ERAY_INT1_ENABLED"
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bitfld.long 0x00 0. "EINT0_,Enable Interrupt Line 0" "0: ERAY_INT0_DISABLED,1: ERAY_INT0_ENABLED"
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group.long 0x44++0x03
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line.long 0x00 "T0C,Timer 0 Configuration"
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hexmask.long.word 0x00 16.--29. 1. "T0MO,Timer 0 Macrotick Offset Configures the macrotick offset from the beginning of the cycle where the interrupt is to occur"
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hexmask.long.byte 0x00 8.--14. 1. "T0CC,Timer 0 Cycle Code The 7-bit timer 0 cycle code determines the cycle set used for generation of the timer 0 interrupt"
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bitfld.long 0x00 1. "T0MS,Timer 0 Mode Select" "0: TIMER_0_SINGLE_SHOT_MODE,1: TIMER_0_CONTINUOUS_MODE"
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bitfld.long 0x00 0. "T0RC,Timer 0 Run Control" "0: TIMER_0_HALTED,1: TIMER_0_RUNNING"
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group.long 0x48++0x03
|
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line.long 0x00 "T1C,Timer 1 Configuration"
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hexmask.long.word 0x00 16.--29. 1. "T1MC,Timer 1 Macrotick Count When the configured macrotick count is reached the timer 1 interrupt is generated"
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bitfld.long 0x00 1. "T1MS,Timer 1 Mode Select" "0: TIMER_1_SINGLE_SHOT_MODE,1: TIMER_1_CONTINUOUS_MODE"
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bitfld.long 0x00 0. "T1RC,Timer 1 Run Control" "0: TIMER_1_HALTED,1: TIMER_1_RUNNING"
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group.long 0x4C++0x03
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line.long 0x00 "STPW1,Stop Watch Register 1"
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hexmask.long.word 0x00 16.--29. 1. "SMTV,Stop Watch Captured Macrotick Value State of the macrotick counter when the stop watch event occurred"
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rbitfld.long 0x00 8.--13. "SCCV,Stop Watch Captured Cycle Counter Value State of the cycle counter when the stop watch event occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "EINT1,Enable Interrupt 1 Trigger Enables stop watch trigger by interrupt 1event if ESWT = '1'" "0: STPWT_TRIGGER_BY_INT1_DISABLED,1: STPWT_TRIGGER_BY_INT1_ENABLED"
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bitfld.long 0x00 5. "EINT0,Enable Interrupt 0 Trigger Enables stop watch trigger by interrupt 0 event if ESWT = '1'" "0: STPWT_TRIGGER_BY_INT0_DISABLED,1: STPWT_TRIGGER_BY_INT0_ENABLED"
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bitfld.long 0x00 4. "EETP,Enable External Trigger Pin Enables stop watch trigger event via pin eray_stpwt if ESWT = '1'" "0: ESTPWT_DISABLED,1: ESTPWT_ENABLED"
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bitfld.long 0x00 3. "SSWT,Software Stop Watch Trigger When the Host writes this bit to '1' the stop watch is activated" "0: STOP_WATCH_SOFTWARE_TRIGGER_RESET,1: STOP_WATCH_SOFTWARE_TRIGGER_ACTIVATED"
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bitfld.long 0x00 2. "EDGE,Stop Watch Trigger Edge Select" "0: STOP_WATCH_FALLING_EDGE,1: STOP_WATCH_RISING_EDGE"
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bitfld.long 0x00 1. "SWMS,Stop Watch Mode Select" "0: STOP_WATCH_SINGLE_SHOT_MODE,1: STOP_WATCH_CONTINUOUS_MODE"
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bitfld.long 0x00 0. "ESWT,Enable Stop Watch Trigger If enabled an edge on input eray_stpwt or an interrupt 0 1 event (rising edge on pin eray_int0 or eray_int1) activates the stop watch" "0: STOP_WATCH_TRIGGER_DISABLED,1: STOP_WATCH_TRIGGER_ENABLED"
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rgroup.long 0x50++0x03
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line.long 0x00 "STPW2,Stop Watch Register 2"
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hexmask.long.word 0x00 16.--26. 1. "SSCVB,Stop Watch Captured Slot Counter Value Channel B State of the slot counter for channel B when the stop watch event occurred"
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hexmask.long.word 0x00 0.--10. 1. "SSCVA,Stop Watch Captured Slot Counter Value Channel A State of the slot counter for channel A when the stop watch event occurred"
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group.long 0x80++0x03
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line.long 0x00 "SUCC1,SUC Configuration Register 1"
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bitfld.long 0x00 27. "CCHB,Connected to Channel B (pChannels) Configures whether the node is connected to channel B" "0: CH_B_NOT_CONNECTED,1: CH_B_CONNECTED"
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bitfld.long 0x00 26. "CCHA,Connected to Channel A (pChannels) Configures whether the node is connected to channel A" "0: CH_A_NOT_CONNECTED,1: CH_A_CONNECTED"
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bitfld.long 0x00 25. "MTSB_,Select Channel B for MTS Transmission The bit selects channel B for MTS symbol transmission" "0: CH_B_DISABLED_FOR_MTS_TXMN,1: CH_B_SELECTED_FOR_MTS_TXMN"
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bitfld.long 0x00 24. "MTSA_,Select Channel A for MTS Transmission The bit selects channel A for MTS symbol transmission" "0: CH_A_DISABLED_FOR_MTS_TXMN,1: CH_A_SELECTED_FOR_MTS_TXMN"
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bitfld.long 0x00 23. "HCSE,Halt due to Clock Sync Error (pAllowHaltDueToClock) Controls the transition to HALT state due to a clock synchronization error" "0: CC_TO_ENTER_NORMAL_PASSIVE,1: CC_TO_ENTER_HALT"
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bitfld.long 0x00 22. "TSM,Transmission Slot Mode (pSingleSlotEnabled) Selects the initial transmission slot mode" "0: ALL_SLOT_MODE,1: SINGLE_SLOT_MODE"
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bitfld.long 0x00 21. "WUCS,Wakeup Channel Select (pWakeupChannel) With this bit the Host selects the channel on which the CC sends the Wakeup pattern" "0: SEND_WKUP_PATTERN_ON_CH_A,1: SEND_WKUP_PATTERN_ON_CH_B"
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bitfld.long 0x00 16.--20. "PTA,Passive to Active (pAllowPassiveToActive) Defines the number of consecutive even / odd cycle pairs that must have valid clock correction terms before the CC is allowed to transit from NORMAL_PASSIVE to NORMAL_ACTIVE state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 11.--15. "CSA,Cold Start Attempts (gColdStartAttempts) Configures the maximum number of attempts that a cold starting node is permitted to try to start up the network without receiving any valid response from another node" "?,?,2: MIN,?..."
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bitfld.long 0x00 9. "TXSY,Transmit Sync Frame in Key Slot (pKeySlotUsedForSync) Defines whether the key slot is used to transmit sync frames" "0: NO_SYNC_FRAME_TXMN,1: SYNC_FRAME_TXMN"
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bitfld.long 0x00 8. "TXST,Transmit Startup Frame in Key Slot (pKeySlotUsedForStartup) Defines whether the key slot is used to transmit startup frames" "0: NO_STARTUP_FRAME_TXMN,1: STARTUP_FRAME_TXMN"
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rbitfld.long 0x00 7. "PBSY,POC Busy Signals that the POC is busy and cannot accept a command from the Host" "0: POC_NOT_BUSY,1: POC_BUSY"
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bitfld.long 0x00 0.--3. "CMD,N/A" "0: CMD_NOT_ACCEPTED,1: CONFIG,2: READY,3: WAKEUP,4: RUN,5: ALL_SLOTS,6: HALT,7: FREEZE,8: SEND_MTS,9: ALLOW_COLDSTART,10: RESET_STATUS_INDICATORS,11: MONITOR_MODE,12: CLEAR_RAMS,?..."
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group.long 0x84++0x03
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line.long 0x00 "SUCC2,SUC Configuration Register 2"
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bitfld.long 0x00 24.--27. "LTN,Listen Timeout Noise (gListenNoise - 1) Configures the upper limit for startup and wakeup listen timeout in the presence of noise expressed as a multiple of pdListenTimeout" "?,1: MIN,?..."
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hexmask.long.tbyte 0x00 0.--20. 1. "LT,Listen Timeout (pdListenTimeout) Configures wakeup / startup listen timeout in uT"
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group.long 0x88++0x03
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line.long 0x00 "SUCC3,SUC Configuration Register 3"
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bitfld.long 0x00 4.--7. "WCF,Maximum Without Clock Correction Fatal (gMaxWithoutClockCorrectionFatal) Defines the number of consecutive even / odd cycle pairs with missing clock correction terms that will cause a transition from NORMAL_ACTIVE or NORMAL_PASSIVE to HALT state" "?,1: MIN,?..."
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bitfld.long 0x00 0.--3. "WCP,Maximum Without Clock Correction Passive (gMaxWithoutClockCorrectionPassive) Defines the number of consecutive even / odd cycle pairs with missing clock correction terms that will cause a transition from NORMAL_ACTIVE to NORMAL_PASSIVE state" "?,1: MIN,?..."
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group.long 0x8C++0x03
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line.long 0x00 "NEMC,NEM Configuration Register"
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bitfld.long 0x00 0.--3. "NML,Network Management Vector Length (gNetworkManagementVectorLength) These bits configure the length of the NM vector" "?,?,?,?,?,?,?,?,?,?,?,?,12: MAX,?..."
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group.long 0x90++0x03
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line.long 0x00 "PRTC1,PRT Configuration Register 1"
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bitfld.long 0x00 26.--31. "RWP,Repetitions of Tx Wakeup Pattern (pWakeupPattern) Configures the number of repetitions (sequences) of the Tx wakeup symbol" "?,?,2: MIN,?..."
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hexmask.long.word 0x00 16.--24. 1. "RXW,Wakeup Symbol Receive Window Length (gdWakeupSymbolRxWindow) Configures the number of bit times used by the node to test the duration of the received wakeup pattern"
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bitfld.long 0x00 14.--15. "BRP,Baud Rate Prescaler (gdSampleClockPeriod pSamplesPerMicrotick) The Baud Rate Prescaler configures the baud rate on the FlexRay bus" "0: BAUD_10_MBPS,1: BAUD_5_MBPS,2: BAUD_2P5_MBPS,3: BAUD_2P5_MBPS_MIRROR"
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bitfld.long 0x00 12.--13. "SPP,Strobe Point Position Defines the sample count value for strobing" "0: SAMPLE_5,1: SAMPLE_4,2: SAMPLE_6,3: SAMPLE_5_MIRROR"
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rbitfld.long 0x00 10. "CASM6,Part of CASM[6:0] but fixed to 1" "0,1"
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bitfld.long 0x00 4.--9. "CASM,Collision Avoidance Symbol Max (gdCASRxLowMax) Configures the upper limit of the acceptance window for a collision avoidance symbol (CAS)" "?,?,?,3: MIN,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,35: MAX,?..."
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bitfld.long 0x00 0.--3. "TSST,Transmission Start Sequence Transmitter (gdTSSTransmitter) Configures the duration of the Transmission Start Sequence (TSS) in terms of bit times (1 bit time = 4 uT = 100ns@10Mbps)" "?,?,?,3: MIN,?,?,?,?,?,?,?,?,?,?,?,15: MAX"
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group.long 0x94++0x03
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line.long 0x00 "PRTC2,PRT Configuration Register 2"
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bitfld.long 0x00 24.--29. "TXL,Wakeup Symbol Transmit Low (gdWakeupSymbolTxLow) Configures the number of bit times used by the node to transmit the low phase of the wakeup symbol" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: MIN,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,60: MAX,?..."
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hexmask.long.byte 0x00 16.--23. 1. "TXI_,Wakeup Symbol Transmit Idle (gdWakeupSymbolTxIdle) Configures the number of bit times used by the node to transmit the idle phase of the wakeup symbol"
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bitfld.long 0x00 8.--13. "RXL,Wakeup Symbol Receive Low (gdWakeupSymbolRxLow) Configures the number of bit times used by the node to test the duration of the low phase of the received wakeup symbol" "?,?,?,?,?,?,?,?,?,?,10: MIN,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,55: MAX,?..."
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bitfld.long 0x00 0.--5. "RXI_,Wakeup Symbol Receive Idle (gdWakeupSymbolRxIdle) Configures the number of bit times used by the node to test the duration of the idle phase of the received wakeup symbol" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,14: MIN,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: MAX,?..."
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group.long 0x98++0x03
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line.long 0x00 "MHDC,MHD Configuration Register"
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hexmask.long.word 0x00 16.--28. 1. "SLT,Start of Latest Transmit (pLatestTx) Configures the maximum minislot value allowed before inhibiting frame transmission in the dynamic segment of the cycle"
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hexmask.long.byte 0x00 0.--6. 1. "SFDL,Static Frame Data Length (gPayloadLengthStatic) Configures the cluster-wide payload length for all frames sent in the static segment in double bytes"
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group.long 0xA0++0x03
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line.long 0x00 "GTUC1,GTU Configuration Register 1"
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hexmask.long.tbyte 0x00 0.--19. 1. "UT,Microtick per Cycle (pMicroPerCycle) Configures the duration of the communication cycle in microticks"
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group.long 0xA4++0x03
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line.long 0x00 "GTUC2,GTU Configuration Register 2"
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bitfld.long 0x00 16.--19. "SNM,Sync Node Max (gSyncNodeMax) Maximum number of frames within a cluster with sync frame indicator bit SYN set to '1'" "?,?,2: MIN,?,?,?,?,?,?,?,?,?,?,?,?,15: MAX"
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hexmask.long.word 0x00 0.--13. 1. "MPC,Macrotick Per Cycle (gMacroPerCycle) Configures the duration of one communication cycle in macroticks"
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group.long 0xA8++0x03
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line.long 0x00 "GTUC3,GTU Configuration Register 3"
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hexmask.long.byte 0x00 24.--30. 1. "MIOB,Macrotick Initial Offset Channel B (pMacroInitialOffset[B]) Configures the number of macroticks between the static slot boundary and the subsequent macrotick boundary of the secondary time reference point based on the nominal macrotick duration"
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hexmask.long.byte 0x00 16.--22. 1. "MIOA,Macrotick Initial Offset Channel A (pMacroInitialOffset[A]) Configures the number of macroticks between the static slot boundary and the subsequent macrotick boundary of the secondary time reference point based on the nominal macrotick duration"
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hexmask.long.byte 0x00 8.--15. 1. "UIOB,Microtick Initial Offset Channel B (pMicroInitialOffset[B]) Configures the number of microticks between the actual time reference point on channel B and the subsequent macrotick boundary of the secondary time reference point"
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hexmask.long.byte 0x00 0.--7. 1. "UIOA,Microtick Initial Offset Channel A (pMicroInitialOffset[A]) Configures the number of microticks between the actual time reference point on channel A and the subsequent macrotick boundary of the secondary time reference point"
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group.long 0xAC++0x03
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line.long 0x00 "GTUC4,GTU Configuration Register 4"
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hexmask.long.word 0x00 16.--29. 1. "OCS,Offset Correction Start (gOffsetCorrectionStart - 1) Determines the start of the offset correction within the NIT phase calculated from start of cycle"
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hexmask.long.word 0x00 0.--13. 1. "NIT,Network Idle Time Start (gMacroPerCycle - gdNIT - 1) Configures the starting point of the Network Idle Time NIT at the end of the communication cycle expressed in terms of macroticks from the beginning of the cycle"
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group.long 0xB0++0x03
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line.long 0x00 "GTUC5,GTU Configuration Register 5"
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hexmask.long.byte 0x00 24.--31. 1. "DEC,Decoding Correction (pDecodingCorrection) Configures the decoding correction value used to determine the primary time reference point"
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bitfld.long 0x00 16.--20. "CDD,Cluster Drift Damping (pClusterDriftDamping) Configures the cluster drift damping value used in clock synchronization to minimize accumulation of rounding errors" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,20: MAX,?..."
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hexmask.long.byte 0x00 8.--15. 1. "DCB,Delay Compensation Channel B (pDelayCompensation[B]) Used to compensate for reception delays on the indicated channel"
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hexmask.long.byte 0x00 0.--7. 1. "DCA,Delay Compensation Channel A (pDelayCompensation[A]) Used to compensate for reception delays on the indicated channel"
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group.long 0xB4++0x03
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line.long 0x00 "GTUC6,GTU Configuration Register 6"
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hexmask.long.word 0x00 16.--26. 1. "MOD,Maximum Oscillator Drift (pdMaxDrift) Maximum drift offset between two nodes that operate with unsynchronized clocks over one communication cycle in uT"
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hexmask.long.word 0x00 0.--10. 1. "ASR,Accepted Startup Range (pdAcceptedStartupRange) Number of microticks constituting the expanded range of measured deviation for startup frames during integration"
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group.long 0xB8++0x03
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line.long 0x00 "GTUC7,GTU Configuration Register 7"
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hexmask.long.word 0x00 16.--25. 1. "NSS,Number of Static Slots (gNumberOfStaticSlots) Configures the number of static slots in a cycle"
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hexmask.long.word 0x00 0.--9. 1. "SSL,Static Slot Length (gdStaticSlot) Configures the duration of a static slot in macroticks"
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group.long 0xBC++0x03
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line.long 0x00 "GTUC8,GTU Configuration Register 8"
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hexmask.long.word 0x00 16.--28. 1. "NMS,Number of Minislots (gNumberOfMinislots) Configures the number of minislots within the dynamic segment of a cycle"
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bitfld.long 0x00 0.--5. "MSL,Minislot Length (gdMinislot) Configures the duration of a minislot in macroticks" "?,?,2: MIN,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: MAX"
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group.long 0xC0++0x03
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line.long 0x00 "GTUC9,GTU Configuration Register 9"
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bitfld.long 0x00 16.--17. "DSI,Dynamic Slot Idle Phase (gdDynamicSlotIdlePhase) The duration of the dynamic slot idle phase has to be greater or equal than the idle detection time" "?,?,2: MAX,?..."
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bitfld.long 0x00 8.--12. "MAPO,Minislot Action Point Offset (gdMinislotActionPointOffset) Configures the action point offset in macroticks within the minislots of the dynamic segment" "?,1: MIN,?..."
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bitfld.long 0x00 0.--5. "APO,Action Point Offset (gdActionPointOffset) Configures the action point offset in macroticks within static slots and symbol window" "?,1: MIN,?..."
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group.long 0xC4++0x03
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line.long 0x00 "GTUC10,GTU Configuration Register 10"
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hexmask.long.word 0x00 16.--26. 1. "MRC,Maximum Rate Correction (pRateCorrectionOut) Holds the maximum permitted rate correction value to be applied by the internal clock synchronization algorithm"
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hexmask.long.word 0x00 0.--13. 1. "MOC,Maximum Offset Correction (pOffsetCorrectionOut) Holds the maximum permitted offset correction value to be applied by the internal clock synchronization algorithm (absolute value)"
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group.long 0xC8++0x03
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line.long 0x00 "GTUC11,GTU Configuration Register 11"
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bitfld.long 0x00 24.--26. "ERC,External Rate Correction (pExternRateCorrection) Holds the external rate correction value in microticks to be applied by the internal clock synchronization algorithm" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "EOC,External Offset Correction (pExternOffsetCorrection) Holds the external offset correction value in microticks to be applied by the internal clock synchronization algorithm" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--9. "ERCC,External Rate Correction Control (vExternRateControl) By writing to ERCC[1:0] the external rate correction is enabled as specified below" "0: NO_EXT_RATE_CORRECTION,1: NO_EXT_RATE_CORRECTION_MIRROR,2: EXT_RATE_CORRECTION_SUBTRACTED,3: EXT_RATE_CORRECTION_ADDED"
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bitfld.long 0x00 0.--1. "EOCC,External Offset Correction Control (vExternOffsetControl) By writing to EOCC[1:0] the external offset correction is enabled as specified below" "0: NO_EXT_OFFSET_CORRECTION,1: NO_EXT_OFFSET_CORRECTION_MIRROR,2: EXT_OFFSET_CORRECTION_SUBTRACTED,3: EXT_OFFSET_CORRECTION_ADDED"
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rgroup.long 0x100++0x03
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line.long 0x00 "CCSV,CC Status Vector"
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bitfld.long 0x00 24.--29. "PSL,POC Status Log Status of POCS[5:0] immediately before entering HALT state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 19.--23. "RCA,Remaining Coldstart Attempts (vRemainingColdstartAttempts) Indicates the number of remaining coldstart attempts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--18. "WSV,N/A" "0: UNDEFINED,1: RECEIVED_HEADER,2: RECEIVED_WUP,3: COLLISION_HEADER,4: COLLISION_WUP,5: COLLISION_UNKNOWN,6: TRANSMITTED,?..."
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bitfld.long 0x00 14. "CSI,Cold Start Inhibit (vColdStartInhibit) Indicates that the node is disabled from cold starting" "0: NODE_COLD_START_ENABLED,1: NODE_COLD_START_DISABLED"
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bitfld.long 0x00 13. "CSAI,Coldstart Abort Indicator Coldstart aborted" "0,1"
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bitfld.long 0x00 12. "CSNI,Coldstart Noise Indicator (vPOC!ColdstartNoise) Indicates that the cold start procedure occurred under noisy conditions" "0,1"
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bitfld.long 0x00 8.--9. "SLM,N/A" "0: SINGLE,?,2: ALL_PENDING,3: ALL"
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bitfld.long 0x00 7. "HRQ,Halt Request (vPOC!CHIHaltRequest) Indicates that a request from the Host has been received to halt the POC at the end of the communication cycle" "0,1"
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bitfld.long 0x00 6. "FSI,Freeze Status Indicator (vPOC!Freeze) Indicates that the POC has entered the HALT state due to CHI command FREEZE or due to an error condition requiring an immediate POC halt" "0,1"
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bitfld.long 0x00 0.--5. "POCS,N/A" "0: DEFAULT_CONFIG,1: READY,2: NORMAL_ACTIVE,3: NORMAL_PASSIVE,4: HALT,5: MONITOR_MODE,?,?,?,?,?,?,?,?,?,15: CONFIG,16: WAKEUP_STANDBY,17: WAKEUP_LISTEN,18: WAKEUP_SEND,19: WAKEUP_DETECT,?,?,?,?,?,?,?,?,?,?,?,?,32: STARTUP_PREPARE,33: COLDSTART_LISTEN,34: COLDSTART_COLLISION_RESOLUTION,35: COLDSTART_CONSISTENCY_CHECK,36: COLDSTART_GAP,37: COLDSTART_JOIN,38: INTEGRATION_COLDSTART_CHECK,39: INTEGRATION_LISTEN,40: INTEGRATION_CONSISTENCY_CHECK,41: INITIALIZE_SCHEDULE,42: ABORT_STARTUP,43: STARTUP_SUCCESS,?..."
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rgroup.long 0x104++0x03
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line.long 0x00 "CCEV,CC Error Vector"
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bitfld.long 0x00 8.--12. "PTAC,Passive to Active Count (vAllowPassiveToActive) Indicates the number of consecutive even / odd cycle pairs that have passed with valid rate and offset correction terms while the node is waiting to transit from NORMAL_PASSIVE state to NORMAL_ACTIVE.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--7. "ERRM,N/A" "0: ACTIVE,1: PASSIVE,2: COMM_HALT,?..."
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bitfld.long 0x00 0.--3. "CCFC,Clock Correction Failed Counter (vClockCorrectionFailed) The Clock Correction Failed Counter is incremented by one at the end of any odd communication cycle where either the missing offset correction error or missing rate correction error are active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x110++0x03
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line.long 0x00 "SCV,Slot Counter Value"
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hexmask.long.word 0x00 16.--26. 1. "SCCB,Slot Counter Channel B (vSlotCounter[B]) Current slot counter value on channel B"
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hexmask.long.word 0x00 0.--10. 1. "SCCA,Slot Counter Channel A (vSlotCounter[A]) Current slot counter value on channel A"
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rgroup.long 0x114++0x03
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line.long 0x00 "MTCCV,Macrotick and Cycle Counter Value"
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bitfld.long 0x00 16.--21. "CCV,Cycle Counter Value (vCycleCounter) Current cycle counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--13. 1. "MTV,Macrotick Value (vMacrotick) Current macrotick value"
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rgroup.long 0x118++0x03
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line.long 0x00 "RCV,Rate Correction Value"
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hexmask.long.word 0x00 0.--11. 1. "RCV,Rate Correction Value (vRateCorrection) Rate correction value (two's complement)"
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|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "OCV,Offset Correction Value"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. "OCV,Offset Correction Value (vOffsetCorrection) Offset correction value (two's complement)"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "SFS,Sync Frame Status"
|
|
bitfld.long 0x00 19. "RCLR,Rate Correction Limit Reached The Rate Correction Limit Reached flag signals to the Host that the rate correction value has exceeded its limit as defined by GTUC10.MRC[10:0]" "0: RATE_CORRECTION_BELOW_LIMIT,1: RATE_CORRECTION_LIMIT_REACHED"
|
|
bitfld.long 0x00 18. "MRCS,Missing Rate Correction Signal The Missing Rate Correction flag signals to the Host that no rate correction calculation can be performed because no pairs of even / odd sync frames were received" "0: RATE_CORRECTION_SIGNAL_VALID,1: RATE_CORRECTION_SIGNAL_INVALID"
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|
newline
|
|
bitfld.long 0x00 17. "OCLR,Offset Correction Limit Reached The Offset Correction Limit Reached flag signals to the Host that the offset correction value has exceeded its limit as defined by GTUC10.MOC[13:0]" "0: OFFSET_CORRECTION_BELOW_LIMIT,1: OFFSET_CORRECTION_LIMIT_REACHED"
|
|
bitfld.long 0x00 16. "MOCS,Missing Offset Correction Signal The Missing Offset Correction flag signals to the Host that no offset correction calculation can be performed because no sync frames were received" "0: OFFSET_CORRECTION_SIGNAL_VALID,1: OFFSET_CORRECTION_SIGNAL_INVALID"
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|
newline
|
|
bitfld.long 0x00 12.--15. "VSBO,Valid Sync Frames Channel B odd communication cycle Holds the number of valid sync frames received on channel B in the odd communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. "VSBE,Valid Sync Frames Channel B even communication cycle Holds the number of valid sync frames received on channel B in the even communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 4.--7. "VSAO,Valid Sync Frames Channel A odd communication cycle Holds the number of valid sync frames received on channel A in the odd communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. "VSAE,Valid Sync Frames Channel A even communication cycle Holds the number of valid sync frames received on channel A in the even communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SWNIT,Symbol Window and NIT Status"
|
|
bitfld.long 0x00 11. "SBNB,Slot Boundary Violation during NIT Channel B (vSS!BViolationB)" "0: NO_BNDRY_VIOLATION_ERROR_IN_CH_B,1: BNDRY_VIOLATION_ERROR_IN_CH_B"
|
|
bitfld.long 0x00 10. "SENB,Syntax Error during NIT Channel B (vSS!SyntaxErrorB)" "0: NO_SYNTAX_ERROR_DETECTED_ON_CH_B,1: SYNTAX_ERROR_DETECTED_ON_CH_B"
|
|
newline
|
|
bitfld.long 0x00 9. "SBNA,Slot Boundary Violation during NIT Channel A (vSS!BViolationA)" "0: NO_BNDRY_VIOLATION_ERROR_IN_CH_A,1: BNDRY_VIOLATION_ERROR_IN_CH_A"
|
|
bitfld.long 0x00 8. "SENA,Syntax Error during NIT Channel A (vSS!SyntaxErrorA)" "0: NO_SYNTAX_ERROR_DETECTED_ON_CH_A,1: SYNTAX_ERROR_DETECTED_ON_CH_A"
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|
newline
|
|
bitfld.long 0x00 7. "MTSB__,MTS Received on Channel B (vSS!ValidMTSB) Media Access Test symbol received on channel B during the preceding symbol window" "0: NO_MTS_SYMBOL_RXD_IN_CH_B,1: MTS_SYMBOL_RXD_IN_CH_B"
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|
bitfld.long 0x00 6. "MTSA__,MTS Received on Channel A (vSS!ValidMTSA) Media Access Test symbol received on channel A during the preceding symbol window" "0: NO_MTS_SYMBOL_RXD_IN_CH_A,1: MTS_SYMBOL_RXD_IN_CH_A"
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|
newline
|
|
bitfld.long 0x00 5. "TCSB,Transmission Conflict in Symbol Window Channel B (vSS!TxConflictB)" "0: NO_TXMN_CONFLICT_IN_CH_B,1: TXMN_CONFLICT_IN_CH_B"
|
|
bitfld.long 0x00 4. "SBSB,Slot Boundary Violation in Symbol Window Channel B (vSS!BViolationB)" "0: NO_BNDRY_VIOLATION_ERROR_IN_CH_B,1: BNDRY_VIOLATION_ERROR_IN_CH_B"
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|
newline
|
|
bitfld.long 0x00 3. "SESB,Syntax Error in Symbol Window Channel B (vSS!SyntaxErrorB)" "0: NO_SYNTAX_ERROR_IN_CH_B,1: SYNTAX_ERR_IN_CH_B"
|
|
bitfld.long 0x00 2. "TCSA,Transmission Conflict in Symbol Window Channel A (vSS!TxConflictA)" "0: NO_TXMN_CONFLICT_IN_CH_A,1: TXMN_CONFLICT_IN_CH_A"
|
|
newline
|
|
bitfld.long 0x00 1. "SBSA,Slot Boundary Violation in Symbol Window Channel A (vSS!BViolationA)" "0: NO_BNDRY_VIOLATION_ERROR_IN_CH_A,1: BNDRY_VIOLATION_ERROR_IN_CH_A"
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|
bitfld.long 0x00 0. "SESA,Syntax Error in Symbol Window Channel A (vSS!SyntaxErrorA)" "0: NO_SYNTAX_ERROR_IN_CH_A,1: SYNTAX_ERR_IN_CH_A"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "ACS,Aggregated Channel Status"
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|
bitfld.long 0x00 12. "SBVB,Slot Boundary Violation on Channel B (vSS!BViolationB) One or more slot boundary violations were observed on channel B at any time during the observation period (static or dynamic slots symbol window and NIT)" "0: NO_BNDRY_VIOLATION_ERROR_IN_CH_B,1: BNDRY_VIOLATION_ERROR_IN_CH_B"
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|
bitfld.long 0x00 11. "CIB,Communication Indicator Channel B One or more valid frames were received on channel B in slots that also contained any additional communication during the observation period i.e" "0: NO_VALID_FRAME_RXD_ON_CH_B_IN_SLOTS,1: VALID_FRAME_RXD_ON_CH_B_IN_SLOTS"
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|
newline
|
|
bitfld.long 0x00 10. "CEDB,Content Error Detected on Channel B (vSS!ContentErrorB) One or more frames with a content error were received on channel B in any static or dynamic slot during the observation period" "0: NO_FRAME_WITH_CONTENT_ERR_ON_CH_B,1: FRAME_WITH_CONTENT_ERR_RXD_ON_CH_B"
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|
bitfld.long 0x00 9. "SEDB,Syntax Error Detected on Channel B (vSS!SyntaxErrorB) One or more syntax errors in static or dynamic slots symbol window and NIT were observed on channel B" "0: NO_SYNTAX_ERR_OBSVD_ON_CH_B,1: SYNTAX_ERR_OBSVD_ON_CH_B"
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|
newline
|
|
bitfld.long 0x00 8. "VFRB_,Valid Frame Received on Channel B (vSS!ValidFrameB) One or more valid frames were received on channel B in any static or dynamic slot during the observation period" "0: NO_VALID_FRAME_RXD_ON_CH_B,1: VALID_FRAME_RXD_ON_CH_B"
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|
bitfld.long 0x00 4. "SBVA,Slot Boundary Violation on Channel A (vSS!BViolationA) One or more slot boundary violations were observed on channel A at any time during the observation period (static or dynamic slots symbol window and NIT)" "0: NO_BNDRY_VIOLATION_ERROR_IN_CH_A,1: BNDRY_VIOLATION_ERROR_IN_CH_A"
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|
newline
|
|
bitfld.long 0x00 3. "CIA,Communication Indicator Channel A One or more valid frames were received on channel A in slots that also contained any additional communication during the observation period i.e" "0: NO_VALID_FRAME_RXD_ON_CH_A_IN_SLOTS,1: VALID_FRAME_RXD_ON_CH_A_IN_SLOTS"
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|
bitfld.long 0x00 2. "CEDA,Content Error Detected on Channel A (vSS!ContentErrorA) One or more frames with a content error were received on channel A in any static or dynamic slot during the observation period" "0: NO_FRAME_WITH_CONTENT_ERR_ON_CH_A,1: FRAME_WITH_CONTENT_ERR_RXD_ON_CH_A"
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|
newline
|
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bitfld.long 0x00 1. "SEDA,Syntax Error Detected on Channel A (vSS!SyntaxErrorA) One or more syntax errors in static or dynamic slots symbol window and NIT were observed on channel A" "0: NO_SYNTAX_ERR_OBSVD_ON_CH_A,1: SYNTAX_ERR_OBSVD_ON_CH_A"
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|
bitfld.long 0x00 0. "VFRA_,Valid Frame Received on Channel A (vSS!ValidFrameA) One or more valid frames were received on channel A in any static or dynamic slot during the observation period" "0: NO_VALID_FRAME_RXD_ON_CH_A,1: VALID_FRAME_RXD_ON_CH_A"
|
|
repeat 15. (increment 0 1) (increment 0 0x04)
|
|
rgroup.long ($2+0x130)++0x03
|
|
line.long 0x00 "ESID[$1],Even Sync ID $1"
|
|
bitfld.long 0x00 15. "RXEB,Received / Configured Even Sync ID on Channel B Signals that a sync frame corresponding to the stored even sync ID was received on channel B or that the node is configured to be a sync node with key slot = EID[9:0] (ESID1 only)" "0: NO_SYNC_FRAME_RXD_ON_CH_B,1: SYNC_FRAME_RXD_ON_CH_B"
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|
bitfld.long 0x00 14. "RXEA,Received / Configured Even Sync ID on Channel A Signals that a sync frame corresponding to the stored even sync ID was received on channel A or that the node is configured to be a sync node with key slot = EID[9:0] (ESID1 only)" "0: NO_SYNC_FRAME_RXD_ON_CH_A,1: SYNC_FRAME_RXD_ON_CH_A"
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|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "EID,Even Sync ID (vsSyncIDListA B even) Sync frame ID even communication cycle"
|
|
repeat.end
|
|
repeat 15. (increment 0 1) (increment 0 0x04)
|
|
rgroup.long ($2+0x170)++0x03
|
|
line.long 0x00 "OSID[$1],Odd Sync ID $1"
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|
bitfld.long 0x00 15. "RXOB,Received / Configured Odd Sync ID on Channel B Signals that a sync frame corresponding to the stored odd sync ID was received on channel B or that the node is configured to be a sync node with key slot = OID[9:0] (OSID1 only)" "0: NO_SYNC_FRAME_RXD_ON_CH_B,1: SYNC_FRAME_RXD_ON_CH_B"
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bitfld.long 0x00 14. "RXOA,Received / Configured Odd Sync ID on Channel A Signals that a sync frame corresponding to the stored odd sync ID was received on channel A or that the node is configured to be a sync node with key slot = OID[9:0] (OSID1 only)" "0: NO_SYNC_FRAME_RXD_ON_CH_A,1: SYNC_FRAME_RXD_ON_CH_A"
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|
newline
|
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hexmask.long.word 0x00 0.--9. 1. "OID,Odd Sync ID (vsSyncIDListA B odd) Sync frame ID odd communication cycle"
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|
repeat.end
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "NMV1,Network Management Vector 1"
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|
hexmask.long.byte 0x00 24.--31. 1. "DATA3,Data3"
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|
hexmask.long.byte 0x00 16.--23. 1. "DATA2,Data2"
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|
newline
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hexmask.long.byte 0x00 8.--15. 1. "DATA1,Data1"
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|
hexmask.long.byte 0x00 0.--7. 1. "DATA0,Data0"
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|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "NMV2,Network Management Vector 2"
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|
hexmask.long.byte 0x00 24.--31. 1. "DATA7,Data7"
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|
hexmask.long.byte 0x00 16.--23. 1. "DATA6,Data6"
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|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DATA5,Data5"
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|
hexmask.long.byte 0x00 0.--7. 1. "DATA4,Data4"
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|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "NMV3,Network Management Vector 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA11,Data11"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA10,Data10"
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|
newline
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hexmask.long.byte 0x00 8.--15. 1. "DATA9,Data9"
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|
hexmask.long.byte 0x00 0.--7. 1. "DATA8,Data8"
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|
group.long 0x300++0x03
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line.long 0x00 "MRC,Message RAM Configuration"
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|
bitfld.long 0x00 26. "SPLM,Sync Frame Payload Multiplex This bit is only evaluated if the node is configured as sync node (SUCC1.TXSY = '1') or for single slot mode operation (SUCC1.TSM = '1')" "0: MSG_BUFFER_0_LOCKED,1: MSG_BUFFER_0_AND_1_LOCKED"
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bitfld.long 0x00 24.--25. "SEC,Secure Buffers Not evaluated when the CC is in DEFAULT_CONFIG or CONFIG state" "0: MSG_BUFFERS_LT_FFB_ENABLED,1: MSG_BUFFERS_LT_FDB_ENABLED_AND_GT_FFB_LOCKED,2: ALL_MSG_BUFFERS_LOCKED,3:.."
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newline
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hexmask.long.byte 0x00 16.--23. 1. "LCB,Last Configured Buffer 0...127 = Number of message buffers is LCB + 1"
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|
abitfld.long 0x00 8.--15. "FFB,First Buffer of FIFO" "0x00=0: All message buffers assigned to the FIFO..,0x80=128: No message buffer assigned to the FIFO"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "FDB,N/A"
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|
group.long 0x304++0x03
|
|
line.long 0x00 "FRF,FIFO Rejection Filter"
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|
bitfld.long 0x00 24. "RNF,Reject Null Frames If this bit is set received null frames are not stored in the FIFO" "0: NULL_FRAMES_FIFO_STORAGE_ENABLED,1: NULL_FRAMES_FIFO_STORAGE_DISABLED"
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bitfld.long 0x00 23. "RSS,Reject in Static Segment If this bit is set the FIFO is used only for the dynamic segment" "0: FIFO_STATIC_SEGMENT_STORAGE_ENABLED,1: FIFO_STATIC_SEGMENT_STORAGE_DISABLED"
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|
newline
|
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hexmask.long.byte 0x00 16.--22. 1. "CYF,Cycle Counter Filter The 7-bit cycle counter filter determines the cycle set to which frame ID and channel rejection filter are applied"
|
|
hexmask.long.word 0x00 2.--12. 1. "FID_,Frame ID Filter Determines the frame ID to be rejected by the FIFO"
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newline
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bitfld.long 0x00 0.--1. "CH,Channel Filter" "0: RECEIVE_ON_BOTH_CHANNELS,1: RECEIVE_ONLY_ON_CHANNEL_B,2: RECEIVE_ONLY_ON_CHANNEL_A,3: NO_RECEPTION"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "FRFM,FIFO Rejection Filter Mask"
|
|
abitfld.long 0x00 2.--12. "MFID,Mask Frame ID Filter" "0x000=0: Corresponding frame ID filter bit is..,0x001=1: Ignore corresponding frame ID filter bit"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "FCL,FIFO Critical Level"
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|
hexmask.long.byte 0x00 0.--7. 1. "CL,Critical Level When the receive FIFO fill level FSR.RFFL[7:0] is equal or greater than the critical level configured by CL[7:0] the receive FIFO critical level flag FSR.RFCL is set"
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|
group.long 0x310++0x03
|
|
line.long 0x00 "MHDS,Message Handler Status"
|
|
hexmask.long.byte 0x00 24.--30. 1. "MBU,Message Buffer Updated Number of message buffer that was updated last by the CC"
|
|
hexmask.long.byte 0x00 16.--22. 1. "MBT,Message Buffer Transmitted Number of last successfully transmitted message buffer"
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|
newline
|
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hexmask.long.byte 0x00 8.--14. 1. "FMB,Faulty Message Buffer Parity error occurred when reading from the message buffer or when transferring data from Input Buffer or Transient Buffer 1 2 to the message buffer referenced by FMB[6:0]"
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rbitfld.long 0x00 7. "CRAM,Clear all internal RAM's Signals that execution of the CHI command CLEAR_RAMS is ongoing (all bits of all internal RAM blocks are written to '0')" "0: CLEAR_RAMS_NOT_IN_PROGRESS,1: CLEAR_RAMS_IN_PROGRESS"
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newline
|
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bitfld.long 0x00 6. "MFMB,Multiple Faulty Message Buffers detected" "0: NO_ADDITIONAL_FAULTY_MSG_BUFFER,1: ADDITIONAL_FAULTY_MSG_BUFFER_ERROR"
|
|
bitfld.long 0x00 5. "FMBD,Faulty Message Buffer Detected" "0: NO_FAULTY_MSG_BUFFER,1: FAULTY_MSG_BUFFER_ERROR"
|
|
newline
|
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bitfld.long 0x00 4. "PTBF2,Parity Error Transient Buffer RAM B" "0: NO_PARITY_ERROR,1: PARITY_ERROR_IN_TRAN_BUF_RAM_B"
|
|
bitfld.long 0x00 3. "PTBF1,Parity Error Transient Buffer RAM A" "0: NO_PARITY_ERROR,1: PARITY_ERROR_IN_TRAN_BUF_RAM_A"
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newline
|
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bitfld.long 0x00 2. "PMR,Parity Error Message RAM" "0: NO_PARITY_ERROR,1: PARITY_ERROR_IN_MSG_RAM"
|
|
bitfld.long 0x00 1. "POBF,Parity Error Output Buffer RAM 1 2" "0: NO_PARITY_ERROR,1: PARITY_ERROR_IN_OBF_RAM_1_2"
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|
newline
|
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bitfld.long 0x00 0. "PIBF,Parity Error Input Buffer RAM 1 2" "0: NO_PARITY_ERROR,1: PARITY_ERROR_IN_IBF_RAM_1_2"
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "LDTS,Last Dynamic Transmit Slot"
|
|
hexmask.long.word 0x00 16.--26. 1. "LDTB,Last Dynamic Transmission Channel B Value of vSlotCounter[B] at the time of the last frame transmission on channel B in the dynamic segment of this node"
|
|
hexmask.long.word 0x00 0.--10. 1. "LDTA,Last Dynamic Transmission Channel A Value of vSlotCounter[A] at the time of the last frame transmission on channel A in the dynamic segment of this node"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RFFL,Receive FIFO Fill Level Number of FIFO buffers filled with new data not yet read by the Host"
|
|
bitfld.long 0x00 2. "RFO_,Receive FIFO Overrun The flag is set by the CC when a receive FIFO overrun is detected" "0: RX_FIFO_NO_OVERRUN,1: RX_FIFO_OVERRUN"
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|
newline
|
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bitfld.long 0x00 1. "RFCL_,Receive FIFO Critical Level This flag is set when the receive FIFO fill level RFFL[7:0] is equal or greater than the critical level as configured by FCL.CL[7:0]" "0: RX_FIFO_LT_CRITICAL_LEVEL,1: RX_FIFO_CRITICAL_LEVEL"
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|
bitfld.long 0x00 0. "RFNE_,Receive FIFO Not Empty This flag is set by the CC when a received valid frame (data or null frame depending on rejection mask) was stored in the FIFO" "0: RX_FIFO_EMPTY,1: RX_FIFO_NOT_EMPTY"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "MHDF,Message Handler Constraints Flags"
|
|
bitfld.long 0x00 8. "WAHP,Write Attempt to Header Partition Outside DEFAULT_CONFIG and CONFIG state this flag is set by the CC when the message handler tries to write message data into the header partition of the Message RAM due to faulty configuration of a message buffer" "0: HEADER_PARTITION_NO_,1: HEADER_PARTITION_"
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|
bitfld.long 0x00 7. "TNSB,Transmission Not Started Channel B This flag is set by the CC when the Message Handler was not ready to start a scheduled transmission on channel B at the action point of the configured slot" "0: NO_CH_B_TXMN_NOT_STARTED,1: CH_B_TXMN_NOT_STARTED"
|
|
newline
|
|
bitfld.long 0x00 6. "TNSA,Transmission Not Started Channel A This flag is set by the CC when the Message Handler was not ready to start a scheduled transmission on channel A at the action point of the configured slot" "0: NO_CH_A_TXMN_NOT_STARTED,1: CH_A_TXMN_NOT_STARTED"
|
|
bitfld.long 0x00 5. "TBFB,Transient Buffer Access Failure B This flag is set by the CC when a read or write access to TBF B requested by PRT B could not complete within the available time" "0: TBF_CH_B_ACCESS_NOT_FAILED,1: TBF_CH_B_ACCESS_FAILED"
|
|
newline
|
|
bitfld.long 0x00 4. "TBFA,Transient Buffer Access Failure A This flag is set by the CC when a read or write access to TBF A requested by PRT A could not complete within the available time" "0: TBF_CH_A_ACCESS_NOT_FAILED,1: TBF_CH_A_ACCESS_FAILED"
|
|
bitfld.long 0x00 3. "FNFB,Find Sequence Not Finished Channel B This flag is set by the CC when the Message Handler due to overload condition was not able to finish a find sequence (scan of Message RAM for matching message buffer) with respect to channel B" "0: NO_CH_B_FIND_SEQ_NOT_FINISHED,1: CH_B_FIND_SEQ_NOT_FINISHED"
|
|
newline
|
|
bitfld.long 0x00 2. "FNFA,Find Sequence Not Finished Channel A This flag is set by the CC when the Message Handler due to overload condition was not able to finish a find sequence (scan of Message RAM for matching message buffer) with respect to channel A" "0: NO_CH_A_FIND_SEQ_NOT_FINISHED,1: CH_A_FIND_SEQ_NOT_FINISHED"
|
|
bitfld.long 0x00 1. "SNUB,Status Not Updated Channel B This flag is set by the CC when the Message Handler due to overload condition was not able to update a message buffer's status MBS with respect to channel B" "0: MBS_FOR_CH_B_UPDATED,1: MBS_FOR_CH_B_NOT_UPDATED"
|
|
newline
|
|
bitfld.long 0x00 0. "SNUA,Status Not Updated Channel A This flag is set by the CC when the Message Handler due to overload condition was not able to update a message buffer's status MBS with respect to channel A" "0: MBS_FOR_CH_A_UPDATED,1: MBS_FOR_CH_A_NOT_UPDATED"
|
|
rgroup.long 0x320++0x03
|
|
line.long 0x00 "TXRQ1,Transmission Request 1"
|
|
hexmask.long 0x00 0.--31. 1. "TXR,Transmission Request TRX[31:0] If the flag is set the respective message buffer is ready for transmission respectively transmission of this message buffer is in progress"
|
|
rgroup.long 0x324++0x03
|
|
line.long 0x00 "TXRQ2,Transmission Request 2"
|
|
hexmask.long 0x00 0.--31. 1. "TXR,Transmission Request TRX[63:32] If the flag is set the respective message buffer is ready for transmission respectively transmission of this message buffer is in progress"
|
|
rgroup.long 0x328++0x03
|
|
line.long 0x00 "TXRQ3,Transmission Request 3"
|
|
hexmask.long 0x00 0.--31. 1. "TXR,Transmission Request TRX[95:64] If the flag is set the respective message buffer is ready for transmission respectively transmission of this message buffer is in progress"
|
|
rgroup.long 0x32C++0x03
|
|
line.long 0x00 "TXRQ4,Transmission Request 4"
|
|
hexmask.long 0x00 0.--31. 1. "TXR,Transmission Request TRX[127:96] If the flag is set the respective message buffer is ready for transmission respectively transmission of this message buffer is in progress"
|
|
rgroup.long 0x330++0x03
|
|
line.long 0x00 "NDAT1,New Data 1"
|
|
hexmask.long 0x00 0.--31. 1. "ND,New Data ND[31:0] The flags are set when a valid received data frame matches the message buffer's filter configuration independent of the payload length received or the payload length configured for that message buffer"
|
|
rgroup.long 0x334++0x03
|
|
line.long 0x00 "NDAT2,New Data 2"
|
|
hexmask.long 0x00 0.--31. 1. "ND,New Data ND[63:32] The flags are set when a valid received data frame matches the message buffer's filter configuration independent of the payload length received or the payload length configured for that message buffer"
|
|
rgroup.long 0x338++0x03
|
|
line.long 0x00 "NDAT3,New Data 3"
|
|
hexmask.long 0x00 0.--31. 1. "ND,New Data ND[95:64] The flags are set when a valid received data frame matches the message buffer's filter configuration independent of the payload length received or the payload length configured for that message buffer"
|
|
rgroup.long 0x33C++0x03
|
|
line.long 0x00 "NDAT4,New Data 4"
|
|
hexmask.long 0x00 0.--31. 1. "ND,New Data ND[127:96] The flags are set when a valid received data frame matches the message buffer's filter configuration independent of the payload length received or the payload length configured for that message buffer"
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "MBSC1,Message Buffer Status Changed 1"
|
|
hexmask.long 0x00 0.--31. 1. "MBC,Message Buffer Status Changed MBC[31:0] An MBC flag is set whenever the Message Handler changes one of the status flags VFRA VFRB SEOA SEOB CEOA CEOB SVOA SVOB TCIA TCIB ESA ESB MLST FTA FTB in the header section (see 4.11.5 Message Buffer Status.."
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "MBSC2,Message Buffer Status Changed 2"
|
|
hexmask.long 0x00 0.--31. 1. "MBC,Message Buffer Status Changed MBC[63:32] An MBC flag is set whenever the Message Handler changes one of the status flags VFRA VFRB SEOA SEOB CEOA CEOB SVOA SVOB TCIA TCIB ESA ESB MLST FTA FTB in the header section (see 4.11.5 Message Buffer Status.."
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "MBSC3,Message Buffer Status Changed 3"
|
|
hexmask.long 0x00 0.--31. 1. "MBC,Message Buffer Status Changed MBC[95:64] An MBC flag is set whenever the Message Handler changes one of the status flags VFRA VFRB SEOA SEOB CEOA CEOB SVOA SVOB TCIA TCIB ESA ESB MLST FTA FTB in the header section (see 4.11.5 Message Buffer Status.."
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "MBSC4,Message Buffer Status Changed 4"
|
|
hexmask.long 0x00 0.--31. 1. "MBC,Message Buffer Status Changed MBC[127:96] An MBC flag is set whenever the Message Handler changes one of the status flags VFRA VFRB SEOA SEOB CEOA CEOB SVOA SVOB TCIA TCIB ESA ESB MLST FTA FTB in the header section (see 4.11.5 Message Buffer Status.."
|
|
rgroup.long 0x3F0++0x03
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. "REL,Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 20.--27. 1. "STEP,Step of Core Release Two digits BCD-coded"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "YEAR,Design Time Stamp Year One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "MON,Design Time Stamp Month Two digits BCD-coded"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAY,Design Time Stamp Day Two digits BCD-coded"
|
|
rgroup.long 0x3F4++0x03
|
|
line.long 0x00 "ENDN,Endian Register"
|
|
hexmask.long 0x00 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 0x87654321"
|
|
repeat 64. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x400)++0x03
|
|
line.long 0x00 "WRDS[$1],Write Data Section $1"
|
|
hexmask.long 0x00 0.--31. 1. "MD,Message Data MD[7:0] = DW2n-1 byte4n-4 MD[15:8] = DW2n-1 byte4n-3 MD[23:16] = DW2n byte4n-2 MD[31:24] = DW2n byte4n-1"
|
|
repeat.end
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "WRHS1,Write Header Section 1"
|
|
bitfld.long 0x00 29. "MBI,Message Buffer Interrupt This bit enables the receive / transmit interrupt for the corresponding message buffer" "0: MSG_BUFF_INTR_DISABLED,1: MSG_BUFF_INTR_ENABLED"
|
|
bitfld.long 0x00 28. "TXM,Transmission Mode This bit is used to select the transmission mode (see [01]Section 5.8.3 Transmit Buffers)" "0: CONTINUOUS_MODE,1: SINGLE_SHOT_MODE"
|
|
newline
|
|
bitfld.long 0x00 27. "PPIT,Payload Preamble Indicator Transmit This bit is used to control the state of the Payload Preamble Indicator in transmit frames" "0: PAYLOAD_PREAMBLE_NOT_SET,1: PAYLOAD_PREAMBLE_SET"
|
|
bitfld.long 0x00 26. "CFG,Message Buffer Direction Configuration Bit This bit is used to configure the corresponding buffer as transmit buffer or as receive buffer" "0: RX_BUFF,1: TX_BUFF"
|
|
newline
|
|
bitfld.long 0x00 25. "CHB,Channel Filter Control B The 2-bit channel filtering field associated with each buffer serves as a filter for receive buffers and as a control field for transmit buffers" "0: CH_B_DISABLED,1: CH_B_ENABLED"
|
|
bitfld.long 0x00 24. "CHA,Channel Filter Control A The 2-bit channel filtering field associated with each buffer serves as a filter for receive buffers and as a control field for transmit buffers" "0: CH_A_DISABLED,1: CH_A_ENABLED"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "CYC,Cycle Code The 7-bit cycle code determines the cycle set used for cycle counter filtering"
|
|
hexmask.long.word 0x00 0.--10. 1. "FID,Frame ID Frame ID of the selected message buffer"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "WRHS2,Write Header Section 2"
|
|
hexmask.long.byte 0x00 16.--22. 1. "PLC,Payload Length Configured Length of data section (number of 2-byte words) as configured by the Host"
|
|
hexmask.long.word 0x00 0.--10. 1. "CRC,Header CRC (vRF!Header!HeaderCRC) Receive Buffer: Configuration not required Transmit Buffer: Header CRC calculated and configured by the Host For calculation of the header CRC the payload length of the frame send on the bus has to be considered"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "WRHS3,Write Header Section 3"
|
|
hexmask.long.word 0x00 0.--10. 1. "DP,Data Pointer Pointer to the first 32-bit word of the data section of the addressed message buffer in the Message RAM"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "IBCM,Input Buffer Command Mask"
|
|
rbitfld.long 0x00 18. "STXRS,Set Transmission Request Shadow" "0: TXR_FLAG_RESET,1: TXR_FLAG_SET"
|
|
rbitfld.long 0x00 17. "LDSS,Load Data Section Shadow" "0: DATA_SECTION_NOT_UPDATED,1: DATA_SECTION_UPDATED"
|
|
newline
|
|
rbitfld.long 0x00 16. "LHSS,Load Header Section Shadow" "0: HEADER_SECTION_NOT_UPDATED,1: HEADER_SECTION_UPDATED"
|
|
bitfld.long 0x00 2. "STXRH,Set Transmission Request Host If this bit is set to '1' the TXR flag for the selected message buffer is set in the TXRQ1/2/3/4 registers to release the message buffer for transmission" "0: TXR_FLAG_RESET,1: TXR_FLAG_SET"
|
|
newline
|
|
bitfld.long 0x00 1. "LDSH,Load Data Section Host" "0: DATA_SECTION_NOT_UPDATED,1: DATA_SECTION_UPDATED"
|
|
bitfld.long 0x00 0. "LHSH,Load Header Section Host" "0: HEADER_SECTION_NOT_UPDATED,1: HEADER_SECTION_UPDATED"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "IBCR,Input Buffer Command Request"
|
|
rbitfld.long 0x00 31. "IBSYS,Input Buffer Busy Shadow Set to '1' after writing IBRH[6:0]" "0: TXFR_IBF2MSRAM_COMPLETE,1: TXFR_IBF2MSRAM_IN_PROGRESS"
|
|
hexmask.long.byte 0x00 16.--22. 1. "IBRS,Input Buffer Request Shadow Number of the target message buffer actually updated / lately updated"
|
|
newline
|
|
rbitfld.long 0x00 15. "IBSYH,Input Buffer Busy Host Set to '1' by writing IBRH[6:0] while IBSYS is still '1'" "0: REQUEST_NOT_PENDING,1: REQUEST_IN_PROGRESS"
|
|
hexmask.long.byte 0x00 0.--6. 1. "IBRH,Input Buffer Request Host Selects the target message buffer in the Message RAM for data transfer from Input Buffer"
|
|
repeat 64. (increment 0 1) (increment 0 0x04)
|
|
rgroup.long ($2+0x600)++0x03
|
|
line.long 0x00 "RDDS[$1],Read Data Section $1"
|
|
hexmask.long 0x00 0.--31. 1. "MD,Message Data MD[7:0] = DW2n-1 byte4n-4 MD[15:8] = DW2n-1 byte4n-3 MD[23:16] = DW2n byte4n-2 MD[31:24] = DW2n byte4n-1"
|
|
repeat.end
|
|
rgroup.long 0x700++0x03
|
|
line.long 0x00 "RDHS1,Read Header Section 1"
|
|
bitfld.long 0x00 29. "MBI,Message Buffer Interrupt" "0,1"
|
|
bitfld.long 0x00 28. "TXM,Transmission Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "PPIT,Payload Preamble Indicator Transmit" "0,1"
|
|
bitfld.long 0x00 26. "CFG,Message Buffer Direction Configuration Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "CHB,Channel Filter Control B" "0,1"
|
|
bitfld.long 0x00 24. "CHA,Channel Filter Control A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "CYC,Cycle Code"
|
|
hexmask.long.word 0x00 0.--10. 1. "FID,Frame ID"
|
|
rgroup.long 0x704++0x03
|
|
line.long 0x00 "RDHS2,Read Header Section 2"
|
|
hexmask.long.byte 0x00 24.--30. 1. "PLR,Payload Length Received (vRF!Header!Length) Payload length value updated from received data frames (exception: if message buffer belongs to the receive FIFO PLR[6:0] is also updated from received null frames) When a message is stored into a message.."
|
|
hexmask.long.byte 0x00 16.--22. 1. "PLC,Payload Length Configured Length of data section (number of 2-byte words) as configured by the Host"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "CRC,Header CRC (vRF!Header!HeaderCRC) Receive Buffer: Header CRC updated from received data frames Transmit Buffer: Header CRC calculated and configured by the Host"
|
|
rgroup.long 0x708++0x03
|
|
line.long 0x00 "RDHS3,Read Header Section 3"
|
|
bitfld.long 0x00 29. "RES,N/A" "0,1"
|
|
bitfld.long 0x00 28. "PPI,Payload Preamble Indicator (vRF!Header!PPIndicator) The payload preamble indicator defines whether a network management vector or message ID is contained within the payload segment of the received frame" "0: PAYLOAD_SEGMENT_HAS_NO_NMV_MID,1: PAYLOAD_SEGMENT_WITH_NMV_MID"
|
|
newline
|
|
bitfld.long 0x00 27. "NFI,Null Frame Indicator (vRF!Header!NFIndicator) Is set to '1' after storage of the first received data frame" "0: DATA_FRAME_NOT_STORED,1: DATA_FRAME_STORED"
|
|
bitfld.long 0x00 26. "SYN,Sync Frame Indicator (vRF!Header!SyFIndicator) A sync frame is marked by the sync frame indicator" "0: RXD_FRAME_NOT_SYNC_FRAME,1: RXD_FRAME_SYNC_FRAME"
|
|
newline
|
|
bitfld.long 0x00 25. "SFI,Startup Frame Indicator (vRF!Header!SuFIndicator) A startup frame is marked by the startup frame indicator" "0: RXD_FRAME_NOT_STARTUP_FRAME,1: RXD_FRAME_STARTUP_FRAME"
|
|
bitfld.long 0x00 24. "RCI,Received on Channel Indicator (vSS!Channel) Indicates the channel from which the received data frame was taken to update the respective receive buffer" "0: CH_B_FRAME_RECEIVED,1: CH_A_FRAME_RECEIVED"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "RCC,Receive Cycle Count (vRF!Header!CycleCount) Cycle counter value updated from received data frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--10. 1. "DP,Data Pointer Pointer to the first 32-bit word of the data section of the addressed message buffer in the Message RAM"
|
|
rgroup.long 0x70C++0x03
|
|
line.long 0x00 "MBS,Message Buffer Status"
|
|
bitfld.long 0x00 29. "RESS,N/A" "0,1"
|
|
bitfld.long 0x00 28. "PPIS,Payload Preamble Indicator Status (vRF!Header!PPIndicator) The payload preamble indicator defines whether a network management vector or message ID is contained within the payload segment of the received frame" "0: PAYLOAD_SEGMENT_HAS_NO_NMV_MID,1: PAYLOAD_SEGMENT_WITH_NMV_MID"
|
|
newline
|
|
bitfld.long 0x00 27. "NFIS,Null Frame Indicator Status (vRF!Header!NFIndicator) If set to '0' the payload segment of the received frame contains no usable data" "0: NULL_FRAME_RECEIVED,1: NO_NULL_FRAME_RECEIVED"
|
|
bitfld.long 0x00 26. "SYNS,Sync Frame Indicator Status (vRF!Header!SyFIndicator) A sync frame is marked by the sync frame indicator" "0: NO_SYNC_FRAME_RECEIVED,1: SYNC_FRAME_RECEIVED"
|
|
newline
|
|
bitfld.long 0x00 25. "SFIS,Startup Frame Indicator Status (vRF!Header!SuFIndicator) A startup frame is marked by the startup frame indicator" "0: NO_STARTUP_FRAME_RECEIVED,1: STARTUP_FRAME_RECEIVED"
|
|
bitfld.long 0x00 24. "RCIS,Received on Channel Indicator Status (vSS!Channel) Indicates the channel on which the frame was received" "0: CH_B_FRAME_RECEIVED,1: CH_A_FRAME_RECEIVED"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "CCS,Cycle Count Status Actual cycle count when status was updated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15. "FTB,Frame Transmitted on Channel B Indicates that this node has transmitted a data frame in the configured slot on channel B" "0: DATA_FRAME_NOT_TXD_ON_CH_B,1: DATA_FRAME_TXD_ON_CH_B"
|
|
newline
|
|
bitfld.long 0x00 14. "FTA,Frame Transmitted on Channel A Indicates that this node has transmitted a data frame in the configured slot on channel A" "0: DATA_FRAME_NOT_TXD_ON_CH_A,1: DATA_FRAME_TXD_ON_CH_A"
|
|
bitfld.long 0x00 12. "MLST,Message Lost The flag is set in case the Host did not read the message before the message buffer was updated from a received data frame" "0: NO_MSG_LOST,1: MSG_LOST"
|
|
newline
|
|
bitfld.long 0x00 11. "ESB,Empty Slot Channel B In an empty slot there is no activity detected on the bus" "0: CH_B_HAS_BUS_ACTIVITY,1: CH_B_NO_BUS_ACTIVITY"
|
|
bitfld.long 0x00 10. "ESA,Empty Slot Channel A In an empty slot there is no activity detected on the bus" "0: CH_A_HAS_BUS_ACTIVITY,1: CH_A_NO_BUS_ACTIVITY"
|
|
newline
|
|
bitfld.long 0x00 9. "TCIB,Transmission Conflict Indication Channel B (vSS!TxConflictB) A transmission conflict indication is set if a transmission conflict has occurred on channel B" "0: CH_B_NO_TXMN_CONFLICT,1: CH_B_HAS_TXMN_CONFLICT"
|
|
bitfld.long 0x00 8. "TCIA,Transmission Conflict Indication Channel A (vSS!TxConflictA) A transmission conflict indication is set if a transmission conflict has occurred on channel A" "0: CH_A_NO_TXMN_CONFLICT,1: CH_A_HAS_TXMN_CONFLICT"
|
|
newline
|
|
bitfld.long 0x00 7. "SVOB,Slot Boundary Violation Observed on Channel B (vSS!BViolationB) A slot boundary violation (channel active at the start or at the end of the assigned slot) was observed on channel B" "0: CH_B_NO_SLOT_BNDRY_VIOLATION,1: CH_B_HAS_SLOT_BNDRY_VIOLATION"
|
|
bitfld.long 0x00 6. "SVOA,Slot Boundary Violation Observed on Channel A (vSS!BViolationA) A slot boundary violation (channel active at the start or at the end of the assigned slot) was observed on channel A" "0: CH_A_NO_SLOT_BNDRY_VIOLATION,1: CH_A_HAS_SLOT_BNDRY_VIOLATION"
|
|
newline
|
|
bitfld.long 0x00 5. "CEOB,Content Error Observed on Channel B (vSS!ContentErrorB) A content error was observed in the assigned slot on channel B" "0: CH_B_NO_CONTENT_ERROR,1: CH_B_HAS_CONTENT_ERROR"
|
|
bitfld.long 0x00 4. "CEOA,Content Error Observed on Channel A (vSS!ContentErrorA) A content error was observed in the assigned slot on channel A" "0: CH_A_NO_CONTENT_ERROR,1: CH_A_HAS_CONTENT_ERROR"
|
|
newline
|
|
bitfld.long 0x00 3. "SEOB,Syntax Error Observed on Channel B (vSS!SyntaxErrorB) A syntax error was observed in the assigned slot on channel B" "0: CH_B_NO_SYNTAX_ERROR,1: CH_B_HAS_SYNTAX_ERROR"
|
|
bitfld.long 0x00 2. "SEOA,Syntax Error Observed on Channel A (vSS!SyntaxErrorA) A syntax error was observed in the assigned slot on channel A" "0: CH_A_NO_SYNTAX_ERROR,1: CH_A_HAS_SYNTAX_ERROR"
|
|
newline
|
|
bitfld.long 0x00 1. "VFRB,Valid Frame Received on Channel B (vSS!ValidFrameB) A valid frame indication is set if a valid frame was received on channel B" "0: CH_B_NO_VALID_FRAME,1: CH_B_WITH_VALID_FRAME"
|
|
bitfld.long 0x00 0. "VFRA,Valid Frame Received on Channel A (vSS!ValidFrameA) A valid frame indication is set if a valid frame was received on channel A" "0: CH_A_NO_VALID_FRAME,1: CH_A_WITH_VALID_FRAME"
|
|
group.long 0x710++0x03
|
|
line.long 0x00 "OBCM,Output Buffer Command Mask"
|
|
rbitfld.long 0x00 17. "RDSH,Read Data Section Host" "0: DATA_SECTION_NOT_READ,1: DATA_SECTION_FOR_MSRAM2OBF_TXFR"
|
|
rbitfld.long 0x00 16. "RHSH,Read Header Section Host" "0: HEADER_SECTION_NOT_READ,1: HEADER_SECTION_FOR_MSRAM2OBF_TXFR"
|
|
newline
|
|
bitfld.long 0x00 1. "RDSS,Read Data Section Shadow" "0: DATA_SECTION_NOT_READ,1: DATA_SECTION_FOR_MSRAM2OBF_TXFR"
|
|
bitfld.long 0x00 0. "RHSS,Read Header Section Shadow" "0: HEADER_SECTION_NOT_READ,1: HEADER_SECTION_FOR_MSRAM2OBF_TXFR"
|
|
group.long 0x714++0x03
|
|
line.long 0x00 "OBCR,Output Buffer Command Request"
|
|
hexmask.long.byte 0x00 16.--22. 1. "OBRH,Output Buffer Request Host Number of message buffer currently accessible by the Host via RDHS[1...3] MBS and RDDS[1...64]"
|
|
rbitfld.long 0x00 15. "OBSYS,Output Buffer Busy Shadow Set to '1' after setting bit REQ" "0: NO_TXFR_IN_PROGRESS,1: TXFR_BTW_MSRAM_AND_OBFS"
|
|
newline
|
|
bitfld.long 0x00 9. "REQ,Request Message RAM Transfer Requests transfer of message buffer addressed by OBRS[6:0] from Message RAM to OBF Shadow" "0: NO_REQUEST,1: TXFR_TO_OBFS_REQ"
|
|
bitfld.long 0x00 8. "VIEW,View Shadow Buffer Toggles between OBF Shadow and OBF Host" "0: NO_ACTION,1: SWP_OBFS_AND_OBFH"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OBRS,Output Buffer Request Shadow Number of source message buffer to be transferred from the Message RAM to OBF Shadow"
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "WRHS1_MIR2,Write Header Section 1 (2nd mirror)"
|
|
bitfld.long 0x00 29. "MBI,Message Buffer Interrupt This bit enables the receive / transmit interrupt for the corresponding message buffer" "0: MSG_BUFF_INTR_DISABLED,1: MSG_BUFF_INTR_ENABLED"
|
|
bitfld.long 0x00 28. "TXM,Transmission Mode This bit is used to select the transmission mode (see [01]Section 5.8.3 Transmit Buffers)" "0: CONTINUOUS_MODE,1: SINGLE_SHOT_MODE"
|
|
newline
|
|
bitfld.long 0x00 27. "PPIT,Payload Preamble Indicator Transmit This bit is used to control the state of the Payload Preamble Indicator in transmit frames" "0: PAYLOAD_PREAMBLE_NOT_SET,1: PAYLOAD_PREAMBLE_SET"
|
|
bitfld.long 0x00 26. "CFG,Message Buffer Direction Configuration Bit This bit is used to configure the corresponding buffer as transmit buffer or as receive buffer" "0: RX_BUFF,1: TX_BUFF"
|
|
newline
|
|
bitfld.long 0x00 25. "CHB,Channel Filter Control B The 2-bit channel filtering field associated with each buffer serves as a filter for receive buffers and as a control field for transmit buffers" "0: CH_B_DISABLED,1: CH_B_ENABLED"
|
|
bitfld.long 0x00 24. "CHA,Channel Filter Control A The 2-bit channel filtering field associated with each buffer serves as a filter for receive buffers and as a control field for transmit buffers" "0: CH_A_DISABLED,1: CH_A_ENABLED"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "CYC,Cycle Code The 7-bit cycle code determines the cycle set used for cycle counter filtering"
|
|
hexmask.long.word 0x00 0.--10. 1. "FID,Frame ID Frame ID of the selected message buffer"
|
|
group.long 0xBF4++0x03
|
|
line.long 0x00 "WRHS2_MIR2,Write Header Section 2 (2nd mirror)"
|
|
hexmask.long.byte 0x00 16.--22. 1. "PLC,Payload Length Configured Length of data section (number of 2-byte words) as configured by the Host"
|
|
hexmask.long.word 0x00 0.--10. 1. "CRC,Header CRC (vRF!Header!HeaderCRC) Receive Buffer: Configuration not required Transmit Buffer: Header CRC calculated and configured by the Host For calculation of the header CRC the payload length of the frame send on the bus has to be considered"
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "WRHS3_MIR2,Write Header Section 3 (2nd mirror)"
|
|
hexmask.long.word 0x00 0.--10. 1. "DP,Data Pointer Pointer to the first 32-bit word of the data section of the addressed message buffer in the Message RAM"
|
|
repeat 64. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0xC00)++0x03
|
|
line.long 0x00 "WRDS_MIR[$1],Write Data Section [1...64] (mirror $1"
|
|
hexmask.long 0x00 0.--31. 1. "MD,Message Data MD[7:0] = DW2n-1 byte4n-4 MD[15:8] = DW2n-1 byte4n-3 MD[23:16] = DW2n byte4n-2 MD[31:24] = DW2n byte4n-1"
|
|
repeat.end
|
|
group.long 0xD00++0x03
|
|
line.long 0x00 "WRHS1_MIR,Write Header Section 1 (mirror)"
|
|
bitfld.long 0x00 29. "MBI,Message Buffer Interrupt This bit enables the receive / transmit interrupt for the corresponding message buffer" "0: MSG_BUFF_INTR_DISABLED,1: MSG_BUFF_INTR_ENABLED"
|
|
bitfld.long 0x00 28. "TXM,Transmission Mode This bit is used to select the transmission mode (see [01]Section 5.8.3 Transmit Buffers)" "0: CONTINUOUS_MODE,1: SINGLE_SHOT_MODE"
|
|
newline
|
|
bitfld.long 0x00 27. "PPIT,Payload Preamble Indicator Transmit This bit is used to control the state of the Payload Preamble Indicator in transmit frames" "0: PAYLOAD_PREAMBLE_NOT_SET,1: PAYLOAD_PREAMBLE_SET"
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bitfld.long 0x00 26. "CFG,Message Buffer Direction Configuration Bit This bit is used to configure the corresponding buffer as transmit buffer or as receive buffer" "0: RX_BUFF,1: TX_BUFF"
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newline
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bitfld.long 0x00 25. "CHB,Channel Filter Control B The 2-bit channel filtering field associated with each buffer serves as a filter for receive buffers and as a control field for transmit buffers" "0: CH_B_DISABLED,1: CH_B_ENABLED"
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bitfld.long 0x00 24. "CHA,Channel Filter Control A The 2-bit channel filtering field associated with each buffer serves as a filter for receive buffers and as a control field for transmit buffers" "0: CH_A_DISABLED,1: CH_A_ENABLED"
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newline
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hexmask.long.byte 0x00 16.--22. 1. "CYC,Cycle Code The 7-bit cycle code determines the cycle set used for cycle counter filtering"
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|
hexmask.long.word 0x00 0.--10. 1. "FID,Frame ID Frame ID of the selected message buffer"
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|
group.long 0xD04++0x03
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|
line.long 0x00 "WRHS2_MIR,Write Header Section 2 (mirror)"
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|
hexmask.long.byte 0x00 16.--22. 1. "PLC,Payload Length Configured Length of data section (number of 2-byte words) as configured by the Host"
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hexmask.long.word 0x00 0.--10. 1. "CRC,Header CRC (vRF!Header!HeaderCRC) Receive Buffer: Configuration not required Transmit Buffer: Header CRC calculated and configured by the Host For calculation of the header CRC the payload length of the frame send on the bus has to be considered"
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group.long 0xD08++0x03
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line.long 0x00 "WRHS3_MIR,Write Header Section 3 (mirror)"
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|
hexmask.long.word 0x00 0.--10. 1. "DP,Data Pointer Pointer to the first 32-bit word of the data section of the addressed message buffer in the Message RAM"
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|
group.long 0xD10++0x03
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line.long 0x00 "IBCM_MIR,Input Buffer Command Mask (mirror)"
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|
rbitfld.long 0x00 18. "STXRS,Set Transmission Request Shadow" "0: TXR_FLAG_RESET,1: TXR_FLAG_SET"
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rbitfld.long 0x00 17. "LDSS,Load Data Section Shadow" "0: DATA_SECTION_NOT_UPDATED,1: DATA_SECTION_UPDATED"
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newline
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rbitfld.long 0x00 16. "LHSS,Load Header Section Shadow" "0: HEADER_SECTION_NOT_UPDATED,1: HEADER_SECTION_UPDATED"
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bitfld.long 0x00 2. "STXRH,Set Transmission Request Host If this bit is set to '1' the TXR flag for the selected message buffer is set in the TXRQ1/2/3/4 registers to release the message buffer for transmission" "0: TXR_FLAG_RESET,1: TXR_FLAG_SET"
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newline
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bitfld.long 0x00 1. "LDSH,Load Data Section Host" "0: DATA_SECTION_NOT_UPDATED,1: DATA_SECTION_UPDATED"
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bitfld.long 0x00 0. "LHSH,Load Header Section Host" "0: HEADER_SECTION_NOT_UPDATED,1: HEADER_SECTION_UPDATED"
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group.long 0xD14++0x03
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line.long 0x00 "IBCR_MIR,Input Buffer Command Request (mirror)"
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rbitfld.long 0x00 31. "IBSYS,Input Buffer Busy Shadow Set to '1' after writing IBRH[6:0]" "0: TXFR_IBF2MSRAM_COMPLETE,1: TXFR_IBF2MSRAM_IN_PROGRESS"
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hexmask.long.byte 0x00 16.--22. 1. "IBRS,Input Buffer Request Shadow Number of the target message buffer actually updated / lately updated"
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newline
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rbitfld.long 0x00 15. "IBSYH,Input Buffer Busy Host Set to '1' by writing IBRH[6:0] while IBSYS is still '1'" "0: REQUEST_NOT_PENDING,1: REQUEST_IN_PROGRESS"
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hexmask.long.byte 0x00 0.--6. 1. "IBRH,Input Buffer Request Host Selects the target message buffer in the Message RAM for data transfer from Input Buffer"
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rgroup.long 0xDF0++0x03
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line.long 0x00 "RDHS1_MIR2,Read Header Section 1 (2nd mirror)"
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bitfld.long 0x00 29. "MBI,Message Buffer Interrupt" "0,1"
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bitfld.long 0x00 28. "TXM,Transmission Mode" "0,1"
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newline
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bitfld.long 0x00 27. "PPIT,Payload Preamble Indicator Transmit" "0,1"
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bitfld.long 0x00 26. "CFG,Message Buffer Direction Configuration Bit" "0,1"
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newline
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bitfld.long 0x00 25. "CHB,Channel Filter Control B" "0,1"
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|
bitfld.long 0x00 24. "CHA,Channel Filter Control A" "0,1"
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|
newline
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hexmask.long.byte 0x00 16.--22. 1. "CYC,Cycle Code"
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|
hexmask.long.word 0x00 0.--10. 1. "FID,Frame ID"
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|
rgroup.long 0xDF4++0x03
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line.long 0x00 "RDHS2_MIR2,Read Header Section 2 (2nd mirror)"
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|
hexmask.long.byte 0x00 24.--30. 1. "PLR,Payload Length Received (vRF!Header!Length) Payload length value updated from received data frames (exception: if message buffer belongs to the receive FIFO PLR[6:0] is also updated from received null frames) When a message is stored into a message.."
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hexmask.long.byte 0x00 16.--22. 1. "PLC,Payload Length Configured Length of data section (number of 2-byte words) as configured by the Host"
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newline
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hexmask.long.word 0x00 0.--10. 1. "CRC,Header CRC (vRF!Header!HeaderCRC) Receive Buffer: Header CRC updated from received data frames Transmit Buffer: Header CRC calculated and configured by the Host"
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|
rgroup.long 0xDF8++0x03
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line.long 0x00 "RDHS3_MIR2,Read Header Section 3 (2nd mirror)"
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bitfld.long 0x00 29. "RES,N/A" "0,1"
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bitfld.long 0x00 28. "PPI,Payload Preamble Indicator (vRF!Header!PPIndicator) The payload preamble indicator defines whether a network management vector or message ID is contained within the payload segment of the received frame" "0: PAYLOAD_SEGMENT_HAS_NO_NMV_MID,1: PAYLOAD_SEGMENT_WITH_NMV_MID"
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newline
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bitfld.long 0x00 27. "NFI,Null Frame Indicator (vRF!Header!NFIndicator) Is set to '1' after storage of the first received data frame" "0: DATA_FRAME_NOT_STORED,1: DATA_FRAME_STORED"
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bitfld.long 0x00 26. "SYN,Sync Frame Indicator (vRF!Header!SyFIndicator) A sync frame is marked by the sync frame indicator" "0: RXD_FRAME_NOT_SYNC_FRAME,1: RXD_FRAME_SYNC_FRAME"
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newline
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bitfld.long 0x00 25. "SFI,Startup Frame Indicator (vRF!Header!SuFIndicator) A startup frame is marked by the startup frame indicator" "0: RXD_FRAME_NOT_STARTUP_FRAME,1: RXD_FRAME_STARTUP_FRAME"
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bitfld.long 0x00 24. "RCI,Received on Channel Indicator (vSS!Channel) Indicates the channel from which the received data frame was taken to update the respective receive buffer" "0: CH_B_FRAME_RECEIVED,1: CH_A_FRAME_RECEIVED"
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newline
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bitfld.long 0x00 16.--21. "RCC,Receive Cycle Count (vRF!Header!CycleCount) Cycle counter value updated from received data frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--10. 1. "DP,Data Pointer Pointer to the first 32-bit word of the data section of the addressed message buffer in the Message RAM"
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rgroup.long 0xDFC++0x03
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line.long 0x00 "MBS_MIR2,Message Buffer Status (2nd mirror)"
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bitfld.long 0x00 29. "RESS,N/A" "0,1"
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bitfld.long 0x00 28. "PPIS,Payload Preamble Indicator Status (vRF!Header!PPIndicator) The payload preamble indicator defines whether a network management vector or message ID is contained within the payload segment of the received frame" "0: PAYLOAD_SEGMENT_HAS_NO_NMV_MID,1: PAYLOAD_SEGMENT_WITH_NMV_MID"
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newline
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bitfld.long 0x00 27. "NFIS,Null Frame Indicator Status (vRF!Header!NFIndicator) If set to '0' the payload segment of the received frame contains no usable data" "0: NULL_FRAME_RECEIVED,1: NO_NULL_FRAME_RECEIVED"
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bitfld.long 0x00 26. "SYNS,Sync Frame Indicator Status (vRF!Header!SyFIndicator) A sync frame is marked by the sync frame indicator" "0: NO_SYNC_FRAME_RECEIVED,1: SYNC_FRAME_RECEIVED"
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newline
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bitfld.long 0x00 25. "SFIS,Startup Frame Indicator Status (vRF!Header!SuFIndicator) A startup frame is marked by the startup frame indicator" "0: NO_STARTUP_FRAME_RECEIVED,1: STARTUP_FRAME_RECEIVED"
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bitfld.long 0x00 24. "RCIS,Received on Channel Indicator Status (vSS!Channel) Indicates the channel on which the frame was received" "0: CH_B_FRAME_RECEIVED,1: CH_A_FRAME_RECEIVED"
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newline
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bitfld.long 0x00 16.--21. "CCS,Cycle Count Status Actual cycle count when status was updated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "FTB,Frame Transmitted on Channel B Indicates that this node has transmitted a data frame in the configured slot on channel B" "0: DATA_FRAME_NOT_TXD_ON_CH_B,1: DATA_FRAME_TXD_ON_CH_B"
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newline
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bitfld.long 0x00 14. "FTA,Frame Transmitted on Channel A Indicates that this node has transmitted a data frame in the configured slot on channel A" "0: DATA_FRAME_NOT_TXD_ON_CH_A,1: DATA_FRAME_TXD_ON_CH_A"
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bitfld.long 0x00 12. "MLST,Message Lost The flag is set in case the Host did not read the message before the message buffer was updated from a received data frame" "0: NO_MSG_LOST,1: MSG_LOST"
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newline
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bitfld.long 0x00 11. "ESB,Empty Slot Channel B In an empty slot there is no activity detected on the bus" "0: CH_B_HAS_BUS_ACTIVITY,1: CH_B_NO_BUS_ACTIVITY"
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bitfld.long 0x00 10. "ESA,Empty Slot Channel A In an empty slot there is no activity detected on the bus" "0: CH_A_HAS_BUS_ACTIVITY,1: CH_A_NO_BUS_ACTIVITY"
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newline
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bitfld.long 0x00 9. "TCIB,Transmission Conflict Indication Channel B (vSS!TxConflictB) A transmission conflict indication is set if a transmission conflict has occurred on channel B" "0: CH_B_NO_TXMN_CONFLICT,1: CH_B_HAS_TXMN_CONFLICT"
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bitfld.long 0x00 8. "TCIA,Transmission Conflict Indication Channel A (vSS!TxConflictA) A transmission conflict indication is set if a transmission conflict has occurred on channel A" "0: CH_A_NO_TXMN_CONFLICT,1: CH_A_HAS_TXMN_CONFLICT"
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newline
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bitfld.long 0x00 7. "SVOB,Slot Boundary Violation Observed on Channel B (vSS!BViolationB) A slot boundary violation (channel active at the start or at the end of the assigned slot) was observed on channel B" "0: CH_B_NO_SLOT_BNDRY_VIOLATION,1: CH_B_HAS_SLOT_BNDRY_VIOLATION"
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bitfld.long 0x00 6. "SVOA,Slot Boundary Violation Observed on Channel A (vSS!BViolationA) A slot boundary violation (channel active at the start or at the end of the assigned slot) was observed on channel A" "0: CH_A_NO_SLOT_BNDRY_VIOLATION,1: CH_A_HAS_SLOT_BNDRY_VIOLATION"
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newline
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bitfld.long 0x00 5. "CEOB,Content Error Observed on Channel B (vSS!ContentErrorB) A content error was observed in the assigned slot on channel B" "0: CH_B_NO_CONTENT_ERROR,1: CH_B_HAS_CONTENT_ERROR"
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bitfld.long 0x00 4. "CEOA,Content Error Observed on Channel A (vSS!ContentErrorA) A content error was observed in the assigned slot on channel A" "0: CH_A_NO_CONTENT_ERROR,1: CH_A_HAS_CONTENT_ERROR"
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newline
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bitfld.long 0x00 3. "SEOB,Syntax Error Observed on Channel B (vSS!SyntaxErrorB) A syntax error was observed in the assigned slot on channel B" "0: CH_B_NO_SYNTAX_ERROR,1: CH_B_HAS_SYNTAX_ERROR"
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bitfld.long 0x00 2. "SEOA,Syntax Error Observed on Channel A (vSS!SyntaxErrorA) A syntax error was observed in the assigned slot on channel A" "0: CH_A_NO_SYNTAX_ERROR,1: CH_A_HAS_SYNTAX_ERROR"
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newline
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bitfld.long 0x00 1. "VFRB,Valid Frame Received on Channel B (vSS!ValidFrameB) A valid frame indication is set if a valid frame was received on channel B" "0: CH_B_NO_VALID_FRAME,1: CH_B_WITH_VALID_FRAME"
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bitfld.long 0x00 0. "VFRA,Valid Frame Received on Channel A (vSS!ValidFrameA) A valid frame indication is set if a valid frame was received on channel A" "0: CH_A_NO_VALID_FRAME,1: CH_A_WITH_VALID_FRAME"
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repeat 64. (increment 0 1) (increment 0 0x04)
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rgroup.long ($2+0xE00)++0x03
|
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line.long 0x00 "RDDS_MIR[$1],Read Data Section [1...64] (mirror $1"
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hexmask.long 0x00 0.--31. 1. "MD,Message Data MD[7:0] = DW2n-1 byte4n-4 MD[15:8] = DW2n-1 byte4n-3 MD[23:16] = DW2n byte4n-2 MD[31:24] = DW2n byte4n-1"
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repeat.end
|
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rgroup.long 0xF00++0x03
|
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line.long 0x00 "RDHS1_MIR,Read Header Section 1 (mirror)"
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bitfld.long 0x00 29. "MBI,Message Buffer Interrupt" "0,1"
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bitfld.long 0x00 28. "TXM,Transmission Mode" "0,1"
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newline
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bitfld.long 0x00 27. "PPIT,Payload Preamble Indicator Transmit" "0,1"
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bitfld.long 0x00 26. "CFG,Message Buffer Direction Configuration Bit" "0,1"
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newline
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bitfld.long 0x00 25. "CHB,Channel Filter Control B" "0,1"
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bitfld.long 0x00 24. "CHA,Channel Filter Control A" "0,1"
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newline
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hexmask.long.byte 0x00 16.--22. 1. "CYC,Cycle Code"
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hexmask.long.word 0x00 0.--10. 1. "FID,Frame ID"
|
|
rgroup.long 0xF04++0x03
|
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line.long 0x00 "RDHS2_MIR,Read Header Section 2 (mirror)"
|
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hexmask.long.byte 0x00 24.--30. 1. "PLR,Payload Length Received (vRF!Header!Length) Payload length value updated from received data frames (exception: if message buffer belongs to the receive FIFO PLR[6:0] is also updated from received null frames) When a message is stored into a message.."
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hexmask.long.byte 0x00 16.--22. 1. "PLC,Payload Length Configured Length of data section (number of 2-byte words) as configured by the Host"
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newline
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hexmask.long.word 0x00 0.--10. 1. "CRC,Header CRC (vRF!Header!HeaderCRC) Receive Buffer: Header CRC updated from received data frames Transmit Buffer: Header CRC calculated and configured by the Host"
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rgroup.long 0xF08++0x03
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line.long 0x00 "RDHS3_MIR,Read Header Section 3 (mirror)"
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bitfld.long 0x00 29. "RES,N/A" "0,1"
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bitfld.long 0x00 28. "PPI,Payload Preamble Indicator (vRF!Header!PPIndicator) The payload preamble indicator defines whether a network management vector or message ID is contained within the payload segment of the received frame" "0: PAYLOAD_SEGMENT_HAS_NO_NMV_MID,1: PAYLOAD_SEGMENT_WITH_NMV_MID"
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newline
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bitfld.long 0x00 27. "NFI,Null Frame Indicator (vRF!Header!NFIndicator) Is set to '1' after storage of the first received data frame" "0: DATA_FRAME_NOT_STORED,1: DATA_FRAME_STORED"
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bitfld.long 0x00 26. "SYN,Sync Frame Indicator (vRF!Header!SyFIndicator) A sync frame is marked by the sync frame indicator" "0: RXD_FRAME_NOT_SYNC_FRAME,1: RXD_FRAME_SYNC_FRAME"
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newline
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bitfld.long 0x00 25. "SFI,Startup Frame Indicator (vRF!Header!SuFIndicator) A startup frame is marked by the startup frame indicator" "0: RXD_FRAME_NOT_STARTUP_FRAME,1: RXD_FRAME_STARTUP_FRAME"
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bitfld.long 0x00 24. "RCI,Received on Channel Indicator (vSS!Channel) Indicates the channel from which the received data frame was taken to update the respective receive buffer" "0: CH_B_FRAME_RECEIVED,1: CH_A_FRAME_RECEIVED"
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newline
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bitfld.long 0x00 16.--21. "RCC,Receive Cycle Count (vRF!Header!CycleCount) Cycle counter value updated from received data frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--10. 1. "DP,Data Pointer Pointer to the first 32-bit word of the data section of the addressed message buffer in the Message RAM"
|
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rgroup.long 0xF0C++0x03
|
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line.long 0x00 "MBS_MIR,Message Buffer Status (mirror)"
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bitfld.long 0x00 29. "RESS,N/A" "0,1"
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bitfld.long 0x00 28. "PPIS,Payload Preamble Indicator Status (vRF!Header!PPIndicator) The payload preamble indicator defines whether a network management vector or message ID is contained within the payload segment of the received frame" "0: PAYLOAD_SEGMENT_HAS_NO_NMV_MID,1: PAYLOAD_SEGMENT_WITH_NMV_MID"
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newline
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bitfld.long 0x00 27. "NFIS,Null Frame Indicator Status (vRF!Header!NFIndicator) If set to '0' the payload segment of the received frame contains no usable data" "0: NULL_FRAME_RECEIVED,1: NO_NULL_FRAME_RECEIVED"
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bitfld.long 0x00 26. "SYNS,Sync Frame Indicator Status (vRF!Header!SyFIndicator) A sync frame is marked by the sync frame indicator" "0: NO_SYNC_FRAME_RECEIVED,1: SYNC_FRAME_RECEIVED"
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newline
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bitfld.long 0x00 25. "SFIS,Startup Frame Indicator Status (vRF!Header!SuFIndicator) A startup frame is marked by the startup frame indicator" "0: NO_STARTUP_FRAME_RECEIVED,1: STARTUP_FRAME_RECEIVED"
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bitfld.long 0x00 24. "RCIS,Received on Channel Indicator Status (vSS!Channel) Indicates the channel on which the frame was received" "0: CH_B_FRAME_RECEIVED,1: CH_A_FRAME_RECEIVED"
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newline
|
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bitfld.long 0x00 16.--21. "CCS,Cycle Count Status Actual cycle count when status was updated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "FTB,Frame Transmitted on Channel B Indicates that this node has transmitted a data frame in the configured slot on channel B" "0: DATA_FRAME_NOT_TXD_ON_CH_B,1: DATA_FRAME_TXD_ON_CH_B"
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newline
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bitfld.long 0x00 14. "FTA,Frame Transmitted on Channel A Indicates that this node has transmitted a data frame in the configured slot on channel A" "0: DATA_FRAME_NOT_TXD_ON_CH_A,1: DATA_FRAME_TXD_ON_CH_A"
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bitfld.long 0x00 12. "MLST,Message Lost The flag is set in case the Host did not read the message before the message buffer was updated from a received data frame" "0: NO_MSG_LOST,1: MSG_LOST"
|
|
newline
|
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bitfld.long 0x00 11. "ESB,Empty Slot Channel B In an empty slot there is no activity detected on the bus" "0: CH_B_HAS_BUS_ACTIVITY,1: CH_B_NO_BUS_ACTIVITY"
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bitfld.long 0x00 10. "ESA,Empty Slot Channel A In an empty slot there is no activity detected on the bus" "0: CH_A_HAS_BUS_ACTIVITY,1: CH_A_NO_BUS_ACTIVITY"
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newline
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bitfld.long 0x00 9. "TCIB,Transmission Conflict Indication Channel B (vSS!TxConflictB) A transmission conflict indication is set if a transmission conflict has occurred on channel B" "0: CH_B_NO_TXMN_CONFLICT,1: CH_B_HAS_TXMN_CONFLICT"
|
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bitfld.long 0x00 8. "TCIA,Transmission Conflict Indication Channel A (vSS!TxConflictA) A transmission conflict indication is set if a transmission conflict has occurred on channel A" "0: CH_A_NO_TXMN_CONFLICT,1: CH_A_HAS_TXMN_CONFLICT"
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newline
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bitfld.long 0x00 7. "SVOB,Slot Boundary Violation Observed on Channel B (vSS!BViolationB) A slot boundary violation (channel active at the start or at the end of the assigned slot) was observed on channel B" "0: CH_B_NO_SLOT_BNDRY_VIOLATION,1: CH_B_HAS_SLOT_BNDRY_VIOLATION"
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bitfld.long 0x00 6. "SVOA,Slot Boundary Violation Observed on Channel A (vSS!BViolationA) A slot boundary violation (channel active at the start or at the end of the assigned slot) was observed on channel A" "0: CH_A_NO_SLOT_BNDRY_VIOLATION,1: CH_A_HAS_SLOT_BNDRY_VIOLATION"
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newline
|
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bitfld.long 0x00 5. "CEOB,Content Error Observed on Channel B (vSS!ContentErrorB) A content error was observed in the assigned slot on channel B" "0: CH_B_NO_CONTENT_ERROR,1: CH_B_HAS_CONTENT_ERROR"
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|
bitfld.long 0x00 4. "CEOA,Content Error Observed on Channel A (vSS!ContentErrorA) A content error was observed in the assigned slot on channel A" "0: CH_A_NO_CONTENT_ERROR,1: CH_A_HAS_CONTENT_ERROR"
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newline
|
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bitfld.long 0x00 3. "SEOB,Syntax Error Observed on Channel B (vSS!SyntaxErrorB) A syntax error was observed in the assigned slot on channel B" "0: CH_B_NO_SYNTAX_ERROR,1: CH_B_HAS_SYNTAX_ERROR"
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|
bitfld.long 0x00 2. "SEOA,Syntax Error Observed on Channel A (vSS!SyntaxErrorA) A syntax error was observed in the assigned slot on channel A" "0: CH_A_NO_SYNTAX_ERROR,1: CH_A_HAS_SYNTAX_ERROR"
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newline
|
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bitfld.long 0x00 1. "VFRB,Valid Frame Received on Channel B (vSS!ValidFrameB) A valid frame indication is set if a valid frame was received on channel B" "0: CH_B_NO_VALID_FRAME,1: CH_B_WITH_VALID_FRAME"
|
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bitfld.long 0x00 0. "VFRA,Valid Frame Received on Channel A (vSS!ValidFrameA) A valid frame indication is set if a valid frame was received on channel A" "0: CH_A_NO_VALID_FRAME,1: CH_A_WITH_VALID_FRAME"
|
|
group.long 0xF10++0x03
|
|
line.long 0x00 "OBCM_MIR,Output Buffer Command Mask (mirror)"
|
|
rbitfld.long 0x00 17. "RDSH,Read Data Section Host" "0: DATA_SECTION_NOT_READ,1: DATA_SECTION_FOR_MSRAM2OBF_TXFR"
|
|
rbitfld.long 0x00 16. "RHSH,Read Header Section Host" "0: HEADER_SECTION_NOT_READ,1: HEADER_SECTION_FOR_MSRAM2OBF_TXFR"
|
|
newline
|
|
bitfld.long 0x00 1. "RDSS,Read Data Section Shadow" "0: DATA_SECTION_NOT_READ,1: DATA_SECTION_FOR_MSRAM2OBF_TXFR"
|
|
bitfld.long 0x00 0. "RHSS,Read Header Section Shadow" "0: HEADER_SECTION_NOT_READ,1: HEADER_SECTION_FOR_MSRAM2OBF_TXFR"
|
|
group.long 0xF14++0x03
|
|
line.long 0x00 "OBCR_MIR,Output Buffer Command Request (mirror)"
|
|
hexmask.long.byte 0x00 16.--22. 1. "OBRH,Output Buffer Request Host Number of message buffer currently accessible by the Host via RDHS[1...3] MBS and RDDS[1...64]"
|
|
rbitfld.long 0x00 15. "OBSYS,Output Buffer Busy Shadow Set to '1' after setting bit REQ" "0: NO_TXFR_IN_PROGRESS,1: TXFR_BTW_MSRAM_AND_OBFS"
|
|
newline
|
|
bitfld.long 0x00 9. "REQ,Request Message RAM Transfer Requests transfer of message buffer addressed by OBRS[6:0] from Message RAM to OBF Shadow" "0: NO_REQUEST,1: TXFR_TO_OBFS_REQ"
|
|
bitfld.long 0x00 8. "VIEW,View Shadow Buffer Toggles between OBF Shadow and OBF Host" "0: NO_ACTION,1: SWP_OBFS_AND_OBFH"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "OBRS,Output Buffer Request Shadow Number of source message buffer to be transferred from the Message RAM to OBF Shadow"
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O Ports and Peripheral I/O Lines)"
|
|
base ad:0x40310000
|
|
rgroup.long 0x4000++0x03
|
|
line.long 0x00 "INTR_CAUSE0,Interrupt port cause register 0"
|
|
hexmask.long 0x00 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register"
|
|
repeat 3. (strings "1" "2" "3" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x4004)++0x03
|
|
line.long 0x00 "INTR_CAUSE$1,Interrupt port cause register $1"
|
|
hexmask.long 0x00 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register"
|
|
repeat.end
|
|
rgroup.long 0x4010++0x03
|
|
line.long 0x00 "VDD_ACTIVE,Extern power supply detection register"
|
|
bitfld.long 0x00 31. "VDDD_ACTIVE,This bit indicates presence of the VDDD supply" "0,1"
|
|
bitfld.long 0x00 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA" "0,1"
|
|
abitfld.long 0x00 0.--15. "VDDIO_ACTIVE,Indicates presence or absence of VDDIO supplies (i.e. other than VDDD VDDA) on the device (supplies are numbered 0..n-1)" "0x0000=0: vbackup,0x0001=1: vddio_0,0x0002=2: vddio_1,0x0003=3: vddio_a,0x0004=4: vddio_r,0x0005=5: vddusb'"
|
|
group.long 0x4014++0x03
|
|
line.long 0x00 "VDD_INTR,Supply detection interrupt register"
|
|
bitfld.long 0x00 31. "VDDD_ACTIVE,The VDDD supply is always present during operation so a supply transition can not occur" "0,1"
|
|
bitfld.long 0x00 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDDIO_ACTIVE,Supply state change detected"
|
|
group.long 0x4018++0x03
|
|
line.long 0x00 "VDD_INTR_MASK,Supply detection interrupt mask register"
|
|
bitfld.long 0x00 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD" "0,1"
|
|
bitfld.long 0x00 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDDIO_ACTIVE,Masks supply interrupt on VDDIO"
|
|
rgroup.long 0x401C++0x03
|
|
line.long 0x00 "VDD_INTR_MASKED,Supply detection interrupt masked register"
|
|
bitfld.long 0x00 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD" "0,1"
|
|
bitfld.long 0x00 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDDIO_ACTIVE,Supply transition detected AND masked '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU"
|
|
group.long 0x4020++0x03
|
|
line.long 0x00 "VDD_INTR_SET,Supply detection interrupt set register"
|
|
bitfld.long 0x00 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD" "0,1"
|
|
bitfld.long 0x00 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDDIO_ACTIVE,Sets supply interrupt"
|
|
repeat 35. (increment 0 1)(increment 0 0x80)
|
|
tree "PRT[$1]"
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "OUT,Port output data register"
|
|
bitfld.long 0x00 7. "OUT7,IO output data for pin 7" "0,1"
|
|
bitfld.long 0x00 6. "OUT6,IO output data for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OUT5,IO output data for pin 5" "0,1"
|
|
bitfld.long 0x00 4. "OUT4,IO output data for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OUT3,IO output data for pin 3" "0,1"
|
|
bitfld.long 0x00 2. "OUT2,IO output data for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OUT1,IO output data for pin 1" "0,1"
|
|
bitfld.long 0x00 0. "OUT0,IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'" "0,1"
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "OUT_CLR,Port output data clear register"
|
|
bitfld.long 0x00 7. "OUT7,IO clear output for pin 7" "0,1"
|
|
bitfld.long 0x00 6. "OUT6,IO clear output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OUT5,IO clear output for pin 5" "0,1"
|
|
bitfld.long 0x00 4. "OUT4,IO clear output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OUT3,IO clear output for pin 3" "0,1"
|
|
bitfld.long 0x00 2. "OUT2,IO clear output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OUT1,IO clear output for pin 1" "0,1"
|
|
bitfld.long 0x00 0. "OUT0,IO clear output for pin" "0,1"
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "OUT_SET,Port output data set register"
|
|
bitfld.long 0x00 7. "OUT7,IO set output for pin 7" "0,1"
|
|
bitfld.long 0x00 6. "OUT6,IO set output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OUT5,IO set output for pin 5" "0,1"
|
|
bitfld.long 0x00 4. "OUT4,IO set output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OUT3,IO set output for pin 3" "0,1"
|
|
bitfld.long 0x00 2. "OUT2,IO set output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OUT1,IO set output for pin 1" "0,1"
|
|
bitfld.long 0x00 0. "OUT0,IO set output for pin" "0,1"
|
|
group.long ($2+0x0C)++0x03
|
|
line.long 0x00 "OUT_INV,Port output data invert register"
|
|
bitfld.long 0x00 7. "OUT7,IO invert output for pin 7" "0,1"
|
|
bitfld.long 0x00 6. "OUT6,IO invert output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OUT5,IO invert output for pin 5" "0,1"
|
|
bitfld.long 0x00 4. "OUT4,IO invert output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "OUT3,IO invert output for pin 3" "0,1"
|
|
bitfld.long 0x00 2. "OUT2,IO invert output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OUT1,IO invert output for pin 1" "0,1"
|
|
bitfld.long 0x00 0. "OUT0,IO invert output for pin" "0,1"
|
|
rgroup.long ($2+0x10)++0x03
|
|
line.long 0x00 "IN,Port input state register"
|
|
bitfld.long 0x00 8. "FLT_IN,Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register" "0,1"
|
|
bitfld.long 0x00 7. "IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "IN6,IO pin state for pin 6" "0,1"
|
|
bitfld.long 0x00 5. "IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "IN4,IO pin state for pin 4" "0,1"
|
|
bitfld.long 0x00 3. "IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "IN2,IO pin state for pin 2" "0,1"
|
|
bitfld.long 0x00 1. "IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IN0,IO pin state for pin 0 '0': Low logic level present on pin" "0,1"
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "INTR,Port interrupt status register"
|
|
rbitfld.long 0x00 24. "FLT_IN_IN,Filtered pin state for pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
rbitfld.long 0x00 23. "IN_IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 22. "IN_IN6,IO pin state for pin 6" "0,1"
|
|
rbitfld.long 0x00 21. "IN_IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "IN_IN4,IO pin state for pin 4" "0,1"
|
|
rbitfld.long 0x00 19. "IN_IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 18. "IN_IN2,IO pin state for pin 2" "0,1"
|
|
rbitfld.long 0x00 17. "IN_IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "IN_IN0,IO pin state for pin 0" "0,1"
|
|
bitfld.long 0x00 8. "FLT_EDGE,Edge detected on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "EDGE7,Edge detect for IO pin 7" "0,1"
|
|
bitfld.long 0x00 6. "EDGE6,Edge detect for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "EDGE5,Edge detect for IO pin 5" "0,1"
|
|
bitfld.long 0x00 4. "EDGE4,Edge detect for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EDGE3,Edge detect for IO pin 3" "0,1"
|
|
bitfld.long 0x00 2. "EDGE2,Edge detect for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EDGE1,Edge detect for IO pin 1" "0,1"
|
|
bitfld.long 0x00 0. "EDGE0,Edge detect for IO pin 0 '0': No edge was detected on pin" "0,1"
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "INTR_MASK,Port interrupt mask register"
|
|
bitfld.long 0x00 8. "FLT_EDGE,Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x00 7. "EDGE7,Masks edge interrupt on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "EDGE6,Masks edge interrupt on IO pin 6" "0,1"
|
|
bitfld.long 0x00 5. "EDGE5,Masks edge interrupt on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "EDGE4,Masks edge interrupt on IO pin 4" "0,1"
|
|
bitfld.long 0x00 3. "EDGE3,Masks edge interrupt on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EDGE2,Masks edge interrupt on IO pin 2" "0,1"
|
|
bitfld.long 0x00 1. "EDGE1,Masks edge interrupt on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "EDGE0,Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled" "0,1"
|
|
rgroup.long ($2+0x1C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Port interrupt masked status register"
|
|
bitfld.long 0x00 8. "FLT_EDGE,Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x00 7. "EDGE7,Edge detected and masked on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "EDGE6,Edge detected and masked on IO pin 6" "0,1"
|
|
bitfld.long 0x00 5. "EDGE5,Edge detected and masked on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "EDGE4,Edge detected and masked on IO pin 4" "0,1"
|
|
bitfld.long 0x00 3. "EDGE3,Edge detected and masked on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EDGE2,Edge detected and masked on IO pin 2" "0,1"
|
|
bitfld.long 0x00 1. "EDGE1,Edge detected and masked on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "EDGE0,Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU" "0,1"
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "INTR_SET,Port interrupt set register"
|
|
bitfld.long 0x00 8. "FLT_EDGE,Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x00 7. "EDGE7,Sets edge detect interrupt for IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "EDGE6,Sets edge detect interrupt for IO pin 6" "0,1"
|
|
bitfld.long 0x00 5. "EDGE5,Sets edge detect interrupt for IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "EDGE4,Sets edge detect interrupt for IO pin 4" "0,1"
|
|
bitfld.long 0x00 3. "EDGE3,Sets edge detect interrupt for IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EDGE2,Sets edge detect interrupt for IO pin 2" "0,1"
|
|
bitfld.long 0x00 1. "EDGE1,Sets edge detect interrupt for IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "EDGE0,Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set" "0,1"
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "INTR_CFG,Port interrupt configuration register"
|
|
bitfld.long 0x00 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. "FLT_EDGE_SEL,Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pin 0" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
group.long ($2+0x44)++0x03
|
|
line.long 0x00 "CFG,Port configuration register"
|
|
bitfld.long 0x00 31. "IN_EN7,Enables the input buffer for IO pin 7" "0,1"
|
|
bitfld.long 0x00 28.--30. "DRIVE_MODE7,The GPIO drive mode for IO pin 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. "IN_EN6,Enables the input buffer for IO pin 6" "0,1"
|
|
bitfld.long 0x00 24.--26. "DRIVE_MODE6,The GPIO drive mode for IO pin 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. "IN_EN5,Enables the input buffer for IO pin 5" "0,1"
|
|
bitfld.long 0x00 20.--22. "DRIVE_MODE5,The GPIO drive mode for IO pin 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. "IN_EN4,Enables the input buffer for IO pin 4" "0,1"
|
|
bitfld.long 0x00 16.--18. "DRIVE_MODE4,The GPIO drive mode for IO pin4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "IN_EN3,Enables the input buffer for IO pin 3" "0,1"
|
|
bitfld.long 0x00 12.--14. "DRIVE_MODE3,The GPIO drive mode for IO pin 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "IN_EN2,Enables the input buffer for IO pin 2" "0,1"
|
|
bitfld.long 0x00 8.--10. "DRIVE_MODE2,The GPIO drive mode for IO pin 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. "IN_EN1,Enables the input buffer for IO pin 1" "0,1"
|
|
bitfld.long 0x00 4.--6. "DRIVE_MODE1,The GPIO drive mode for IO pin 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "IN_EN0,Enables the input buffer for IO pin 0" "0,1"
|
|
bitfld.long 0x00 0.--2. "DRIVE_MODE0,The GPIO drive mode for IO pin 0" "0: Output buffer is off creating a high..,1: RSVD,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "CFG_IN,Port input buffer configuration register"
|
|
bitfld.long 0x00 7. "VTRIP_SEL7_0,Configures the pin 7 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x00 6. "VTRIP_SEL6_0,Configures the pin 6 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "VTRIP_SEL5_0,Configures the pin 5 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x00 4. "VTRIP_SEL4_0,Configures the pin 4 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "VTRIP_SEL3_0,Configures the pin 3 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x00 2. "VTRIP_SEL2_0,Configures the pin 2 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "VTRIP_SEL1_0,Configures the pin 1 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x00 0. "VTRIP_SEL0_0,Configures the pin 0 input buffer mode (trip points and hysteresis)" "0: PSoC6,1: PSoC6"
|
|
group.long ($2+0x4C)++0x03
|
|
line.long 0x00 "CFG_OUT,Port output buffer configuration register"
|
|
bitfld.long 0x00 30.--31. "DRIVE_SEL7,Sets the GPIO drive strength for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "DRIVE_SEL6,Sets the GPIO drive strength for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "DRIVE_SEL5,Sets the GPIO drive strength for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "DRIVE_SEL4,Sets the GPIO drive strength for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "DRIVE_SEL3,Sets the GPIO drive strength for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "DRIVE_SEL2,Sets the GPIO drive strength for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "DRIVE_SEL1,Sets the GPIO drive strength for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "DRIVE_SEL0,Sets the GPIO drive strength for IO pin 0" "0: DRIVE_SEL_ZERO,1: DRIVE_SEL_ONE,2: DRIVE_SEL_TWO,3: DRIVE_SEL_THREE"
|
|
newline
|
|
bitfld.long 0x00 7. "SLOW7,Enables slow slew rate for IO pin 7" "0,1"
|
|
bitfld.long 0x00 6. "SLOW6,Enables slow slew rate for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SLOW5,Enables slow slew rate for IO pin 5" "0,1"
|
|
bitfld.long 0x00 4. "SLOW4,Enables slow slew rate for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SLOW3,Enables slow slew rate for IO pin 3" "0,1"
|
|
bitfld.long 0x00 2. "SLOW2,Enables slow slew rate for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SLOW1,Enables slow slew rate for IO pin 1" "0,1"
|
|
bitfld.long 0x00 0. "SLOW0,Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate" "0,1"
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "CFG_SIO,Port SIO configuration register"
|
|
bitfld.long 0x00 29.--31. "VOH_SEL67,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 27.--28. "VREF_SEL67,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26. "VTRIP_SEL67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x00 25. "IBUF_SEL67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "VREG_EN67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x00 21.--23. "VOH_SEL45,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "VREF_SEL45,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
bitfld.long 0x00 18. "VTRIP_SEL45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "IBUF_SEL45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x00 16. "VREG_EN45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "VOH_SEL23,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11.--12. "VREF_SEL23,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10. "VTRIP_SEL23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x00 9. "IBUF_SEL23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "VREG_EN23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x00 5.--7. "VOH_SEL01,Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "VREF_SEL01,Selects reference voltage (Vref) trip-point of the input buffer: '0': Trip-point reference from pin_ref '1': Trip-point reference of SRSS internal reference Vref (1.2 V) '2': Trip-point reference of AMUXBUS_A '3': Trip-point reference of.." "0,1,2,3"
|
|
bitfld.long 0x00 2. "VTRIP_SEL01,Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'): '0': Input buffer functions as a CMOS input buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IBUF_SEL01,Selects the input buffer mode" "0: Singled ended input buffer,1: Differential input buffer"
|
|
bitfld.long 0x00 0. "VREG_EN01,Selects the output buffer mode: '0': Unregulated output buffer '1': Regulated output buffer The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode" "0,1"
|
|
group.long ($2+0x58)++0x03
|
|
line.long 0x00 "CFG_IN_AUTOLVL,Port input buffer AUTOLVL configuration register"
|
|
bitfld.long 0x00 7. "VTRIP_SEL7_1,Input buffer compatible with automotive (elevated Vil) interfaces" "0,1"
|
|
bitfld.long 0x00 6. "VTRIP_SEL6_1,Input buffer compatible with automotive (elevated Vil) interfaces" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "VTRIP_SEL5_1,Input buffer compatible with automotive (elevated Vil) interfaces" "0,1"
|
|
bitfld.long 0x00 4. "VTRIP_SEL4_1,Input buffer compatible with automotive (elevated Vil) interfaces" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "VTRIP_SEL3_1,Input buffer compatible with automotive (elevated Vil) interfaces" "0,1"
|
|
bitfld.long 0x00 2. "VTRIP_SEL2_1,Input buffer compatible with automotive (elevated Vil) interfaces" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "VTRIP_SEL1_1,Input buffer compatible with automotive (elevated Vil) interfaces" "0,1"
|
|
bitfld.long 0x00 0. "VTRIP_SEL0_1,Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit" "0: Input buffer compatible with CMOS/TTL..,1: Input buffer compatible with AUTO (elevated.."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "HSIOM (High Speed IO Matrix)"
|
|
base ad:0x40300000
|
|
repeat 64. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x2000)++0x03
|
|
line.long 0x00 "AMUX_SPLIT_CTL[$1],AMUX splitter cell control $1"
|
|
bitfld.long 0x00 6. "SWITCH_BB_S0,T-switch control for AMUXBUSB vssa/ground switch" "0,1"
|
|
bitfld.long 0x00 5. "SWITCH_BB_SR,T-switch control for Right AMUXBUSB switch" "0,1"
|
|
bitfld.long 0x00 4. "SWITCH_BB_SL,T-switch control for Left AMUXBUSB switch" "0,1"
|
|
bitfld.long 0x00 2. "SWITCH_AA_S0,T-switch control for AMUXBUSA vssa/ground switch: '0': switch open" "0,1"
|
|
bitfld.long 0x00 1. "SWITCH_AA_SR,T-switch control for Right AMUXBUSA switch: '0': switch open" "0,1"
|
|
bitfld.long 0x00 0. "SWITCH_AA_SL,T-switch control for Left AMUXBUSA switch: '0': switch open" "0,1"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x2200)++0x03
|
|
line.long 0x00 "MONITOR_CTL_$1,Power/Ground Monitor cell control $1"
|
|
hexmask.long 0x00 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: '0': switch open"
|
|
repeat.end
|
|
group.long 0x2240++0x03
|
|
line.long 0x00 "ALT_JTAG_EN,Alternate JTAG IF selection register"
|
|
bitfld.long 0x00 31. "ENABLE,Provides the selection for alternate JTAG IF connectivity" "0: Primary JTAG interface is selected,1: Secondary (alternate) JTAG interface is.."
|
|
repeat 35. (increment 0 1)(increment 0 0x10)
|
|
tree "PRT[$1]"
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PORT_SEL0,Port selection 0"
|
|
bitfld.long 0x00 24.--28. "IO3_SEL,Selects connection for IO pin 3 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "IO2_SEL,Selects connection for IO pin 2 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. "IO1_SEL,Selects connection for IO pin 1 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "IO0_SEL,Selects connection for IO pin 0 route" "0: GPIO controls 'out',1: GPIO controls 'out' DSI controls 'output..,2: DSI controls 'out' and 'output enable',3: DSI controls 'out' GPIO controls 'output..,4: Analog mux bus A,5: Analog mux bus B,6: Analog mux bus A DSI control,7: Analog mux bus B DSI control,8: Active functionality 0,9: Active functionality 1,10: Active functionality 2,11: Active functionality 3,12: DeepSleep functionality 0,13: DeepSleep functionality 1,14: DeepSleep functionality 2,15: DeepSleep functionality 3,16: Active functionality 4,17: Active functionality 5,18: Active functionality 6,19: Active functionality 7,20: Active functionality 8,21: Active functionality 9,22: Active functionality 10,23: Active functionality 11,24: Active functionality 12,25: Active functionality 13,26: Active functionality 14,27: Active functionality 15,28: DeepSleep functionality 4,29: DeepSleep functionality 5,30: DeepSleep functionality 6,31: DeepSleep functionality 7"
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "PORT_SEL1,Port selection 1"
|
|
bitfld.long 0x00 24.--28. "IO7_SEL,Selects connection for IO pin 7 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "IO6_SEL,Selects connection for IO pin 6 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. "IO5_SEL,Selects connection for IO pin 5 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "IO4_SEL,Selects connection for IO pin 4 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "I2S (Inter-Integrated Sound Bus Controller)"
|
|
repeat 3. (list 0. 1. 2.) (list ad:0x40800000 ad:0x40801000 ad:0x40802000)
|
|
tree "I2S$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control"
|
|
bitfld.long 0x00 31. "RX_ENABLED,Enables the I2S RX component: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 30. "TX_ENABLED,Enables the I2S TX component: '0': Disabled" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CLOCK_CTL,Clock control"
|
|
bitfld.long 0x00 16. "MCLK_EN,Enable MCLK - enables MCLK divider operation Upon assertion allows MCLK Divider to begin operation" "0,1"
|
|
bitfld.long 0x00 12.--13. "MCLK_DIV,Selects clock divider for MCLK_OUT" "0: Divide clk_audio_i2s by 1 (Bypass),1: Divide clk_audio_i2s by 2,2: Divide clk_audio_i2s by 4,3: Divide clk-audio_i2s by 8"
|
|
newline
|
|
bitfld.long 0x00 8. "CLOCK_SEL,Selects clock to be used by I2S: '0': Internal clock ('clk_audio_i2s') '1': External clock ('clk_i2s_if')" "0,1"
|
|
bitfld.long 0x00 0.--5. "CLOCK_DIV,Frequency divisor for generating I2S clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CLOCK_STAT,Clock Status"
|
|
bitfld.long 0x00 0. "MCLK_DIV_OFF,MCLK Divider OFF" "0: Indicates MCLK Divider not a reset state,1: Indicates MCLK Divider at reset state"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMD,Command"
|
|
bitfld.long 0x00 16. "RX_START,Receiver enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 8. "TX_PAUSE,Pause enable: '0': Disabled (TX FIFO data is sent over I2S)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TX_START,Transmitter enable: '0': Disabled" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 16. "RX_REQ_EN,Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception '0': Disabled" "0,1"
|
|
bitfld.long 0x00 0. "TX_REQ_EN,Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission '0': Disabled" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TX_CTL,Transmitter control"
|
|
bitfld.long 0x00 25. "SCKI_POL,TX slave bit clock polarity" "0,1"
|
|
bitfld.long 0x00 24. "SCKO_POL,TX master bit clock polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "WORD_LEN,Word length in number of bits: Note: - When this field is configured to '6' or '7' the length is set to 32-bit (same as '5')" "0: BIT_LEN8,1: BIT_LEN16,2: BIT_LEN18,3: BIT_LEN20,4: BIT_LEN24,5: BIT_LEN32,?..."
|
|
bitfld.long 0x00 16.--18. "CH_LEN,Channel length in number of bits: Note: - When this field is configured to '6' or '7' the length is set to 32-bit (same as '5')" "0: BIT_LEN8,1: BIT_LEN16,2: BIT_LEN18,3: BIT_LEN20,4: BIT_LEN24,5: BIT_LEN32,?..."
|
|
newline
|
|
bitfld.long 0x00 13. "WD_EN,Set watchdog for 'tx_ws_in': '0': Disabled" "0,1"
|
|
bitfld.long 0x00 12. "OVHDATA,Set overhead value: '0': Set to '0' '1': Set to '1' (Note: This bit is connected to AR38U12.TX_CFG.TX_OVHDATA)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "WS_PULSE,Set WS pulse width in TDM mode: (Note: This bit is connected to AR38U12.TX_CFG.TX_WS_PULSE) Note: When not TDM mode must be '1'" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x00 8.--9. "I2S_MODE,Select I2S left-justified or TDM: (Note: These bits are connected to AR38U12.TX_CFG.TX_I2S_MODE)" "0: LEFT_JUSTIFIED,1: I2S mode,2: TDM mode A the 1st Channel align to WSO..,3: TDM mode B the 1st Channel align to WSO.."
|
|
newline
|
|
bitfld.long 0x00 7. "MS,Set interface in master or slave mode: (Note: This bit is connected to AR38U12.TX_CFG.TX_MS)" "0: SLAVE,1: MASTER"
|
|
bitfld.long 0x00 4.--6. "CH_NR,Specifies number of channels per frame: Note: only '2channels' is supported during Left Justfied or I2S mode" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x00 3. "B_CLOCK_INV,Serial data transmission is advanced by 0.5 SCK cycles" "0: SDO transmitted at SCK falling edge when..,1: SDO transmitted at SCK rising edge when.."
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TX_WATCHDOG,Transmitter watchdog"
|
|
hexmask.long 0x00 0.--31. 1. "WD_COUNTER,Start value of the TX watchdog"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RX_CTL,Receiver control"
|
|
bitfld.long 0x00 25. "SCKI_POL,RX slave bit clock polarity" "0,1"
|
|
bitfld.long 0x00 24. "SCKO_POL,RX master bit clock polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "BIT_EXTENSION,When reception word length is shorter than the word length of RX_FIFO_RD extension mode of upper bit should be set" "0,1"
|
|
bitfld.long 0x00 20.--22. "WORD_LEN,Word length in number of bits: Note: - When this field is configured to '6' or '7' the length is set to 32-bit (same as '5')" "0: BIT_LEN8,1: BIT_LEN16,2: BIT_LEN18,3: BIT_LEN20,4: BIT_LEN24,5: BIT_LEN32,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--18. "CH_LEN,Channel length in number of bits: Note: - When this field is configured to '6' or '7' the length is set to 32-bit (same as '5')" "0: BIT_LEN8,1: BIT_LEN16,2: BIT_LEN18,3: BIT_LEN20,4: BIT_LEN24,5: BIT_LEN32,?..."
|
|
bitfld.long 0x00 13. "WD_EN,Set watchdog for 'rx_ws_in' '0': Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "WS_PULSE,Set WS pulse width in TDM mode: (Note: This bit is connected to AR38U12.RX_CFG.RX_WS_PULSE) Note: When not TDM mode must be '1'" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x00 8.--9. "I2S_MODE,Select I2S left-justified or TDM: (Note: These bits are connected to AR38U12.RX_CFG.RX_I2S_MODE)" "0: LEFT_JUSTIFIED,1: I2S mode,2: TDM mode A the 1st Channel align to WSO..,3: TDM mode B the 1st Channel align to WSO.."
|
|
newline
|
|
bitfld.long 0x00 7. "MS,Set interface in master or slave mode: (Note: This bit is connected to AR38U12.TX_CFG.RX_MS)" "0: SLAVE,1: MASTER"
|
|
bitfld.long 0x00 4.--6. "CH_NR,Specifies number of channels per frame: Note: only '2channels' is supported during Left Justfied or I2S mode" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x00 3. "B_CLOCK_INV,Serial data capture is delayed by 0.5 SCK cycles" "0: SDI received at SCK rising edge when..,1: SDI received at SCK falling edge when.."
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RX_WATCHDOG,Receiver watchdog"
|
|
hexmask.long 0x00 0.--31. 1. "WD_COUNTER,Start value of the RX watchdog"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TX_FIFO_CTL,TX FIFO control"
|
|
bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the TX FIFO do not remove FIFO entries" "0,1"
|
|
bitfld.long 0x00 16. "CLEAR,When '1' the TX FIFO and TX_BUF are cleared/invalidated" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "TX_FIFO_STATUS,TX FIFO status"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,TX FIFO write pointer: FIFO location at which a new data frame is written by the host"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "USED,Number of entries in the TX FIFO"
|
|
wgroup.long 0x208++0x03
|
|
line.long 0x00 "TX_FIFO_WR,TX FIFO"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Data written into the TX FIFO"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "RX_FIFO_CTL,RX FIFO control"
|
|
bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the RX FIFO have no effect" "0,1"
|
|
bitfld.long 0x00 16. "CLEAR,When '1' the RX FIFO and RX_BUF are cleared/invalidated" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "RX_FIFO_STATUS,RX FIFO status"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,RX FIFO read pointer: FIFO location from which a data frame is read by the host"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "USED,Number of entries in the RX FIFO"
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "RX_FIFO_RD,RX FIFO"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Data read from the RX FIFO"
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "RX_FIFO_RD_SILENT,RX FIFO silent"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Data read from the RX FIFO"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "INTR,Interrupt register"
|
|
bitfld.long 0x00 24. "RX_WD,Triggers (sets to '1') when the Rx watchdog event occurs" "0,1"
|
|
bitfld.long 0x00 22. "RX_UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RX_OVERFLOW,Attempt to write to a full RX FIFO" "0,1"
|
|
bitfld.long 0x00 19. "RX_FULL,RX FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "RX_NOT_EMPTY,RX FIFO is not empty" "0,1"
|
|
bitfld.long 0x00 16. "RX_TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TX_WD,Triggers (sets to '1') when the Tx watchdog event occurs" "0,1"
|
|
bitfld.long 0x00 6. "TX_UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TX_OVERFLOW,Attempt to write to a full TX FIFO" "0,1"
|
|
bitfld.long 0x00 4. "TX_EMPTY,TX FIFO is empty i.e" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TX_NOT_FULL,TX FIFO is not full" "0,1"
|
|
bitfld.long 0x00 0. "TX_TRIGGER,Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL" "0,1"
|
|
group.long 0xF04++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x00 24. "RX_WD,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 22. "RX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 19. "RX_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "RX_NOT_EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 16. "RX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TX_WD,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 6. "TX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 4. "TX_EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TX_NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 0. "TX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long 0xF08++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 24. "RX_WD,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 22. "RX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RX_OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 19. "RX_FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "RX_NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 16. "RX_TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TX_WD,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 6. "TX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TX_OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 4. "TX_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TX_NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 0. "TX_TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long 0xF0C++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x00 24. "RX_WD,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 22. "RX_UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RX_OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 19. "RX_FULL,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "RX_NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 16. "RX_TRIGGER,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TX_WD,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 6. "TX_UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TX_OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 4. "TX_EMPTY,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TX_NOT_FULL,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 0. "TX_TRIGGER,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "IPC (Interprocessor Communication)"
|
|
base ad:0x40220000
|
|
repeat 8. (increment 0 1)(increment 0 0x20)
|
|
tree "STRUCT[$1]"
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "ACQUIRE,IPC acquire"
|
|
bitfld.long 0x00 31. "SUCCESS,Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired i.e" "0,1"
|
|
bitfld.long 0x00 8.--11. "MS,This field specifies the bus master identifier that successfully acquired the lock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "PC,This field specifies the protection context that successfully acquired the lock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. "NS,Secure/non-secure access control: '0': secure" "0,1"
|
|
bitfld.long 0x00 0. "P,User/privileged access control: '0': user mode" "0,1"
|
|
wgroup.long ($2+0x04)++0x03
|
|
line.long 0x00 "RELEASE,IPC release"
|
|
hexmask.long.word 0x00 0.--15. 1. "INTR_RELEASE,Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1')"
|
|
wgroup.long ($2+0x08)++0x03
|
|
line.long 0x00 "NOTIFY,IPC notification"
|
|
hexmask.long.word 0x00 0.--15. 1. "INTR_NOTIFY,This field allows for the generation of notification events to the IPC interrupt structures"
|
|
group.long ($2+0x0C)++0x03
|
|
line.long 0x00 "DATA0,IPC data 0"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure"
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "DATA1,IPC data 1"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure"
|
|
rgroup.long ($2+0x1C)++0x03
|
|
line.long 0x00 "LOCK_STATUS,IPC lock status"
|
|
bitfld.long 0x00 31. "ACQUIRED,Specifies if the lock is acquired" "0,1"
|
|
bitfld.long 0x00 8.--11. "MS,This field specifies the bus master identifier that successfully acquired the lock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "PC,This field specifies the protection context that successfully acquired the lock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. "NS,This field specifies the secure/non-secure access control: '0': secure" "0,1"
|
|
bitfld.long 0x00 0. "P,This field specifies the user/privileged access control: '0': user mode" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (increment 0 1)(increment 0 0x1020)
|
|
tree "INTR_STRUCT[$1]"
|
|
group.long ($2+0x1000)++0x03
|
|
line.long 0x00 "INTR,Interrupt"
|
|
hexmask.long.word 0x00 16.--31. 1. "NOTIFY,These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELEASE,These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected"
|
|
group.long ($2+0x1004)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set"
|
|
hexmask.long.word 0x00 16.--31. 1. "NOTIFY,SW writes a '1' to this field to set the corresponding field in the INTR register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELEASE,SW writes a '1' to this field to set the corresponding field in the INTR register"
|
|
group.long ($2+0x1008)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask"
|
|
hexmask.long.word 0x00 16.--31. 1. "NOTIFY,Mask bit for corresponding field in the INTR register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELEASE,Mask bit for corresponding field in the INTR register"
|
|
rgroup.long ($2+0x100C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked"
|
|
hexmask.long.word 0x00 16.--31. 1. "NOTIFY,Logical and of corresponding INTR and INTR_MASK fields"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELEASE,Logical and of corresponding request and mask bits"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LIN0"
|
|
base ad:0x40500000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ERROR_CTL,Error control"
|
|
bitfld.long 0x00 31. "ENABLED,Error injection enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 23. "TX_CHECKSUM_STOP_ERROR,The checksum field STOP bits are inverted to '0'" "0,1"
|
|
bitfld.long 0x00 22. "TX_CHECKSUM_ERROR,The checksum field is inverted" "0,1"
|
|
bitfld.long 0x00 21. "TX_DATA_STOP_ERROR,The data field STOP bits are inverted to '0'" "0,1"
|
|
bitfld.long 0x00 19. "TX_PID_STOP_ERROR,The PID field STOP bits are inverted to '0'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TX_PARITY_ERROR,In LIN mode the PID parity bit P[1] is inverted from !(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^ ID[1])" "0,1"
|
|
bitfld.long 0x00 17. "TX_SYNC_STOP_ERROR,The synchronization field STOP bits are inverted to '0'" "0,1"
|
|
bitfld.long 0x00 16. "TX_SYNC_ERROR,The synchronization field is changed from 0x55 to 0x00" "0,1"
|
|
bitfld.long 0x00 0.--4. "CH_IDX,Specifies the channel index of the channel to which HW injected channel transmitter errors applies" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TEST_CTL,Test control"
|
|
bitfld.long 0x00 31. "ENABLED,Test enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 16. "MODE,Test mode: '0': Partial disconnect from IOSS" "0,1"
|
|
bitfld.long 0x00 0.--4. "CH_IDX,Specifies the channel index of the channel to which test applies" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 20. (increment 0 1)(increment 0 0x100)
|
|
tree "CH[$1]"
|
|
group.long ($2+0x8000)++0x03
|
|
line.long 0x00 "CTL0,Control 0"
|
|
bitfld.long 0x00 31. "ENABLED,Channel enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 30. "FILTER_EN,RX filter (for 'lin_rx_in'): '0': No filter" "0,1"
|
|
bitfld.long 0x00 29. "PARITY_EN,Parity generation enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 28. "PARITY,Parity mode: '0': Even parity: even number of '1' bits (including parity)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "BIT_ERROR_IGNORE,Specifies behavior on a detected bit error during header or response transmission: '0': Message transfer is aborted" "0,1"
|
|
bitfld.long 0x00 24. "MODE,Mode of operation: '0': LIN mode" "0: LIN mode,1: UART mode"
|
|
bitfld.long 0x00 16.--20. "BREAK_WAKEUP_LENGTH,Break/wakeup length (minus 1) in bit periods: '0': 1 bit period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. "BREAK_DELIMITER_LENGTH,In LIN mode this field specifies the break delimiter length: (used in header transmission not used in header reception)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4. "AUTO_EN,LIN transceiver auto enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 0.--1. "STOP_BITS,STOP bit periods: '0': 1/2 bit period" "0,1,2,3"
|
|
group.long ($2+0x8004)++0x03
|
|
line.long 0x00 "CTL1,Control 1"
|
|
bitfld.long 0x00 24.--25. "FRAME_TIMEOUT_SEL,Specifies the frame timeout mode: '0': No timeout functionality (default value)" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FRAME_TIMEOUT,Specifies the maximum allowed length (timeout value) for a frame frame header or frame response in bit periods"
|
|
bitfld.long 0x00 8. "CHECKSUM_ENHANCED,Checksum mode: '0': Classic mode" "0,1"
|
|
bitfld.long 0x00 0.--2. "DATA_NR,Number of data fields (minus 1) in the response (not including the checksum): '0': 1 data field" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0x8008)++0x03
|
|
line.long 0x00 "STATUS,Status"
|
|
bitfld.long 0x00 28. "RX_RESPONSE_CHECKSUM_ERROR,Copy of INTR.RX_RESPONSE_CHECKSUM_ERROR" "0,1"
|
|
bitfld.long 0x00 27. "RX_RESPONSE_FRAME_ERROR,Copy of INTR.RX_RESPONSE_FRAME_ERROR" "0,1"
|
|
bitfld.long 0x00 26. "RX_HEADER_PARITY_ERROR,Copy of INTR.RX_HEADER_PARITY_ERROR" "0,1"
|
|
bitfld.long 0x00 25. "RX_HEADER_SYNC_ERROR,Copy of INTR.RX_HEADER_SYNC_ERROR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RX_HEADER_FRAME_ERROR,Copy of INTR.RX_HEADER_FRAME_ERROR" "0,1"
|
|
bitfld.long 0x00 17. "TX_RESPONSE_BIT_ERROR,Copy of INTR.TX_RESPONSE_BIT_ERROR" "0,1"
|
|
bitfld.long 0x00 16. "TX_HEADER_BIT_ERROR,Copy of INTR.TX_HEADER_BIT_ERROR" "0,1"
|
|
bitfld.long 0x00 13. "RX_DONE,Receiver done: - Set to '0' on the start of a new command" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "TX_DONE,Transmitter done: - Set to '0' on the start of a new command" "0,1"
|
|
bitfld.long 0x00 9. "RX_BUSY,Receiver busy" "0,1"
|
|
bitfld.long 0x00 8. "TX_BUSY,Transmitter busy" "0,1"
|
|
bitfld.long 0x00 5. "RX_DATA0_FRAME_ERROR,Frame response first data field frame error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "HEADER_RESPONSE,Frame header / response identifier (only valid when TX_BUSY or RX_BUSY is '1'): '0': Frame header being transferred" "0,1"
|
|
bitfld.long 0x00 0.--3. "DATA_IDX,Number of transferred data and checksum fields in the response (also acts as an index/address into response data field and checksum field registers (DATA0 DATA1 PID_CHECKSUM)) : '0': No data fields transferred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long ($2+0x8010)++0x03
|
|
line.long 0x00 "CMD,Command"
|
|
bitfld.long 0x00 9. "RX_RESPONSE,SW sets this field to '1' to receive a response" "0,1"
|
|
bitfld.long 0x00 8. "RX_HEADER,SW sets this field to '1' to receive a header" "0,1"
|
|
bitfld.long 0x00 2. "TX_WAKEUP,SW sets this field to '1' to transmit a wakeup signal" "0,1"
|
|
bitfld.long 0x00 1. "TX_RESPONSE,SW sets this field to '1' to transmit a response" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TX_HEADER,SW sets this field to '1' to transmit a header" "0,1"
|
|
group.long ($2+0x8060)++0x03
|
|
line.long 0x00 "TX_RX_STATUS,TX/RX status"
|
|
bitfld.long 0x00 26. "EN_OUT,LIN transceiver enable ('en_out' 'lin_en_out')" "0,1"
|
|
rbitfld.long 0x00 24. "TX_OUT,LIN transmitter output ('tx_out' 'lin_tx_out')" "0,1"
|
|
rbitfld.long 0x00 17. "RX_IN,LIN receiver input ('rx_in' 'lin_rx_in' in functional mode)" "0,1"
|
|
rbitfld.long 0x00 16. "TX_IN,LIN transmitter input ('tx_in' 'lin_tx_in' in functional mode)" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "SYNC_COUNTER,Synchronization counter in LIN channel clock periods"
|
|
group.long ($2+0x8080)++0x03
|
|
line.long 0x00 "PID_CHECKSUM,PID and checksum"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CHECKSUM,Checksum"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PID,Header protected identifier (PID)"
|
|
group.long ($2+0x8084)++0x03
|
|
line.long 0x00 "DATA0,Response data 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA4,Data field 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA3,Data field 3"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA2,Data field 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA1,Data field 1"
|
|
group.long ($2+0x8088)++0x03
|
|
line.long 0x00 "DATA1,Response data 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA8,Data field 8"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA7,Data field 7"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA6,Data field 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA5,Data field 5"
|
|
group.long ($2+0x80C0)++0x03
|
|
line.long 0x00 "INTR,Interrupt"
|
|
bitfld.long 0x00 28. "RX_RESPONSE_CHECKSUM_ERROR,HW sets this field to '1' when the calculated checksum over the received PID and data fields is not the same as the received checksum" "0,1"
|
|
bitfld.long 0x00 27. "RX_RESPONSE_FRAME_ERROR,HW sets this field to '1' when the received START or STOP bits have an unexpected value (during response reception)" "0,1"
|
|
bitfld.long 0x00 26. "RX_HEADER_PARITY_ERROR,HW sets this field to '1' when the received PID field has a parity error" "0,1"
|
|
bitfld.long 0x00 25. "RX_HEADER_SYNC_ERROR,HW sets this field to '1' when the received synchronization field is not received within the synchronization counter range [106 152] (see TX_RX_STATUS.SYNC_COUNTER)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RX_HEADER_FRAME_ERROR,HW sets this field to '1' when the received START or STOP bits have an unexpected value (during header reception)" "0,1"
|
|
bitfld.long 0x00 17. "TX_RESPONSE_BIT_ERROR,HW sets this field to '1' when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during response transmission)" "0,1"
|
|
bitfld.long 0x00 16. "TX_HEADER_BIT_ERROR,HW sets this field to '1' when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during header transmission)" "0,1"
|
|
bitfld.long 0x00 14. "TIMEOUT,HW sets this field to '1' when a frame frame header or frame response timeout is detected (per CTL.FRAME_TIMEOUT_SEL)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "RX_NOISE_DETECT,HW sets this field to '1' when isolated '0' or '1' 'in_rx_in' values are observed or when during sampling the last three 'lin_rx_in' values do NOT all have the same value" "0,1"
|
|
bitfld.long 0x00 11. "RX_HEADER_SYNC_DONE,HW sets this field to '1' when a synchronization field is received (including trailing STOP bits)" "0,1"
|
|
bitfld.long 0x00 10. "RX_BREAK_WAKEUP_DONE,HW sets this field to '1' when a break or wakeup signal is received (per CTL.BREAK_WAKEUP_LENGTH)" "0,1"
|
|
bitfld.long 0x00 9. "RX_RESPONSE_DONE,HW sets this field to '1' when a frame response (data fields and checksum field) is received (the CMD.RX_RESPONSE is completed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RX_HEADER_DONE,HW sets this field to '1' when a frame header (break field synchronization field and PID field) is received (the CMD.RX_HEADER is completed)" "0,1"
|
|
bitfld.long 0x00 2. "TX_WAKEUP_DONE,HW sets this field to '1' when a wakeup signal is transmitted (per CTL.BREAK_WAKEUP_LENGTH)" "0,1"
|
|
bitfld.long 0x00 1. "TX_RESPONSE_DONE,HW sets this field to '1' when a frame response (data fields and checksum field) is transmitted (the CMD.TX_RESPONSE is completed)" "0,1"
|
|
bitfld.long 0x00 0. "TX_HEADER_DONE,HW sets this field to '1' when a frame header (break field synchronization field and PID field) is transmitted (the CMD.TX_HEADER is completed)" "0,1"
|
|
group.long ($2+0x80C4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x00 28. "RX_RESPONSE_CHECKSUM_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 27. "RX_RESPONSE_FRAME_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 26. "RX_HEADER_PARITY_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 25. "RX_HEADER_SYNC_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RX_HEADER_FRAME_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 17. "TX_RESPONSE_BIT_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 16. "TX_HEADER_BIT_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 14. "TIMEOUT,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "RX_NOISE_DETECT,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 11. "RX_HEADER_SYNC_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 10. "RX_BREAK_WAKEUP_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 9. "RX_RESPONSE_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RX_HEADER_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 2. "TX_WAKEUP_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 1. "TX_RESPONSE_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
bitfld.long 0x00 0. "TX_HEADER_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" "0,1"
|
|
group.long ($2+0x80C8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x00 28. "RX_RESPONSE_CHECKSUM_ERROR,Mask for corresponding field in INTR register" "0,1"
|
|
bitfld.long 0x00 27. "RX_RESPONSE_FRAME_ERROR,Mask for corresponding field in INTR register" "0,1"
|
|
bitfld.long 0x00 26. "RX_HEADER_PARITY_ERROR,Mask for corresponding field in INTR register" "0,1"
|
|
bitfld.long 0x00 25. "RX_HEADER_SYNC_ERROR,Mask for corresponding field in INTR register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RX_HEADER_FRAME_ERROR,Mask for corresponding field in INTR register" "0,1"
|
|
bitfld.long 0x00 17. "TX_RESPONSE_BIT_ERROR,Mask for corresponding field in INTR register" "0,1"
|
|
bitfld.long 0x00 16. "TX_HEADER_BIT_ERROR,Mask for corresponding field in INTR register" "0,1"
|
|
bitfld.long 0x00 14. "TIMEOUT,Mask for corresponding field in INTR register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "RX_NOISE_DETECT,Mask for corresponding field in INTR register" "0,1"
|
|
bitfld.long 0x00 11. "RX_HEADER_SYNC_DONE,Mask for corresponding field in INTR register" "0,1"
|
|
bitfld.long 0x00 10. "RX_BREAK_WAKEUP_DONE,Mask for corresponding field in INTR register" "0,1"
|
|
bitfld.long 0x00 9. "RX_RESPONSE_DONE,Mask for corresponding field in INTR register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RX_HEADER_DONE,Mask for corresponding field in INTR register" "0,1"
|
|
bitfld.long 0x00 2. "TX_WAKEUP_DONE,Mask for corresponding field in INTR register" "0,1"
|
|
bitfld.long 0x00 1. "TX_RESPONSE_DONE,Mask for corresponding field in INTR register" "0,1"
|
|
bitfld.long 0x00 0. "TX_HEADER_DONE,Mask for corresponding field in INTR register" "0,1"
|
|
rgroup.long ($2+0x80CC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x00 28. "RX_RESPONSE_CHECKSUM_ERROR,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
bitfld.long 0x00 27. "RX_RESPONSE_FRAME_ERROR,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
bitfld.long 0x00 26. "RX_HEADER_PARITY_ERROR,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
bitfld.long 0x00 25. "RX_HEADER_SYNC_ERROR,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RX_HEADER_FRAME_ERROR,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
bitfld.long 0x00 17. "TX_RESPONSE_BIT_ERROR,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
bitfld.long 0x00 16. "TX_HEADER_BIT_ERROR,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
bitfld.long 0x00 14. "TIMEOUT,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "RX_NOISE_DETECT,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
bitfld.long 0x00 11. "RX_HEADER_SYNC_DONE,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
bitfld.long 0x00 10. "RX_BREAK_WAKEUP_DONE,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
bitfld.long 0x00 9. "RX_RESPONSE_DONE,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RX_HEADER_DONE,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
bitfld.long 0x00 2. "TX_WAKEUP_DONE,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
bitfld.long 0x00 1. "TX_RESPONSE_DONE,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
bitfld.long 0x00 0. "TX_HEADER_DONE,Logical AND of corresponding INTR and INTR_MASK fields" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PASS0 (Programmable Analog Subsystem)"
|
|
base ad:0x40900000
|
|
repeat 3. (increment 0 1)(increment 0 0x1000)
|
|
tree "SAR[$1]"
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "CTL,Analog control register"
|
|
bitfld.long 0x00 31. "ENABLED," "0: SAR IP disabled (put analog in power,1: SAR IP enabled"
|
|
bitfld.long 0x00 30. "ADC_EN,Enable the SAR ADC and SAR sequencer (only valid if ENABLED=1)" "0: SARADC and SARSEQ are disabled (put SARADC,1: SAR ADC and SARSEQ are enabled"
|
|
newline
|
|
bitfld.long 0x00 29. "SARMUX_EN,Enable the SARMUX (only valid if ENABLED=1)" "0: SARMUX disabled (put analog in power down),1: SARMUX enabled"
|
|
bitfld.long 0x00 10. "HALF_LSB,When set take an extra cycle to convert the half LSB and add it to 12-bit result for Missing Code Recovery This bit should always be set to '1'" "0: disable half LSB conversion (not recommended),1: enable half LSB conversion"
|
|
newline
|
|
bitfld.long 0x00 9. "MSB_STRETCH,When set use 2 cycles for the Most Significant Bit (MSB)" "0: Use 1 clock cycle for MSB,1: Use 2 clock cycles for MSB"
|
|
bitfld.long 0x00 8. "IDLE_PWRDWN,When idle automatically power down the analog" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PWRUP_TIME,Number cycles to wait to power up after IDLE_PWRDWN"
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "DIAG_CTL,Diagnostic Reference control register"
|
|
bitfld.long 0x00 31. "DIAG_EN,Diagnostic Reference enable (only valid if ENABLED=1)" "0: Diagnostic Reference disabled (powered down,1: Diagnostic Reference enabled output signal"
|
|
bitfld.long 0x00 0.--3. "DIAG_SEL,Select Diagnostic Reference function" "0: DiagOut = VrefL,1: DiagOut = VrefH * 1/8,2: DiagOut = VrefH * 2/8,3: DiagOut = VrefH * 3/8,4: DiagOut = VrefH * 4/8,5: DiagOut = VrefH * 5/8,6: DiagOut = VrefH * 6/8,7: DiagOut = VrefH * 7/8,8: DiagOut = VrefH,9: DiagOut = VrefX = VrefH * 199/200,10: DiagOut = Vbg from SRSS,11: DiagOut = Vin1,12: DiagOut = Vin2,13: DiagOut = Vin3,14: DiagOut = Isource (10uA),15: DiagOut = Isink (10uA)"
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "PRECOND_CTL,Preconditioning control register"
|
|
bitfld.long 0x00 0.--3. "PRECOND_TIME,Number ADC clock cycles that Preconditioning is done before the sample window starts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "ANA_CAL,Current analog calibration values"
|
|
bitfld.long 0x00 16.--20. "AGAIN,Analog gain correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AOFFSET,Analog offset correction"
|
|
group.long ($2+0x84)++0x03
|
|
line.long 0x00 "DIG_CAL,Current digital calibration values"
|
|
bitfld.long 0x00 16.--21. "DGAIN,Digital gain correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--11. 1. "DOFFSET,Digital offset correction Subtract DOFFSET from ADC output"
|
|
group.long ($2+0x90)++0x03
|
|
line.long 0x00 "ANA_CAL_ALT,Alternate analog calibration values"
|
|
bitfld.long 0x00 16.--20. "AGAIN,See corresponding ANA_CAL field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AOFFSET,See corresponding ANA_CAL field"
|
|
group.long ($2+0x94)++0x03
|
|
line.long 0x00 "DIG_CAL_ALT,Alternate digital calibration values"
|
|
bitfld.long 0x00 16.--21. "DGAIN,See corresponding DIG_CAL field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--11. 1. "DOFFSET,See corresponding DIG_CAL field"
|
|
group.long ($2+0x98)++0x03
|
|
line.long 0x00 "CAL_UPD_CMD,Calibration update command"
|
|
bitfld.long 0x00 0. "UPDATE,Calibration update command: coherently copy values from alternate calibration regs to current calibration regs" "0,1"
|
|
rgroup.long ($2+0x100)++0x03
|
|
line.long 0x00 "TR_PEND,Trigger pending status"
|
|
hexmask.long 0x00 0.--31. 1. "TR_PEND,Trigger Pending"
|
|
rgroup.long ($2+0x180)++0x03
|
|
line.long 0x00 "WORK_VALID,Channel working data register 'valid' bits"
|
|
hexmask.long 0x00 0.--31. 1. "WORK_VALID,If set the corresponding WORK register is valid i.e"
|
|
rgroup.long ($2+0x184)++0x03
|
|
line.long 0x00 "WORK_RANGE,Range detected"
|
|
hexmask.long 0x00 0.--31. 1. "RANGE,N/A"
|
|
rgroup.long ($2+0x188)++0x03
|
|
line.long 0x00 "WORK_RANGE_HI,Range detect above Hi flag"
|
|
hexmask.long 0x00 0.--31. 1. "ABOVE_HI,Out of range was detected and the value was above the Hi threshold"
|
|
rgroup.long ($2+0x18C)++0x03
|
|
line.long 0x00 "WORK_PULSE,Pulse detected"
|
|
hexmask.long 0x00 0.--31. 1. "PULSE,N/A"
|
|
rgroup.long ($2+0x1A0)++0x03
|
|
line.long 0x00 "RESULT_VALID,Channel result data register 'valid' bits"
|
|
hexmask.long 0x00 0.--31. 1. "RESULT_VALID,If set the corresponding RESULT register is valid i.e"
|
|
rgroup.long ($2+0x1A4)++0x03
|
|
line.long 0x00 "RESULT_RANGE_HI,Channel Range above Hi flags"
|
|
hexmask.long 0x00 0.--31. 1. "ABOVE_HI,Out of range was detected and the value was above the Hi threshold"
|
|
rgroup.long ($2+0x200)++0x03
|
|
line.long 0x00 "STATUS,Current status of internal SAR registers (mostly for debug)"
|
|
bitfld.long 0x00 31. "BUSY,If high then the SAR is busy with a conversion" "0,1"
|
|
bitfld.long 0x00 30. "PWRUP_BUSY,If high then the SAR is waiting for PWRUP_TIME due to IDLE_PWRDWN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "DBG_FREEZE,If high then the SAR is prevented from starting a new acquisition see DBG_FREEZE_EN" "0,1"
|
|
bitfld.long 0x00 12.--13. "CUR_PREEMPT_TYPE,Preempting type of current group/channel only valid if BUSY" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "CUR_PRIO,priority of current group/channel only valid if BUSY" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "CUR_CHAN,current channel being acquired only valid if BUSY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long ($2+0x204)++0x03
|
|
line.long 0x00 "AVG_STAT,Current averaging status (for debug)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CUR_AVG_CNT,the current value of the averaging counter"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "CUR_AVG_ACCU,the current value of the averaging accumulator"
|
|
tree "CH[0]"
|
|
group.long ($2+0x800)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0x804)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0x808)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0x80C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0x810)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0x814)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x818)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x81C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0x820)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0x824)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
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bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0x828)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0x838)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0x83C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[1]"
|
|
group.long ($2+0x840)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0x844)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
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bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0x848)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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|
newline
|
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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|
group.long ($2+0x84C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0x850)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0x854)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x858)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x85C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0x860)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0x864)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0x868)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0x878)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0x87C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[2]"
|
|
group.long ($2+0x880)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0x884)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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newline
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bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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newline
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long ($2+0x888)++0x03
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line.long 0x00 "POST_CTL,Post processing control"
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|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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newline
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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newline
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
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newline
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
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newline
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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group.long ($2+0x88C)++0x03
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0x890)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
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group.long ($2+0x894)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x898)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x89C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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rgroup.long ($2+0x8A0)++0x03
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line.long 0x00 "WORK,Working data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
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newline
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bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
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newline
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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newline
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hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
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rgroup.long ($2+0x8A4)++0x03
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line.long 0x00 "RESULT,Result data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
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newline
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bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
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newline
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
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rgroup.long ($2+0x8A8)++0x03
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line.long 0x00 "GRP_STAT,Group status register"
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bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
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newline
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
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group.long ($2+0x8B8)++0x03
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line.long 0x00 "ENABLE,Enable register"
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bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
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group.long ($2+0x8BC)++0x03
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line.long 0x00 "TR_CMD,Software triggers"
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bitfld.long 0x00 0. "START,Software start trigger" "0,1"
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tree.end
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tree "CH[3]"
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group.long ($2+0x8C0)++0x03
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line.long 0x00 "TR_CTL,Trigger control"
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bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
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newline
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bitfld.long 0x00 11. "GROUP_END," "0,1"
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newline
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bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
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newline
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bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
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group.long ($2+0x8C4)++0x03
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line.long 0x00 "SAMPLE_CTL,Sample control"
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bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
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newline
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hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
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newline
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bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
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newline
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bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
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newline
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bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
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newline
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bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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newline
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bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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newline
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long ($2+0x8C8)++0x03
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line.long 0x00 "POST_CTL,Post processing control"
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bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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newline
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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newline
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
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newline
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
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newline
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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group.long ($2+0x8CC)++0x03
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0x8D0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
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group.long ($2+0x8D4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x8D8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x8DC)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0x8E0)++0x03
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line.long 0x00 "WORK,Working data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
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newline
|
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bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0x8E4)++0x03
|
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line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
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newline
|
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bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
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bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0x8E8)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
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newline
|
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
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newline
|
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bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0x8F8)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0x8FC)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[4]"
|
|
group.long ($2+0x900)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
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bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
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bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0x904)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
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|
newline
|
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bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
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bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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|
newline
|
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0x908)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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|
newline
|
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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newline
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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|
group.long ($2+0x90C)++0x03
|
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line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
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group.long ($2+0x910)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0x914)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x918)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x91C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0x920)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
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bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0x924)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0x928)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0x938)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0x93C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[5]"
|
|
group.long ($2+0x940)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0x944)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0x948)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0x94C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0x950)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0x954)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x958)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x95C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0x960)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0x964)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0x968)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0x978)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0x97C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[6]"
|
|
group.long ($2+0x980)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0x984)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0x988)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0x98C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0x990)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0x994)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x998)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x99C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0x9A0)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0x9A4)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0x9A8)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0x9B8)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0x9BC)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[7]"
|
|
group.long ($2+0x9C0)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0x9C4)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0x9C8)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0x9CC)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0x9D0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0x9D4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x9D8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x9DC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0x9E0)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0x9E4)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0x9E8)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0x9F8)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0x9FC)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[8]"
|
|
group.long ($2+0xA00)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
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bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xA04)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
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hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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|
newline
|
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xA08)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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|
newline
|
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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|
newline
|
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0xA0C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0xA10)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0xA14)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xA18)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xA1C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xA20)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xA24)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xA28)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xA38)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xA3C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[9]"
|
|
group.long ($2+0xA40)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xA44)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xA48)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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|
newline
|
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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|
group.long ($2+0xA4C)++0x03
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0xA50)++0x03
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line.long 0x00 "INTR,Interrupt request register"
|
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
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group.long ($2+0xA54)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
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newline
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
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group.long ($2+0xA58)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0xA5C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
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bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
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newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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rgroup.long ($2+0xA60)++0x03
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line.long 0x00 "WORK,Working data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
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newline
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bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
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newline
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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newline
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hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
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rgroup.long ($2+0xA64)++0x03
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line.long 0x00 "RESULT,Result data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
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bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
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newline
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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newline
|
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hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
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rgroup.long ($2+0xA68)++0x03
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line.long 0x00 "GRP_STAT,Group status register"
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bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
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newline
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
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newline
|
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bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
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newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
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group.long ($2+0xA78)++0x03
|
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line.long 0x00 "ENABLE,Enable register"
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bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
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|
group.long ($2+0xA7C)++0x03
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line.long 0x00 "TR_CMD,Software triggers"
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bitfld.long 0x00 0. "START,Software start trigger" "0,1"
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tree.end
|
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tree "CH[10]"
|
|
group.long ($2+0xA80)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
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bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
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newline
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bitfld.long 0x00 11. "GROUP_END," "0,1"
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newline
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bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
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newline
|
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bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
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group.long ($2+0xA84)++0x03
|
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line.long 0x00 "SAMPLE_CTL,Sample control"
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bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
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newline
|
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hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
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newline
|
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bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
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newline
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bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
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newline
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bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
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newline
|
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bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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newline
|
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bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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newline
|
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long ($2+0xA88)++0x03
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line.long 0x00 "POST_CTL,Post processing control"
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|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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newline
|
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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newline
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
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|
newline
|
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
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newline
|
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
|
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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group.long ($2+0xA8C)++0x03
|
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
|
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
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group.long ($2+0xA90)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
|
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
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newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
|
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
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group.long ($2+0xA94)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xA98)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xA9C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xAA0)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xAA4)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xAA8)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xAB8)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xABC)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[11]"
|
|
group.long ($2+0xAC0)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
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bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
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group.long ($2+0xAC4)++0x03
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line.long 0x00 "SAMPLE_CTL,Sample control"
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bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
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newline
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hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
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newline
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bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
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newline
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bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
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newline
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bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
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newline
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bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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newline
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bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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newline
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long ($2+0xAC8)++0x03
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line.long 0x00 "POST_CTL,Post processing control"
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bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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newline
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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newline
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
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newline
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
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newline
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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group.long ($2+0xACC)++0x03
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0xAD0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
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group.long ($2+0xAD4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0xAD8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0xADC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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rgroup.long ($2+0xAE0)++0x03
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line.long 0x00 "WORK,Working data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
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newline
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bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
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newline
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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newline
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hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
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rgroup.long ($2+0xAE4)++0x03
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line.long 0x00 "RESULT,Result data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
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newline
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bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
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newline
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
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rgroup.long ($2+0xAE8)++0x03
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line.long 0x00 "GRP_STAT,Group status register"
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bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
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newline
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
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group.long ($2+0xAF8)++0x03
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line.long 0x00 "ENABLE,Enable register"
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bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
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group.long ($2+0xAFC)++0x03
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line.long 0x00 "TR_CMD,Software triggers"
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bitfld.long 0x00 0. "START,Software start trigger" "0,1"
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tree.end
|
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tree "CH[12]"
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group.long ($2+0xB00)++0x03
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line.long 0x00 "TR_CTL,Trigger control"
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bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
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newline
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bitfld.long 0x00 11. "GROUP_END," "0,1"
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newline
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bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
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newline
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bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
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group.long ($2+0xB04)++0x03
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line.long 0x00 "SAMPLE_CTL,Sample control"
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bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
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newline
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hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
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newline
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bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
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newline
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bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
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newline
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bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
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newline
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bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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newline
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bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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newline
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long ($2+0xB08)++0x03
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line.long 0x00 "POST_CTL,Post processing control"
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bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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newline
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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newline
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
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newline
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
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newline
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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group.long ($2+0xB0C)++0x03
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0xB10)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
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group.long ($2+0xB14)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
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newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0xB18)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xB1C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
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bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
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rgroup.long ($2+0xB20)++0x03
|
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line.long 0x00 "WORK,Working data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
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newline
|
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
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bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xB24)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
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bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xB28)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xB38)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xB3C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[13]"
|
|
group.long ($2+0xB40)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
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|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
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|
newline
|
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bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xB44)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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|
newline
|
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xB48)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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|
newline
|
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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|
newline
|
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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|
newline
|
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0xB4C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0xB50)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0xB54)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xB58)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xB5C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xB60)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xB64)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xB68)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xB78)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xB7C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[14]"
|
|
group.long ($2+0xB80)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xB84)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xB88)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0xB8C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0xB90)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0xB94)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xB98)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xB9C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xBA0)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xBA4)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xBA8)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xBB8)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xBBC)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[15]"
|
|
group.long ($2+0xBC0)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xBC4)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xBC8)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0xBCC)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0xBD0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0xBD4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xBD8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xBDC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xBE0)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xBE4)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xBE8)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xBF8)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xBFC)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[16]"
|
|
group.long ($2+0xC00)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xC04)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xC08)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0xC0C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0xC10)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0xC14)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xC18)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xC1C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xC20)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xC24)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
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bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xC28)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
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group.long ($2+0xC38)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xC3C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
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|
tree.end
|
|
tree "CH[17]"
|
|
group.long ($2+0xC40)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
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bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
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bitfld.long 0x00 11. "GROUP_END," "0,1"
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|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
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|
newline
|
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bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xC44)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
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hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
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|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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|
newline
|
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long ($2+0xC48)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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|
newline
|
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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|
newline
|
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0xC4C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0xC50)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0xC54)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xC58)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xC5C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xC60)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xC64)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xC68)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xC78)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xC7C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[18]"
|
|
group.long ($2+0xC80)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xC84)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long ($2+0xC88)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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newline
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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newline
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
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|
newline
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
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newline
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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|
group.long ($2+0xC8C)++0x03
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0xC90)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
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group.long ($2+0xC94)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0xC98)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0xC9C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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rgroup.long ($2+0xCA0)++0x03
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line.long 0x00 "WORK,Working data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
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newline
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bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
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newline
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
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rgroup.long ($2+0xCA4)++0x03
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line.long 0x00 "RESULT,Result data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
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newline
|
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bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
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|
newline
|
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
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rgroup.long ($2+0xCA8)++0x03
|
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line.long 0x00 "GRP_STAT,Group status register"
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bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
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newline
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
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newline
|
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bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
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newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
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newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
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newline
|
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bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
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group.long ($2+0xCB8)++0x03
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line.long 0x00 "ENABLE,Enable register"
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bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
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|
group.long ($2+0xCBC)++0x03
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line.long 0x00 "TR_CMD,Software triggers"
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bitfld.long 0x00 0. "START,Software start trigger" "0,1"
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tree.end
|
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tree "CH[19]"
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group.long ($2+0xCC0)++0x03
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line.long 0x00 "TR_CTL,Trigger control"
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bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
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newline
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bitfld.long 0x00 11. "GROUP_END," "0,1"
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newline
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bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
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newline
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bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
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group.long ($2+0xCC4)++0x03
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line.long 0x00 "SAMPLE_CTL,Sample control"
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bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
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newline
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hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
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newline
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bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
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newline
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bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
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newline
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bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
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newline
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bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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newline
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bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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newline
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long ($2+0xCC8)++0x03
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line.long 0x00 "POST_CTL,Post processing control"
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bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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newline
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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newline
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
|
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
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newline
|
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
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newline
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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group.long ($2+0xCCC)++0x03
|
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
|
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0xCD0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
|
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
|
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
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group.long ($2+0xCD4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xCD8)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xCDC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xCE0)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xCE4)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xCE8)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xCF8)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xCFC)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[20]"
|
|
group.long ($2+0xD00)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
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|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
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newline
|
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bitfld.long 0x00 11. "GROUP_END," "0,1"
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|
newline
|
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bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
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|
newline
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bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
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group.long ($2+0xD04)++0x03
|
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line.long 0x00 "SAMPLE_CTL,Sample control"
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bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
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hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
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|
newline
|
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bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
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|
newline
|
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bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
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newline
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bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
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newline
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bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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newline
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bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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newline
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long ($2+0xD08)++0x03
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line.long 0x00 "POST_CTL,Post processing control"
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|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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newline
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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newline
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
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newline
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
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newline
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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group.long ($2+0xD0C)++0x03
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0xD10)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
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group.long ($2+0xD14)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0xD18)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0xD1C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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|
newline
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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rgroup.long ($2+0xD20)++0x03
|
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line.long 0x00 "WORK,Working data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
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newline
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bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
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newline
|
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
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rgroup.long ($2+0xD24)++0x03
|
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line.long 0x00 "RESULT,Result data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
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newline
|
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bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
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|
newline
|
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
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rgroup.long ($2+0xD28)++0x03
|
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line.long 0x00 "GRP_STAT,Group status register"
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bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
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newline
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
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newline
|
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bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
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newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
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newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
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newline
|
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bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
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group.long ($2+0xD38)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
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bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xD3C)++0x03
|
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line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
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tree.end
|
|
tree "CH[21]"
|
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group.long ($2+0xD40)++0x03
|
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line.long 0x00 "TR_CTL,Trigger control"
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bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
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newline
|
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bitfld.long 0x00 11. "GROUP_END," "0,1"
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|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
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|
newline
|
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bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
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group.long ($2+0xD44)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
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|
newline
|
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hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
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bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
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bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
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|
newline
|
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bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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|
newline
|
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bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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newline
|
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long ($2+0xD48)++0x03
|
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line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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|
newline
|
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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|
newline
|
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
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|
newline
|
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
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|
newline
|
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
|
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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|
group.long ($2+0xD4C)++0x03
|
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
|
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0xD50)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
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group.long ($2+0xD54)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xD58)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xD5C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xD60)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xD64)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xD68)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xD78)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xD7C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[22]"
|
|
group.long ($2+0xD80)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xD84)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
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|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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newline
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long ($2+0xD88)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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|
newline
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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|
newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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|
group.long ($2+0xD8C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0xD90)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0xD94)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xD98)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xD9C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xDA0)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xDA4)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xDA8)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xDB8)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xDBC)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[23]"
|
|
group.long ($2+0xDC0)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xDC4)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xDC8)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0xDCC)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0xDD0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0xDD4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xDD8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xDDC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xDE0)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xDE4)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xDE8)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xDF8)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xDFC)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[24]"
|
|
group.long ($2+0xE00)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xE04)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xE08)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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|
newline
|
|
bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0xE0C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0xE10)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0xE14)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xE18)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xE1C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xE20)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xE24)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xE28)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xE38)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xE3C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[25]"
|
|
group.long ($2+0xE40)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xE44)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xE48)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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|
group.long ($2+0xE4C)++0x03
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0xE50)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
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group.long ($2+0xE54)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0xE58)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0xE5C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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rgroup.long ($2+0xE60)++0x03
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line.long 0x00 "WORK,Working data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
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newline
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bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
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newline
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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newline
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hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
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rgroup.long ($2+0xE64)++0x03
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line.long 0x00 "RESULT,Result data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
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newline
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bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
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newline
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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|
newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
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rgroup.long ($2+0xE68)++0x03
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line.long 0x00 "GRP_STAT,Group status register"
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bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
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newline
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
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group.long ($2+0xE78)++0x03
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line.long 0x00 "ENABLE,Enable register"
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bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xE7C)++0x03
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line.long 0x00 "TR_CMD,Software triggers"
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|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
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tree.end
|
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tree "CH[26]"
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|
group.long ($2+0xE80)++0x03
|
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line.long 0x00 "TR_CTL,Trigger control"
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bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
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newline
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bitfld.long 0x00 11. "GROUP_END," "0,1"
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newline
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bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
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newline
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bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
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group.long ($2+0xE84)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
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bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
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newline
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hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
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newline
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bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
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newline
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bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
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newline
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bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
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newline
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bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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newline
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bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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newline
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long ($2+0xE88)++0x03
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line.long 0x00 "POST_CTL,Post processing control"
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bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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newline
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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newline
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
|
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
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newline
|
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
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newline
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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group.long ($2+0xE8C)++0x03
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0xE90)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
|
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
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group.long ($2+0xE94)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xE98)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
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newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
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rgroup.long ($2+0xE9C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
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rgroup.long ($2+0xEA0)++0x03
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line.long 0x00 "WORK,Working data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
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|
newline
|
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
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bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xEA4)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xEA8)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xEB8)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xEBC)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[27]"
|
|
group.long ($2+0xEC0)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
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newline
|
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bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
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bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
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|
group.long ($2+0xEC4)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
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|
newline
|
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hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
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|
newline
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bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
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newline
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bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
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newline
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bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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newline
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bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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newline
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long ($2+0xEC8)++0x03
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line.long 0x00 "POST_CTL,Post processing control"
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bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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newline
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
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newline
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
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newline
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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group.long ($2+0xECC)++0x03
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0xED0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
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group.long ($2+0xED4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0xED8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0xEDC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
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rgroup.long ($2+0xEE0)++0x03
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line.long 0x00 "WORK,Working data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
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newline
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bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
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newline
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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newline
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hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
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rgroup.long ($2+0xEE4)++0x03
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line.long 0x00 "RESULT,Result data register"
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
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newline
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bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
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newline
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bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
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newline
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
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rgroup.long ($2+0xEE8)++0x03
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line.long 0x00 "GRP_STAT,Group status register"
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bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
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newline
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
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group.long ($2+0xEF8)++0x03
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line.long 0x00 "ENABLE,Enable register"
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bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
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group.long ($2+0xEFC)++0x03
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line.long 0x00 "TR_CMD,Software triggers"
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bitfld.long 0x00 0. "START,Software start trigger" "0,1"
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tree.end
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tree "CH[28]"
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group.long ($2+0xF00)++0x03
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line.long 0x00 "TR_CTL,Trigger control"
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bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
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newline
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bitfld.long 0x00 11. "GROUP_END," "0,1"
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newline
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bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
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newline
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bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
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group.long ($2+0xF04)++0x03
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line.long 0x00 "SAMPLE_CTL,Sample control"
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bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
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newline
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hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
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newline
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bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
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newline
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bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
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newline
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bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
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newline
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bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
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newline
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bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
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newline
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bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long ($2+0xF08)++0x03
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line.long 0x00 "POST_CTL,Post processing control"
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bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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newline
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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newline
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bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
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newline
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bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
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newline
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bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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newline
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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group.long ($2+0xF0C)++0x03
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line.long 0x00 "RANGE_CTL,Range thresholds"
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hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
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group.long ($2+0xF10)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
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newline
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
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newline
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bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
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newline
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bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
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newline
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bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
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newline
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
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group.long ($2+0xF14)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
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newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0xF18)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
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rgroup.long ($2+0xF1C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
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bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
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newline
|
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bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xF20)++0x03
|
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line.long 0x00 "WORK,Working data register"
|
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
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newline
|
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bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
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bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xF24)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
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bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
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newline
|
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bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
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newline
|
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bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
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bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xF28)++0x03
|
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line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
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newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xF38)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xF3C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[29]"
|
|
group.long ($2+0xF40)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xF44)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xF48)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
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|
newline
|
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bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
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|
newline
|
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bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
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|
group.long ($2+0xF4C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0xF50)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0xF54)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xF58)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xF5C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xF60)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xF64)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xF68)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xF78)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xF7C)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[30]"
|
|
group.long ($2+0xF80)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xF84)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xF88)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0xF8C)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0xF90)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0xF94)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xF98)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xF9C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xFA0)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xFA4)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xFA8)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xFB8)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xFBC)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree "CH[31]"
|
|
group.long ($2+0xFC0)++0x03
|
|
line.long 0x00 "TR_CTL,Trigger control"
|
|
bitfld.long 0x00 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output Also see POST_CTL.TR_DONE_GRP_VIO" "0: tr_ch_done generates a 2 cycle pulse..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x00 11. "GROUP_END," "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PRIO,Channel priority: '0': highest priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first..,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: GENERIC1,4: GENERIC2,5: GENERIC3,6: GENERIC4,7: Always triggered (also called idle) can only.."
|
|
group.long ($2+0xFC4)++0x03
|
|
line.long 0x00 "SAMPLE_CTL,Sample control"
|
|
bitfld.long 0x00 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values" "0: use regular calibration values (ANA/DIG_CAL),1: use alternate calibration values.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used" "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PRECOND_MODE,Select preconditioning mode" "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output.."
|
|
newline
|
|
bitfld.long 0x00 11. "EXT_MUX_EN,External analog mux enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "EXT_MUX_SEL,External analog mux select" "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PORT_ADDR,Select the physical port" "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0..,2: ADC0 uses SARMUX2 (only valid for ADC0..,3: ADC0 uses SARMUX3 (only valid for ADC0.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PIN_ADDR,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long ($2+0xFC8)++0x03
|
|
line.long 0x00 "POST_CTL,Post processing control"
|
|
bitfld.long 0x00 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels Also see TR_CTL.DONE_LEVEL" "0: Default,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value Averaging Count for channels that have averaging enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SIGN_EXT,Output data is sign extended" "0: Default,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x00 6. "LEFT_ALIGN,Left or right align data in result[15:0]" "0: the data is right aligned in result[11:0] with,1: the data is left aligned in result[15:4] with"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: RSVD0,6: RSVD1,7: RSVD2"
|
|
group.long ($2+0xFCC)++0x03
|
|
line.long 0x00 "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0x00 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
group.long ($2+0xFD0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done" "0,1"
|
|
group.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xFD8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xFDC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits" "0,1"
|
|
rgroup.long ($2+0xFE0)++0x03
|
|
line.long 0x00 "WORK,Working data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
|
|
rgroup.long ($2+0xFE4)++0x03
|
|
line.long 0x00 "RESULT,Result data register"
|
|
bitfld.long 0x00 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
|
|
rgroup.long ($2+0xFE8)++0x03
|
|
line.long 0x00 "GRP_STAT,Group status register"
|
|
bitfld.long 0x00 16. "GRP_BUSY,Group acquisition busy" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CH_OVERFLOW,Channel Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH_PULSE_COMPLETE,Channel Pulse complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CH_RANGE_COMPLETE,Channel Range complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GRP_OVERFLOW,Group Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "GRP_CANCELLED,Group Cancelled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GRP_COMPLETE,Group acquisition complete" "0,1"
|
|
group.long ($2+0xFF8)++0x03
|
|
line.long 0x00 "ENABLE,Enable register"
|
|
bitfld.long 0x00 0. "CHAN_EN,Channel enable" "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
group.long ($2+0xFFC)++0x03
|
|
line.long 0x00 "TR_CMD,Software triggers"
|
|
bitfld.long 0x00 0. "START,Software start trigger" "0,1"
|
|
tree.end
|
|
tree.end
|
|
repeat.end
|
|
tree "EPASS_MMIO"
|
|
group.long 0xF0000++0x03
|
|
line.long 0x00 "PASS_CTL,PASS control register"
|
|
bitfld.long 0x00 28.--31. "DBG_FREEZE_EN,Debug pause enable 1 per ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21.--22. "REFBUF_MODE,Reference mode" "0: No reference,1: Reference = buffered Vbg from SRSS,2: undefined,3: Reference = unbuffered Vbg from SRSS"
|
|
newline
|
|
bitfld.long 0x00 5. "SUPPLY_MON_LVL_B,Supply monitor level select for AMUXBUS_B" "0: amuxbus_b_mon = VRL,1: amuxbus_b_mon = VRH"
|
|
bitfld.long 0x00 4. "SUPPLY_MON_EN_B,Supply monitor enable for AMUXBUS_B (amuxbus_b_mon)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SUPPLY_MON_LVL_A,Supply monitor level select for AMUXBUS_A" "0: amuxbus_a_mon = VRL,1: amuxbus_a_mon = VRH"
|
|
bitfld.long 0x00 0. "SUPPLY_MON_EN_A,Supply monitor enable for AMUXBUS_A (amuxbus_a_mon)" "0,1"
|
|
repeat 4. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0xF0020)++0x03
|
|
line.long 0x00 "SAR_TR_IN_SEL[$1],per SAR generic input trigger select $1"
|
|
bitfld.long 0x00 16.--19. "IN4_SEL,Select generic trigger for SAR generic trigger input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "IN3_SEL,Select generic trigger for SAR generic trigger input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "IN2_SEL,Select generic trigger for SAR generic trigger input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "IN1_SEL,Select generic trigger for SAR generic trigger input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "IN0_SEL,Select generic trigger for SAR generic trigger input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
repeat 4. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0xF0040)++0x03
|
|
line.long 0x00 "SAR_TR_OUT_SEL[$1],per SAR generic output trigger select $1"
|
|
bitfld.long 0x00 8.--13. "OUT1_SEL,Select SAR output trigger for generic trigger output 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "OUT0_SEL,Select SAR output trigger for generic trigger output 0 0-31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0xF0080++0x03
|
|
line.long 0x00 "TEST_CTL,Test control bits"
|
|
bitfld.long 0x00 12. "TS_CAL_SPARE,Spare" "0,1"
|
|
bitfld.long 0x00 8.--9. "TS_CAL_CUR_SEL,Select the current going into the BJT for Temperature Sensor Calibration" "0: Select 1 uA,1: Select 2 uA,2: Select 5 uA,3: Select 10 uA"
|
|
newline
|
|
bitfld.long 0x00 6. "TS_CAL_VI_SEL,Select current or voltage output on 'v_temp' pin for Temperature Sensor Calibration" "0: Current is selected,1: Voltage is selected"
|
|
bitfld.long 0x00 5. "TS_CAL_DIODE_PNP_EN,Enable signal for PNP transistor" "0: Turn PNP off,1: Configure PNP as a diode (short"
|
|
newline
|
|
bitfld.long 0x00 4. "TS_CAL_DIODE_EN,Diode Enable disconnect or connect the base and collector terminal of the BJT" "0,1"
|
|
bitfld.long 0x00 3. "TS_CAL_VE_OUT,Voltage Emitter switch control for Temperature Sensor Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TS_CAL_VB_OUT,Voltage Base switch control for Temperature Sensor Calibration" "0,1"
|
|
bitfld.long 0x00 0. "TS_CAL_CUR_IN,External current input switch control for Temperature Sensor Calibration" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "PERI (Peripheral Interconnect)"
|
|
base ad:0x40000000
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TIMEOUT_CTL,Timeout control"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMEOUT,This field specifies a number of clock cycles (clk_slow)"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "TR_CMD,Trigger command"
|
|
bitfld.long 0x00 31. "ACTIVATE,SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL TR_EDGE and OUT_SEL" "0,1"
|
|
bitfld.long 0x00 30. "OUT_SEL,Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer" "0,1"
|
|
bitfld.long 0x00 29. "TR_EDGE,Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8.--12. "GROUP_SEL,Specifies the trigger group: '0'-'15': trigger multiplexer groups" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies the activated trigger when ACTIVATE is '1'"
|
|
group.long 0x2000++0x03
|
|
line.long 0x00 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR"
|
|
bitfld.long 0x00 18. "ECC_INJ_EN,Enable error injection for PERI protection structure SRAM" "0,1"
|
|
bitfld.long 0x00 16. "ECC_EN,Enable ECC: '0': Disabled (on write ECC parity bits will not be correctly written)" "0,1"
|
|
hexmask.long.word 0x00 0.--10. 1. "WORD_ADDR,Specifies the word address where the parity is injected"
|
|
repeat 10. (increment 0 1)(increment 0 0x40)
|
|
tree "GR[$1]"
|
|
group.long ($2+0x4000)++0x03
|
|
line.long 0x00 "CLOCK_CTL,Clock control"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]')"
|
|
group.long ($2+0x4010)++0x03
|
|
line.long 0x00 "SL_CTL,Slave control"
|
|
bitfld.long 0x00 15. "ENABLED_15,N/A" "0,1"
|
|
bitfld.long 0x00 14. "ENABLED_14,N/A" "0,1"
|
|
bitfld.long 0x00 13. "ENABLED_13,N/A" "0,1"
|
|
bitfld.long 0x00 12. "ENABLED_12,N/A" "0,1"
|
|
bitfld.long 0x00 11. "ENABLED_11,N/A" "0,1"
|
|
bitfld.long 0x00 10. "ENABLED_10,N/A" "0,1"
|
|
bitfld.long 0x00 9. "ENABLED_9,N/A" "0,1"
|
|
bitfld.long 0x00 8. "ENABLED_8,N/A" "0,1"
|
|
bitfld.long 0x00 7. "ENABLED_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "ENABLED_6,N/A" "0,1"
|
|
bitfld.long 0x00 5. "ENABLED_5,N/A" "0,1"
|
|
bitfld.long 0x00 4. "ENABLED_4,N/A" "0,1"
|
|
bitfld.long 0x00 3. "ENABLED_3,N/A" "0,1"
|
|
bitfld.long 0x00 2. "ENABLED_2,Peripheral group slave 2 enable" "0,1"
|
|
bitfld.long 0x00 1. "ENABLED_1,Peripheral group slave 1 enable" "0,1"
|
|
bitfld.long 0x00 0. "ENABLED_0,Peripheral group slave 0 enable" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 13. (increment 0 1)(increment 0 0x4400)
|
|
tree "TR_GR[$1]"
|
|
group.long ($2+0x8000)++0x03
|
|
line.long 0x00 "TR_CTL[0],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8004)++0x03
|
|
line.long 0x00 "TR_CTL[1],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8008)++0x03
|
|
line.long 0x00 "TR_CTL[2],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x800C)++0x03
|
|
line.long 0x00 "TR_CTL[3],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8010)++0x03
|
|
line.long 0x00 "TR_CTL[4],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8014)++0x03
|
|
line.long 0x00 "TR_CTL[5],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8018)++0x03
|
|
line.long 0x00 "TR_CTL[6],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x801C)++0x03
|
|
line.long 0x00 "TR_CTL[7],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8020)++0x03
|
|
line.long 0x00 "TR_CTL[8],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8024)++0x03
|
|
line.long 0x00 "TR_CTL[9],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8028)++0x03
|
|
line.long 0x00 "TR_CTL[10],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x802C)++0x03
|
|
line.long 0x00 "TR_CTL[11],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8030)++0x03
|
|
line.long 0x00 "TR_CTL[12],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8034)++0x03
|
|
line.long 0x00 "TR_CTL[13],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8038)++0x03
|
|
line.long 0x00 "TR_CTL[14],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x803C)++0x03
|
|
line.long 0x00 "TR_CTL[15],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8040)++0x03
|
|
line.long 0x00 "TR_CTL[16],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8044)++0x03
|
|
line.long 0x00 "TR_CTL[17],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8048)++0x03
|
|
line.long 0x00 "TR_CTL[18],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x804C)++0x03
|
|
line.long 0x00 "TR_CTL[19],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8050)++0x03
|
|
line.long 0x00 "TR_CTL[20],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8054)++0x03
|
|
line.long 0x00 "TR_CTL[21],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8058)++0x03
|
|
line.long 0x00 "TR_CTL[22],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x805C)++0x03
|
|
line.long 0x00 "TR_CTL[23],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8060)++0x03
|
|
line.long 0x00 "TR_CTL[24],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8064)++0x03
|
|
line.long 0x00 "TR_CTL[25],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8068)++0x03
|
|
line.long 0x00 "TR_CTL[26],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x806C)++0x03
|
|
line.long 0x00 "TR_CTL[27],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8070)++0x03
|
|
line.long 0x00 "TR_CTL[28],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8074)++0x03
|
|
line.long 0x00 "TR_CTL[29],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8078)++0x03
|
|
line.long 0x00 "TR_CTL[30],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x807C)++0x03
|
|
line.long 0x00 "TR_CTL[31],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8080)++0x03
|
|
line.long 0x00 "TR_CTL[32],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8084)++0x03
|
|
line.long 0x00 "TR_CTL[33],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8088)++0x03
|
|
line.long 0x00 "TR_CTL[34],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x808C)++0x03
|
|
line.long 0x00 "TR_CTL[35],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8090)++0x03
|
|
line.long 0x00 "TR_CTL[36],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8094)++0x03
|
|
line.long 0x00 "TR_CTL[37],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8098)++0x03
|
|
line.long 0x00 "TR_CTL[38],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x809C)++0x03
|
|
line.long 0x00 "TR_CTL[39],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80A0)++0x03
|
|
line.long 0x00 "TR_CTL[40],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80A4)++0x03
|
|
line.long 0x00 "TR_CTL[41],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80A8)++0x03
|
|
line.long 0x00 "TR_CTL[42],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80AC)++0x03
|
|
line.long 0x00 "TR_CTL[43],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80B0)++0x03
|
|
line.long 0x00 "TR_CTL[44],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80B4)++0x03
|
|
line.long 0x00 "TR_CTL[45],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80B8)++0x03
|
|
line.long 0x00 "TR_CTL[46],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80BC)++0x03
|
|
line.long 0x00 "TR_CTL[47],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80C0)++0x03
|
|
line.long 0x00 "TR_CTL[48],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80C4)++0x03
|
|
line.long 0x00 "TR_CTL[49],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80C8)++0x03
|
|
line.long 0x00 "TR_CTL[50],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80CC)++0x03
|
|
line.long 0x00 "TR_CTL[51],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80D0)++0x03
|
|
line.long 0x00 "TR_CTL[52],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80D4)++0x03
|
|
line.long 0x00 "TR_CTL[53],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80D8)++0x03
|
|
line.long 0x00 "TR_CTL[54],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80DC)++0x03
|
|
line.long 0x00 "TR_CTL[55],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80E0)++0x03
|
|
line.long 0x00 "TR_CTL[56],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80E4)++0x03
|
|
line.long 0x00 "TR_CTL[57],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80E8)++0x03
|
|
line.long 0x00 "TR_CTL[58],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80EC)++0x03
|
|
line.long 0x00 "TR_CTL[59],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80F0)++0x03
|
|
line.long 0x00 "TR_CTL[60],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80F4)++0x03
|
|
line.long 0x00 "TR_CTL[61],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80F8)++0x03
|
|
line.long 0x00 "TR_CTL[62],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x80FC)++0x03
|
|
line.long 0x00 "TR_CTL[63],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8100)++0x03
|
|
line.long 0x00 "TR_CTL[64],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8104)++0x03
|
|
line.long 0x00 "TR_CTL[65],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8108)++0x03
|
|
line.long 0x00 "TR_CTL[66],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x810C)++0x03
|
|
line.long 0x00 "TR_CTL[67],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8110)++0x03
|
|
line.long 0x00 "TR_CTL[68],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8114)++0x03
|
|
line.long 0x00 "TR_CTL[69],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8118)++0x03
|
|
line.long 0x00 "TR_CTL[70],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x811C)++0x03
|
|
line.long 0x00 "TR_CTL[71],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8120)++0x03
|
|
line.long 0x00 "TR_CTL[72],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8124)++0x03
|
|
line.long 0x00 "TR_CTL[73],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8128)++0x03
|
|
line.long 0x00 "TR_CTL[74],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x812C)++0x03
|
|
line.long 0x00 "TR_CTL[75],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8130)++0x03
|
|
line.long 0x00 "TR_CTL[76],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8134)++0x03
|
|
line.long 0x00 "TR_CTL[77],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8138)++0x03
|
|
line.long 0x00 "TR_CTL[78],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x813C)++0x03
|
|
line.long 0x00 "TR_CTL[79],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8140)++0x03
|
|
line.long 0x00 "TR_CTL[80],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8144)++0x03
|
|
line.long 0x00 "TR_CTL[81],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8148)++0x03
|
|
line.long 0x00 "TR_CTL[82],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x814C)++0x03
|
|
line.long 0x00 "TR_CTL[83],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8150)++0x03
|
|
line.long 0x00 "TR_CTL[84],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8154)++0x03
|
|
line.long 0x00 "TR_CTL[85],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8158)++0x03
|
|
line.long 0x00 "TR_CTL[86],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x815C)++0x03
|
|
line.long 0x00 "TR_CTL[87],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8160)++0x03
|
|
line.long 0x00 "TR_CTL[88],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8164)++0x03
|
|
line.long 0x00 "TR_CTL[89],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8168)++0x03
|
|
line.long 0x00 "TR_CTL[90],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x816C)++0x03
|
|
line.long 0x00 "TR_CTL[91],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8170)++0x03
|
|
line.long 0x00 "TR_CTL[92],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8174)++0x03
|
|
line.long 0x00 "TR_CTL[93],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8178)++0x03
|
|
line.long 0x00 "TR_CTL[94],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x817C)++0x03
|
|
line.long 0x00 "TR_CTL[95],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8180)++0x03
|
|
line.long 0x00 "TR_CTL[96],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8184)++0x03
|
|
line.long 0x00 "TR_CTL[97],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8188)++0x03
|
|
line.long 0x00 "TR_CTL[98],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x818C)++0x03
|
|
line.long 0x00 "TR_CTL[99],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8190)++0x03
|
|
line.long 0x00 "TR_CTL[100],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8194)++0x03
|
|
line.long 0x00 "TR_CTL[101],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8198)++0x03
|
|
line.long 0x00 "TR_CTL[102],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x819C)++0x03
|
|
line.long 0x00 "TR_CTL[103],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81A0)++0x03
|
|
line.long 0x00 "TR_CTL[104],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81A4)++0x03
|
|
line.long 0x00 "TR_CTL[105],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81A8)++0x03
|
|
line.long 0x00 "TR_CTL[106],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81AC)++0x03
|
|
line.long 0x00 "TR_CTL[107],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81B0)++0x03
|
|
line.long 0x00 "TR_CTL[108],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81B4)++0x03
|
|
line.long 0x00 "TR_CTL[109],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81B8)++0x03
|
|
line.long 0x00 "TR_CTL[110],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81BC)++0x03
|
|
line.long 0x00 "TR_CTL[111],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81C0)++0x03
|
|
line.long 0x00 "TR_CTL[112],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81C4)++0x03
|
|
line.long 0x00 "TR_CTL[113],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81C8)++0x03
|
|
line.long 0x00 "TR_CTL[114],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81CC)++0x03
|
|
line.long 0x00 "TR_CTL[115],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81D0)++0x03
|
|
line.long 0x00 "TR_CTL[116],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81D4)++0x03
|
|
line.long 0x00 "TR_CTL[117],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81D8)++0x03
|
|
line.long 0x00 "TR_CTL[118],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81DC)++0x03
|
|
line.long 0x00 "TR_CTL[119],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81E0)++0x03
|
|
line.long 0x00 "TR_CTL[120],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81E4)++0x03
|
|
line.long 0x00 "TR_CTL[121],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81E8)++0x03
|
|
line.long 0x00 "TR_CTL[122],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81EC)++0x03
|
|
line.long 0x00 "TR_CTL[123],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81F0)++0x03
|
|
line.long 0x00 "TR_CTL[124],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81F4)++0x03
|
|
line.long 0x00 "TR_CTL[125],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81F8)++0x03
|
|
line.long 0x00 "TR_CTL[126],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x81FC)++0x03
|
|
line.long 0x00 "TR_CTL[127],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8200)++0x03
|
|
line.long 0x00 "TR_CTL[128],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8204)++0x03
|
|
line.long 0x00 "TR_CTL[129],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8208)++0x03
|
|
line.long 0x00 "TR_CTL[130],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x820C)++0x03
|
|
line.long 0x00 "TR_CTL[131],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8210)++0x03
|
|
line.long 0x00 "TR_CTL[132],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8214)++0x03
|
|
line.long 0x00 "TR_CTL[133],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8218)++0x03
|
|
line.long 0x00 "TR_CTL[134],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x821C)++0x03
|
|
line.long 0x00 "TR_CTL[135],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8220)++0x03
|
|
line.long 0x00 "TR_CTL[136],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8224)++0x03
|
|
line.long 0x00 "TR_CTL[137],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8228)++0x03
|
|
line.long 0x00 "TR_CTL[138],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x822C)++0x03
|
|
line.long 0x00 "TR_CTL[139],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8230)++0x03
|
|
line.long 0x00 "TR_CTL[140],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8234)++0x03
|
|
line.long 0x00 "TR_CTL[141],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8238)++0x03
|
|
line.long 0x00 "TR_CTL[142],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x823C)++0x03
|
|
line.long 0x00 "TR_CTL[143],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8240)++0x03
|
|
line.long 0x00 "TR_CTL[144],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8244)++0x03
|
|
line.long 0x00 "TR_CTL[145],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8248)++0x03
|
|
line.long 0x00 "TR_CTL[146],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x824C)++0x03
|
|
line.long 0x00 "TR_CTL[147],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8250)++0x03
|
|
line.long 0x00 "TR_CTL[148],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8254)++0x03
|
|
line.long 0x00 "TR_CTL[149],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8258)++0x03
|
|
line.long 0x00 "TR_CTL[150],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x825C)++0x03
|
|
line.long 0x00 "TR_CTL[151],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8260)++0x03
|
|
line.long 0x00 "TR_CTL[152],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8264)++0x03
|
|
line.long 0x00 "TR_CTL[153],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8268)++0x03
|
|
line.long 0x00 "TR_CTL[154],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x826C)++0x03
|
|
line.long 0x00 "TR_CTL[155],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8270)++0x03
|
|
line.long 0x00 "TR_CTL[156],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8274)++0x03
|
|
line.long 0x00 "TR_CTL[157],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8278)++0x03
|
|
line.long 0x00 "TR_CTL[158],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x827C)++0x03
|
|
line.long 0x00 "TR_CTL[159],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8280)++0x03
|
|
line.long 0x00 "TR_CTL[160],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8284)++0x03
|
|
line.long 0x00 "TR_CTL[161],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8288)++0x03
|
|
line.long 0x00 "TR_CTL[162],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x828C)++0x03
|
|
line.long 0x00 "TR_CTL[163],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8290)++0x03
|
|
line.long 0x00 "TR_CTL[164],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8294)++0x03
|
|
line.long 0x00 "TR_CTL[165],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8298)++0x03
|
|
line.long 0x00 "TR_CTL[166],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x829C)++0x03
|
|
line.long 0x00 "TR_CTL[167],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82A0)++0x03
|
|
line.long 0x00 "TR_CTL[168],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82A4)++0x03
|
|
line.long 0x00 "TR_CTL[169],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82A8)++0x03
|
|
line.long 0x00 "TR_CTL[170],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82AC)++0x03
|
|
line.long 0x00 "TR_CTL[171],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82B0)++0x03
|
|
line.long 0x00 "TR_CTL[172],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82B4)++0x03
|
|
line.long 0x00 "TR_CTL[173],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82B8)++0x03
|
|
line.long 0x00 "TR_CTL[174],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82BC)++0x03
|
|
line.long 0x00 "TR_CTL[175],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82C0)++0x03
|
|
line.long 0x00 "TR_CTL[176],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82C4)++0x03
|
|
line.long 0x00 "TR_CTL[177],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82C8)++0x03
|
|
line.long 0x00 "TR_CTL[178],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82CC)++0x03
|
|
line.long 0x00 "TR_CTL[179],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82D0)++0x03
|
|
line.long 0x00 "TR_CTL[180],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82D4)++0x03
|
|
line.long 0x00 "TR_CTL[181],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82D8)++0x03
|
|
line.long 0x00 "TR_CTL[182],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82DC)++0x03
|
|
line.long 0x00 "TR_CTL[183],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82E0)++0x03
|
|
line.long 0x00 "TR_CTL[184],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82E4)++0x03
|
|
line.long 0x00 "TR_CTL[185],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82E8)++0x03
|
|
line.long 0x00 "TR_CTL[186],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82EC)++0x03
|
|
line.long 0x00 "TR_CTL[187],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82F0)++0x03
|
|
line.long 0x00 "TR_CTL[188],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82F4)++0x03
|
|
line.long 0x00 "TR_CTL[189],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82F8)++0x03
|
|
line.long 0x00 "TR_CTL[190],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x82FC)++0x03
|
|
line.long 0x00 "TR_CTL[191],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8300)++0x03
|
|
line.long 0x00 "TR_CTL[192],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8304)++0x03
|
|
line.long 0x00 "TR_CTL[193],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8308)++0x03
|
|
line.long 0x00 "TR_CTL[194],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x830C)++0x03
|
|
line.long 0x00 "TR_CTL[195],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8310)++0x03
|
|
line.long 0x00 "TR_CTL[196],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8314)++0x03
|
|
line.long 0x00 "TR_CTL[197],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8318)++0x03
|
|
line.long 0x00 "TR_CTL[198],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x831C)++0x03
|
|
line.long 0x00 "TR_CTL[199],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8320)++0x03
|
|
line.long 0x00 "TR_CTL[200],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8324)++0x03
|
|
line.long 0x00 "TR_CTL[201],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8328)++0x03
|
|
line.long 0x00 "TR_CTL[202],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x832C)++0x03
|
|
line.long 0x00 "TR_CTL[203],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8330)++0x03
|
|
line.long 0x00 "TR_CTL[204],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8334)++0x03
|
|
line.long 0x00 "TR_CTL[205],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8338)++0x03
|
|
line.long 0x00 "TR_CTL[206],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x833C)++0x03
|
|
line.long 0x00 "TR_CTL[207],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8340)++0x03
|
|
line.long 0x00 "TR_CTL[208],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8344)++0x03
|
|
line.long 0x00 "TR_CTL[209],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8348)++0x03
|
|
line.long 0x00 "TR_CTL[210],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x834C)++0x03
|
|
line.long 0x00 "TR_CTL[211],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8350)++0x03
|
|
line.long 0x00 "TR_CTL[212],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8354)++0x03
|
|
line.long 0x00 "TR_CTL[213],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8358)++0x03
|
|
line.long 0x00 "TR_CTL[214],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x835C)++0x03
|
|
line.long 0x00 "TR_CTL[215],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8360)++0x03
|
|
line.long 0x00 "TR_CTL[216],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8364)++0x03
|
|
line.long 0x00 "TR_CTL[217],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8368)++0x03
|
|
line.long 0x00 "TR_CTL[218],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x836C)++0x03
|
|
line.long 0x00 "TR_CTL[219],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8370)++0x03
|
|
line.long 0x00 "TR_CTL[220],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8374)++0x03
|
|
line.long 0x00 "TR_CTL[221],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8378)++0x03
|
|
line.long 0x00 "TR_CTL[222],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x837C)++0x03
|
|
line.long 0x00 "TR_CTL[223],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8380)++0x03
|
|
line.long 0x00 "TR_CTL[224],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8384)++0x03
|
|
line.long 0x00 "TR_CTL[225],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8388)++0x03
|
|
line.long 0x00 "TR_CTL[226],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x838C)++0x03
|
|
line.long 0x00 "TR_CTL[227],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8390)++0x03
|
|
line.long 0x00 "TR_CTL[228],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8394)++0x03
|
|
line.long 0x00 "TR_CTL[229],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x8398)++0x03
|
|
line.long 0x00 "TR_CTL[230],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x839C)++0x03
|
|
line.long 0x00 "TR_CTL[231],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83A0)++0x03
|
|
line.long 0x00 "TR_CTL[232],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83A4)++0x03
|
|
line.long 0x00 "TR_CTL[233],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83A8)++0x03
|
|
line.long 0x00 "TR_CTL[234],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83AC)++0x03
|
|
line.long 0x00 "TR_CTL[235],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83B0)++0x03
|
|
line.long 0x00 "TR_CTL[236],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83B4)++0x03
|
|
line.long 0x00 "TR_CTL[237],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83B8)++0x03
|
|
line.long 0x00 "TR_CTL[238],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83BC)++0x03
|
|
line.long 0x00 "TR_CTL[239],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83C0)++0x03
|
|
line.long 0x00 "TR_CTL[240],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83C4)++0x03
|
|
line.long 0x00 "TR_CTL[241],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83C8)++0x03
|
|
line.long 0x00 "TR_CTL[242],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83CC)++0x03
|
|
line.long 0x00 "TR_CTL[243],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83D0)++0x03
|
|
line.long 0x00 "TR_CTL[244],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83D4)++0x03
|
|
line.long 0x00 "TR_CTL[245],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83D8)++0x03
|
|
line.long 0x00 "TR_CTL[246],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83DC)++0x03
|
|
line.long 0x00 "TR_CTL[247],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83E0)++0x03
|
|
line.long 0x00 "TR_CTL[248],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83E4)++0x03
|
|
line.long 0x00 "TR_CTL[249],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83E8)++0x03
|
|
line.long 0x00 "TR_CTL[250],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83EC)++0x03
|
|
line.long 0x00 "TR_CTL[251],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83F0)++0x03
|
|
line.long 0x00 "TR_CTL[252],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83F4)++0x03
|
|
line.long 0x00 "TR_CTL[253],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83F8)++0x03
|
|
line.long 0x00 "TR_CTL[254],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
group.long ($2+0x83FC)++0x03
|
|
line.long 0x00 "TR_CTL[255],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TR_SEL,Specifies input trigger"
|
|
tree.end
|
|
repeat.end
|
|
repeat 14. (increment 0 1)(increment 0 0x8400)
|
|
tree "TR_1TO1_GR[$1]"
|
|
group.long ($2+0xC000)++0x03
|
|
line.long 0x00 "TR_CTL[0],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC004)++0x03
|
|
line.long 0x00 "TR_CTL[1],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC008)++0x03
|
|
line.long 0x00 "TR_CTL[2],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC00C)++0x03
|
|
line.long 0x00 "TR_CTL[3],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC010)++0x03
|
|
line.long 0x00 "TR_CTL[4],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC014)++0x03
|
|
line.long 0x00 "TR_CTL[5],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC018)++0x03
|
|
line.long 0x00 "TR_CTL[6],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC01C)++0x03
|
|
line.long 0x00 "TR_CTL[7],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC020)++0x03
|
|
line.long 0x00 "TR_CTL[8],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC024)++0x03
|
|
line.long 0x00 "TR_CTL[9],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC028)++0x03
|
|
line.long 0x00 "TR_CTL[10],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC02C)++0x03
|
|
line.long 0x00 "TR_CTL[11],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC030)++0x03
|
|
line.long 0x00 "TR_CTL[12],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC034)++0x03
|
|
line.long 0x00 "TR_CTL[13],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC038)++0x03
|
|
line.long 0x00 "TR_CTL[14],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC03C)++0x03
|
|
line.long 0x00 "TR_CTL[15],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC040)++0x03
|
|
line.long 0x00 "TR_CTL[16],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC044)++0x03
|
|
line.long 0x00 "TR_CTL[17],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC048)++0x03
|
|
line.long 0x00 "TR_CTL[18],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC04C)++0x03
|
|
line.long 0x00 "TR_CTL[19],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC050)++0x03
|
|
line.long 0x00 "TR_CTL[20],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC054)++0x03
|
|
line.long 0x00 "TR_CTL[21],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC058)++0x03
|
|
line.long 0x00 "TR_CTL[22],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC05C)++0x03
|
|
line.long 0x00 "TR_CTL[23],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC060)++0x03
|
|
line.long 0x00 "TR_CTL[24],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC064)++0x03
|
|
line.long 0x00 "TR_CTL[25],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC068)++0x03
|
|
line.long 0x00 "TR_CTL[26],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC06C)++0x03
|
|
line.long 0x00 "TR_CTL[27],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC070)++0x03
|
|
line.long 0x00 "TR_CTL[28],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC074)++0x03
|
|
line.long 0x00 "TR_CTL[29],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC078)++0x03
|
|
line.long 0x00 "TR_CTL[30],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC07C)++0x03
|
|
line.long 0x00 "TR_CTL[31],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC080)++0x03
|
|
line.long 0x00 "TR_CTL[32],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC084)++0x03
|
|
line.long 0x00 "TR_CTL[33],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC088)++0x03
|
|
line.long 0x00 "TR_CTL[34],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC08C)++0x03
|
|
line.long 0x00 "TR_CTL[35],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC090)++0x03
|
|
line.long 0x00 "TR_CTL[36],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC094)++0x03
|
|
line.long 0x00 "TR_CTL[37],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC098)++0x03
|
|
line.long 0x00 "TR_CTL[38],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC09C)++0x03
|
|
line.long 0x00 "TR_CTL[39],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0A0)++0x03
|
|
line.long 0x00 "TR_CTL[40],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0A4)++0x03
|
|
line.long 0x00 "TR_CTL[41],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0A8)++0x03
|
|
line.long 0x00 "TR_CTL[42],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0AC)++0x03
|
|
line.long 0x00 "TR_CTL[43],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0B0)++0x03
|
|
line.long 0x00 "TR_CTL[44],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0B4)++0x03
|
|
line.long 0x00 "TR_CTL[45],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0B8)++0x03
|
|
line.long 0x00 "TR_CTL[46],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0BC)++0x03
|
|
line.long 0x00 "TR_CTL[47],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0C0)++0x03
|
|
line.long 0x00 "TR_CTL[48],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0C4)++0x03
|
|
line.long 0x00 "TR_CTL[49],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0C8)++0x03
|
|
line.long 0x00 "TR_CTL[50],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0CC)++0x03
|
|
line.long 0x00 "TR_CTL[51],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0D0)++0x03
|
|
line.long 0x00 "TR_CTL[52],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0D4)++0x03
|
|
line.long 0x00 "TR_CTL[53],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0D8)++0x03
|
|
line.long 0x00 "TR_CTL[54],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0DC)++0x03
|
|
line.long 0x00 "TR_CTL[55],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0E0)++0x03
|
|
line.long 0x00 "TR_CTL[56],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0E4)++0x03
|
|
line.long 0x00 "TR_CTL[57],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0E8)++0x03
|
|
line.long 0x00 "TR_CTL[58],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0EC)++0x03
|
|
line.long 0x00 "TR_CTL[59],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0F0)++0x03
|
|
line.long 0x00 "TR_CTL[60],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0F4)++0x03
|
|
line.long 0x00 "TR_CTL[61],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0F8)++0x03
|
|
line.long 0x00 "TR_CTL[62],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC0FC)++0x03
|
|
line.long 0x00 "TR_CTL[63],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC100)++0x03
|
|
line.long 0x00 "TR_CTL[64],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC104)++0x03
|
|
line.long 0x00 "TR_CTL[65],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC108)++0x03
|
|
line.long 0x00 "TR_CTL[66],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC10C)++0x03
|
|
line.long 0x00 "TR_CTL[67],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC110)++0x03
|
|
line.long 0x00 "TR_CTL[68],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC114)++0x03
|
|
line.long 0x00 "TR_CTL[69],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC118)++0x03
|
|
line.long 0x00 "TR_CTL[70],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC11C)++0x03
|
|
line.long 0x00 "TR_CTL[71],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC120)++0x03
|
|
line.long 0x00 "TR_CTL[72],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC124)++0x03
|
|
line.long 0x00 "TR_CTL[73],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC128)++0x03
|
|
line.long 0x00 "TR_CTL[74],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC12C)++0x03
|
|
line.long 0x00 "TR_CTL[75],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC130)++0x03
|
|
line.long 0x00 "TR_CTL[76],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC134)++0x03
|
|
line.long 0x00 "TR_CTL[77],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC138)++0x03
|
|
line.long 0x00 "TR_CTL[78],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC13C)++0x03
|
|
line.long 0x00 "TR_CTL[79],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC140)++0x03
|
|
line.long 0x00 "TR_CTL[80],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC144)++0x03
|
|
line.long 0x00 "TR_CTL[81],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC148)++0x03
|
|
line.long 0x00 "TR_CTL[82],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC14C)++0x03
|
|
line.long 0x00 "TR_CTL[83],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC150)++0x03
|
|
line.long 0x00 "TR_CTL[84],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC154)++0x03
|
|
line.long 0x00 "TR_CTL[85],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC158)++0x03
|
|
line.long 0x00 "TR_CTL[86],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC15C)++0x03
|
|
line.long 0x00 "TR_CTL[87],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC160)++0x03
|
|
line.long 0x00 "TR_CTL[88],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC164)++0x03
|
|
line.long 0x00 "TR_CTL[89],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC168)++0x03
|
|
line.long 0x00 "TR_CTL[90],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC16C)++0x03
|
|
line.long 0x00 "TR_CTL[91],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC170)++0x03
|
|
line.long 0x00 "TR_CTL[92],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC174)++0x03
|
|
line.long 0x00 "TR_CTL[93],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC178)++0x03
|
|
line.long 0x00 "TR_CTL[94],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC17C)++0x03
|
|
line.long 0x00 "TR_CTL[95],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC180)++0x03
|
|
line.long 0x00 "TR_CTL[96],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC184)++0x03
|
|
line.long 0x00 "TR_CTL[97],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC188)++0x03
|
|
line.long 0x00 "TR_CTL[98],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC18C)++0x03
|
|
line.long 0x00 "TR_CTL[99],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC190)++0x03
|
|
line.long 0x00 "TR_CTL[100],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC194)++0x03
|
|
line.long 0x00 "TR_CTL[101],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC198)++0x03
|
|
line.long 0x00 "TR_CTL[102],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC19C)++0x03
|
|
line.long 0x00 "TR_CTL[103],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1A0)++0x03
|
|
line.long 0x00 "TR_CTL[104],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1A4)++0x03
|
|
line.long 0x00 "TR_CTL[105],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1A8)++0x03
|
|
line.long 0x00 "TR_CTL[106],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1AC)++0x03
|
|
line.long 0x00 "TR_CTL[107],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1B0)++0x03
|
|
line.long 0x00 "TR_CTL[108],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1B4)++0x03
|
|
line.long 0x00 "TR_CTL[109],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1B8)++0x03
|
|
line.long 0x00 "TR_CTL[110],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1BC)++0x03
|
|
line.long 0x00 "TR_CTL[111],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1C0)++0x03
|
|
line.long 0x00 "TR_CTL[112],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1C4)++0x03
|
|
line.long 0x00 "TR_CTL[113],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1C8)++0x03
|
|
line.long 0x00 "TR_CTL[114],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1CC)++0x03
|
|
line.long 0x00 "TR_CTL[115],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1D0)++0x03
|
|
line.long 0x00 "TR_CTL[116],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1D4)++0x03
|
|
line.long 0x00 "TR_CTL[117],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1D8)++0x03
|
|
line.long 0x00 "TR_CTL[118],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1DC)++0x03
|
|
line.long 0x00 "TR_CTL[119],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1E0)++0x03
|
|
line.long 0x00 "TR_CTL[120],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1E4)++0x03
|
|
line.long 0x00 "TR_CTL[121],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1E8)++0x03
|
|
line.long 0x00 "TR_CTL[122],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1EC)++0x03
|
|
line.long 0x00 "TR_CTL[123],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1F0)++0x03
|
|
line.long 0x00 "TR_CTL[124],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1F4)++0x03
|
|
line.long 0x00 "TR_CTL[125],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1F8)++0x03
|
|
line.long 0x00 "TR_CTL[126],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC1FC)++0x03
|
|
line.long 0x00 "TR_CTL[127],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC200)++0x03
|
|
line.long 0x00 "TR_CTL[128],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC204)++0x03
|
|
line.long 0x00 "TR_CTL[129],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC208)++0x03
|
|
line.long 0x00 "TR_CTL[130],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC20C)++0x03
|
|
line.long 0x00 "TR_CTL[131],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC210)++0x03
|
|
line.long 0x00 "TR_CTL[132],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC214)++0x03
|
|
line.long 0x00 "TR_CTL[133],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC218)++0x03
|
|
line.long 0x00 "TR_CTL[134],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC21C)++0x03
|
|
line.long 0x00 "TR_CTL[135],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC220)++0x03
|
|
line.long 0x00 "TR_CTL[136],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC224)++0x03
|
|
line.long 0x00 "TR_CTL[137],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC228)++0x03
|
|
line.long 0x00 "TR_CTL[138],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC22C)++0x03
|
|
line.long 0x00 "TR_CTL[139],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC230)++0x03
|
|
line.long 0x00 "TR_CTL[140],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC234)++0x03
|
|
line.long 0x00 "TR_CTL[141],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC238)++0x03
|
|
line.long 0x00 "TR_CTL[142],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC23C)++0x03
|
|
line.long 0x00 "TR_CTL[143],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC240)++0x03
|
|
line.long 0x00 "TR_CTL[144],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC244)++0x03
|
|
line.long 0x00 "TR_CTL[145],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC248)++0x03
|
|
line.long 0x00 "TR_CTL[146],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC24C)++0x03
|
|
line.long 0x00 "TR_CTL[147],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC250)++0x03
|
|
line.long 0x00 "TR_CTL[148],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC254)++0x03
|
|
line.long 0x00 "TR_CTL[149],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC258)++0x03
|
|
line.long 0x00 "TR_CTL[150],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC25C)++0x03
|
|
line.long 0x00 "TR_CTL[151],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC260)++0x03
|
|
line.long 0x00 "TR_CTL[152],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC264)++0x03
|
|
line.long 0x00 "TR_CTL[153],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC268)++0x03
|
|
line.long 0x00 "TR_CTL[154],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC26C)++0x03
|
|
line.long 0x00 "TR_CTL[155],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC270)++0x03
|
|
line.long 0x00 "TR_CTL[156],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC274)++0x03
|
|
line.long 0x00 "TR_CTL[157],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC278)++0x03
|
|
line.long 0x00 "TR_CTL[158],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC27C)++0x03
|
|
line.long 0x00 "TR_CTL[159],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC280)++0x03
|
|
line.long 0x00 "TR_CTL[160],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC284)++0x03
|
|
line.long 0x00 "TR_CTL[161],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC288)++0x03
|
|
line.long 0x00 "TR_CTL[162],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC28C)++0x03
|
|
line.long 0x00 "TR_CTL[163],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC290)++0x03
|
|
line.long 0x00 "TR_CTL[164],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC294)++0x03
|
|
line.long 0x00 "TR_CTL[165],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC298)++0x03
|
|
line.long 0x00 "TR_CTL[166],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC29C)++0x03
|
|
line.long 0x00 "TR_CTL[167],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2A0)++0x03
|
|
line.long 0x00 "TR_CTL[168],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2A4)++0x03
|
|
line.long 0x00 "TR_CTL[169],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2A8)++0x03
|
|
line.long 0x00 "TR_CTL[170],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2AC)++0x03
|
|
line.long 0x00 "TR_CTL[171],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2B0)++0x03
|
|
line.long 0x00 "TR_CTL[172],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2B4)++0x03
|
|
line.long 0x00 "TR_CTL[173],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2B8)++0x03
|
|
line.long 0x00 "TR_CTL[174],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2BC)++0x03
|
|
line.long 0x00 "TR_CTL[175],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2C0)++0x03
|
|
line.long 0x00 "TR_CTL[176],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2C4)++0x03
|
|
line.long 0x00 "TR_CTL[177],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2C8)++0x03
|
|
line.long 0x00 "TR_CTL[178],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2CC)++0x03
|
|
line.long 0x00 "TR_CTL[179],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2D0)++0x03
|
|
line.long 0x00 "TR_CTL[180],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2D4)++0x03
|
|
line.long 0x00 "TR_CTL[181],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2D8)++0x03
|
|
line.long 0x00 "TR_CTL[182],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2DC)++0x03
|
|
line.long 0x00 "TR_CTL[183],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2E0)++0x03
|
|
line.long 0x00 "TR_CTL[184],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2E4)++0x03
|
|
line.long 0x00 "TR_CTL[185],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2E8)++0x03
|
|
line.long 0x00 "TR_CTL[186],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2EC)++0x03
|
|
line.long 0x00 "TR_CTL[187],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2F0)++0x03
|
|
line.long 0x00 "TR_CTL[188],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2F4)++0x03
|
|
line.long 0x00 "TR_CTL[189],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2F8)++0x03
|
|
line.long 0x00 "TR_CTL[190],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC2FC)++0x03
|
|
line.long 0x00 "TR_CTL[191],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC300)++0x03
|
|
line.long 0x00 "TR_CTL[192],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC304)++0x03
|
|
line.long 0x00 "TR_CTL[193],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC308)++0x03
|
|
line.long 0x00 "TR_CTL[194],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC30C)++0x03
|
|
line.long 0x00 "TR_CTL[195],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC310)++0x03
|
|
line.long 0x00 "TR_CTL[196],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC314)++0x03
|
|
line.long 0x00 "TR_CTL[197],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC318)++0x03
|
|
line.long 0x00 "TR_CTL[198],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC31C)++0x03
|
|
line.long 0x00 "TR_CTL[199],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC320)++0x03
|
|
line.long 0x00 "TR_CTL[200],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC324)++0x03
|
|
line.long 0x00 "TR_CTL[201],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC328)++0x03
|
|
line.long 0x00 "TR_CTL[202],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC32C)++0x03
|
|
line.long 0x00 "TR_CTL[203],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC330)++0x03
|
|
line.long 0x00 "TR_CTL[204],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC334)++0x03
|
|
line.long 0x00 "TR_CTL[205],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC338)++0x03
|
|
line.long 0x00 "TR_CTL[206],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC33C)++0x03
|
|
line.long 0x00 "TR_CTL[207],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC340)++0x03
|
|
line.long 0x00 "TR_CTL[208],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC344)++0x03
|
|
line.long 0x00 "TR_CTL[209],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC348)++0x03
|
|
line.long 0x00 "TR_CTL[210],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC34C)++0x03
|
|
line.long 0x00 "TR_CTL[211],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC350)++0x03
|
|
line.long 0x00 "TR_CTL[212],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC354)++0x03
|
|
line.long 0x00 "TR_CTL[213],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC358)++0x03
|
|
line.long 0x00 "TR_CTL[214],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC35C)++0x03
|
|
line.long 0x00 "TR_CTL[215],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC360)++0x03
|
|
line.long 0x00 "TR_CTL[216],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC364)++0x03
|
|
line.long 0x00 "TR_CTL[217],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC368)++0x03
|
|
line.long 0x00 "TR_CTL[218],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC36C)++0x03
|
|
line.long 0x00 "TR_CTL[219],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC370)++0x03
|
|
line.long 0x00 "TR_CTL[220],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC374)++0x03
|
|
line.long 0x00 "TR_CTL[221],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC378)++0x03
|
|
line.long 0x00 "TR_CTL[222],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC37C)++0x03
|
|
line.long 0x00 "TR_CTL[223],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC380)++0x03
|
|
line.long 0x00 "TR_CTL[224],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC384)++0x03
|
|
line.long 0x00 "TR_CTL[225],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC388)++0x03
|
|
line.long 0x00 "TR_CTL[226],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC38C)++0x03
|
|
line.long 0x00 "TR_CTL[227],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC390)++0x03
|
|
line.long 0x00 "TR_CTL[228],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC394)++0x03
|
|
line.long 0x00 "TR_CTL[229],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC398)++0x03
|
|
line.long 0x00 "TR_CTL[230],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC39C)++0x03
|
|
line.long 0x00 "TR_CTL[231],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3A0)++0x03
|
|
line.long 0x00 "TR_CTL[232],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3A4)++0x03
|
|
line.long 0x00 "TR_CTL[233],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3A8)++0x03
|
|
line.long 0x00 "TR_CTL[234],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3AC)++0x03
|
|
line.long 0x00 "TR_CTL[235],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3B0)++0x03
|
|
line.long 0x00 "TR_CTL[236],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3B4)++0x03
|
|
line.long 0x00 "TR_CTL[237],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3B8)++0x03
|
|
line.long 0x00 "TR_CTL[238],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3BC)++0x03
|
|
line.long 0x00 "TR_CTL[239],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3C0)++0x03
|
|
line.long 0x00 "TR_CTL[240],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3C4)++0x03
|
|
line.long 0x00 "TR_CTL[241],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3C8)++0x03
|
|
line.long 0x00 "TR_CTL[242],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3CC)++0x03
|
|
line.long 0x00 "TR_CTL[243],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3D0)++0x03
|
|
line.long 0x00 "TR_CTL[244],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3D4)++0x03
|
|
line.long 0x00 "TR_CTL[245],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3D8)++0x03
|
|
line.long 0x00 "TR_CTL[246],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3DC)++0x03
|
|
line.long 0x00 "TR_CTL[247],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3E0)++0x03
|
|
line.long 0x00 "TR_CTL[248],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3E4)++0x03
|
|
line.long 0x00 "TR_CTL[249],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3E8)++0x03
|
|
line.long 0x00 "TR_CTL[250],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3EC)++0x03
|
|
line.long 0x00 "TR_CTL[251],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3F0)++0x03
|
|
line.long 0x00 "TR_CTL[252],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3F4)++0x03
|
|
line.long 0x00 "TR_CTL[253],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3F8)++0x03
|
|
line.long 0x00 "TR_CTL[254],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
group.long ($2+0xC3FC)++0x03
|
|
line.long 0x00 "TR_CTL[255],Trigger control register"
|
|
bitfld.long 0x00 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode" "0,1"
|
|
bitfld.long 0x00 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger" "0,1"
|
|
bitfld.long 0x00 8. "TR_INV,Specifies if the output trigger is inverted" "0,1"
|
|
bitfld.long 0x00 0. "TR_SEL,Specifies input trigger: '0'': constant signal level '0'" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PERI_MS (Peripheral Interconnect Master Interface)"
|
|
base ad:0x40020000
|
|
repeat 16. (increment 0 1)(increment 0 0x40)
|
|
tree "PPU_PR[$1]"
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "SL_ADDR,Slave region base address"
|
|
hexmask.long 0x00 2.--31. 1. "ADDR30,This field specifies the base address of the slave region"
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "SL_SIZE,Slave region size"
|
|
bitfld.long 0x00 31. "VALID,Slave region enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the size of the slave region: '0': Undefined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x00 28. "PC3_NS,Protection context 3 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC3_PW,Protection context 3 privileged write enable" "0,1"
|
|
bitfld.long 0x00 26. "PC3_PR,Protection context 3 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC3_UW,Protection context 3 user write enable" "0,1"
|
|
bitfld.long 0x00 24. "PC3_UR,Protection context 3 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC2_NS,Protection context 2 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC2_PW,Protection context 2 privileged write enable" "0,1"
|
|
bitfld.long 0x00 18. "PC2_PR,Protection context 2 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC2_UW,Protection context 2 user write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PC2_UR,Protection context 2 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC1_NS,Protection context 1 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC1_PW,Protection context 1 privileged write enable" "0,1"
|
|
bitfld.long 0x00 10. "PC1_PR,Protection context 1 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC1_UW,Protection context 1 user write enable" "0,1"
|
|
bitfld.long 0x00 8. "PC1_UR,Protection context 1 user read enable" "0,1"
|
|
rbitfld.long 0x00 4. "PC0_NS,Protection context 0 non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 3. "PC0_PW,Protection context 0 privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 2. "PC0_PR,Protection context 0 privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "PC0_UW,Protection context 0 user write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 0. "PC0_UR,Protection context 0 user read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x00 28. "PC7_NS,Protection context 7 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC7_PW,Protection context 7 privileged write enable" "0,1"
|
|
bitfld.long 0x00 26. "PC7_PR,Protection context 7 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC7_UW,Protection context 7 user write enable" "0,1"
|
|
bitfld.long 0x00 24. "PC7_UR,Protection context 7 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC6_NS,Protection context 6 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC6_PW,Protection context 6 privileged write enable" "0,1"
|
|
bitfld.long 0x00 18. "PC6_PR,Protection context 6 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC6_UW,Protection context 6 user write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PC6_UR,Protection context 6 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC5_NS,Protection context 5 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC5_PW,Protection context 5 privileged write enable" "0,1"
|
|
bitfld.long 0x00 10. "PC5_PR,Protection context 5 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC5_UW,Protection context 5 user write enable" "0,1"
|
|
bitfld.long 0x00 8. "PC5_UR,Protection context 5 user read enable" "0,1"
|
|
bitfld.long 0x00 4. "PC4_NS,Protection context 4 non-secure" "0,1"
|
|
bitfld.long 0x00 3. "PC4_PW,Protection context 4 privileged write enable" "0,1"
|
|
bitfld.long 0x00 2. "PC4_PR,Protection context 4 privileged read enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC4_UW,Protection context 4 user write enable" "0,1"
|
|
bitfld.long 0x00 0. "PC4_UR,Protection context 4 user read enable" "0,1"
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x00 28. "PC11_NS,Protection context 11 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC11_PW,Protection context 11 privileged write enable" "0,1"
|
|
bitfld.long 0x00 26. "PC11_PR,Protection context 11 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC11_UW,Protection context 11 user write enable" "0,1"
|
|
bitfld.long 0x00 24. "PC11_UR,Protection context 11 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC10_NS,Protection context 10 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC10_PW,Protection context 10 privileged write enable" "0,1"
|
|
bitfld.long 0x00 18. "PC10_PR,Protection context 10 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC10_UW,Protection context 10 user write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PC10_UR,Protection context 10 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC9_NS,Protection context 9 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC9_PW,Protection context 9 privileged write enable" "0,1"
|
|
bitfld.long 0x00 10. "PC9_PR,Protection context 9 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC9_UW,Protection context 9 user write enable" "0,1"
|
|
bitfld.long 0x00 8. "PC9_UR,Protection context 9 user read enable" "0,1"
|
|
bitfld.long 0x00 4. "PC8_NS,Protection context 8 non-secure" "0,1"
|
|
bitfld.long 0x00 3. "PC8_PW,Protection context 8 privileged write enable" "0,1"
|
|
bitfld.long 0x00 2. "PC8_PR,Protection context 8 privileged read enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC8_UW,Protection context 8 user write enable" "0,1"
|
|
bitfld.long 0x00 0. "PC8_UR,Protection context 8 user read enable" "0,1"
|
|
group.long ($2+0x1C)++0x03
|
|
line.long 0x00 "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0x00 28. "PC15_NS,Protection context 15 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC15_PW,Protection context 15 privileged write enable" "0,1"
|
|
bitfld.long 0x00 26. "PC15_PR,Protection context 15 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC15_UW,Protection context 15 user write enable" "0,1"
|
|
bitfld.long 0x00 24. "PC15_UR,Protection context 15 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC14_NS,Protection context 14 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC14_PW,Protection context 14 privileged write enable" "0,1"
|
|
bitfld.long 0x00 18. "PC14_PR,Protection context 14 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC14_UW,Protection context 14 user write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PC14_UR,Protection context 14 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC13_NS,Protection context 13 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC13_PW,Protection context 13 privileged write enable" "0,1"
|
|
bitfld.long 0x00 10. "PC13_PR,Protection context 13 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC13_UW,Protection context 13 user write enable" "0,1"
|
|
bitfld.long 0x00 8. "PC13_UR,Protection context 13 user read enable" "0,1"
|
|
bitfld.long 0x00 4. "PC12_NS,Protection context 12 non-secure" "0,1"
|
|
bitfld.long 0x00 3. "PC12_PW,Protection context 12 privileged write enable" "0,1"
|
|
bitfld.long 0x00 2. "PC12_PR,Protection context 12 privileged read enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC12_UW,Protection context 12 user write enable" "0,1"
|
|
bitfld.long 0x00 0. "PC12_UR,Protection context 12 user read enable" "0,1"
|
|
rgroup.long ($2+0x20)++0x03
|
|
line.long 0x00 "MS_ADDR,Master region base address"
|
|
hexmask.long 0x00 6.--31. 1. "ADDR26,This field specifies the base address of the master region"
|
|
rgroup.long ($2+0x24)++0x03
|
|
line.long 0x00 "MS_SIZE,Master region size"
|
|
bitfld.long 0x00 31. "VALID,Master region enable: '1': Enabled" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the size of the master region: '5': 64 B region The master region includes the SL_ADDR SL_SIZE SL_ATT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long ($2+0x30)++0x03
|
|
line.long 0x00 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x00 28. "PC3_NS,Protection context 3 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC3_PW,Protection context 3 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 26. "PC3_PR,Protection context 3 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC3_UW,Protection context 3 user write enable" "0,1"
|
|
rbitfld.long 0x00 24. "PC3_UR,Protection context 3 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC2_NS,Protection context 2 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC2_PW,Protection context 2 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 18. "PC2_PR,Protection context 2 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC2_UW,Protection context 2 user write enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "PC2_UR,Protection context 2 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC1_NS,Protection context 1 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC1_PW,Protection context 1 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 10. "PC1_PR,Protection context 1 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC1_UW,Protection context 1 user write enable" "0,1"
|
|
rbitfld.long 0x00 8. "PC1_UR,Protection context 1 user read enable" "0,1"
|
|
rbitfld.long 0x00 4. "PC0_NS,Protection context 0 non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 3. "PC0_PW,Protection context 0 privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 2. "PC0_PR,Protection context 0 privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "PC0_UW,Protection context 0 user write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 0. "PC0_UR,Protection context 0 user read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
group.long ($2+0x34)++0x03
|
|
line.long 0x00 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x00 28. "PC7_NS,Protection context 7 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC7_PW,Protection context 7 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 26. "PC7_PR,Protection context 7 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC7_UW,Protection context 7 user write enable" "0,1"
|
|
rbitfld.long 0x00 24. "PC7_UR,Protection context 7 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC6_NS,Protection context 6 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC6_PW,Protection context 6 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 18. "PC6_PR,Protection context 6 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC6_UW,Protection context 6 user write enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "PC6_UR,Protection context 6 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC5_NS,Protection context 5 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC5_PW,Protection context 5 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 10. "PC5_PR,Protection context 5 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC5_UW,Protection context 5 user write enable" "0,1"
|
|
rbitfld.long 0x00 8. "PC5_UR,Protection context 5 user read enable" "0,1"
|
|
bitfld.long 0x00 4. "PC4_NS,Protection context 4 non-secure" "0,1"
|
|
bitfld.long 0x00 3. "PC4_PW,Protection context 4 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 2. "PC4_PR,Protection context 4 privileged read enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC4_UW,Protection context 4 user write enable" "0,1"
|
|
rbitfld.long 0x00 0. "PC4_UR,Protection context 4 user read enable" "0,1"
|
|
group.long ($2+0x38)++0x03
|
|
line.long 0x00 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x00 28. "PC11_NS,Protection context 11 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC11_PW,Protection context 11 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 26. "PC11_PR,Protection context 11 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC11_UW,Protection context 11 user write enable" "0,1"
|
|
rbitfld.long 0x00 24. "PC11_UR,Protection context 11 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC10_NS,Protection context 10 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC10_PW,Protection context 10 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 18. "PC10_PR,Protection context 10 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC10_UW,Protection context 10 user write enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "PC10_UR,Protection context 10 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC9_NS,Protection context 9 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC9_PW,Protection context 9 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 10. "PC9_PR,Protection context 9 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC9_UW,Protection context 9 user write enable" "0,1"
|
|
rbitfld.long 0x00 8. "PC9_UR,Protection context 9 user read enable" "0,1"
|
|
bitfld.long 0x00 4. "PC8_NS,Protection context 8 non-secure" "0,1"
|
|
bitfld.long 0x00 3. "PC8_PW,Protection context 8 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 2. "PC8_PR,Protection context 8 privileged read enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC8_UW,Protection context 8 user write enable" "0,1"
|
|
rbitfld.long 0x00 0. "PC8_UR,Protection context 8 user read enable" "0,1"
|
|
group.long ($2+0x3C)++0x03
|
|
line.long 0x00 "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0x00 28. "PC15_NS,Protection context 15 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC15_PW,Protection context 15 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 26. "PC15_PR,Protection context 15 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC15_UW,Protection context 15 user write enable" "0,1"
|
|
rbitfld.long 0x00 24. "PC15_UR,Protection context 15 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC14_NS,Protection context 14 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC14_PW,Protection context 14 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 18. "PC14_PR,Protection context 14 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC14_UW,Protection context 14 user write enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "PC14_UR,Protection context 14 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC13_NS,Protection context 13 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC13_PW,Protection context 13 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 10. "PC13_PR,Protection context 13 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC13_UW,Protection context 13 user write enable" "0,1"
|
|
rbitfld.long 0x00 8. "PC13_UR,Protection context 13 user read enable" "0,1"
|
|
bitfld.long 0x00 4. "PC12_NS,Protection context 12 non-secure" "0,1"
|
|
bitfld.long 0x00 3. "PC12_PW,Protection context 12 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 2. "PC12_PR,Protection context 12 privileged read enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC12_UW,Protection context 12 user write enable" "0,1"
|
|
rbitfld.long 0x00 0. "PC12_UR,Protection context 12 user read enable" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 702. (increment 0 1)(increment 0 0x840)
|
|
tree "PPU_FX[$1]"
|
|
rgroup.long ($2+0x800)++0x03
|
|
line.long 0x00 "SL_ADDR,Slave region base address"
|
|
hexmask.long 0x00 2.--31. 1. "ADDR30,This field specifies the base address of the slave region"
|
|
rgroup.long ($2+0x804)++0x03
|
|
line.long 0x00 "SL_SIZE,Slave region size"
|
|
bitfld.long 0x00 31. "VALID,Slave region enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the size of the slave region: '0': Undefined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long ($2+0x810)++0x03
|
|
line.long 0x00 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x00 28. "PC3_NS,Protection context 3 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC3_PW,Protection context 3 privileged write enable" "0,1"
|
|
bitfld.long 0x00 26. "PC3_PR,Protection context 3 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC3_UW,Protection context 3 user write enable" "0,1"
|
|
bitfld.long 0x00 24. "PC3_UR,Protection context 3 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC2_NS,Protection context 2 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC2_PW,Protection context 2 privileged write enable" "0,1"
|
|
bitfld.long 0x00 18. "PC2_PR,Protection context 2 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC2_UW,Protection context 2 user write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PC2_UR,Protection context 2 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC1_NS,Protection context 1 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC1_PW,Protection context 1 privileged write enable" "0,1"
|
|
bitfld.long 0x00 10. "PC1_PR,Protection context 1 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC1_UW,Protection context 1 user write enable" "0,1"
|
|
bitfld.long 0x00 8. "PC1_UR,Protection context 1 user read enable" "0,1"
|
|
rbitfld.long 0x00 4. "PC0_NS,Protection context 0 non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 3. "PC0_PW,Protection context 0 privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 2. "PC0_PR,Protection context 0 privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "PC0_UW,Protection context 0 user write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 0. "PC0_UR,Protection context 0 user read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
group.long ($2+0x814)++0x03
|
|
line.long 0x00 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x00 28. "PC7_NS,Protection context 7 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC7_PW,Protection context 7 privileged write enable" "0,1"
|
|
bitfld.long 0x00 26. "PC7_PR,Protection context 7 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC7_UW,Protection context 7 user write enable" "0,1"
|
|
bitfld.long 0x00 24. "PC7_UR,Protection context 7 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC6_NS,Protection context 6 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC6_PW,Protection context 6 privileged write enable" "0,1"
|
|
bitfld.long 0x00 18. "PC6_PR,Protection context 6 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC6_UW,Protection context 6 user write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PC6_UR,Protection context 6 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC5_NS,Protection context 5 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC5_PW,Protection context 5 privileged write enable" "0,1"
|
|
bitfld.long 0x00 10. "PC5_PR,Protection context 5 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC5_UW,Protection context 5 user write enable" "0,1"
|
|
bitfld.long 0x00 8. "PC5_UR,Protection context 5 user read enable" "0,1"
|
|
bitfld.long 0x00 4. "PC4_NS,Protection context 4 non-secure" "0,1"
|
|
bitfld.long 0x00 3. "PC4_PW,Protection context 4 privileged write enable" "0,1"
|
|
bitfld.long 0x00 2. "PC4_PR,Protection context 4 privileged read enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC4_UW,Protection context 4 user write enable" "0,1"
|
|
bitfld.long 0x00 0. "PC4_UR,Protection context 4 user read enable" "0,1"
|
|
group.long ($2+0x818)++0x03
|
|
line.long 0x00 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x00 28. "PC11_NS,Protection context 11 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC11_PW,Protection context 11 privileged write enable" "0,1"
|
|
bitfld.long 0x00 26. "PC11_PR,Protection context 11 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC11_UW,Protection context 11 user write enable" "0,1"
|
|
bitfld.long 0x00 24. "PC11_UR,Protection context 11 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC10_NS,Protection context 10 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC10_PW,Protection context 10 privileged write enable" "0,1"
|
|
bitfld.long 0x00 18. "PC10_PR,Protection context 10 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC10_UW,Protection context 10 user write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PC10_UR,Protection context 10 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC9_NS,Protection context 9 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC9_PW,Protection context 9 privileged write enable" "0,1"
|
|
bitfld.long 0x00 10. "PC9_PR,Protection context 9 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC9_UW,Protection context 9 user write enable" "0,1"
|
|
bitfld.long 0x00 8. "PC9_UR,Protection context 9 user read enable" "0,1"
|
|
bitfld.long 0x00 4. "PC8_NS,Protection context 8 non-secure" "0,1"
|
|
bitfld.long 0x00 3. "PC8_PW,Protection context 8 privileged write enable" "0,1"
|
|
bitfld.long 0x00 2. "PC8_PR,Protection context 8 privileged read enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC8_UW,Protection context 8 user write enable" "0,1"
|
|
bitfld.long 0x00 0. "PC8_UR,Protection context 8 user read enable" "0,1"
|
|
group.long ($2+0x81C)++0x03
|
|
line.long 0x00 "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0x00 28. "PC15_NS,Protection context 15 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC15_PW,Protection context 15 privileged write enable" "0,1"
|
|
bitfld.long 0x00 26. "PC15_PR,Protection context 15 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC15_UW,Protection context 15 user write enable" "0,1"
|
|
bitfld.long 0x00 24. "PC15_UR,Protection context 15 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC14_NS,Protection context 14 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC14_PW,Protection context 14 privileged write enable" "0,1"
|
|
bitfld.long 0x00 18. "PC14_PR,Protection context 14 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC14_UW,Protection context 14 user write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PC14_UR,Protection context 14 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC13_NS,Protection context 13 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC13_PW,Protection context 13 privileged write enable" "0,1"
|
|
bitfld.long 0x00 10. "PC13_PR,Protection context 13 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC13_UW,Protection context 13 user write enable" "0,1"
|
|
bitfld.long 0x00 8. "PC13_UR,Protection context 13 user read enable" "0,1"
|
|
bitfld.long 0x00 4. "PC12_NS,Protection context 12 non-secure" "0,1"
|
|
bitfld.long 0x00 3. "PC12_PW,Protection context 12 privileged write enable" "0,1"
|
|
bitfld.long 0x00 2. "PC12_PR,Protection context 12 privileged read enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC12_UW,Protection context 12 user write enable" "0,1"
|
|
bitfld.long 0x00 0. "PC12_UR,Protection context 12 user read enable" "0,1"
|
|
rgroup.long ($2+0x820)++0x03
|
|
line.long 0x00 "MS_ADDR,Master region base address"
|
|
hexmask.long 0x00 6.--31. 1. "ADDR26,This field specifies the base address of the master region"
|
|
rgroup.long ($2+0x824)++0x03
|
|
line.long 0x00 "MS_SIZE,Master region size"
|
|
bitfld.long 0x00 31. "VALID,Master region enable: '1': Enabled" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the size of the master region: '5': 64 B region The master region includes the SL_ADDR SL_SIZE SL_ATT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long ($2+0x830)++0x03
|
|
line.long 0x00 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x00 28. "PC3_NS,Protection context 3 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC3_PW,Protection context 3 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 26. "PC3_PR,Protection context 3 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC3_UW,Protection context 3 user write enable" "0,1"
|
|
rbitfld.long 0x00 24. "PC3_UR,Protection context 3 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC2_NS,Protection context 2 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC2_PW,Protection context 2 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 18. "PC2_PR,Protection context 2 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC2_UW,Protection context 2 user write enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "PC2_UR,Protection context 2 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC1_NS,Protection context 1 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC1_PW,Protection context 1 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 10. "PC1_PR,Protection context 1 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC1_UW,Protection context 1 user write enable" "0,1"
|
|
rbitfld.long 0x00 8. "PC1_UR,Protection context 1 user read enable" "0,1"
|
|
rbitfld.long 0x00 4. "PC0_NS,Protection context 0 non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 3. "PC0_PW,Protection context 0 privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 2. "PC0_PR,Protection context 0 privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "PC0_UW,Protection context 0 user write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 0. "PC0_UR,Protection context 0 user read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
group.long ($2+0x834)++0x03
|
|
line.long 0x00 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x00 28. "PC7_NS,Protection context 7 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC7_PW,Protection context 7 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 26. "PC7_PR,Protection context 7 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC7_UW,Protection context 7 user write enable" "0,1"
|
|
rbitfld.long 0x00 24. "PC7_UR,Protection context 7 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC6_NS,Protection context 6 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC6_PW,Protection context 6 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 18. "PC6_PR,Protection context 6 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC6_UW,Protection context 6 user write enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "PC6_UR,Protection context 6 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC5_NS,Protection context 5 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC5_PW,Protection context 5 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 10. "PC5_PR,Protection context 5 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC5_UW,Protection context 5 user write enable" "0,1"
|
|
rbitfld.long 0x00 8. "PC5_UR,Protection context 5 user read enable" "0,1"
|
|
bitfld.long 0x00 4. "PC4_NS,Protection context 4 non-secure" "0,1"
|
|
bitfld.long 0x00 3. "PC4_PW,Protection context 4 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 2. "PC4_PR,Protection context 4 privileged read enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC4_UW,Protection context 4 user write enable" "0,1"
|
|
rbitfld.long 0x00 0. "PC4_UR,Protection context 4 user read enable" "0,1"
|
|
group.long ($2+0x838)++0x03
|
|
line.long 0x00 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x00 28. "PC11_NS,Protection context 11 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC11_PW,Protection context 11 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 26. "PC11_PR,Protection context 11 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC11_UW,Protection context 11 user write enable" "0,1"
|
|
rbitfld.long 0x00 24. "PC11_UR,Protection context 11 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC10_NS,Protection context 10 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC10_PW,Protection context 10 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 18. "PC10_PR,Protection context 10 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC10_UW,Protection context 10 user write enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "PC10_UR,Protection context 10 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC9_NS,Protection context 9 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC9_PW,Protection context 9 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 10. "PC9_PR,Protection context 9 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC9_UW,Protection context 9 user write enable" "0,1"
|
|
rbitfld.long 0x00 8. "PC9_UR,Protection context 9 user read enable" "0,1"
|
|
bitfld.long 0x00 4. "PC8_NS,Protection context 8 non-secure" "0,1"
|
|
bitfld.long 0x00 3. "PC8_PW,Protection context 8 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 2. "PC8_PR,Protection context 8 privileged read enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC8_UW,Protection context 8 user write enable" "0,1"
|
|
rbitfld.long 0x00 0. "PC8_UR,Protection context 8 user read enable" "0,1"
|
|
group.long ($2+0x83C)++0x03
|
|
line.long 0x00 "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0x00 28. "PC15_NS,Protection context 15 non-secure" "0,1"
|
|
bitfld.long 0x00 27. "PC15_PW,Protection context 15 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 26. "PC15_PR,Protection context 15 privileged read enable" "0,1"
|
|
bitfld.long 0x00 25. "PC15_UW,Protection context 15 user write enable" "0,1"
|
|
rbitfld.long 0x00 24. "PC15_UR,Protection context 15 user read enable" "0,1"
|
|
bitfld.long 0x00 20. "PC14_NS,Protection context 14 non-secure" "0,1"
|
|
bitfld.long 0x00 19. "PC14_PW,Protection context 14 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 18. "PC14_PR,Protection context 14 privileged read enable" "0,1"
|
|
bitfld.long 0x00 17. "PC14_UW,Protection context 14 user write enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "PC14_UR,Protection context 14 user read enable" "0,1"
|
|
bitfld.long 0x00 12. "PC13_NS,Protection context 13 non-secure" "0,1"
|
|
bitfld.long 0x00 11. "PC13_PW,Protection context 13 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 10. "PC13_PR,Protection context 13 privileged read enable" "0,1"
|
|
bitfld.long 0x00 9. "PC13_UW,Protection context 13 user write enable" "0,1"
|
|
rbitfld.long 0x00 8. "PC13_UR,Protection context 13 user read enable" "0,1"
|
|
bitfld.long 0x00 4. "PC12_NS,Protection context 12 non-secure" "0,1"
|
|
bitfld.long 0x00 3. "PC12_PW,Protection context 12 privileged write enable" "0,1"
|
|
rbitfld.long 0x00 2. "PC12_PR,Protection context 12 privileged read enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC12_UW,Protection context 12 user write enable" "0,1"
|
|
rbitfld.long 0x00 0. "PC12_UR,Protection context 12 user read enable" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PERI_PCLK (Peripheral PCLK)"
|
|
base ad:0x40040000
|
|
repeat 2. (increment 0 1)(increment 0 0x2000)
|
|
tree "GR[$1]"
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "DIV_CMD,Divider command"
|
|
bitfld.long 0x00 31. "ENABLE,Clock divider enable command (mutually exclusive with DISABLE)" "0: Disable the divider using the DIV_CMD.DISABLE,1: Configure the divider's DIV_XXX_CTL register"
|
|
bitfld.long 0x00 30. "DISABLE,Clock divider disable command (mutually exclusive with ENABLE)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PA_TYPE_SEL,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PA_DIV_SEL,(PA_TYPE_SEL PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies the divider type of the divider on which the command is performed" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,(TYPE_SEL DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed"
|
|
group.long ($2+0xC00)++0x03
|
|
line.long 0x00 "CLOCK_CTL[0],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC04)++0x03
|
|
line.long 0x00 "CLOCK_CTL[1],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC08)++0x03
|
|
line.long 0x00 "CLOCK_CTL[2],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC0C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[3],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC10)++0x03
|
|
line.long 0x00 "CLOCK_CTL[4],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC14)++0x03
|
|
line.long 0x00 "CLOCK_CTL[5],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC18)++0x03
|
|
line.long 0x00 "CLOCK_CTL[6],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC1C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[7],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC20)++0x03
|
|
line.long 0x00 "CLOCK_CTL[8],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC24)++0x03
|
|
line.long 0x00 "CLOCK_CTL[9],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC28)++0x03
|
|
line.long 0x00 "CLOCK_CTL[10],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC2C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[11],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC30)++0x03
|
|
line.long 0x00 "CLOCK_CTL[12],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC34)++0x03
|
|
line.long 0x00 "CLOCK_CTL[13],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC38)++0x03
|
|
line.long 0x00 "CLOCK_CTL[14],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC3C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[15],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC40)++0x03
|
|
line.long 0x00 "CLOCK_CTL[16],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC44)++0x03
|
|
line.long 0x00 "CLOCK_CTL[17],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC48)++0x03
|
|
line.long 0x00 "CLOCK_CTL[18],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC4C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[19],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC50)++0x03
|
|
line.long 0x00 "CLOCK_CTL[20],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC54)++0x03
|
|
line.long 0x00 "CLOCK_CTL[21],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC58)++0x03
|
|
line.long 0x00 "CLOCK_CTL[22],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC5C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[23],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC60)++0x03
|
|
line.long 0x00 "CLOCK_CTL[24],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC64)++0x03
|
|
line.long 0x00 "CLOCK_CTL[25],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC68)++0x03
|
|
line.long 0x00 "CLOCK_CTL[26],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC6C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[27],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC70)++0x03
|
|
line.long 0x00 "CLOCK_CTL[28],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC74)++0x03
|
|
line.long 0x00 "CLOCK_CTL[29],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC78)++0x03
|
|
line.long 0x00 "CLOCK_CTL[30],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC7C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[31],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC80)++0x03
|
|
line.long 0x00 "CLOCK_CTL[32],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC84)++0x03
|
|
line.long 0x00 "CLOCK_CTL[33],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC88)++0x03
|
|
line.long 0x00 "CLOCK_CTL[34],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC8C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[35],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC90)++0x03
|
|
line.long 0x00 "CLOCK_CTL[36],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC94)++0x03
|
|
line.long 0x00 "CLOCK_CTL[37],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC98)++0x03
|
|
line.long 0x00 "CLOCK_CTL[38],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xC9C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[39],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCA0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[40],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCA4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[41],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCA8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[42],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCAC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[43],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCB0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[44],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCB4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[45],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCB8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[46],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCBC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[47],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCC0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[48],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCC4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[49],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCC8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[50],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCCC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[51],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCD0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[52],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCD4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[53],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCD8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[54],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCDC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[55],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCE0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[56],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCE4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[57],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCE8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[58],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCEC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[59],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCF0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[60],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCF4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[61],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCF8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[62],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xCFC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[63],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD00)++0x03
|
|
line.long 0x00 "CLOCK_CTL[64],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD04)++0x03
|
|
line.long 0x00 "CLOCK_CTL[65],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD08)++0x03
|
|
line.long 0x00 "CLOCK_CTL[66],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD0C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[67],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD10)++0x03
|
|
line.long 0x00 "CLOCK_CTL[68],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD14)++0x03
|
|
line.long 0x00 "CLOCK_CTL[69],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD18)++0x03
|
|
line.long 0x00 "CLOCK_CTL[70],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD1C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[71],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD20)++0x03
|
|
line.long 0x00 "CLOCK_CTL[72],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD24)++0x03
|
|
line.long 0x00 "CLOCK_CTL[73],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD28)++0x03
|
|
line.long 0x00 "CLOCK_CTL[74],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD2C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[75],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD30)++0x03
|
|
line.long 0x00 "CLOCK_CTL[76],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD34)++0x03
|
|
line.long 0x00 "CLOCK_CTL[77],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD38)++0x03
|
|
line.long 0x00 "CLOCK_CTL[78],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD3C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[79],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD40)++0x03
|
|
line.long 0x00 "CLOCK_CTL[80],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD44)++0x03
|
|
line.long 0x00 "CLOCK_CTL[81],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD48)++0x03
|
|
line.long 0x00 "CLOCK_CTL[82],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD4C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[83],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD50)++0x03
|
|
line.long 0x00 "CLOCK_CTL[84],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD54)++0x03
|
|
line.long 0x00 "CLOCK_CTL[85],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD58)++0x03
|
|
line.long 0x00 "CLOCK_CTL[86],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD5C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[87],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD60)++0x03
|
|
line.long 0x00 "CLOCK_CTL[88],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD64)++0x03
|
|
line.long 0x00 "CLOCK_CTL[89],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD68)++0x03
|
|
line.long 0x00 "CLOCK_CTL[90],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD6C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[91],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD70)++0x03
|
|
line.long 0x00 "CLOCK_CTL[92],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD74)++0x03
|
|
line.long 0x00 "CLOCK_CTL[93],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD78)++0x03
|
|
line.long 0x00 "CLOCK_CTL[94],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD7C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[95],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD80)++0x03
|
|
line.long 0x00 "CLOCK_CTL[96],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD84)++0x03
|
|
line.long 0x00 "CLOCK_CTL[97],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD88)++0x03
|
|
line.long 0x00 "CLOCK_CTL[98],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD8C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[99],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD90)++0x03
|
|
line.long 0x00 "CLOCK_CTL[100],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD94)++0x03
|
|
line.long 0x00 "CLOCK_CTL[101],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD98)++0x03
|
|
line.long 0x00 "CLOCK_CTL[102],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xD9C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[103],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDA0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[104],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDA4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[105],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDA8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[106],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDAC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[107],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDB0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[108],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDB4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[109],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDB8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[110],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDBC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[111],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDC0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[112],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDC4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[113],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDC8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[114],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDCC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[115],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDD0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[116],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDD4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[117],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDD8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[118],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDDC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[119],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDE0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[120],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDE4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[121],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDE8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[122],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDEC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[123],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDF0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[124],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDF4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[125],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDF8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[126],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xDFC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[127],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE00)++0x03
|
|
line.long 0x00 "CLOCK_CTL[128],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE04)++0x03
|
|
line.long 0x00 "CLOCK_CTL[129],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE08)++0x03
|
|
line.long 0x00 "CLOCK_CTL[130],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE0C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[131],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE10)++0x03
|
|
line.long 0x00 "CLOCK_CTL[132],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE14)++0x03
|
|
line.long 0x00 "CLOCK_CTL[133],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE18)++0x03
|
|
line.long 0x00 "CLOCK_CTL[134],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE1C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[135],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE20)++0x03
|
|
line.long 0x00 "CLOCK_CTL[136],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE24)++0x03
|
|
line.long 0x00 "CLOCK_CTL[137],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE28)++0x03
|
|
line.long 0x00 "CLOCK_CTL[138],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE2C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[139],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE30)++0x03
|
|
line.long 0x00 "CLOCK_CTL[140],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE34)++0x03
|
|
line.long 0x00 "CLOCK_CTL[141],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE38)++0x03
|
|
line.long 0x00 "CLOCK_CTL[142],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE3C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[143],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE40)++0x03
|
|
line.long 0x00 "CLOCK_CTL[144],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE44)++0x03
|
|
line.long 0x00 "CLOCK_CTL[145],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE48)++0x03
|
|
line.long 0x00 "CLOCK_CTL[146],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE4C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[147],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE50)++0x03
|
|
line.long 0x00 "CLOCK_CTL[148],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE54)++0x03
|
|
line.long 0x00 "CLOCK_CTL[149],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE58)++0x03
|
|
line.long 0x00 "CLOCK_CTL[150],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE5C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[151],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE60)++0x03
|
|
line.long 0x00 "CLOCK_CTL[152],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE64)++0x03
|
|
line.long 0x00 "CLOCK_CTL[153],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE68)++0x03
|
|
line.long 0x00 "CLOCK_CTL[154],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE6C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[155],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE70)++0x03
|
|
line.long 0x00 "CLOCK_CTL[156],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE74)++0x03
|
|
line.long 0x00 "CLOCK_CTL[157],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE78)++0x03
|
|
line.long 0x00 "CLOCK_CTL[158],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE7C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[159],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE80)++0x03
|
|
line.long 0x00 "CLOCK_CTL[160],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE84)++0x03
|
|
line.long 0x00 "CLOCK_CTL[161],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE88)++0x03
|
|
line.long 0x00 "CLOCK_CTL[162],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE8C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[163],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE90)++0x03
|
|
line.long 0x00 "CLOCK_CTL[164],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE94)++0x03
|
|
line.long 0x00 "CLOCK_CTL[165],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE98)++0x03
|
|
line.long 0x00 "CLOCK_CTL[166],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xE9C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[167],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEA0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[168],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEA4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[169],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEA8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[170],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEAC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[171],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEB0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[172],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEB4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[173],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEB8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[174],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEBC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[175],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEC0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[176],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEC4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[177],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEC8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[178],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xECC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[179],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xED0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[180],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xED4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[181],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xED8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[182],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEDC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[183],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEE0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[184],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEE4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[185],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEE8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[186],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEEC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[187],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEF0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[188],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEF4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[189],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEF8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[190],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xEFC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[191],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF00)++0x03
|
|
line.long 0x00 "CLOCK_CTL[192],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF04)++0x03
|
|
line.long 0x00 "CLOCK_CTL[193],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF08)++0x03
|
|
line.long 0x00 "CLOCK_CTL[194],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF0C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[195],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF10)++0x03
|
|
line.long 0x00 "CLOCK_CTL[196],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF14)++0x03
|
|
line.long 0x00 "CLOCK_CTL[197],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF18)++0x03
|
|
line.long 0x00 "CLOCK_CTL[198],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF1C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[199],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF20)++0x03
|
|
line.long 0x00 "CLOCK_CTL[200],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF24)++0x03
|
|
line.long 0x00 "CLOCK_CTL[201],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF28)++0x03
|
|
line.long 0x00 "CLOCK_CTL[202],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF2C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[203],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF30)++0x03
|
|
line.long 0x00 "CLOCK_CTL[204],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF34)++0x03
|
|
line.long 0x00 "CLOCK_CTL[205],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF38)++0x03
|
|
line.long 0x00 "CLOCK_CTL[206],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF3C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[207],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF40)++0x03
|
|
line.long 0x00 "CLOCK_CTL[208],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF44)++0x03
|
|
line.long 0x00 "CLOCK_CTL[209],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF48)++0x03
|
|
line.long 0x00 "CLOCK_CTL[210],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF4C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[211],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF50)++0x03
|
|
line.long 0x00 "CLOCK_CTL[212],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF54)++0x03
|
|
line.long 0x00 "CLOCK_CTL[213],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF58)++0x03
|
|
line.long 0x00 "CLOCK_CTL[214],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF5C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[215],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF60)++0x03
|
|
line.long 0x00 "CLOCK_CTL[216],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF64)++0x03
|
|
line.long 0x00 "CLOCK_CTL[217],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF68)++0x03
|
|
line.long 0x00 "CLOCK_CTL[218],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF6C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[219],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF70)++0x03
|
|
line.long 0x00 "CLOCK_CTL[220],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF74)++0x03
|
|
line.long 0x00 "CLOCK_CTL[221],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF78)++0x03
|
|
line.long 0x00 "CLOCK_CTL[222],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF7C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[223],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF80)++0x03
|
|
line.long 0x00 "CLOCK_CTL[224],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF84)++0x03
|
|
line.long 0x00 "CLOCK_CTL[225],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF88)++0x03
|
|
line.long 0x00 "CLOCK_CTL[226],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF8C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[227],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF90)++0x03
|
|
line.long 0x00 "CLOCK_CTL[228],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF94)++0x03
|
|
line.long 0x00 "CLOCK_CTL[229],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF98)++0x03
|
|
line.long 0x00 "CLOCK_CTL[230],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xF9C)++0x03
|
|
line.long 0x00 "CLOCK_CTL[231],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFA0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[232],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFA4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[233],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFA8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[234],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFAC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[235],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFB0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[236],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFB4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[237],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFB8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[238],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFBC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[239],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFC0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[240],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFC4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[241],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFC8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[242],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFCC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[243],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFD0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[244],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[245],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFD8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[246],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFDC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[247],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFE0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[248],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFE4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[249],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFE8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[250],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFEC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[251],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CLOCK_CTL[252],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFF4)++0x03
|
|
line.long 0x00 "CLOCK_CTL[253],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFF8)++0x03
|
|
line.long 0x00 "CLOCK_CTL[254],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0xFFC)++0x03
|
|
line.long 0x00 "CLOCK_CTL[255],Clock control"
|
|
bitfld.long 0x00 8.--9. "TYPE_SEL,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL"
|
|
group.long ($2+0x1000)++0x03
|
|
line.long 0x00 "DIV_8_CTL[0],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1004)++0x03
|
|
line.long 0x00 "DIV_8_CTL[1],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1008)++0x03
|
|
line.long 0x00 "DIV_8_CTL[2],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x100C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[3],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1010)++0x03
|
|
line.long 0x00 "DIV_8_CTL[4],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1014)++0x03
|
|
line.long 0x00 "DIV_8_CTL[5],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1018)++0x03
|
|
line.long 0x00 "DIV_8_CTL[6],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x101C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[7],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1020)++0x03
|
|
line.long 0x00 "DIV_8_CTL[8],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1024)++0x03
|
|
line.long 0x00 "DIV_8_CTL[9],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1028)++0x03
|
|
line.long 0x00 "DIV_8_CTL[10],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x102C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[11],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1030)++0x03
|
|
line.long 0x00 "DIV_8_CTL[12],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1034)++0x03
|
|
line.long 0x00 "DIV_8_CTL[13],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1038)++0x03
|
|
line.long 0x00 "DIV_8_CTL[14],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x103C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[15],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1040)++0x03
|
|
line.long 0x00 "DIV_8_CTL[16],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1044)++0x03
|
|
line.long 0x00 "DIV_8_CTL[17],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1048)++0x03
|
|
line.long 0x00 "DIV_8_CTL[18],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x104C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[19],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1050)++0x03
|
|
line.long 0x00 "DIV_8_CTL[20],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1054)++0x03
|
|
line.long 0x00 "DIV_8_CTL[21],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1058)++0x03
|
|
line.long 0x00 "DIV_8_CTL[22],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x105C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[23],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1060)++0x03
|
|
line.long 0x00 "DIV_8_CTL[24],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1064)++0x03
|
|
line.long 0x00 "DIV_8_CTL[25],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1068)++0x03
|
|
line.long 0x00 "DIV_8_CTL[26],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x106C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[27],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1070)++0x03
|
|
line.long 0x00 "DIV_8_CTL[28],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1074)++0x03
|
|
line.long 0x00 "DIV_8_CTL[29],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1078)++0x03
|
|
line.long 0x00 "DIV_8_CTL[30],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x107C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[31],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1080)++0x03
|
|
line.long 0x00 "DIV_8_CTL[32],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1084)++0x03
|
|
line.long 0x00 "DIV_8_CTL[33],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1088)++0x03
|
|
line.long 0x00 "DIV_8_CTL[34],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x108C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[35],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1090)++0x03
|
|
line.long 0x00 "DIV_8_CTL[36],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1094)++0x03
|
|
line.long 0x00 "DIV_8_CTL[37],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1098)++0x03
|
|
line.long 0x00 "DIV_8_CTL[38],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x109C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[39],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10A0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[40],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10A4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[41],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10A8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[42],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10AC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[43],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10B0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[44],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10B4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[45],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10B8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[46],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10BC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[47],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10C0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[48],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10C4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[49],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10C8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[50],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10CC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[51],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10D0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[52],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10D4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[53],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10D8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[54],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10DC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[55],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10E0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[56],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10E4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[57],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10E8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[58],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10EC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[59],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10F0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[60],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10F4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[61],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10F8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[62],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x10FC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[63],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1100)++0x03
|
|
line.long 0x00 "DIV_8_CTL[64],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1104)++0x03
|
|
line.long 0x00 "DIV_8_CTL[65],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1108)++0x03
|
|
line.long 0x00 "DIV_8_CTL[66],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x110C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[67],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1110)++0x03
|
|
line.long 0x00 "DIV_8_CTL[68],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1114)++0x03
|
|
line.long 0x00 "DIV_8_CTL[69],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1118)++0x03
|
|
line.long 0x00 "DIV_8_CTL[70],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x111C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[71],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1120)++0x03
|
|
line.long 0x00 "DIV_8_CTL[72],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1124)++0x03
|
|
line.long 0x00 "DIV_8_CTL[73],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1128)++0x03
|
|
line.long 0x00 "DIV_8_CTL[74],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x112C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[75],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1130)++0x03
|
|
line.long 0x00 "DIV_8_CTL[76],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1134)++0x03
|
|
line.long 0x00 "DIV_8_CTL[77],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1138)++0x03
|
|
line.long 0x00 "DIV_8_CTL[78],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x113C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[79],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1140)++0x03
|
|
line.long 0x00 "DIV_8_CTL[80],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1144)++0x03
|
|
line.long 0x00 "DIV_8_CTL[81],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1148)++0x03
|
|
line.long 0x00 "DIV_8_CTL[82],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x114C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[83],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1150)++0x03
|
|
line.long 0x00 "DIV_8_CTL[84],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1154)++0x03
|
|
line.long 0x00 "DIV_8_CTL[85],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1158)++0x03
|
|
line.long 0x00 "DIV_8_CTL[86],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x115C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[87],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1160)++0x03
|
|
line.long 0x00 "DIV_8_CTL[88],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1164)++0x03
|
|
line.long 0x00 "DIV_8_CTL[89],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1168)++0x03
|
|
line.long 0x00 "DIV_8_CTL[90],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x116C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[91],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1170)++0x03
|
|
line.long 0x00 "DIV_8_CTL[92],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1174)++0x03
|
|
line.long 0x00 "DIV_8_CTL[93],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1178)++0x03
|
|
line.long 0x00 "DIV_8_CTL[94],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x117C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[95],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1180)++0x03
|
|
line.long 0x00 "DIV_8_CTL[96],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1184)++0x03
|
|
line.long 0x00 "DIV_8_CTL[97],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1188)++0x03
|
|
line.long 0x00 "DIV_8_CTL[98],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x118C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[99],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1190)++0x03
|
|
line.long 0x00 "DIV_8_CTL[100],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1194)++0x03
|
|
line.long 0x00 "DIV_8_CTL[101],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1198)++0x03
|
|
line.long 0x00 "DIV_8_CTL[102],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x119C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[103],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11A0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[104],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11A4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[105],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11A8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[106],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11AC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[107],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11B0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[108],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11B4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[109],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11B8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[110],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11BC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[111],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11C0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[112],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11C4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[113],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11C8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[114],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11CC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[115],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11D0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[116],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11D4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[117],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11D8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[118],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11DC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[119],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11E0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[120],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11E4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[121],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11E8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[122],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11EC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[123],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11F0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[124],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11F4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[125],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11F8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[126],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x11FC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[127],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1200)++0x03
|
|
line.long 0x00 "DIV_8_CTL[128],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1204)++0x03
|
|
line.long 0x00 "DIV_8_CTL[129],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1208)++0x03
|
|
line.long 0x00 "DIV_8_CTL[130],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x120C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[131],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1210)++0x03
|
|
line.long 0x00 "DIV_8_CTL[132],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1214)++0x03
|
|
line.long 0x00 "DIV_8_CTL[133],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1218)++0x03
|
|
line.long 0x00 "DIV_8_CTL[134],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x121C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[135],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1220)++0x03
|
|
line.long 0x00 "DIV_8_CTL[136],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1224)++0x03
|
|
line.long 0x00 "DIV_8_CTL[137],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1228)++0x03
|
|
line.long 0x00 "DIV_8_CTL[138],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x122C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[139],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1230)++0x03
|
|
line.long 0x00 "DIV_8_CTL[140],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1234)++0x03
|
|
line.long 0x00 "DIV_8_CTL[141],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1238)++0x03
|
|
line.long 0x00 "DIV_8_CTL[142],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x123C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[143],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1240)++0x03
|
|
line.long 0x00 "DIV_8_CTL[144],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1244)++0x03
|
|
line.long 0x00 "DIV_8_CTL[145],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1248)++0x03
|
|
line.long 0x00 "DIV_8_CTL[146],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x124C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[147],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1250)++0x03
|
|
line.long 0x00 "DIV_8_CTL[148],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1254)++0x03
|
|
line.long 0x00 "DIV_8_CTL[149],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1258)++0x03
|
|
line.long 0x00 "DIV_8_CTL[150],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x125C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[151],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1260)++0x03
|
|
line.long 0x00 "DIV_8_CTL[152],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1264)++0x03
|
|
line.long 0x00 "DIV_8_CTL[153],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1268)++0x03
|
|
line.long 0x00 "DIV_8_CTL[154],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x126C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[155],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1270)++0x03
|
|
line.long 0x00 "DIV_8_CTL[156],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1274)++0x03
|
|
line.long 0x00 "DIV_8_CTL[157],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1278)++0x03
|
|
line.long 0x00 "DIV_8_CTL[158],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x127C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[159],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1280)++0x03
|
|
line.long 0x00 "DIV_8_CTL[160],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1284)++0x03
|
|
line.long 0x00 "DIV_8_CTL[161],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1288)++0x03
|
|
line.long 0x00 "DIV_8_CTL[162],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x128C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[163],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1290)++0x03
|
|
line.long 0x00 "DIV_8_CTL[164],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1294)++0x03
|
|
line.long 0x00 "DIV_8_CTL[165],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1298)++0x03
|
|
line.long 0x00 "DIV_8_CTL[166],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x129C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[167],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12A0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[168],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12A4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[169],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12A8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[170],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12AC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[171],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12B0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[172],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12B4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[173],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12B8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[174],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12BC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[175],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12C0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[176],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12C4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[177],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12C8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[178],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12CC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[179],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12D0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[180],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12D4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[181],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12D8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[182],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12DC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[183],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12E0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[184],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12E4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[185],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12E8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[186],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12EC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[187],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12F0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[188],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12F4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[189],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12F8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[190],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x12FC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[191],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1300)++0x03
|
|
line.long 0x00 "DIV_8_CTL[192],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1304)++0x03
|
|
line.long 0x00 "DIV_8_CTL[193],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1308)++0x03
|
|
line.long 0x00 "DIV_8_CTL[194],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x130C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[195],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1310)++0x03
|
|
line.long 0x00 "DIV_8_CTL[196],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1314)++0x03
|
|
line.long 0x00 "DIV_8_CTL[197],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1318)++0x03
|
|
line.long 0x00 "DIV_8_CTL[198],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x131C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[199],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1320)++0x03
|
|
line.long 0x00 "DIV_8_CTL[200],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1324)++0x03
|
|
line.long 0x00 "DIV_8_CTL[201],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1328)++0x03
|
|
line.long 0x00 "DIV_8_CTL[202],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x132C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[203],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1330)++0x03
|
|
line.long 0x00 "DIV_8_CTL[204],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1334)++0x03
|
|
line.long 0x00 "DIV_8_CTL[205],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1338)++0x03
|
|
line.long 0x00 "DIV_8_CTL[206],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x133C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[207],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1340)++0x03
|
|
line.long 0x00 "DIV_8_CTL[208],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1344)++0x03
|
|
line.long 0x00 "DIV_8_CTL[209],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1348)++0x03
|
|
line.long 0x00 "DIV_8_CTL[210],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x134C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[211],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1350)++0x03
|
|
line.long 0x00 "DIV_8_CTL[212],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1354)++0x03
|
|
line.long 0x00 "DIV_8_CTL[213],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1358)++0x03
|
|
line.long 0x00 "DIV_8_CTL[214],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x135C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[215],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1360)++0x03
|
|
line.long 0x00 "DIV_8_CTL[216],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1364)++0x03
|
|
line.long 0x00 "DIV_8_CTL[217],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1368)++0x03
|
|
line.long 0x00 "DIV_8_CTL[218],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x136C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[219],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1370)++0x03
|
|
line.long 0x00 "DIV_8_CTL[220],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1374)++0x03
|
|
line.long 0x00 "DIV_8_CTL[221],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1378)++0x03
|
|
line.long 0x00 "DIV_8_CTL[222],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x137C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[223],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1380)++0x03
|
|
line.long 0x00 "DIV_8_CTL[224],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1384)++0x03
|
|
line.long 0x00 "DIV_8_CTL[225],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1388)++0x03
|
|
line.long 0x00 "DIV_8_CTL[226],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x138C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[227],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1390)++0x03
|
|
line.long 0x00 "DIV_8_CTL[228],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1394)++0x03
|
|
line.long 0x00 "DIV_8_CTL[229],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1398)++0x03
|
|
line.long 0x00 "DIV_8_CTL[230],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x139C)++0x03
|
|
line.long 0x00 "DIV_8_CTL[231],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13A0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[232],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13A4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[233],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13A8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[234],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13AC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[235],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13B0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[236],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13B4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[237],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13B8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[238],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13BC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[239],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13C0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[240],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13C4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[241],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13C8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[242],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13CC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[243],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13D0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[244],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13D4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[245],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13D8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[246],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13DC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[247],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13E0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[248],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13E4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[249],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13E8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[250],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13EC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[251],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13F0)++0x03
|
|
line.long 0x00 "DIV_8_CTL[252],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13F4)++0x03
|
|
line.long 0x00 "DIV_8_CTL[253],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13F8)++0x03
|
|
line.long 0x00 "DIV_8_CTL[254],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x13FC)++0x03
|
|
line.long 0x00 "DIV_8_CTL[255],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1400)++0x03
|
|
line.long 0x00 "DIV_16_CTL[0],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1404)++0x03
|
|
line.long 0x00 "DIV_16_CTL[1],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1408)++0x03
|
|
line.long 0x00 "DIV_16_CTL[2],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x140C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[3],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1410)++0x03
|
|
line.long 0x00 "DIV_16_CTL[4],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1414)++0x03
|
|
line.long 0x00 "DIV_16_CTL[5],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1418)++0x03
|
|
line.long 0x00 "DIV_16_CTL[6],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x141C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[7],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1420)++0x03
|
|
line.long 0x00 "DIV_16_CTL[8],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1424)++0x03
|
|
line.long 0x00 "DIV_16_CTL[9],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1428)++0x03
|
|
line.long 0x00 "DIV_16_CTL[10],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x142C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[11],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1430)++0x03
|
|
line.long 0x00 "DIV_16_CTL[12],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1434)++0x03
|
|
line.long 0x00 "DIV_16_CTL[13],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1438)++0x03
|
|
line.long 0x00 "DIV_16_CTL[14],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x143C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[15],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1440)++0x03
|
|
line.long 0x00 "DIV_16_CTL[16],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1444)++0x03
|
|
line.long 0x00 "DIV_16_CTL[17],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1448)++0x03
|
|
line.long 0x00 "DIV_16_CTL[18],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x144C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[19],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1450)++0x03
|
|
line.long 0x00 "DIV_16_CTL[20],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1454)++0x03
|
|
line.long 0x00 "DIV_16_CTL[21],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1458)++0x03
|
|
line.long 0x00 "DIV_16_CTL[22],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x145C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[23],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1460)++0x03
|
|
line.long 0x00 "DIV_16_CTL[24],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1464)++0x03
|
|
line.long 0x00 "DIV_16_CTL[25],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1468)++0x03
|
|
line.long 0x00 "DIV_16_CTL[26],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x146C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[27],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1470)++0x03
|
|
line.long 0x00 "DIV_16_CTL[28],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1474)++0x03
|
|
line.long 0x00 "DIV_16_CTL[29],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1478)++0x03
|
|
line.long 0x00 "DIV_16_CTL[30],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x147C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[31],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1480)++0x03
|
|
line.long 0x00 "DIV_16_CTL[32],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1484)++0x03
|
|
line.long 0x00 "DIV_16_CTL[33],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1488)++0x03
|
|
line.long 0x00 "DIV_16_CTL[34],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x148C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[35],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1490)++0x03
|
|
line.long 0x00 "DIV_16_CTL[36],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1494)++0x03
|
|
line.long 0x00 "DIV_16_CTL[37],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1498)++0x03
|
|
line.long 0x00 "DIV_16_CTL[38],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x149C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[39],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14A0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[40],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14A4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[41],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14A8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[42],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14AC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[43],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14B0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[44],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14B4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[45],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14B8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[46],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14BC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[47],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14C0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[48],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14C4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[49],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14C8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[50],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14CC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[51],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14D0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[52],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14D4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[53],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14D8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[54],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14DC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[55],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14E0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[56],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14E4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[57],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14E8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[58],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14EC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[59],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14F0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[60],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14F4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[61],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14F8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[62],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x14FC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[63],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1500)++0x03
|
|
line.long 0x00 "DIV_16_CTL[64],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1504)++0x03
|
|
line.long 0x00 "DIV_16_CTL[65],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1508)++0x03
|
|
line.long 0x00 "DIV_16_CTL[66],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x150C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[67],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1510)++0x03
|
|
line.long 0x00 "DIV_16_CTL[68],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1514)++0x03
|
|
line.long 0x00 "DIV_16_CTL[69],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1518)++0x03
|
|
line.long 0x00 "DIV_16_CTL[70],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x151C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[71],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1520)++0x03
|
|
line.long 0x00 "DIV_16_CTL[72],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1524)++0x03
|
|
line.long 0x00 "DIV_16_CTL[73],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1528)++0x03
|
|
line.long 0x00 "DIV_16_CTL[74],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x152C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[75],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1530)++0x03
|
|
line.long 0x00 "DIV_16_CTL[76],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1534)++0x03
|
|
line.long 0x00 "DIV_16_CTL[77],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1538)++0x03
|
|
line.long 0x00 "DIV_16_CTL[78],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x153C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[79],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1540)++0x03
|
|
line.long 0x00 "DIV_16_CTL[80],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1544)++0x03
|
|
line.long 0x00 "DIV_16_CTL[81],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1548)++0x03
|
|
line.long 0x00 "DIV_16_CTL[82],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x154C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[83],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1550)++0x03
|
|
line.long 0x00 "DIV_16_CTL[84],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1554)++0x03
|
|
line.long 0x00 "DIV_16_CTL[85],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1558)++0x03
|
|
line.long 0x00 "DIV_16_CTL[86],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x155C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[87],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1560)++0x03
|
|
line.long 0x00 "DIV_16_CTL[88],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1564)++0x03
|
|
line.long 0x00 "DIV_16_CTL[89],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1568)++0x03
|
|
line.long 0x00 "DIV_16_CTL[90],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x156C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[91],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1570)++0x03
|
|
line.long 0x00 "DIV_16_CTL[92],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1574)++0x03
|
|
line.long 0x00 "DIV_16_CTL[93],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1578)++0x03
|
|
line.long 0x00 "DIV_16_CTL[94],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x157C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[95],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1580)++0x03
|
|
line.long 0x00 "DIV_16_CTL[96],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1584)++0x03
|
|
line.long 0x00 "DIV_16_CTL[97],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1588)++0x03
|
|
line.long 0x00 "DIV_16_CTL[98],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x158C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[99],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1590)++0x03
|
|
line.long 0x00 "DIV_16_CTL[100],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1594)++0x03
|
|
line.long 0x00 "DIV_16_CTL[101],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1598)++0x03
|
|
line.long 0x00 "DIV_16_CTL[102],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x159C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[103],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15A0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[104],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15A4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[105],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15A8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[106],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15AC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[107],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15B0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[108],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15B4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[109],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15B8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[110],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15BC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[111],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15C0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[112],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15C4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[113],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15C8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[114],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15CC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[115],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15D0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[116],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15D4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[117],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15D8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[118],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15DC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[119],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15E0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[120],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15E4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[121],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15E8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[122],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15EC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[123],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15F0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[124],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15F4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[125],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15F8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[126],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x15FC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[127],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1600)++0x03
|
|
line.long 0x00 "DIV_16_CTL[128],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1604)++0x03
|
|
line.long 0x00 "DIV_16_CTL[129],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1608)++0x03
|
|
line.long 0x00 "DIV_16_CTL[130],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x160C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[131],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1610)++0x03
|
|
line.long 0x00 "DIV_16_CTL[132],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1614)++0x03
|
|
line.long 0x00 "DIV_16_CTL[133],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1618)++0x03
|
|
line.long 0x00 "DIV_16_CTL[134],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x161C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[135],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1620)++0x03
|
|
line.long 0x00 "DIV_16_CTL[136],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1624)++0x03
|
|
line.long 0x00 "DIV_16_CTL[137],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1628)++0x03
|
|
line.long 0x00 "DIV_16_CTL[138],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x162C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[139],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1630)++0x03
|
|
line.long 0x00 "DIV_16_CTL[140],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1634)++0x03
|
|
line.long 0x00 "DIV_16_CTL[141],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1638)++0x03
|
|
line.long 0x00 "DIV_16_CTL[142],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x163C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[143],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1640)++0x03
|
|
line.long 0x00 "DIV_16_CTL[144],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1644)++0x03
|
|
line.long 0x00 "DIV_16_CTL[145],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1648)++0x03
|
|
line.long 0x00 "DIV_16_CTL[146],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x164C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[147],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1650)++0x03
|
|
line.long 0x00 "DIV_16_CTL[148],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1654)++0x03
|
|
line.long 0x00 "DIV_16_CTL[149],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1658)++0x03
|
|
line.long 0x00 "DIV_16_CTL[150],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x165C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[151],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1660)++0x03
|
|
line.long 0x00 "DIV_16_CTL[152],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1664)++0x03
|
|
line.long 0x00 "DIV_16_CTL[153],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1668)++0x03
|
|
line.long 0x00 "DIV_16_CTL[154],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x166C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[155],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1670)++0x03
|
|
line.long 0x00 "DIV_16_CTL[156],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1674)++0x03
|
|
line.long 0x00 "DIV_16_CTL[157],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1678)++0x03
|
|
line.long 0x00 "DIV_16_CTL[158],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x167C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[159],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1680)++0x03
|
|
line.long 0x00 "DIV_16_CTL[160],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1684)++0x03
|
|
line.long 0x00 "DIV_16_CTL[161],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1688)++0x03
|
|
line.long 0x00 "DIV_16_CTL[162],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x168C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[163],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1690)++0x03
|
|
line.long 0x00 "DIV_16_CTL[164],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1694)++0x03
|
|
line.long 0x00 "DIV_16_CTL[165],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1698)++0x03
|
|
line.long 0x00 "DIV_16_CTL[166],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x169C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[167],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16A0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[168],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16A4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[169],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16A8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[170],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16AC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[171],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16B0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[172],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16B4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[173],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16B8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[174],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16BC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[175],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16C0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[176],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16C4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[177],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16C8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[178],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16CC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[179],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16D0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[180],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16D4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[181],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16D8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[182],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16DC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[183],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16E0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[184],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16E4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[185],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16E8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[186],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16EC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[187],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16F0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[188],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16F4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[189],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16F8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[190],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x16FC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[191],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1700)++0x03
|
|
line.long 0x00 "DIV_16_CTL[192],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1704)++0x03
|
|
line.long 0x00 "DIV_16_CTL[193],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1708)++0x03
|
|
line.long 0x00 "DIV_16_CTL[194],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x170C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[195],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1710)++0x03
|
|
line.long 0x00 "DIV_16_CTL[196],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1714)++0x03
|
|
line.long 0x00 "DIV_16_CTL[197],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1718)++0x03
|
|
line.long 0x00 "DIV_16_CTL[198],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x171C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[199],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1720)++0x03
|
|
line.long 0x00 "DIV_16_CTL[200],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1724)++0x03
|
|
line.long 0x00 "DIV_16_CTL[201],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1728)++0x03
|
|
line.long 0x00 "DIV_16_CTL[202],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x172C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[203],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1730)++0x03
|
|
line.long 0x00 "DIV_16_CTL[204],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1734)++0x03
|
|
line.long 0x00 "DIV_16_CTL[205],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1738)++0x03
|
|
line.long 0x00 "DIV_16_CTL[206],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x173C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[207],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1740)++0x03
|
|
line.long 0x00 "DIV_16_CTL[208],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1744)++0x03
|
|
line.long 0x00 "DIV_16_CTL[209],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1748)++0x03
|
|
line.long 0x00 "DIV_16_CTL[210],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x174C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[211],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1750)++0x03
|
|
line.long 0x00 "DIV_16_CTL[212],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1754)++0x03
|
|
line.long 0x00 "DIV_16_CTL[213],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1758)++0x03
|
|
line.long 0x00 "DIV_16_CTL[214],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x175C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[215],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1760)++0x03
|
|
line.long 0x00 "DIV_16_CTL[216],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1764)++0x03
|
|
line.long 0x00 "DIV_16_CTL[217],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1768)++0x03
|
|
line.long 0x00 "DIV_16_CTL[218],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x176C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[219],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1770)++0x03
|
|
line.long 0x00 "DIV_16_CTL[220],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1774)++0x03
|
|
line.long 0x00 "DIV_16_CTL[221],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1778)++0x03
|
|
line.long 0x00 "DIV_16_CTL[222],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x177C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[223],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1780)++0x03
|
|
line.long 0x00 "DIV_16_CTL[224],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1784)++0x03
|
|
line.long 0x00 "DIV_16_CTL[225],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1788)++0x03
|
|
line.long 0x00 "DIV_16_CTL[226],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x178C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[227],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1790)++0x03
|
|
line.long 0x00 "DIV_16_CTL[228],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1794)++0x03
|
|
line.long 0x00 "DIV_16_CTL[229],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1798)++0x03
|
|
line.long 0x00 "DIV_16_CTL[230],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x179C)++0x03
|
|
line.long 0x00 "DIV_16_CTL[231],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17A0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[232],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17A4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[233],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17A8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[234],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17AC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[235],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17B0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[236],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17B4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[237],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17B8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[238],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17BC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[239],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17C0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[240],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17C4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[241],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17C8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[242],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17CC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[243],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17D0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[244],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17D4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[245],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17D8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[246],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17DC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[247],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17E0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[248],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17E4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[249],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17E8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[250],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17EC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[251],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17F0)++0x03
|
|
line.long 0x00 "DIV_16_CTL[252],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17F4)++0x03
|
|
line.long 0x00 "DIV_16_CTL[253],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17F8)++0x03
|
|
line.long 0x00 "DIV_16_CTL[254],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x17FC)++0x03
|
|
line.long 0x00 "DIV_16_CTL[255],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1800)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[0],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1804)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[1],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1808)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[2],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x180C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[3],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1810)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[4],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1814)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[5],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1818)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[6],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x181C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[7],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1820)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[8],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1824)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[9],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1828)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[10],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x182C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[11],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1830)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[12],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1834)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[13],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1838)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[14],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x183C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[15],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1840)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[16],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1844)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[17],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1848)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[18],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x184C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[19],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1850)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[20],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1854)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[21],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1858)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[22],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x185C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[23],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1860)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[24],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1864)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[25],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1868)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[26],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x186C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[27],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1870)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[28],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1874)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[29],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1878)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[30],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x187C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[31],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1880)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[32],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1884)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[33],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1888)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[34],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x188C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[35],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1890)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[36],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1894)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[37],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1898)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[38],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x189C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[39],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18A0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[40],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18A4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[41],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18A8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[42],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18AC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[43],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18B0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[44],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18B4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[45],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18B8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[46],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18BC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[47],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18C0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[48],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18C4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[49],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18C8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[50],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18CC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[51],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18D0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[52],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18D4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[53],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18D8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[54],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18DC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[55],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18E0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[56],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18E4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[57],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18E8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[58],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18EC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[59],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18F0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[60],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18F4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[61],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18F8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[62],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x18FC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[63],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1900)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[64],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1904)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[65],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1908)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[66],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x190C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[67],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1910)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[68],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1914)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[69],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1918)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[70],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x191C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[71],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1920)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[72],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1924)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[73],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1928)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[74],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x192C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[75],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1930)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[76],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1934)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[77],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1938)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[78],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x193C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[79],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1940)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[80],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1944)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[81],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1948)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[82],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x194C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[83],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1950)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[84],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1954)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[85],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1958)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[86],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x195C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[87],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1960)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[88],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1964)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[89],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1968)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[90],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x196C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[91],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1970)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[92],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1974)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[93],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1978)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[94],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x197C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[95],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1980)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[96],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1984)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[97],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1988)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[98],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x198C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[99],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1990)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[100],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1994)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[101],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1998)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[102],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x199C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[103],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19A0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[104],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19A4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[105],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19A8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[106],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19AC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[107],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19B0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[108],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19B4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[109],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19B8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[110],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19BC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[111],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19C0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[112],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19C4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[113],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19C8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[114],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19CC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[115],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19D0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[116],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19D4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[117],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19D8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[118],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19DC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[119],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19E0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[120],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19E4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[121],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19E8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[122],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19EC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[123],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19F0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[124],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19F4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[125],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19F8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[126],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x19FC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[127],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A00)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[128],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A04)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[129],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A08)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[130],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A0C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[131],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A10)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[132],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A14)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[133],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A18)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[134],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A1C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[135],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A20)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[136],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A24)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[137],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A28)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[138],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A2C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[139],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A30)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[140],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A34)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[141],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A38)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[142],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A3C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[143],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A40)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[144],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A44)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[145],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A48)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[146],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A4C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[147],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A50)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[148],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A54)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[149],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A58)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[150],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A5C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[151],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A60)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[152],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A64)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[153],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A68)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[154],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A6C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[155],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A70)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[156],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A74)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[157],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A78)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[158],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A7C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[159],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A80)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[160],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A84)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[161],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A88)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[162],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A8C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[163],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A90)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[164],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A94)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[165],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A98)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[166],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1A9C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[167],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AA0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[168],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AA4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[169],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AA8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[170],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AAC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[171],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AB0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[172],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AB4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[173],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AB8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[174],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1ABC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[175],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AC0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[176],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AC4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[177],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AC8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[178],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1ACC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[179],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AD0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[180],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AD4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[181],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AD8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[182],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1ADC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[183],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AE0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[184],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AE4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[185],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AE8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[186],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AEC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[187],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AF0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[188],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AF4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[189],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AF8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[190],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1AFC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[191],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B00)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[192],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B04)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[193],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B08)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[194],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B0C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[195],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B10)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[196],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B14)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[197],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B18)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[198],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B1C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[199],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B20)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[200],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B24)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[201],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B28)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[202],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B2C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[203],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B30)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[204],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B34)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[205],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B38)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[206],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B3C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[207],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B40)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[208],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B44)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[209],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B48)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[210],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B4C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[211],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B50)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[212],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B54)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[213],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B58)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[214],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B5C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[215],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B60)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[216],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B64)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[217],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B68)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[218],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B6C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[219],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B70)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[220],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B74)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[221],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B78)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[222],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B7C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[223],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B80)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[224],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B84)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[225],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B88)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[226],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B8C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[227],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B90)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[228],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B94)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[229],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B98)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[230],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1B9C)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[231],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BA0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[232],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BA4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[233],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BA8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[234],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BAC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[235],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BB0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[236],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BB4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[237],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BB8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[238],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BBC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[239],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BC0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[240],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BC4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[241],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BC8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[242],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BCC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[243],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BD0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[244],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BD4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[245],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BD8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[246],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BDC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[247],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BE0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[248],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BE4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[249],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BE8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[250],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BEC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[251],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BF0)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[252],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BF4)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[253],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BF8)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[254],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1BFC)++0x03
|
|
line.long 0x00 "DIV_16_5_CTL[255],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C00)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[0],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C04)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[1],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C08)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[2],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C0C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[3],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C10)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[4],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C14)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[5],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C18)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[6],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C1C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[7],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C20)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[8],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C24)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[9],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C28)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[10],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C2C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[11],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C30)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[12],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C34)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[13],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C38)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[14],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C3C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[15],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C40)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[16],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C44)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[17],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C48)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[18],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C4C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[19],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C50)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[20],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C54)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[21],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C58)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[22],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C5C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[23],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C60)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[24],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C64)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[25],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C68)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[26],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C6C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[27],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C70)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[28],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C74)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[29],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C78)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[30],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C7C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[31],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C80)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[32],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C84)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[33],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C88)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[34],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C8C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[35],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C90)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[36],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C94)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[37],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C98)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[38],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1C9C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[39],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CA0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[40],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CA4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[41],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CA8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[42],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CAC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[43],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CB0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[44],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CB4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[45],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CB8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[46],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CBC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[47],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CC0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[48],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CC4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[49],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CC8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[50],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CCC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[51],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CD0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[52],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CD4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[53],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CD8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[54],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CDC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[55],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CE0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[56],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CE4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[57],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CE8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[58],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CEC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[59],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CF0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[60],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CF4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[61],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CF8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[62],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1CFC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[63],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D00)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[64],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D04)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[65],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D08)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[66],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D0C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[67],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D10)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[68],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D14)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[69],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D18)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[70],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D1C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[71],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D20)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[72],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D24)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[73],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D28)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[74],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D2C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[75],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D30)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[76],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D34)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[77],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D38)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[78],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D3C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[79],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D40)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[80],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D44)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[81],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D48)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[82],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D4C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[83],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D50)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[84],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D54)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[85],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D58)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[86],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D5C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[87],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D60)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[88],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D64)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[89],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D68)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[90],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D6C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[91],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D70)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[92],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D74)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[93],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D78)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[94],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D7C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[95],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D80)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[96],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D84)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[97],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D88)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[98],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D8C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[99],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D90)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[100],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D94)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[101],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D98)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[102],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1D9C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[103],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DA0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[104],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DA4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[105],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DA8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[106],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DAC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[107],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DB0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[108],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DB4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[109],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DB8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[110],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DBC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[111],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DC0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[112],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DC4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[113],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DC8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[114],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DCC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[115],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DD0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[116],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DD4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[117],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DD8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[118],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DDC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[119],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DE0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[120],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DE4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[121],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DE8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[122],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DEC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[123],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DF0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[124],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DF4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[125],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DF8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[126],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1DFC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[127],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E00)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[128],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E04)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[129],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E08)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[130],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E0C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[131],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E10)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[132],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E14)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[133],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E18)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[134],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E1C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[135],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E20)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[136],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E24)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[137],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E28)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[138],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E2C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[139],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E30)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[140],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E34)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[141],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E38)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[142],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E3C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[143],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E40)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[144],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E44)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[145],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E48)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[146],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E4C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[147],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E50)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[148],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E54)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[149],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E58)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[150],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E5C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[151],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E60)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[152],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E64)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[153],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E68)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[154],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E6C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[155],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E70)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[156],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E74)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[157],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E78)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[158],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E7C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[159],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E80)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[160],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E84)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[161],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E88)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[162],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E8C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[163],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E90)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[164],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E94)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[165],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E98)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[166],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1E9C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[167],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EA0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[168],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EA4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[169],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EA8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[170],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EAC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[171],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EB0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[172],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EB4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[173],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EB8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[174],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EBC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[175],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EC0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[176],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EC4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[177],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EC8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[178],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1ECC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[179],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1ED0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[180],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1ED4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[181],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1ED8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[182],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EDC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[183],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EE0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[184],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EE4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[185],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EE8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[186],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EEC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[187],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EF0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[188],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EF4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[189],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EF8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[190],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1EFC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[191],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F00)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[192],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F04)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[193],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F08)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[194],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F0C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[195],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F10)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[196],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F14)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[197],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F18)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[198],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F1C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[199],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F20)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[200],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F24)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[201],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F28)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[202],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F2C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[203],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F30)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[204],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F34)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[205],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F38)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[206],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F3C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[207],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F40)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[208],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F44)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[209],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F48)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[210],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F4C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[211],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F50)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[212],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F54)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[213],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F58)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[214],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F5C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[215],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F60)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[216],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F64)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[217],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F68)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[218],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F6C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[219],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F70)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[220],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F74)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[221],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F78)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[222],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F7C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[223],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F80)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[224],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F84)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[225],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F88)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[226],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F8C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[227],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F90)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[228],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F94)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[229],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F98)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[230],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1F9C)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[231],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FA0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[232],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FA4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[233],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FA8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[234],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FAC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[235],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FB0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[236],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FB4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[237],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FB8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[238],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FBC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[239],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FC0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[240],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FC4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[241],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FC8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[242],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FCC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[243],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FD0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[244],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FD4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[245],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FD8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[246],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FDC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[247],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FE0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[248],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FE4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[249],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FE8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[250],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FEC)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[251],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FF0)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[252],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FF4)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[253],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
group.long ($2+0x1FF8)++0x03
|
|
line.long 0x00 "DIV_24_5_CTL[254],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
|
|
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PROT (Protection)"
|
|
base ad:0x40230000
|
|
tree "SMPU"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MS0_CTL,Master 0 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,Protection context mask for protection contexts '15' down to '1'"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,Protection context mask for protection context '0'" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,Device wide bus arbitration priority setting ('0': highest priority '3': lowest priority)" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,Security setting ('0': secure mode '1': non-secure mode)" "0,1"
|
|
bitfld.long 0x00 0. "P,Privileged setting ('0': user mode '1': privileged mode)" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MS1_CTL,Master 1 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MS2_CTL,Master 2 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MS3_CTL,Master 3 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MS4_CTL,Master 4 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MS5_CTL,Master 5 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MS6_CTL,Master 6 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MS7_CTL,Master 7 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MS8_CTL,Master 8 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MS9_CTL,Master 9 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MS10_CTL,Master 10 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MS11_CTL,Master 11 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MS12_CTL,Master 12 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MS13_CTL,Master 13 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MS14_CTL,Master 14 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MS15_CTL,Master 15 protection context control"
|
|
hexmask.long.word 0x00 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1"
|
|
rbitfld.long 0x00 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0" "0,1"
|
|
bitfld.long 0x00 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x00 1. "NS,See MS0_CTL.NS" "0,1"
|
|
bitfld.long 0x00 0. "P,See MS0_CTL.P" "0,1"
|
|
repeat 16. (increment 0 1)(increment 0 0x40)
|
|
tree "SMPU_STRUCT[$1]"
|
|
group.long ($2+0x2000)++0x03
|
|
line.long 0x00 "ADDR0,SMPU region address 0 (slave structure)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region"
|
|
abitfld.long 0x00 0.--7. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned" "0x00=0: subregion 0 disable,0x01=1: subregion 1 disable,0x02=2: subregion 2 disable,0x03=3: subregion 3 disable,0x04=4: subregion 4 disable,0x05=5: subregion 5 disable,0x06=6: subregion 6 disable,0x07=7: subregion 7 disable"
|
|
group.long ($2+0x2004)++0x03
|
|
line.long 0x00 "ATT0,SMPU region attributes 0 (slave structure)"
|
|
bitfld.long 0x00 31. "ENABLED,Region enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the region size: '0'-'6': Undefined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control"
|
|
rbitfld.long 0x00 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'" "0,1"
|
|
bitfld.long 0x00 6. "NS,Non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PX,Privileged execute enable: '0': Disabled (privileged execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 4. "PW,Privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 3. "PR,Privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 2. "UX,User execute enable: '0': Disabled (user execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 1. "UW,User write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 0. "UR,User read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
rgroup.long ($2+0x2020)++0x03
|
|
line.long 0x00 "ADDR1,SMPU region address 1 (master structure)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region"
|
|
abitfld.long 0x00 0.--7. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned" "0x00=0: subregion 0 disable,0x01=1: subregion 1 disable,0x02=2: subregion 2 disable,0x03=3: subregion 3 disable,0x04=4: subregion 4 disable,0x05=5: subregion 5 disable,0x06=6: subregion 6 disable,0x07=7: subregion 7 disable"
|
|
group.long ($2+0x2024)++0x03
|
|
line.long 0x00 "ATT1,SMPU region attributes 1 (master structure)"
|
|
bitfld.long 0x00 31. "ENABLED,Region enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'" "0,1"
|
|
rbitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the region size: '7': 256 B region (8 32 B subregions) Note: this field is read-only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control"
|
|
rbitfld.long 0x00 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'" "0,1"
|
|
bitfld.long 0x00 6. "NS,Non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 5. "PX,Privileged execute enable: '0': Disabled (privileged execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 4. "PW,Privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 3. "PR,Privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 2. "UX,User execute enable: '0': Disabled (user execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 1. "UW,User write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
rbitfld.long 0x00 0. "UR,User read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat 16. (increment 0 1)(increment 0 0x400)
|
|
tree "MPU[$1]"
|
|
group.long ($2+0x4000)++0x03
|
|
line.long 0x00 "MS_CTL,Master control"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Saved protection context" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Active protection context (PC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4004)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[0],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4008)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[1],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x400C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[2],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4010)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[3],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4014)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[4],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4018)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[5],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x401C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[6],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4020)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[7],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4024)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[8],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4028)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[9],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x402C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[10],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4030)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[11],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4034)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[12],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4038)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[13],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x403C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[14],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4040)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[15],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4044)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[16],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4048)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[17],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x404C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[18],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4050)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[19],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4054)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[20],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4058)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[21],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x405C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[22],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4060)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[23],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4064)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[24],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4068)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[25],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x406C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[26],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4070)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[27],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4074)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[28],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4078)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[29],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x407C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[30],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4080)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[31],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4084)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[32],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4088)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[33],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x408C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[34],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4090)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[35],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4094)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[36],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4098)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[37],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x409C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[38],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40A0)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[39],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40A4)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[40],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40A8)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[41],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40AC)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[42],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40B0)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[43],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40B4)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[44],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40B8)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[45],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40BC)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[46],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40C0)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[47],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40C4)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[48],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40C8)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[49],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40CC)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[50],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40D0)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[51],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40D4)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[52],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40D8)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[53],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40DC)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[54],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40E0)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[55],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40E4)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[56],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40E8)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[57],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40EC)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[58],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40F0)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[59],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40F4)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[60],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40F8)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[61],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x40FC)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[62],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4100)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[63],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4104)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[64],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4108)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[65],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x410C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[66],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4110)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[67],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4114)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[68],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4118)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[69],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x411C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[70],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4120)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[71],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4124)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[72],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4128)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[73],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x412C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[74],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4130)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[75],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4134)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[76],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4138)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[77],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x413C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[78],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4140)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[79],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4144)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[80],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4148)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[81],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x414C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[82],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4150)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[83],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4154)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[84],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4158)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[85],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x415C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[86],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4160)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[87],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4164)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[88],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4168)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[89],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x416C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[90],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4170)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[91],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4174)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[92],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4178)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[93],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x417C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[94],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4180)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[95],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4184)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[96],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4188)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[97],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x418C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[98],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4190)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[99],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4194)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[100],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x4198)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[101],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x419C)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[102],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41A0)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[103],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41A4)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[104],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41A8)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[105],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41AC)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[106],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41B0)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[107],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41B4)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[108],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41B8)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[109],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41BC)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[110],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41C0)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[111],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41C4)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[112],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41C8)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[113],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41CC)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[114],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41D0)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[115],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41D4)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[116],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41D8)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[117],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41DC)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[118],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41E0)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[119],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41E4)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[120],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41E8)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[121],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41EC)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[122],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41F0)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[123],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41F4)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[124],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41F8)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[125],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long ($2+0x41FC)++0x03
|
|
line.long 0x00 "MS_CTL_READ_MIR[126],Master control read mirror"
|
|
bitfld.long 0x00 16.--19. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC,Read-only mirror of MS_CTL.PC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree "MPU_STRUCT[0]"
|
|
group.long ($2+0x4200)++0x03
|
|
line.long 0x00 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region"
|
|
abitfld.long 0x00 0.--7. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned" "0x00=0: subregion 0 disable,0x01=1: subregion 1 disable,0x02=2: subregion 2 disable,0x03=3: subregion 3 disable,0x04=4: subregion 4 disable,0x05=5: subregion 5 disable,0x06=6: subregion 6 disable,0x07=7: subregion 7 disable"
|
|
group.long ($2+0x4204)++0x03
|
|
line.long 0x00 "ATT,MPU region attrributes"
|
|
bitfld.long 0x00 31. "ENABLED,Region enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the region size: '0'-'6': Undefined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. "NS,Non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
bitfld.long 0x00 5. "PX,Privileged execute enable: '0': Disabled (privileged execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 4. "PW,Privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 3. "PR,Privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UX,User execute enable: '0': Disabled (user execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 1. "UW,User write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 0. "UR,User read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
tree.end
|
|
tree "MPU_STRUCT[1]"
|
|
group.long ($2+0x4220)++0x03
|
|
line.long 0x00 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region"
|
|
abitfld.long 0x00 0.--7. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned" "0x00=0: subregion 0 disable,0x01=1: subregion 1 disable,0x02=2: subregion 2 disable,0x03=3: subregion 3 disable,0x04=4: subregion 4 disable,0x05=5: subregion 5 disable,0x06=6: subregion 6 disable,0x07=7: subregion 7 disable"
|
|
group.long ($2+0x4224)++0x03
|
|
line.long 0x00 "ATT,MPU region attrributes"
|
|
bitfld.long 0x00 31. "ENABLED,Region enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the region size: '0'-'6': Undefined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. "NS,Non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
bitfld.long 0x00 5. "PX,Privileged execute enable: '0': Disabled (privileged execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 4. "PW,Privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 3. "PR,Privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UX,User execute enable: '0': Disabled (user execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 1. "UW,User write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 0. "UR,User read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
tree.end
|
|
tree "MPU_STRUCT[2]"
|
|
group.long ($2+0x4240)++0x03
|
|
line.long 0x00 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region"
|
|
abitfld.long 0x00 0.--7. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned" "0x00=0: subregion 0 disable,0x01=1: subregion 1 disable,0x02=2: subregion 2 disable,0x03=3: subregion 3 disable,0x04=4: subregion 4 disable,0x05=5: subregion 5 disable,0x06=6: subregion 6 disable,0x07=7: subregion 7 disable"
|
|
group.long ($2+0x4244)++0x03
|
|
line.long 0x00 "ATT,MPU region attrributes"
|
|
bitfld.long 0x00 31. "ENABLED,Region enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the region size: '0'-'6': Undefined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. "NS,Non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
bitfld.long 0x00 5. "PX,Privileged execute enable: '0': Disabled (privileged execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 4. "PW,Privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 3. "PR,Privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UX,User execute enable: '0': Disabled (user execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 1. "UW,User write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 0. "UR,User read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
tree.end
|
|
tree "MPU_STRUCT[3]"
|
|
group.long ($2+0x4260)++0x03
|
|
line.long 0x00 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region"
|
|
abitfld.long 0x00 0.--7. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned" "0x00=0: subregion 0 disable,0x01=1: subregion 1 disable,0x02=2: subregion 2 disable,0x03=3: subregion 3 disable,0x04=4: subregion 4 disable,0x05=5: subregion 5 disable,0x06=6: subregion 6 disable,0x07=7: subregion 7 disable"
|
|
group.long ($2+0x4264)++0x03
|
|
line.long 0x00 "ATT,MPU region attrributes"
|
|
bitfld.long 0x00 31. "ENABLED,Region enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the region size: '0'-'6': Undefined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. "NS,Non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
bitfld.long 0x00 5. "PX,Privileged execute enable: '0': Disabled (privileged execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 4. "PW,Privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 3. "PR,Privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UX,User execute enable: '0': Disabled (user execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 1. "UW,User write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 0. "UR,User read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
tree.end
|
|
tree "MPU_STRUCT[4]"
|
|
group.long ($2+0x4280)++0x03
|
|
line.long 0x00 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region"
|
|
abitfld.long 0x00 0.--7. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned" "0x00=0: subregion 0 disable,0x01=1: subregion 1 disable,0x02=2: subregion 2 disable,0x03=3: subregion 3 disable,0x04=4: subregion 4 disable,0x05=5: subregion 5 disable,0x06=6: subregion 6 disable,0x07=7: subregion 7 disable"
|
|
group.long ($2+0x4284)++0x03
|
|
line.long 0x00 "ATT,MPU region attrributes"
|
|
bitfld.long 0x00 31. "ENABLED,Region enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the region size: '0'-'6': Undefined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. "NS,Non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
bitfld.long 0x00 5. "PX,Privileged execute enable: '0': Disabled (privileged execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 4. "PW,Privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 3. "PR,Privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UX,User execute enable: '0': Disabled (user execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 1. "UW,User write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 0. "UR,User read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
tree.end
|
|
tree "MPU_STRUCT[5]"
|
|
group.long ($2+0x42A0)++0x03
|
|
line.long 0x00 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region"
|
|
abitfld.long 0x00 0.--7. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned" "0x00=0: subregion 0 disable,0x01=1: subregion 1 disable,0x02=2: subregion 2 disable,0x03=3: subregion 3 disable,0x04=4: subregion 4 disable,0x05=5: subregion 5 disable,0x06=6: subregion 6 disable,0x07=7: subregion 7 disable"
|
|
group.long ($2+0x42A4)++0x03
|
|
line.long 0x00 "ATT,MPU region attrributes"
|
|
bitfld.long 0x00 31. "ENABLED,Region enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the region size: '0'-'6': Undefined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. "NS,Non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
bitfld.long 0x00 5. "PX,Privileged execute enable: '0': Disabled (privileged execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 4. "PW,Privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 3. "PR,Privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UX,User execute enable: '0': Disabled (user execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 1. "UW,User write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 0. "UR,User read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
tree.end
|
|
tree "MPU_STRUCT[6]"
|
|
group.long ($2+0x42C0)++0x03
|
|
line.long 0x00 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region"
|
|
abitfld.long 0x00 0.--7. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned" "0x00=0: subregion 0 disable,0x01=1: subregion 1 disable,0x02=2: subregion 2 disable,0x03=3: subregion 3 disable,0x04=4: subregion 4 disable,0x05=5: subregion 5 disable,0x06=6: subregion 6 disable,0x07=7: subregion 7 disable"
|
|
group.long ($2+0x42C4)++0x03
|
|
line.long 0x00 "ATT,MPU region attrributes"
|
|
bitfld.long 0x00 31. "ENABLED,Region enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the region size: '0'-'6': Undefined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. "NS,Non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
bitfld.long 0x00 5. "PX,Privileged execute enable: '0': Disabled (privileged execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 4. "PW,Privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 3. "PR,Privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UX,User execute enable: '0': Disabled (user execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 1. "UW,User write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 0. "UR,User read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
tree.end
|
|
tree "MPU_STRUCT[7]"
|
|
group.long ($2+0x42E0)++0x03
|
|
line.long 0x00 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region"
|
|
abitfld.long 0x00 0.--7. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned" "0x00=0: subregion 0 disable,0x01=1: subregion 1 disable,0x02=2: subregion 2 disable,0x03=3: subregion 3 disable,0x04=4: subregion 4 disable,0x05=5: subregion 5 disable,0x06=6: subregion 6 disable,0x07=7: subregion 7 disable"
|
|
group.long ($2+0x42E4)++0x03
|
|
line.long 0x00 "ATT,MPU region attrributes"
|
|
bitfld.long 0x00 31. "ENABLED,Region enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 24.--28. "REGION_SIZE,This field specifies the region size: '0'-'6': Undefined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6. "NS,Non-secure: '0': Secure (secure accesses allowed non-secure access NOT allowed)" "0,1"
|
|
bitfld.long 0x00 5. "PX,Privileged execute enable: '0': Disabled (privileged execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 4. "PW,Privileged write enable: '0': Disabled (privileged write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 3. "PR,Privileged read enable: '0': Disabled (privileged read accesses are NOT allowed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UX,User execute enable: '0': Disabled (user execute accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 1. "UW,User write enable: '0': Disabled (user write accesses are NOT allowed)" "0,1"
|
|
bitfld.long 0x00 0. "UR,User read enable: '0': Disabled (user read accesses are NOT allowed)" "0,1"
|
|
tree.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SCB (Serial Communications Block (SPI/UART/I2C))"
|
|
repeat 11. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.) (list ad:0x40600000 ad:0x40610000 ad:0x40620000 ad:0x40630000 ad:0x40640000 ad:0x40650000 ad:0x40660000 ad:0x40670000 ad:0x40680000 ad:0x40690000 ad:0x406A0000)
|
|
tree "SCB$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic control"
|
|
bitfld.long 0x00 31. "ENABLED,IP enabled ('1') or not ('0')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory" "0: enable clock_scb_en has no effect on ec_busy_pp,1: disable clock_scb_en enable ec_busy_pp (grant"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode,1: Serial Peripheral Interface (SPI) mode,2: Universal Asynchronous Receiver/Transmitter..,?..."
|
|
newline
|
|
bitfld.long 0x00 17. "BLOCK,Only used in externally clocked mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element" "0: 8-bit FIFO data elements,1: 16-bit FIFO data elements,2: 32-bit FIFO data elements,3: RSVD"
|
|
newline
|
|
bitfld.long 0x00 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "OVS,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic status"
|
|
bitfld.long 0x00 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x00 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x00 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x00 31. "MASTER_MODE,Master ('1') or slave ('0') mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals" "0: Slave 0 SSEL[0],1: Slave 1 SSEL[1],2: Slave 2 SSEL[2],3: Slave 3 SSEL[3]"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "MODE,N/A" "0: SPI Motorola submode,1: SPI Texas Instruments submode,2: SPI National Semiconductors submode,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "SSEL_POLARITY3,Slave select polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "SSEL_POLARITY2,Slave select polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SSEL_POLARITY1,Slave select polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "SSEL_POLARITY0,Slave select polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SCLK_CONTINUOUS,Only applicable in master mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CPOL,Indicates the clock polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CPHA,Indicates the clock phase" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0')" "0,1"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address"
|
|
newline
|
|
bitfld.long 0x00 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BUS_BUSY,SPI bus is busy" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SPI_RX_CTRL,SPI receiver control"
|
|
bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "UART_CTRL,UART control"
|
|
bitfld.long 0x00 24.--25. "MODE,N/A" "0: Standard UART submode,1: SmartCard (ISO7816) submode,2: Infrared Data Association (IrDA) submode,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x00 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "UART_RX_CTRL,UART receiver control"
|
|
bitfld.long 0x00 24. "BREAK_LEVEL," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "BREAK_WIDTH,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 13. "SKIP_START,Only applicable in standard UART submode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "LIN_MODE,Only applicable in standard UART submode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "MP_MODE,Multi-processor mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x00 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x00 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x00 31. "MASTER_MODE,Master mode enabled ('1') or not ('0')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only" "0: clock stretching is performed (till the..,1: a received data element byte the slave is"
|
|
newline
|
|
bitfld.long 0x00 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0')" "0: clock stretching is performed (till the,1: a received (matching or general) slave address"
|
|
newline
|
|
bitfld.long 0x00 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address"
|
|
newline
|
|
bitfld.long 0x00 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BUS_BUSY,I2C bus is busy" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x00 4. "M_STOP,When '1' attempt to transmit a STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "M_START,When '1' transmit a START or REPEATED START" "0,1"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "I2C_S_CMD,I2C slave command"
|
|
bitfld.long 0x00 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x00 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay: '0': 0 ns" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay: '0': 0 ns" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x00 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "TX_FIFO_CTRL,Transmitter FIFO control"
|
|
bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO status"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware"
|
|
newline
|
|
bitfld.long 0x00 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0')" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the transmitter FIFO"
|
|
wgroup.long 0x240++0x03
|
|
line.long 0x00 "TX_FIFO_WR,Transmitter FIFO"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Data frame written into the transmitter FIFO"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x00 9. "MEDIAN,Median filter" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is"
|
|
newline
|
|
bitfld.long 0x00 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0')" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the receiver FIFO"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MASK,Slave device address mask"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "ADDR,Slave device address"
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "RX_FIFO_RD,Receiver FIFO"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Data read from the receiver FIFO"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Data read from the receiver FIFO"
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x00 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0" "0,1"
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
|
|
group.long 0xE88++0x03
|
|
line.long 0x00 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long 0xE8C++0x03
|
|
line.long 0x00 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
|
|
group.long 0xEC0++0x03
|
|
line.long 0x00 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
|
|
group.long 0xEC8++0x03
|
|
line.long 0x00 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long 0xECC++0x03
|
|
line.long 0x00 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x00 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "I2C_STOP,I2C master STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "I2C_ACK,I2C master acknowledgement" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "I2C_NACK,I2C master negative acknowledgement" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line" "0,1"
|
|
group.long 0xF04++0x03
|
|
line.long 0x00 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x00 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long 0xF08++0x03
|
|
line.long 0x00 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x00 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long 0xF0C++0x03
|
|
line.long 0x00 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x00 9. "SPI_DONE,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
|
|
group.long 0xF40++0x03
|
|
line.long 0x00 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x00 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "I2C_GENERAL,I2C slave general call address received" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "I2C_ADDR_MATCH,I2C slave matching address received" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "I2C_START,I2C slave START received" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "I2C_ACK,I2C slave acknowledgement received" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "I2C_NACK,I2C slave negative acknowledgement received" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1')" "0,1"
|
|
group.long 0xF44++0x03
|
|
line.long 0x00 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x00 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long 0xF48++0x03
|
|
line.long 0x00 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x00 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "I2C_START,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long 0xF4C++0x03
|
|
line.long 0x00 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x00 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "I2C_GENERAL,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "I2C_START,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
|
|
group.long 0xF80++0x03
|
|
line.long 0x00 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x00 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "UART_DONE,UART transmitter done event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full TX FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "EMPTY,TX FIFO is empty i.e" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "NOT_FULL,TX FIFO is not full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL" "0,1"
|
|
group.long 0xF84++0x03
|
|
line.long 0x00 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x00 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long 0xF88++0x03
|
|
line.long 0x00 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x00 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long 0xF8C++0x03
|
|
line.long 0x00 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x00 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "UART_DONE,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "UART_NACK,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "EMPTY,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "NOT_FULL,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
|
|
group.long 0xFC0++0x03
|
|
line.long 0x00 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x00 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "BAUD_DETECT,LIN baudrate detection is completed" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PARITY_ERROR,Parity error in received data frame" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "FRAME_ERROR,Frame error in received data frame" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full RX FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "FULL,RX FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "NOT_EMPTY,RX FIFO is not empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL" "0,1"
|
|
group.long 0xFC4++0x03
|
|
line.long 0x00 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x00 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "FULL,Write with '1' to set corresponding bit in interrupt status register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long 0xFC8++0x03
|
|
line.long 0x00 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x00 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x00 11. "BREAK_DETECT,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "BAUD_DETECT,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PARITY_ERROR,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "FRAME_ERROR,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "FULL,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SDHC0 (SD/eMMC Host Controller)"
|
|
base ad:0x40460000
|
|
tree "WRAP"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Top level wrapper control"
|
|
bitfld.long 0x00 31. "ENABLE,IP Enable" "0: IP disabled RAM in DeepSleep SDHC_CORE regs are,1: IP enabled normal operation"
|
|
tree.end
|
|
tree "CORE"
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "SDMASA_R,SDMA System Address register"
|
|
hexmask.long 0x00 0.--31. 1. "BLOCKCNT_SDMASA,32-bit Block Count (SDMA System Address) - SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode"
|
|
group.word 0x1004++0x01
|
|
line.word 0x00 "BLOCKSIZE_R,Block Size register"
|
|
bitfld.word 0x00 12.--14. "SDMA_BUF_BDARY,SDMA Buffer Boundary These bits specify the size of contiguous buffer in system memory" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
abitfld.word 0x00 0.--11. "XFER_BLOCK_SIZE,Transfer Block Size These bits specify the block size of data transfers" "0x001=1: 1 byte,0x002=2: 2 bytes,0x003=3: 3 bytes,0x1FF=511: 511 byte,0x200=512: 512 bytes,0x800=2048: 2048 bytes"
|
|
group.word 0x1006++0x01
|
|
line.word 0x00 "BLOCKCOUNT_R,16-bit Block Count register"
|
|
abitfld.word 0x00 0.--15. "BLOCK_CNT,16-bit Block Count - If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero the 16-bit Block Count register is selected" "0x0000=0: Stop Count,0x0001=1: 1 Block,0x0002=2: 2 Blocks,0xFFFF=65535: 65535 Blocks"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "ARGUMENT_R,Argument register"
|
|
hexmask.long 0x00 0.--31. 1. "ARGUMENT,Command Argument These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format"
|
|
group.word 0x100C++0x01
|
|
line.word 0x00 "XFER_MODE_R,Transfer Mode register"
|
|
bitfld.word 0x00 8. "RESP_INT_DISABLE,Response Interrupt Disable The Host Controller supports response check function to avoid overhead of response error check by the Host driver" "0,1"
|
|
newline
|
|
bitfld.word 0x00 7. "RESP_ERR_CHK_ENABLE,Response Error Check Enable The Host Controller supports response check function to avoid overhead of response error check by Host driver" "0,1"
|
|
newline
|
|
bitfld.word 0x00 6. "RESP_TYPE,Response Type R1/R5 This bit selects either R1 or R5 as a response type when the Response Error Check is selected" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MULTI_BLK_SEL,Multi/Single Block Select This bit is set when issuing multiple-block transfer commands using the DAT line" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. "DATA_XFER_DIR,Data Transfer Direction Select This bit defines the direction of DAT line data transfers" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2.--3. "AUTO_CMD_ENABLE,Auto Command Enable This field determines use of Auto Command functions" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 1. "BLOCK_COUNT_ENABLE,Block Count Enable This bit is used to enable the Block Count register which is relevant for multiple block transfers" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0. "DMA_ENABLE,DMA Enable This bit enables the DMA functionality" "0,1"
|
|
group.word 0x100E++0x01
|
|
line.word 0x00 "CMD_R,Command register"
|
|
bitfld.word 0x00 8.--13. "CMD_INDEX,Command Index These bits are set to the command number that is specified in bits 45-40 of the Command Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.word 0x00 6.--7. "CMD_TYPE,Command Type These bits indicate the command type" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x00 5. "DATA_PRESENT_SEL,Data Present Select This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line" "0,1"
|
|
newline
|
|
bitfld.word 0x00 4. "CMD_IDX_CHK_ENABLE,Command Index Check Enable This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. "CMD_CRC_CHK_ENABLE,Command CRC Check Enable This bit enables the Host Controller to check the CRC field in the response" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. "SUB_CMD_FLAG,Sub Command Flag This bit distinguishes between a main command and a sub command" "0,1"
|
|
newline
|
|
bitfld.word 0x00 0.--1. "RESP_TYPE_SELECT,Response Type Select This bit indicates the type of response expected from the card" "0,1,2,3"
|
|
rgroup.long 0x1010++0x03
|
|
line.long 0x00 "RESP01_R,Response Register 0/1"
|
|
hexmask.long 0x00 0.--31. 1. "RESP01,Command Response These bits reflect 39-8 bits of SD/eMMC Response Field"
|
|
rgroup.long 0x1014++0x03
|
|
line.long 0x00 "RESP23_R,Response Register 2/3"
|
|
hexmask.long 0x00 0.--31. 1. "RESP23,Command Response These bits reflect 71-40 bits of the SD/eMMC Response"
|
|
rgroup.long 0x1018++0x03
|
|
line.long 0x00 "RESP45_R,Response Register 4/5"
|
|
hexmask.long 0x00 0.--31. 1. "RESP45,Command Response These bits reflect 103-72 bits of the Response Field"
|
|
rgroup.long 0x101C++0x03
|
|
line.long 0x00 "RESP67_R,Response Register 6/7"
|
|
hexmask.long 0x00 0.--31. 1. "RESP67,Command Response These bits reflect bits 135-104 of SD/EMMC Response Field"
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "BUF_DATA_R,Buffer Data Port Register"
|
|
hexmask.long 0x00 0.--31. 1. "BUF_DATA,Buffer Data These bits enable access to the Host Controller packet buffer"
|
|
rgroup.long 0x1024++0x03
|
|
line.long 0x00 "PSTATE_REG,Present State Register"
|
|
bitfld.long 0x00 28. "SUB_CMD_STAT,Sub Command Status This bit is used to distinguish between a main command and a sub command status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "CMD_ISSU_ERR,Command Not Issued by Error This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "HOST_REG_VOL,Host Regulator Voltage Stable This bit is used to check whether the host regulator voltage is stable for switching the voltage of UHS-I mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "CMD_LINE_LVL,Command-Line Signal Level This bit is used to check the CMD line level to recover from errors and for debugging" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DAT_3_0,DAT[3:0] Line Signal Level This bit is used to check the DAT line level to recover from errors and for debugging" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "WR_PROTECT_SW_LVL,Write Protect Switch Pin Level This bit is supported only for memory and combo cards" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CARD_DETECT_PIN_LEVEL,Card Detect Pin Level This bit reflects the inverse synchronized value of the card_detect_n signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CARD_STABLE,Card Stable This bit indicates the stability of the Card Detect Pin Level" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CARD_INSERTED,Card Inserted This bit indicates whether a card has been inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BUF_RD_ENABLE,Buffer Read Enable This bit is used for non-DMA transfers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "BUF_WR_ENABLE,Buffer Write Enable This bit is used for non-DMA transfers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "RD_XFER_ACTIVE,Read Transfer Active This bit indicates whether a read transfer is active for SD/eMMC mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "WR_XFER_ACTIVE,Write Transfer Active This status indicates whether a write transfer is active for SD/eMMC mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DAT_7_4,DAT[7:4] Line Signal Level This bit is used to check the DAT line level to recover from errors and for debugging" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2. "DAT_LINE_ACTIVE,DAT Line Active (SD/eMMC Mode only) This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CMD_INHIBIT_DAT,Command Inhibit (DAT) This bit is applicable for SD/eMMC mode and is generated if either DAT line active or Read transfer active is set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CMD_INHIBIT,Command Inhibit (CMD) This bit indicates the following : - SD/eMMC mode: If this bit is set to 0 it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line" "0,1"
|
|
group.byte 0x1028++0x00
|
|
line.byte 0x00 "HOST_CTRL1_R,Host Control 1 Register"
|
|
bitfld.byte 0x00 7. "CARD_DETECT_SIG_SEL,Card Detect Signal Selection This bit selects a source for card detection" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 6. "CARD_DETECT_TEST_LVL,Card Detect Test Level This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates whether a card inserted or not" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "EXT_DAT_XFER,Extended Data Transfer Width This bit controls 8-bit bus width mode of embedded device" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3.--4. "DMA_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x00 2. "HIGH_SPEED_EN,High Speed Enable (SD/eMMC Mode only) Before setting this bit the Host Driver checks the High Speed Support in the Capabilities register" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "DAT_XFER_WIDTH,Data Transfer Width For SD/eMMC mode this bit selects the data transfer width of the Host Controller" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "LED_CTRL,LED Control This bit is used to caution the user not to remove the card while the SD card is being accessed" "0,1"
|
|
group.byte 0x1029++0x00
|
|
line.byte 0x00 "PWR_CTRL_R,Power Control Register"
|
|
bitfld.byte 0x00 1.--3. "SD_BUS_VOL_VDD1,These bits are NON-operational (they can be written and read but they have no effect)" "0,1,2,3,4,5,6,7"
|
|
newline
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bitfld.byte 0x00 0. "SD_BUS_PWR_VDD1,SD Bus Power for VDD1 This bit enables VDD1 power of the card" "0,1"
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group.byte 0x102A++0x00
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line.byte 0x00 "BGAP_CTRL_R,Block Gap Control Register"
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bitfld.byte 0x00 3. "INT_AT_BGAP,Interrupt At Block Gap This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle" "0,1"
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newline
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bitfld.byte 0x00 2. "RD_WAIT_CTRL,N/A" "0,1"
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newline
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bitfld.byte 0x00 1. "CONTINUE_REQ,Continue Request This bit is used to restart the transaction which was stopped using the Stop At Block Gap Request" "0,1"
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newline
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bitfld.byte 0x00 0. "STOP_BG_REQ,Stop At Block Gap Request This bit is used to stop executing read and write transactions at the next block gap for non-DMA SDMA and ADMA transfers" "0,1"
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group.byte 0x102B++0x00
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line.byte 0x00 "WUP_CTRL_R,Wakeup Control Register"
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bitfld.byte 0x00 2. "WUP_CARD_REMOVAL,Wakeup Event Enable on SD Card Removal This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register" "0,1"
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newline
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bitfld.byte 0x00 1. "WUP_CARD_INSERT,Wakeup Event Enable on SD Card Insertion This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register" "0,1"
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newline
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bitfld.byte 0x00 0. "WUP_CARD_INT,Wakeup Event Enable on SDIO Card Interrupt (through DAT[1])" "0,1"
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group.word 0x102C++0x01
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line.word 0x00 "CLK_CTRL_R,Clock Control Register"
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hexmask.word.byte 0x00 8.--15. 1. "FREQ_SEL,SDCLK Frequency Select These bits are used to select the frequency of the SDCLK signal"
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newline
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bitfld.word 0x00 6.--7. "UPPER_FREQ_SEL,These bits specify the upper 2 bits of 10-bit SDCLK Frequency Select control" "0,1,2,3"
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newline
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bitfld.word 0x00 5. "CLK_GEN_SELECT,Clock Generator Select This bit is used to select the clock generator mode in SDCLK Frequency Select" "0,1"
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newline
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bitfld.word 0x00 3. "PLL_ENABLE,PLL Enable This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1)" "0,1"
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newline
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bitfld.word 0x00 2. "SD_CLK_EN,SD/eMMC Clock Enable This bit stops the clk_card output when set to 0" "0,1"
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newline
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rbitfld.word 0x00 1. "INTERNAL_CLK_STABLE,Internal Clock Stable This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set" "0,1"
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newline
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bitfld.word 0x00 0. "INTERNAL_CLK_EN,Internal Clock Enable This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt" "0,1"
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group.byte 0x102E++0x00
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line.byte 0x00 "TOUT_CTRL_R,Timeout Control Register"
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bitfld.byte 0x00 0.--3. "TOUT_CNT,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.byte 0x102F++0x00
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line.byte 0x00 "SW_RST_R,Software Reset Register"
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bitfld.byte 0x00 2. "SW_RST_DAT,Software Reset For DAT line This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset" "0,1"
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newline
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bitfld.byte 0x00 1. "SW_RST_CMD,Software Reset For CMD line This bit resets only a part of the command circuit to be able to issue a command" "0,1"
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newline
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bitfld.byte 0x00 0. "SW_RST_ALL,Software Reset For All This reset affects the entire Host Controller except for the card detection circuit" "0,1"
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group.word 0x1030++0x01
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line.word 0x00 "NORMAL_INT_STAT_R,Normal Interrupt Status Register"
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rbitfld.word 0x00 15. "ERR_INTERRUPT,Error Interrupt If any of the bits in the Error Interrupt Status register are set then this bit is set" "0,1"
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newline
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bitfld.word 0x00 14. "CQE_EVENT,Command Queuing Event This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode" "0,1"
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newline
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rbitfld.word 0x00 13. "FX_EVENT,FX Event This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register" "0,1"
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newline
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rbitfld.word 0x00 8. "CARD_INTERRUPT,Card Interrupt This bit reflects the synchronized value of: - DAT[1] Interrupt Input for SD Mode Values: - 0x0 (FALSE): No Card Interrupt - 0x1 (TRUE): Generate Card Interrupt" "0,1"
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newline
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bitfld.word 0x00 7. "CARD_REMOVAL,Card Removal This bit is set if the Card Inserted in the Present State register changes from 1 to 0" "0,1"
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newline
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bitfld.word 0x00 6. "CARD_INSERTION,Card Insertion This bit is set if the Card Inserted in the Present State register changes from 0 to 1" "0,1"
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newline
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bitfld.word 0x00 5. "BUF_RD_READY,Buffer Read Ready This bit is set if the Buffer Read Enable changes from 0 to 1" "0,1"
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newline
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bitfld.word 0x00 4. "BUF_WR_READY,Buffer Write Ready This bit is set if the Buffer Write Enable changes from 0 to 1" "0,1"
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newline
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bitfld.word 0x00 3. "DMA_INTERRUPT,DMA Interrupt This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer" "0,1"
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newline
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bitfld.word 0x00 2. "BGAP_EVENT,Block Gap Event This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request" "0,1"
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newline
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bitfld.word 0x00 1. "XFER_COMPLETE,Transfer Complete This bit is set when a read/write transfer and a command with status busy is completed" "0,1"
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newline
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bitfld.word 0x00 0. "CMD_COMPLETE,Command Complete In an SD/eMMC Mode this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23" "0,1"
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group.word 0x1032++0x01
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line.word 0x00 "ERROR_INT_STAT_R,Error Interrupt Status Register"
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bitfld.word 0x00 12. "BOOT_ACK_ERR,Boot Acknowledgement Error This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010" "0,1"
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newline
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bitfld.word 0x00 11. "RESP_ERR,Response Error Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "0,1"
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newline
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bitfld.word 0x00 10. "TUNING_ERR,N/A" "0,1"
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newline
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bitfld.word 0x00 9. "ADMA_ERR,ADMA Error This bit is set when the Host Controller detects error during ADMA-based data transfer" "0,1"
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newline
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bitfld.word 0x00 8. "AUTO_CMD_ERR,Auto CMD Error This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode" "0,1"
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newline
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bitfld.word 0x00 7. "CUR_LMT_ERR,Current Limit Error By setting the SD Bus Power bit in the Power Control register the Host Controller is requested to supply power for the SD Bus" "0,1"
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newline
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bitfld.word 0x00 6. "DATA_END_BIT_ERR,Data End Bit Error This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status" "0,1"
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newline
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bitfld.word 0x00 5. "DATA_CRC_ERR,Data CRC Error This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout" "0,1"
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newline
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bitfld.word 0x00 4. "DATA_TOUT_ERR,Data Timeout Error This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: - Busy timeout for R1b R5b type - Busy timeout after Write CRC status - Write CRC Status timeout - Read Data timeout Values: - 0x0.." "0,1"
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newline
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bitfld.word 0x00 3. "CMD_IDX_ERR,Command Index Error This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode" "0,1"
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newline
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bitfld.word 0x00 2. "CMD_END_BIT_ERR,Command End Bit Error This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode" "0,1"
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newline
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bitfld.word 0x00 1. "CMD_CRC_ERR,Command CRC Error Command CRC Error is generated in SD/eMMC mode for following two cases" "0,1"
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newline
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bitfld.word 0x00 0. "CMD_TOUT_ERR,Command Timeout Error In SD/eMMC Mode this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command" "0,1"
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group.word 0x1034++0x01
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line.word 0x00 "NORMAL_INT_STAT_EN_R,Normal Interrupt Status Enable Register"
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bitfld.word 0x00 14. "CQE_EVENT_STAT_EN,CQE Event Status Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 13. "FX_EVENT_STAT_EN,FX Event Status Enable This bit is added from Version 4.10" "0,1"
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newline
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bitfld.word 0x00 12. "RE_TUNE_EVENT_STAT_EN,N/A" "0,1"
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newline
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bitfld.word 0x00 11. "INT_C_STAT_EN,N/A" "0,1"
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newline
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bitfld.word 0x00 10. "INT_B_STAT_EN,N/A" "0,1"
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newline
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bitfld.word 0x00 9. "INT_A_STAT_EN,N/A" "0,1"
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newline
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bitfld.word 0x00 8. "CARD_INTERRUPT_STAT_EN,Card Interrupt Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System" "0,1"
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newline
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bitfld.word 0x00 7. "CARD_REMOVAL_STAT_EN,Card Removal Status Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 6. "CARD_INSERTION_STAT_EN,Card Insertion Status Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 5. "BUF_RD_READY_STAT_EN,Buffer Read Ready Status Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 4. "BUF_WR_READY_STAT_EN,Buffer Write Ready Status Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 3. "DMA_INTERRUPT_STAT_EN,DMA Interrupt Status Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 2. "BGAP_EVENT_STAT_EN,Block Gap Event Status Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 1. "XFER_COMPLETE_STAT_EN,Transfer Complete Status Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 0. "CMD_COMPLETE_STAT_EN,Command Complete Status Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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group.word 0x1036++0x01
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line.word 0x00 "ERROR_INT_STAT_EN_R,Error Interrupt Status Enable Register"
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bitfld.word 0x00 15. "VENDOR_ERR_STAT_EN3,N/A" "0,1"
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newline
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bitfld.word 0x00 14. "VENDOR_ERR_STAT_EN2,N/A" "0,1"
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newline
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bitfld.word 0x00 13. "VENDOR_ERR_STAT_EN1,N/A" "0,1"
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newline
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bitfld.word 0x00 12. "BOOT_ACK_ERR_STAT_EN,Boot Acknowledgment Error (eMMC Mode only) Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (ERROR_INT_STAT_R)" "0,1"
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newline
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bitfld.word 0x00 11. "RESP_ERR_STAT_EN,Response Error Status Enable (SD Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 10. "TUNING_ERR_STAT_EN,Tuning Error Status Enable (UHS-I Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 9. "ADMA_ERR_STAT_EN,ADMA Error Status Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 8. "AUTO_CMD_ERR_STAT_EN,Auto CMD Error Status Enable (SD/eMMC Mode only)" "0,1"
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newline
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bitfld.word 0x00 7. "CUR_LMT_ERR_STAT_EN,Current Limit Error Status Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 6. "DATA_END_BIT_ERR_STAT_EN,Data End Bit Error Status Enable (SD/eMMC Mode only)" "0,1"
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newline
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bitfld.word 0x00 5. "DATA_CRC_ERR_STAT_EN,Data CRC Error Status Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 4. "DATA_TOUT_ERR_STAT_EN,Data Timeout Error Status Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 3. "CMD_IDX_ERR_STAT_EN,Command Index Error Status Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 2. "CMD_END_BIT_ERR_STAT_EN,Command End Bit Error Status Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 1. "CMD_CRC_ERR_STAT_EN,ommand CRC Error Status Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 0. "CMD_TOUT_ERR_STAT_EN,Command Timeout Error Status Enable (SD/eMMC Mode only)" "0,1"
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group.word 0x1038++0x01
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line.word 0x00 "NORMAL_INT_SIGNAL_EN_R,Normal Interrupt Signal Enable Register"
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bitfld.word 0x00 14. "CQE_EVENT_SIGNAL_EN,Command Queuing Engine Event Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 13. "FX_EVENT_SIGNAL_EN,FX Event Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 12. "RE_TUNE_EVENT_SIGNAL_EN,N/A" "0,1"
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newline
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bitfld.word 0x00 11. "INT_C_SIGNAL_EN,N/A" "0,1"
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newline
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bitfld.word 0x00 10. "INT_B_SIGNAL_EN,N/A" "0,1"
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newline
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bitfld.word 0x00 9. "INT_A_SIGNAL_EN,N/A" "0,1"
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newline
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bitfld.word 0x00 8. "CARD_INTERRUPT_SIGNAL_EN,Card Interrupt Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 7. "CARD_REMOVAL_SIGNAL_EN,Card Removal Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 6. "CARD_INSERTION_SIGNAL_EN,Card Insertion Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 5. "BUF_RD_READY_SIGNAL_EN,Buffer Read Ready Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 4. "BUF_WR_READY_SIGNAL_EN,Buffer Write Ready Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 3. "DMA_INTERRUPT_SIGNAL_EN,DMA Interrupt Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 2. "BGAP_EVENT_SIGNAL_EN,Block Gap Event Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 1. "XFER_COMPLETE_SIGNAL_EN,Transfer Complete Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 0. "CMD_COMPLETE_SIGNAL_EN,Command Complete Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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group.word 0x103A++0x01
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line.word 0x00 "ERROR_INT_SIGNAL_EN_R,Error Interrupt Signal Enable Register"
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bitfld.word 0x00 15. "VENDOR_ERR_SIGNAL_EN3,N/A" "0,1"
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newline
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bitfld.word 0x00 14. "VENDOR_ERR_SIGNAL_EN2,N/A" "0,1"
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newline
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bitfld.word 0x00 13. "VENDOR_ERR_SIGNAL_EN1,N/A" "0,1"
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newline
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bitfld.word 0x00 12. "BOOT_ACK_ERR_SIGNAL_EN,Boot Acknowledgment Error (eMMC Mode only)" "0,1"
|
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newline
|
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bitfld.word 0x00 11. "RESP_ERR_SIGNAL_EN,Response Error Signal Enable (SD Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 10. "TUNING_ERR_SIGNAL_EN,N/A" "0,1"
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newline
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bitfld.word 0x00 9. "ADMA_ERR_SIGNAL_EN,ADMA Error Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 8. "AUTO_CMD_ERR_SIGNAL_EN,Auto CMD Error Signal Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 7. "CUR_LMT_ERR_SIGNAL_EN,Current Limit Error Signal Enable Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 6. "DATA_END_BIT_ERR_SIGNAL_EN,Data End Bit Error Signal Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 5. "DATA_CRC_ERR_SIGNAL_EN,Data CRC Error Signal Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 4. "DATA_TOUT_ERR_SIGNAL_EN,Data Timeout Error Signal Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 3. "CMD_IDX_ERR_SIGNAL_EN,Command Index Error Signal Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): No error - 0x1 (TRUE): Error" "0,1"
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newline
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bitfld.word 0x00 2. "CMD_END_BIT_ERR_SIGNAL_EN,Command End Bit Error Signal Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 1. "CMD_CRC_ERR_SIGNAL_EN,Command CRC Error Signal Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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newline
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bitfld.word 0x00 0. "CMD_TOUT_ERR_SIGNAL_EN,Command Timeout Error Signal Enable (SD/eMMC Mode only) Values: - 0x0 (FALSE): Masked - 0x1 (TRUE): Enabled" "0,1"
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rgroup.word 0x103C++0x01
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line.word 0x00 "AUTO_CMD_STAT_R,Auto CMD Status Register"
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bitfld.word 0x00 7. "CMD_NOT_ISSUED_AUTO_CMD12,Command Not Issued By Auto CMD12 Error If this bit is set to 1 CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register" "0,1"
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newline
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bitfld.word 0x00 5. "AUTO_CMD_RESP_ERR,Auto CMD Response Error This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13" "0,1"
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newline
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bitfld.word 0x00 4. "AUTO_CMD_IDX_ERR,Auto CMD Index Error This bit is set if the command index error occurs in response to a command" "0,1"
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newline
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bitfld.word 0x00 3. "AUTO_CMD_EBIT_ERR,Auto CMD End Bit Error This bit is set when detecting that the end bit of command response is 0" "0,1"
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newline
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bitfld.word 0x00 2. "AUTO_CMD_CRC_ERR,Auto CMD CRC Error This bit is set when detecting a CRC error in the command response" "0,1"
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newline
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bitfld.word 0x00 1. "AUTO_CMD_TOUT_ERR,Auto CMD Timeout Error This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command" "0,1"
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newline
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bitfld.word 0x00 0. "AUTO_CMD12_NOT_EXEC,Auto CMD12 Not Executed If multiple memory block data transfer is not started due to a command error this bit is not set because it is not necessary to issue an Auto CMD12" "0,1"
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group.word 0x103E++0x01
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line.word 0x00 "HOST_CTRL2_R,Host Control 2 Register"
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bitfld.word 0x00 15. "PRESET_VAL_ENABLE,N/A" "0,1"
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newline
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bitfld.word 0x00 14. "ASYNC_INT_ENABLE,Asynchronous Interrupt Enable This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register" "0,1"
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bitfld.word 0x00 13. "ADDRESSING,N/A" "0,1"
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bitfld.word 0x00 12. "HOST_VER4_ENABLE,Host Version 4 Enable This bit selects either Version 3.00 compatible mode or Version 4 mode" "0,1"
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bitfld.word 0x00 11. "CMD23_ENABLE,CMD23 Enable If the card supports CMD23 this bit is set to 1" "0,1"
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bitfld.word 0x00 10. "ADMA2_LEN_MODE,ADMA2 Length Mode This bit selects ADMA2 Length mode to be either 16-bit or 26-bit" "0,1"
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bitfld.word 0x00 8. "UHS2_IF_ENABLE,N/A" "0,1"
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bitfld.word 0x00 7. "SAMPLE_CLK_SEL,N/A" "0,1"
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bitfld.word 0x00 6. "EXEC_TUNING,N/A" "0,1"
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bitfld.word 0x00 4.--5. "DRV_STRENGTH_SEL,Driver Strength Select These bits are used to select the Host Controller output driver in 1.8V signaling UHS-I/eMMC speed modes" "0,1,2,3"
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bitfld.word 0x00 3. "SIGNALING_EN,1.8V Signaling Enable This bit controls voltage regulator for I/O cell in SD UHS-I mode" "0,1"
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bitfld.word 0x00 0.--2. "UHS_MODE_SEL,N/A" "0,1,2,3,4,5,6,7"
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rgroup.long 0x1040++0x03
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line.long 0x00 "CAPABILITIES1_R,Capabilities 1 Register - 0 to 31"
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bitfld.long 0x00 30.--31. "SLOT_TYPE_R,Slot Type These bits indicate usage of a slot by a specific Host System" "0,1,2,3"
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bitfld.long 0x00 29. "ASYNC_INT_SUPPORT,Asynchronous Interrupt Support (SD Mode only) Values: - 0x0 (FALSE): Asynchronous Interrupt Not Supported - 0x1 (TRUE): Asynchronous Interrupt Supported" "0,1"
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bitfld.long 0x00 28. "SYS_ADDR_64_V3,64-bit System Address Support for V3 This bit sets the Host controller to support 64-bit System Addressing of V3 mode" "0,1"
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bitfld.long 0x00 27. "SYS_ADDR_64_V4,64-bit System Address Support for V4 This bit sets the Host Controller to support 64-bit System Addressing of V4 mode" "0,1"
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bitfld.long 0x00 26. "VOLT_18,Voltage Support 1.8V Values: - 0x0 (FALSE): 1.8V Not Supported - 0x1 (TRUE): 1.8V Supported" "0,1"
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bitfld.long 0x00 25. "VOLT_30,Voltage Support 3.0V Values: - 0x0 (FALSE): 3.0V Not Supported - 0x1 (TRUE): 3.0V Supported" "0,1"
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bitfld.long 0x00 24. "VOLT_33,Voltage Support 3.3V Values: - 0x0 (FALSE): 3.3V Not Supported - 0x1 (TRUE): 3.3V Supported" "0,1"
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bitfld.long 0x00 23. "SUS_RES_SUPPORT,Suspense/Resume Support This bit indicates whether the Host Controller supports Suspend/Resume functionality" "0,1"
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bitfld.long 0x00 22. "SDMA_SUPPORT,SDMA Support This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly" "0,1"
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bitfld.long 0x00 21. "HIGH_SPEED_SUPPORT,High Speed Support This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz" "0,1"
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bitfld.long 0x00 19. "ADMA2_SUPPORT,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2" "0,1"
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bitfld.long 0x00 18. "EMBEDDED_8_BIT,8-bit Support for Embedded Device This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode" "0,1"
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bitfld.long 0x00 16.--17. "MAX_BLK_LEN,N/A" "0,1,2,3"
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hexmask.long.byte 0x00 8.--15. 1. "BASE_CLK_FREQ,Base Clock Frequency for SD clock These bits indicate the base (maximum) clock frequency for the SD Clock"
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bitfld.long 0x00 7. "TOUT_CLK_UNIT,Timeout Clock Unit This bit shows the unit of base clock frequency used to detect Data TImeout Error" "0,1"
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bitfld.long 0x00 0.--5. "TOUT_CLK_FREQ,Timeout Clock Frequency This bit shows the base clock frequency used to detect Data Timeout Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rgroup.long 0x1044++0x03
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line.long 0x00 "CAPABILITIES2_R,Capabilities Register - 32 to 63"
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bitfld.long 0x00 28. "VDD2_18V_SUPPORT,1.8V VDD2 Support This bit indicates support of VDD2 for the Host System" "0,1"
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bitfld.long 0x00 27. "ADMA3_SUPPORT,ADMA3 Support This bit indicates whether the Host Controller is capable of using ADMA3" "0,1"
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abitfld.long 0x00 16.--23. "CLK_MUL,Clock Multiplier These bits indicate the clock multiplier of the programmable clock generator" "0x00=0: Clock Multiplier is not Supported,0x01=1: Clock Multiplier M =,0x02=2: Clock Multiplier M =,0x03=3: ,0xFF=255: Clock Multiplier M = 256"
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bitfld.long 0x00 14.--15. "RE_TUNING_MODES,N/A" "0,1,2,3"
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bitfld.long 0x00 13. "USE_TUNING_SDR50,Use Tuning for SDR50 (UHS-I only) Values: - 0x0 (ZERO): SDR50 does not require tuning - 0x1 (ONE): SDR50 requires tuning" "0,1"
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bitfld.long 0x00 8.--11. "RETUNE_CNT,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6. "DRV_TYPED,Driver Type D Support (UHS-I only) This bit indicates support of Driver Type D for 1.8 Signaling" "0,1"
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bitfld.long 0x00 5. "DRV_TYPEC,Driver Type C Support (UHS-I only) This bit indicates support of Driver Type C for 1.8 Signaling" "0,1"
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bitfld.long 0x00 4. "DRV_TYPEA,Driver Type A Support (UHS-I only) This bit indicates support of Driver Type A for 1.8 Signaling" "0,1"
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bitfld.long 0x00 3. "UHS2_SUPPORT,UHS-II Support (UHS-II only) This bit indicates whether Host Controller supports UHS-II" "0,1"
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bitfld.long 0x00 2. "DDR50_SUPPORT,DDR50 Support (UHS-I only) Values: - 0x0 (FALSE): DDR50 is not supported - 0x1 (TRUE): DDR50 is supported" "0,1"
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bitfld.long 0x00 1. "SDR104_SUPPORT,SDR104 Support (UHS-I only) This bit mentions that SDR104 requires tuning" "0,1"
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bitfld.long 0x00 0. "SDR50_SUPPORT,SDR50 Support (UHS-I only) Thsi bit indicates that SDR50 is supported" "0,1"
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rgroup.long 0x1048++0x03
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line.long 0x00 "CURR_CAPABILITIES1_R,Current Capabilities Register - 0 to 31"
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abitfld.long 0x00 16.--23. "MAX_CUR_18V,Maximum Current for 1.8V This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card" "0x00=0: Get information,0x01=1: 4mA,0x02=2: 8mA,0x03=3: 13mA,0xFF=255: 1020mA"
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abitfld.long 0x00 8.--15. "MAX_CUR_30V,Maximum Current for 3.0V This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card" "0x00=0: Get information,0x01=1: 4mA,0x02=2: 8mA,0x03=3: 13mA,0xFF=255: 1020mA"
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abitfld.long 0x00 0.--7. "MAX_CUR_33V,Maximum Current for 3.3V This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card" "0x00=0: Get information,0x01=1: 4mA,0x02=2: 8mA,0x03=3: 13mA,0xFF=255: 1020mA"
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rgroup.long 0x104C++0x03
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line.long 0x00 "CURR_CAPABILITIES2_R,Maximum Current Capabilities Register - 32 to 63"
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abitfld.long 0x00 0.--7. "MAX_CUR_VDD2_18V,Maximum Current for 1.8V VDD2 This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card" "0x00=0: Get information,0x01=1: 4mA,0x02=2: 8mA,0x03=3: 13mA,0xFF=255: 1020mA"
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wgroup.word 0x1050++0x01
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line.word 0x00 "FORCE_AUTO_CMD_STAT_R,Force Event Register for Auto CMD Error Status register"
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bitfld.word 0x00 7. "FORCE_CMD_NOT_ISSUED_AUTO_CMD12,Force Event for Command Not Issued By Auto CMD12 Error Values: - 0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set - 0x0 (FALSE): Not Affected" "0,1"
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bitfld.word 0x00 5. "FORCE_AUTO_CMD_RESP_ERR,Force Event for Auto CMD Response Error Values: - 0x1 (TRUE): Auto CMD Response Error Status is set - 0x0 (FALSE): Not Affected" "0,1"
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bitfld.word 0x00 4. "FORCE_AUTO_CMD_IDX_ERR,Force Event for Auto CMD Index Error Values: - 0x1 (TRUE): Auto CMD Index Error Status is set - 0x0 (FALSE): Not Affected" "0,1"
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bitfld.word 0x00 3. "FORCE_AUTO_CMD_EBIT_ERR,Force Event for Auto CMD End Bit Error Values: - 0x1 (TRUE): Auto CMD End Bit Error Status is set - 0x0 (FALSE): Not Affected" "0,1"
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bitfld.word 0x00 2. "FORCE_AUTO_CMD_CRC_ERR,Force Event for Auto CMD CRC Error Values: - 0x1 (TRUE): Auto CMD CRC Error Status is set - 0x0 (FALSE): Not Affected" "0,1"
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bitfld.word 0x00 1. "FORCE_AUTO_CMD_TOUT_ERR,Force Event for Auto CMD Timeout Error Values: - 0x1 (TRUE): Auto CMD Timeout Error Status is set - 0x0 (FALSE): Not Affected" "0,1"
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bitfld.word 0x00 0. "FORCE_AUTO_CMD12_NOT_EXEC,Force Event for Auto CMD12 Not Executed Values: - 0x1 (TRUE): Auto CMD12 Not Executed Status is set - 0x0 (FALSE): Not Affected" "0,1"
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group.word 0x1052++0x01
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line.word 0x00 "FORCE_ERROR_INT_STAT_R,Force Event Register for Error Interrupt Status"
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bitfld.word 0x00 15. "FORCE_VENDOR_ERR3,N/A" "0,1"
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bitfld.word 0x00 14. "FORCE_VENDOR_ERR2,N/A" "0,1"
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bitfld.word 0x00 13. "FORCE_VENDOR_ERR1,N/A" "0,1"
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bitfld.word 0x00 12. "FORCE_BOOT_ACK_ERR,Force Event for Boot Ack error Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): Boot ack Error Status is set" "0,1"
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bitfld.word 0x00 11. "FORCE_RESP_ERR,Force Event for Response Error (SD Mode only) Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): Response Error Status is set" "0,1"
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bitfld.word 0x00 10. "FORCE_TUNING_ERR,Force Event for Tuning Error (UHS-I Mode only) Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): Tuning Error Status is set" "0,1"
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bitfld.word 0x00 9. "FORCE_ADMA_ERR,Force Event for ADMA Error Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): ADMA Error Status is set" "0,1"
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bitfld.word 0x00 8. "FORCE_AUTO_CMD_ERR,Force Event for Auto CMD Error (SD/eMMC Mode only) Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): Auto CMD Error Status is set" "0,1"
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bitfld.word 0x00 7. "FORCE_CUR_LMT_ERR,Force Event for Current Limit Error Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): Current Limit Error Status is set" "0,1"
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bitfld.word 0x00 6. "FORCE_DATA_END_BIT_ERR,Force Event for Data End Bit Error (SD/eMMC Mode only) Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): Data End Bit Error Status is set" "0,1"
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bitfld.word 0x00 5. "FORCE_DATA_CRC_ERR,Force Event for Data CRC Error (SD/eMMC Mode only) Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): Data CRC Error Status is set" "0,1"
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bitfld.word 0x00 4. "FORCE_DATA_TOUT_ERR,Force Event for Data Timeout Error (SD/eMMC Mode only) Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): Data Timeout Error Status is set" "0,1"
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bitfld.word 0x00 3. "FORCE_CMD_IDX_ERR,Force Event for Command Index Error (SD/eMMC Mode only) Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): Command Index Error Status is set" "0,1"
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bitfld.word 0x00 2. "FORCE_CMD_END_BIT_ERR,Force Event for Command End Bit Error (SD/eMMC Mode only) Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): Command End Bit Error Status is set" "0,1"
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bitfld.word 0x00 1. "FORCE_CMD_CRC_ERR,Force Event for Command CRC Error (SD/eMMC Mode only) Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): Command CRC Error Status is set" "0,1"
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bitfld.word 0x00 0. "FORCE_CMD_TOUT_ERR,Force Event for Command Timeout Error (SD/eMMC Mode only) Values: - 0x0 (FALSE): Not Affected - 0x1 (TRUE): Command Timeout Error Status is set" "0,1"
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rgroup.byte 0x1054++0x00
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line.byte 0x00 "ADMA_ERR_STAT_R,ADMA Error Status Register"
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bitfld.byte 0x00 2. "ADMA_LEN_ERR,ADMA Length Mismatch Error States This error occurs in the following instances: - While the Block Count Enable is being set the total data length specified by the Descriptor table is different from that specified by the Block Count and.." "0,1"
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bitfld.byte 0x00 0.--1. "ADMA_ERR_STATES,ADMA Error States These bits indicate the state of ADMA when an error occurs during ADMA data transfer" "0,1,2,3"
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group.long 0x1058++0x03
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line.long 0x00 "ADMA_SA_LOW_R,ADMA System Address Register - Low"
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hexmask.long 0x00 0.--31. 1. "ADMA_SA_LOW,ADMA System Address These bits indicate the lower 32 bits of the ADMA system address"
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group.long 0x1078++0x03
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line.long 0x00 "ADMA_ID_LOW_R,ADMA3 Integrated Descriptor Address Register - Low"
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hexmask.long 0x00 0.--31. 1. "ADMA_ID_LOW,ADMA Integrated Descriptor Address These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address"
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rgroup.word 0x10FE++0x01
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line.word 0x00 "HOST_CNTRL_VERS_R,Host Controller Version"
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hexmask.word.byte 0x00 8.--15. 1. "VENDOR_VERSION_NUM,N/A"
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hexmask.word.byte 0x00 0.--7. 1. "SPEC_VERSION_NUM,N/A"
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rgroup.long 0x1180++0x03
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line.long 0x00 "CQVER,Command Queuing Version register"
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bitfld.long 0x00 8.--11. "EMMC_VER_MAJOR,This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "EMMC_VER_MINOR,This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EMMC_VER_SUFFIX,This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x1184++0x03
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line.long 0x00 "CQCAP,Command Queuing Capabilities register"
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bitfld.long 0x00 28. "CRYPTO_SUPPORT,Crypto Support This bit indicates whether the Host Controller supports cryptographic operations" "0,1"
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bitfld.long 0x00 12.--15. "ITCFMUL,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--9. 1. "ITCFVAL,Internal Timer Clock Frequency Value (ITCFVAL) This field scales the frequency of the timer clock provided by ITCFMUL"
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group.long 0x1188++0x03
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line.long 0x00 "CQCFG,Command Queuing Configuration register"
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bitfld.long 0x00 12. "DCMD_EN,This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor" "0,1"
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bitfld.long 0x00 8. "TASK_DESC_SIZE,Bit Value Description This bit indicates the size of task descriptor used in host memory" "0,1"
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bitfld.long 0x00 1. "CR_GENERAL_EN,N/A" "0,1"
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bitfld.long 0x00 0. "CQ_EN,Enable command queuing engine (CQE)" "0,1"
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group.long 0x118C++0x03
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line.long 0x00 "CQCTL,Command Queuing Control register"
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bitfld.long 0x00 8. "CLR_ALL_TASKS,Clear all tasks This bit can only be written when the controller is halted" "0,1"
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bitfld.long 0x00 0. "HALT,Halt request and resume Values: - 0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus" "0,1"
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group.long 0x1190++0x03
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line.long 0x00 "CQIS,Command Queuing Interrupt Status register"
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bitfld.long 0x00 5. "ICCE,N/A" "0,1"
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bitfld.long 0x00 4. "GCE,N/A" "0,1"
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bitfld.long 0x00 3. "TCL,Task cleared interrupt This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE" "0,1"
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bitfld.long 0x00 2. "RED,Response error detected interrupt This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status field" "0,1"
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bitfld.long 0x00 1. "TCC,Task complete interrupt This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: - A task is completed and the INT bit is set in its Task Descriptor - Interrupt caused by Interrupt Coalescing logic due.." "0,1"
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bitfld.long 0x00 0. "HAC,Halt complete interrupt This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state" "0,1"
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group.long 0x1194++0x03
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line.long 0x00 "CQISE,Command Queuing Interrupt Status Enable register"
|
|
bitfld.long 0x00 5. "ICCE_STE,Invalid Crypto Configuration Error interrupt status enable Values: - 0x1 (INT_STS_ENABLE): CQIS.ICCE is set when its interrupt condition is active - 0x0 (INT_STS_DISABLE): CQIS.ICCE is disabled" "0,1"
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bitfld.long 0x00 4. "GCE_STE,General Crypto Error interrupt status enable Values: - 0x1 (INT_STS_ENABLE): CQIS.GCE is set when its interrupt condition is active - 0x0 (INT_STS_DISABLE): CQIS.GCE is disabled" "0,1"
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bitfld.long 0x00 3. "TCL_STE,Task cleared interrupt status enable Values: - 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active - 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled" "0,1"
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bitfld.long 0x00 2. "RED_STE,Response error detected interrupt status enable Values: - 0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active - 0x0 (INT_STS_DISABLE): CQIS.RED is disabled" "0,1"
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bitfld.long 0x00 1. "TCC_STE,Task complete interrupt status enable Values: - 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active - 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled" "0,1"
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bitfld.long 0x00 0. "HAC_STE,Halt complete interrupt status enable Values: - 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active - 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled" "0,1"
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group.long 0x1198++0x03
|
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line.long 0x00 "CQISGE,Command Queuing Interrupt signal enable register"
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bitfld.long 0x00 5. "ICCE_SGE,Invalid Crypto Configuration Error interrupt signal enable Values: - 0x1 (INT_SIG_ENABLE): CQIS.ICCE interrupt signal generation is active - 0x0 (INT_SIG_DISABLE): CQIS.ICCE interrupt signal generation is disabled" "0,1"
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bitfld.long 0x00 4. "GCE_SGE,General Crypto Error interrupt signal enable Values: - 0x1 (INT_SIG_ENABLE): CQIS.GCE interrupt signal generation is active - 0x0 (INT_SIG_DISABLE): CQIS.GCE interrupt signal generation is disabled" "0,1"
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bitfld.long 0x00 3. "TCL_SGE,Task cleared interrupt signal enable Values: - 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active - 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled" "0,1"
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bitfld.long 0x00 2. "RED_SGE,Response error detected interrupt signal enable Values: - 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active - 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled" "0,1"
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|
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bitfld.long 0x00 1. "TCC_SGE,Task complete interrupt signal enable Values: - 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active - 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled" "0,1"
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|
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bitfld.long 0x00 0. "HAC_SGE,Halt complete interrupt signal enable Values: - 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active - 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled" "0,1"
|
|
group.long 0x119C++0x03
|
|
line.long 0x00 "CQIC,Command Queuing Interrupt Coalescing register"
|
|
bitfld.long 0x00 31. "INTC_EN,Interrupt Coalescing Enable Bit Values: - 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active" "0,1"
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|
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rbitfld.long 0x00 20. "INTC_STAT,Interrupt Coalescing Status Bit This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt coalescing (that is this is set if and only if INTC counter > 0)" "0,1"
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bitfld.long 0x00 16. "INTC_RST,Counter and Timer Reset When host driver writes 1 the interrupt coalescing timer and counter are reset" "0,1"
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bitfld.long 0x00 15. "INTC_TH_WEN,Interrupt Coalescing Counter Threshold Write Enable When software writes 1 to this bit the value INTC_TH is updated with the contents written on the same cycle" "0,1"
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bitfld.long 0x00 8.--12. "INTC_TH,Interrupt Coalescing Counter Threshold filed Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor) which are required in order to generate an interrupt" "0: Interrupt coalescing feature disabled,1: Interrupt coalescing interrupt generated..,2: Interrupt coalescing interrupt generated..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Interrupt coalescing interrupt generated after"
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bitfld.long 0x00 7. "TOUT_VAL_WEN,When software writes 1 to this bit the value TOUT_VAL is updated with the contents written on the same cycle" "0,1"
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abitfld.long 0x00 0.--6. "TOUT_VAL,Interrupt Coalescing Timeout Value Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt" "0x00=0: Timer is disabled,0x01=1: Timeout on 01x1024 cycles of timer clock..,0x02=2: Timeout on 02x1024 cycles of timer clock..,0x7F=127: Timeout on 127x1024 cycles of timer.."
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|
group.long 0x11A0++0x03
|
|
line.long 0x00 "CQTDLBA,Command Queuing Task Descriptor List Base Address register"
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|
hexmask.long 0x00 0.--31. 1. "TDLBA,This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "CQTDBR,Command Queuing DoorBell register"
|
|
hexmask.long 0x00 0.--31. 1. "DBR,The software configures TDLBA and TDLBAU and enable CQE in CQCFG before using this register"
|
|
group.long 0x11AC++0x03
|
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line.long 0x00 "CQTCN,Command Queuing TaskClear Notification register"
|
|
hexmask.long 0x00 0.--31. 1. "TCN,Task Completion Notification Each of the 32 bits are bit mapped to the 32 tasks"
|
|
rgroup.long 0x11B0++0x03
|
|
line.long 0x00 "CQDQS,Device queue status register"
|
|
hexmask.long 0x00 0.--31. 1. "DQS,Device Queue Status Each of the 32 bits are bit mapped to the 32 tasks"
|
|
rgroup.long 0x11B4++0x03
|
|
line.long 0x00 "CQDPT,Device pending tasks register"
|
|
hexmask.long 0x00 0.--31. 1. "DPT,Device-Pending Tasks Each of the 32 bits are bit mapped to the 32 tasks"
|
|
group.long 0x11B8++0x03
|
|
line.long 0x00 "CQTCLR,Command Queuing DoorBell register"
|
|
hexmask.long 0x00 0.--31. 1. "TCLR,Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued"
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|
group.long 0x11C0++0x03
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line.long 0x00 "CQSSC1,CQ Send Status Configuration 1 register"
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bitfld.long 0x00 16.--19. "SQSCMD_BLK_CNT,This field indicates when SQS CMD is sent while data transfer is in progress" "0: SEND_QUEUE_STATUS (CMD13) command is not sent,1: SEND_QUEUE_STATUS command is to be sent during,2: SEND_QUEUE_STATUS command when last 2 blocks..,3: SEND_QUEUE_STATUS command when last 3 blocks..,?,?,?,?,?,?,?,?,?,?,?,15: SEND_QUEUE_STATUS command when last 15 blocks"
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hexmask.long.word 0x00 0.--15. 1. "SQSCMD_IDLE_TMR,This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling"
|
|
group.long 0x11C4++0x03
|
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line.long 0x00 "CQSSC2,CQ Send Status Configuration 2 register"
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hexmask.long.word 0x00 0.--15. 1. "SQSCMD_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument"
|
|
rgroup.long 0x11C8++0x03
|
|
line.long 0x00 "CQCRDCT,Command response for direct command register"
|
|
hexmask.long 0x00 0.--31. 1. "DCMD_RESP,This register contains the response of the command generated by the last direct command (DCMD) task that was sent"
|
|
group.long 0x11D0++0x03
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line.long 0x00 "CQRMEM,Command response mode error mask register"
|
|
abitfld.long 0x00 0.--31. "RESP_ERR_MASK,The bits of this field are bit mapped to the device response" "0x00000000=0: When a R1/R1b response is received..,0x00000001=1: When a R1/R1b response is received.."
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rgroup.long 0x11D4++0x03
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|
line.long 0x00 "CQTERRI,CQ Task Error Information register"
|
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bitfld.long 0x00 31. "TRANS_ERR_FIELDS_VALID,This bit is updated when an error is detected while a data transfer transaction was in progress" "0,1"
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|
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bitfld.long 0x00 24.--28. "TRANS_ERR_TASKID,This field captures the ID of the task that was executed and whose data transfer has errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--21. "TRANS_ERR_CMD_INDX,This field captures the index of the command that was executed and whose data transfer has errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "RESP_ERR_FIELDS_VALID,This bit is updated when an error is detected while a command transaction was in progress" "0,1"
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bitfld.long 0x00 8.--12. "RESP_ERR_TASKID,This field captures the ID of the task which was executed on the command line when the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--5. "RESP_ERR_CMD_INDX,This field captures the index of the command that was executed on the command line when the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
rgroup.long 0x11D8++0x03
|
|
line.long 0x00 "CQCRI,CQ Command response index"
|
|
bitfld.long 0x00 0.--5. "CMD_RESP_INDX,Last Command Response index This field stores the index of the last received command response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
rgroup.long 0x11DC++0x03
|
|
line.long 0x00 "CQCRA,CQ Command response argument register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_RESP_ARG,Last Command Response argument This field stores the argument of the last received command response"
|
|
rgroup.long 0x1500++0x03
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|
line.long 0x00 "MSHC_VER_ID_R,MSHC version"
|
|
hexmask.long 0x00 0.--31. 1. "MSHC_VER_ID,Current release number This field indicates the Synopsys DesignWare Cores DWC_mshc/DWC_mshc_lite current release number that is read by an application"
|
|
rgroup.long 0x1504++0x03
|
|
line.long 0x00 "MSHC_VER_TYPE_R,MSHC version type"
|
|
hexmask.long 0x00 0.--31. 1. "MSHC_VER_TYPE,Current release type This field indicates the Synopsys DesignWare Cores DWC_mshc/DWC_mshc_lite current release type that is read by an application"
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|
group.byte 0x1508++0x00
|
|
line.byte 0x00 "MSHC_CTRL_R,MSHC Control register"
|
|
bitfld.byte 0x00 4. "SW_CG_DIS,Internal clock gating disable control This bit must be used to disable IP's internal clock gating when required" "0,1"
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bitfld.byte 0x00 0. "CMD_CONFLICT_CHECK,Command conflict check This bit enables command conflict check" "0,1"
|
|
group.byte 0x1510++0x00
|
|
line.byte 0x00 "MBIU_CTRL_R,MBIU Control register"
|
|
bitfld.byte 0x00 3. "BURST_INCR16_EN,INCR16 Burst Controls generation of INCR16 transfers on Master interface" "0,1"
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bitfld.byte 0x00 2. "BURST_INCR8_EN,INCR8 Burst Controls generation of INCR8 transfers on Master interface" "0,1"
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|
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bitfld.byte 0x00 1. "BURST_INCR4_EN,INCR4 Burst Controls generation of INCR4 transfers on Master interface" "0,1"
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bitfld.byte 0x00 0. "UNDEFL_INCR_EN,Undefined INCR Burst Controls generation of undefined length INCR transfer on Master interface" "0,1"
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|
group.word 0x152C++0x01
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line.word 0x00 "EMMC_CTRL_R,eMMC Control register"
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bitfld.word 0x00 10. "CQE_PREFETCH_DISABLE,Enable or Disable CQE's PREFETCH feature This field allows Software to disable CQE's data prefetch feature when set to 1" "0,1"
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bitfld.word 0x00 9. "CQE_ALGO_SEL,Scheduler algorithm selected for execution This bit selects the Algorithm used for selecting one of the many ready tasks for execution" "0,1"
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bitfld.word 0x00 3. "EMMC_RST_N_OE,Output Enable (OE) control for EMMC Device Reset signal (card_emmc_reset_n)" "0,1"
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|
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|
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bitfld.word 0x00 2. "EMMC_RST_N,EMMC Device Reset signal control" "0,1"
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bitfld.word 0x00 1. "DISABLE_DATA_CRC_CHK,Disable Data CRC Check This bit controls masking of CRC16 error for Card Write in eMMC mode" "0,1"
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bitfld.word 0x00 0. "CARD_IS_EMMC,eMMC Card present This bit indicates the type of card connected" "0,1"
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|
group.word 0x152E++0x01
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line.word 0x00 "BOOT_CTRL_R,eMMC Boot Control register"
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|
bitfld.word 0x00 12.--15. "BOOT_TOUT_CNT,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 8. "BOOT_ACK_ENABLE,Boot Acknowledge Enable When this bit set SDHC checks for boot acknowledge start pattern of 0-1-0 during boot operation" "0,1"
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bitfld.word 0x00 7. "VALIDATE_BOOT,Validate Mandatory Boot Enable bit This bit is used to validate the MAN_BOOT_EN bit" "0,1"
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|
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bitfld.word 0x00 0. "MAN_BOOT_EN,Mandatory Boot Enable This bit is used to initiate the mandatory boot operation" "0,1"
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rgroup.long 0x1530++0x03
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line.long 0x00 "GP_IN_R,General Purpose Input register"
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|
bitfld.long 0x00 0. "GP_IN,It reflects the value of gp_in ports" "0,1"
|
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group.long 0x1534++0x03
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line.long 0x00 "GP_OUT_R,General Purpose Output register"
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|
bitfld.long 0x00 8.--9. "CARD_CLOCK_IN_DLY,Delay CARD_CLOCK input internally to optimally sample CMD/DAT set according to interface mode" "0: SD Default Speed SD SDR12 eMMC Legacy,1: SD SDR25 SD SDR50,2: SD High Speed eMMC High Speed SDR,3: SD DDR50 eMMC DDR"
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bitfld.long 0x00 6.--7. "CARD_CLOCK_OUT_DLY,N/A" "0,1,2,3"
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bitfld.long 0x00 5. "IO_VOLT_SEL_OE,Active high output enable for the IO voltage selection signal (io_volt_sel) controlled through HOST_CTRL_2.SIGNALING_EN" "0: disable OE to the io_volt_sel output,1: enable OE to the io_volt_sel output"
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bitfld.long 0x00 4. "CARD_IF_PWR_EN_OE,Active high output enable for the card interface power enable output (card_if_pwr_en) controlled through PWR_CTRL_R.SD_BUS_PWR_VDD1" "0: disable OE to the card_if_pwr_en output,1: enable OE to the card_if_pwr_en output"
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newline
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bitfld.long 0x00 3. "CARD_CLOCK_OE,Active high output enable for the card clock output (clk_card) which is gated by CLK_CTRL_R.SD_CLK_EN" "0: disable OE to the clk_card output,1: enable OE to the clk_card output"
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bitfld.long 0x00 2. "LED_CTRL_OE,Active high output enable for the LED output signal (led_ctrl) controlled through HOST_CTRL1_R.LED_CTRL" "0: disable OE associated with the led_ctrl output,1: enable OE associated with the led_ctrl output"
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bitfld.long 0x00 1. "CARD_MECH_WRITE_PROT_EN,card_mech_write_prot despite its name is an active low signal (per the SD Host Controller Standard spec it is officially called SDWP#)" "0: Force card_mech_write_prot input to 0..,1: Allow card_mech_write_prot to work normally per"
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newline
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bitfld.long 0x00 0. "CARD_DETECT_EN," "0,1"
|
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tree.end
|
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tree.end
|
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tree "SMARTIO (Programmable IO configuration)"
|
|
base ad:0x40320000
|
|
repeat 18. (increment 0 1)(increment 0 0x100)
|
|
tree "PRT[$1]"
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group.long ($2+0x00)++0x03
|
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line.long 0x00 "CTL,Control register"
|
|
bitfld.long 0x00 31. "ENABLED,Enable for programmable IO" "0,1"
|
|
bitfld.long 0x00 25. "PIPELINE_EN,Enable for pipeline register: '0': Disabled (register is bypassed)" "0,1"
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bitfld.long 0x00 24. "HLD_OVR,IO cell hold override functionality" "0,1"
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|
bitfld.long 0x00 8.--12. "CLOCK_SRC,Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: '0': io_data_in[0]/'1'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 0.--7. 1. "BYPASS,Bypass of the programmable IO one bit for each IO pin: BYPASS[i] is for IO pin i"
|
|
group.long ($2+0x10)++0x03
|
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line.long 0x00 "SYNC_CTL,Synchronization control register"
|
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hexmask.long.byte 0x00 8.--15. 1. "CHIP_SYNC_EN,Synchronization of the chip input signals to 'clk_fabric' one bit for each input: CHIP_SYNC_EN[i] is for input i"
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hexmask.long.byte 0x00 0.--7. 1. "IO_SYNC_EN,Synchronization of the IO pin input signals to 'clk_fabric' one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i"
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "LUT_SEL[0],LUT component input selection"
|
|
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "LUT_SEL[1],LUT component input selection"
|
|
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "LUT_SEL[2],LUT component input selection"
|
|
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long ($2+0x2C)++0x03
|
|
line.long 0x00 "LUT_SEL[3],LUT component input selection"
|
|
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long ($2+0x30)++0x03
|
|
line.long 0x00 "LUT_SEL[4],LUT component input selection"
|
|
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long ($2+0x34)++0x03
|
|
line.long 0x00 "LUT_SEL[5],LUT component input selection"
|
|
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long ($2+0x38)++0x03
|
|
line.long 0x00 "LUT_SEL[6],LUT component input selection"
|
|
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long ($2+0x3C)++0x03
|
|
line.long 0x00 "LUT_SEL[7],LUT component input selection"
|
|
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "LUT_CTL[0],LUT component control register"
|
|
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
|
|
group.long ($2+0x44)++0x03
|
|
line.long 0x00 "LUT_CTL[1],LUT component control register"
|
|
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "LUT_CTL[2],LUT component control register"
|
|
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
|
|
group.long ($2+0x4C)++0x03
|
|
line.long 0x00 "LUT_CTL[3],LUT component control register"
|
|
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "LUT_CTL[4],LUT component control register"
|
|
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
|
|
group.long ($2+0x54)++0x03
|
|
line.long 0x00 "LUT_CTL[5],LUT component control register"
|
|
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
|
|
group.long ($2+0x58)++0x03
|
|
line.long 0x00 "LUT_CTL[6],LUT component control register"
|
|
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
|
|
group.long ($2+0x5C)++0x03
|
|
line.long 0x00 "LUT_CTL[7],LUT component control register"
|
|
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
|
|
group.long ($2+0xC0)++0x03
|
|
line.long 0x00 "DU_SEL,Data unit component input selection"
|
|
bitfld.long 0x00 28.--29. "DU_DATA1_SEL,Data unit input data 'data1_in' source selection" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "DU_DATA0_SEL,Data unit input data 'data0_in' source selection: '0': Constant '0'" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "DU_TR2_SEL,Data unit input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "DU_TR1_SEL,Data unit input signal 'tr1_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DU_TR0_SEL,Data unit input signal 'tr0_in' source selection: '0': Constant '0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long ($2+0xC4)++0x03
|
|
line.long 0x00 "DU_CTL,Data unit component control register"
|
|
bitfld.long 0x00 8.--11. "DU_OPC,Data unit opcode specifies the data unit operation: '1': INCR '2': DECR '3': INCR_WRAP '4': DECR_WRAP '5': INCR_DECR '6': INCR_DECR_WRAP '7': ROR '8': SHR '9': AND_OR '10': SHR_MAJ3 '11': SHR_EQL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "DU_SIZE,Size/width of the data unit data operands (in bits) is DU_SIZE+1" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xF0)++0x03
|
|
line.long 0x00 "DATA,Data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Data unit input data source"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SMIF0 (Serial Memory Interface)"
|
|
base ad:0x40420000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control"
|
|
bitfld.long 0x00 31. "ENABLED,IP enable: '0': Disabled" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 24. "BLOCK,Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO" "0: 0',1: 1'"
|
|
bitfld.long 0x00 22.--23. "SELECT_HOLD_DELAY,Specifies the duration between last 'spi_clk_out' edge to 'spi_select_out[]' becomes high/'1'): '0': 0 memory interface clock cycles + min. duration (see below). '1': 1 memory interface clock cycle + min. duration (see below). '2': 2.." "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "SELECT_SETUP_DELAY,Specifies the duration between 'spi_select_out[]' becomes low/'0') to 1st 'spi_clk_out' edge: '0': 0 memory interface clock cycles + min. duration (see below). '1': 1 memory interface clock cycle + min. duration (see below). '2': 2.." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DESELECT_DELAY,Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers: '0': 1 memory interface clock cycle" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "CLOCK_IF_RX_SEL,Specifies device interface receiver clock 'clk_if_rx' source" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--11. "INT_CLOCK_CAPTURE_CYCLE,N/A" "0,1,2,3"
|
|
bitfld.long 0x00 9. "INT_CLOCK_DL_ENABLED,Data Learning Enable for internal RX clock based on Data Learning Pattern" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DELAY_TAP_ENABLED,Delay Line Tap Enable" "0,1"
|
|
bitfld.long 0x00 5.--7. "DELAY_LINE_SEL,Specifies the delay line used for RX data capturing with - output / feedback clock based capturing (when CLOCK_IF_RX_SEL = [0..3] and DELAY_TAP_ENABLED = 1) - internal clock based capturing (when CLOCK_IF_RX_SEL = [4..5].." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "CLOCK_IF_TX_SEL,Specifies device interface transmitter clock options" "0,1"
|
|
bitfld.long 0x00 0. "XIP_MODE,Mode of operation" "0: '0',1: '1'"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Status"
|
|
bitfld.long 0x00 31. "BUSY,AHB Cache AXI interface cryptography XIP device interface or any other logic busy in the IP: '0': not busy '1': busy When BUSY is '0' the IP can be safely disabled without: - the potential loss of transient write data" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INT_CLOCK_DELAY_TAP_SEL0,Internal Clocking Delay Tap Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BIT3,Delay line tap selection for data bit 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BIT2,Delay line tap selection for data bit 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BIT1,Delay line tap selection for data bit 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BIT0,Delay line tap selection for data bit 0"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "INT_CLOCK_DELAY_TAP_SEL1,Internal Clocking Delay Tap Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BIT7,Delay line tap selection for data bit 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BIT6,Delay line tap selection for data bit 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BIT5,Delay line tap selection for data bit 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BIT4,Delay line tap selection for data bit 4"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DLP,Data Learning Pattern"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DLP,Data Learning Pattern"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "DL_STATUS0,Data Learning Status Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BIT3,Number of delay line taps for data bit 3 with correctly captured DLP in last read transaction"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BIT2,Number of delay line taps for data bit 2 with correctly captured DLP in last read transaction"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BIT1,Number of delay line taps for data bit 1 with correctly captured DLP in last read transaction"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BIT0,Number of delay line taps for data bit 0 with correctly captured DLP in last read transaction"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DL_STATUS1,Data Learning Status Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BIT7,Number of delay line taps for data bit 7 with correctly captured DLP in last read transaction"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BIT6,Number of delay line taps for data bit 6 with correctly captured DLP in last read transaction"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BIT5,Number of delay line taps for data bit 5 with correctly captured DLP in last read transaction"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BIT4,Number of delay line taps for data bit 4 with correctly captured DLP in last read transaction"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DELAY_TAP_SEL,Delay Tap Select Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SEL,Delay line tap selection in output / feedback clock based capture scheme (CLOCK_IF_RX_SEL = [0..3]) and RWDS capture scheme (CLOCK_IF_RX_SEL = [6..7])"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "TX_CMD_FIFO_STATUS,Transmitter command FIFO status"
|
|
bitfld.long 0x00 0.--3. "USED4,Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "TX_CMD_FIFO_WR,Transmitter command FIFO"
|
|
hexmask.long 0x00 0.--26. 1. "DATA27,N/A"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TX_DATA_FIFO_CTL,Transmitter data FIFO control"
|
|
bitfld.long 0x00 0.--2. "TX_TRIGGER_LEVEL,Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE the trigger is NOT activated in XIP_MODE): - Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TX_DATA_FIFO_STATUS,Transmitter data FIFO status"
|
|
bitfld.long 0x00 0.--3. "USED4,Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x90++0x03
|
|
line.long 0x00 "TX_DATA_FIFO_WR1,Transmitter data FIFO"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA0,TX data (written to TX data FIFO)"
|
|
wgroup.long 0x94++0x03
|
|
line.long 0x00 "TX_DATA_FIFO_WR2,Transmitter data FIFO"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA1,TX data (written to TX data FIFO second byte)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA0,TX data (written to TX data FIFO first byte)"
|
|
wgroup.long 0x98++0x03
|
|
line.long 0x00 "TX_DATA_FIFO_WR4,Transmitter data FIFO"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA3,TX data (written to TX data FIFO fourth byte)"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA2,TX data (written to TX data FIFO third byte)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA1,TX data (written to TX data FIFO second byte)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA0,TX data (written to TX data FIFO first byte)"
|
|
wgroup.long 0x9C++0x03
|
|
line.long 0x00 "TX_DATA_FIFO_WR1ODD,Transmitter data FIFO"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA0,TX data (written to TX data FIFO)"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RX_DATA_MMIO_FIFO_CTL,Receiver data MMIO FIFO control"
|
|
bitfld.long 0x00 0.--2. "RX_TRIGGER_LEVEL,Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE the trigger is NOT activated in XIP_MODE): - Trigger is active when RX_DATA_MMIO_FIFO_STATUS.USED > TRIGGER_LEVEL" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "RX_DATA_MMIO_FIFO_STATUS,Receiver data MMIO FIFO status"
|
|
bitfld.long 0x00 0.--3. "USED4,Number of entries that are used in the RX data MMIO FIFO (only available in MMIO_MODE)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "RX_DATA_FIFO_STATUS,Receiver data FIFO status"
|
|
bitfld.long 0x00 8. "RX_SR_USED,Data available in RX Shift Register i.e" "0,1"
|
|
bitfld.long 0x00 0.--4. "USED5,Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "RX_DATA_MMIO_FIFO_RD1,Receiver data MMIO FIFO"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA0,RX data (read from RX data FIFO)"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "RX_DATA_MMIO_FIFO_RD2,Receiver data MMIO FIFO"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA1,RX data (read from RX data FIFO second byte)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA0,RX data (read from RX data FIFO first byte)"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "RX_DATA_MMIO_FIFO_RD4,Receiver data MMIO FIFO"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA3,RX data (read from RX data FIFO fourth byte)"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA2,RX data (read from RX data FIFO third byte)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA1,RX data (read from RX data FIFO second byte)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA0,RX data (read from RX data FIFO first byte)"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "RX_DATA_MMIO_FIFO_RD1_SILENT,Receiver data MMIO FIFO silent"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA0,RX data (read from RX data FIFO)"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SLOW_CA_CTL,Slow cache control"
|
|
bitfld.long 0x00 31. "ENABLED,Cache enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 30. "PREF_EN,Prefetch enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 24.--25. "SET_ADDR,Specifies the cache set for which cache information is provided in SLOW_CA_STATUS0/1/2" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "WAY,Specifies the cache way for which cache information is provided in SLOW_CA_STATUS0/1/2" "0,1,2,3"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "SLOW_CA_CMD,Slow cache command"
|
|
bitfld.long 0x00 0. "INV,Cache and prefetch buffer invalidation" "0,1"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "FAST_CA_CTL,Fast cache control"
|
|
bitfld.long 0x00 31. "ENABLED,See SLOW_CA_CTL.ENABLED" "0,1"
|
|
bitfld.long 0x00 30. "PREF_EN,See SLOW_CA_CTL.PREF_EN" "0,1"
|
|
bitfld.long 0x00 24.--25. "SET_ADDR,See SLOW_CA_CTL.SET_ADDR" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "WAY,See SLOW_CA_CTL.WAY" "0,1,2,3"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "FAST_CA_CMD,Fast cache command"
|
|
bitfld.long 0x00 0. "INV,See SLOW_CA_CMD.INV" "0,1"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CRYPTO_CMD,Cryptography Command"
|
|
bitfld.long 0x00 0. "START,SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR)" "0,1"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "CRYPTO_INPUT0,Cryptography input 0"
|
|
hexmask.long 0x00 0.--31. 1. "INPUT,Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "CRYPTO_INPUT1,Cryptography input 1"
|
|
hexmask.long 0x00 0.--31. 1. "INPUT,Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "CRYPTO_INPUT2,Cryptography input 2"
|
|
hexmask.long 0x00 0.--31. 1. "INPUT,Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "CRYPTO_INPUT3,Cryptography input 3"
|
|
hexmask.long 0x00 0.--31. 1. "INPUT,Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]"
|
|
wgroup.long 0x240++0x03
|
|
line.long 0x00 "CRYPTO_KEY0,Cryptography key 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]"
|
|
wgroup.long 0x244++0x03
|
|
line.long 0x00 "CRYPTO_KEY1,Cryptography key 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]"
|
|
wgroup.long 0x248++0x03
|
|
line.long 0x00 "CRYPTO_KEY2,Cryptography key 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]"
|
|
wgroup.long 0x24C++0x03
|
|
line.long 0x00 "CRYPTO_KEY3,Cryptography key 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "CRYPTO_OUTPUT0,Cryptography output 0"
|
|
hexmask.long 0x00 0.--31. 1. "OUTPUT,Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "CRYPTO_OUTPUT1,Cryptography output 1"
|
|
hexmask.long 0x00 0.--31. 1. "OUTPUT,Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "CRYPTO_OUTPUT2,Cryptography output 2"
|
|
hexmask.long 0x00 0.--31. 1. "OUTPUT,Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "CRYPTO_OUTPUT3,Cryptography output 3"
|
|
hexmask.long 0x00 0.--31. 1. "OUTPUT,Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "CRC_CMD,CRC Command"
|
|
bitfld.long 0x00 1. "CONTINUE,SW sets this field to '1' to continue a CRC calculation over the 64 CRC input bits provided in CRC_INPUT0 and CRC_INPUT1 using the current CRC output in CRC_OUTPUT as CRC feedback" "0,1"
|
|
bitfld.long 0x00 0. "START,SW sets this field to '1' to start a CRC calculation over the 64 CRC input bits provided in CRC_INPUT0 and CRC_INPUT1 using 0xFF as CRC feedback" "0,1"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "CRC_INPUT0,CRC input 0"
|
|
hexmask.long 0x00 0.--31. 1. "INPUT,Lower 32 input bits to the CRC engine"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "CRC_INPUT1,CRC input 1"
|
|
hexmask.long 0x00 0.--31. 1. "INPUT,Higher 32 input bits to the CRC engine"
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "CRC_OUTPUT,CRC output"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CRC_OUTPUT,CRC engine output"
|
|
group.long 0x7C0++0x03
|
|
line.long 0x00 "INTR,Interrupt register"
|
|
bitfld.long 0x00 17. "FS_STATUS_ERROR,Functional Safety Status Error" "0,1"
|
|
bitfld.long 0x00 16. "CRC_ERROR,CRC Error" "0,1"
|
|
bitfld.long 0x00 12. "DL_WARNING,Data Learning Warning (for at least one input data line only 1 or 2 delay line taps resulted in a correct DLP capturing when CTL.INT_CLOCK_DL_ENABLED = 1)" "0,1"
|
|
bitfld.long 0x00 8. "DL_FAIL,Data Learning Failed (no DLP match found on at least one of the input data lines when CTL.INT_CLOCK_DL_ENABLED = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RX_DATA_MMIO_FIFO_UNDERFLOW,Activated in MMIO mode on an AHB-Lite read transfer from the RX data MMIO FIFO (RX_DATA_MMIO_FIFO_RD1 RX_DATA_MMIO_FIFO_RD2 RX_DATA_MMIO_FIFO_RD4) with not enough entries available" "0,1"
|
|
bitfld.long 0x00 4. "TX_DATA_FIFO_OVERFLOW,Activated in MMIO mode on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1 TX_DATA_FIFO_WR2 TX_DATA_FIFO_WR4) with not enough free entries available" "0,1"
|
|
bitfld.long 0x00 3. "TX_CMD_FIFO_OVERFLOW,Activated in MMIO mode on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available" "0,1"
|
|
bitfld.long 0x00 2. "XIP_ALIGNMENT_ERROR,Activated in XIP mode when: - a write transfer is requested and - Dual-Quad SPI mode (selected device's ADDR_CTL.DIV2 is '1') is selected or - Octal SPI DDR mode (selected device's DATA_CTL.DDR_MODE = '1' and DATA_CTL.WIDTH = '3') or.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TR_RX_REQ,Activated in MMIO mode when a RX data FIFO trigger 'tr_rx_req' is activated" "0,1"
|
|
bitfld.long 0x00 0. "TR_TX_REQ,Activated in MMIO mode when a TX data FIFO trigger 'tr_tx_req' is activated" "0,1"
|
|
group.long 0x7C4++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x00 17. "FS_STATUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 16. "CRC_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 12. "DL_WARNING,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 8. "DL_FAIL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RX_DATA_MMIO_FIFO_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 4. "TX_DATA_FIFO_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 3. "TX_CMD_FIFO_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 2. "XIP_ALIGNMENT_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TR_RX_REQ,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 0. "TR_TX_REQ,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long 0x7C8++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 17. "FS_STATUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 16. "CRC_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 12. "DL_WARNING,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 8. "DL_FAIL,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RX_DATA_MMIO_FIFO_UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 4. "TX_DATA_FIFO_OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 3. "TX_CMD_FIFO_OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 2. "XIP_ALIGNMENT_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TR_RX_REQ,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
bitfld.long 0x00 0. "TR_TX_REQ,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long 0x7CC++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x00 17. "FS_STATUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 16. "CRC_ERROR,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 12. "DL_WARNING,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 8. "DL_FAIL,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RX_DATA_MMIO_FIFO_UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 4. "TX_DATA_FIFO_OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 3. "TX_CMD_FIFO_OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 2. "XIP_ALIGNMENT_ERROR,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TR_RX_REQ,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 0. "TR_TX_REQ,Logical and of corresponding request and mask bits" "0,1"
|
|
repeat 2. (increment 0 1)(increment 0 0x80)
|
|
tree "DEVICE[$1]"
|
|
group.long ($2+0x800)++0x03
|
|
line.long 0x00 "CTL,Control"
|
|
bitfld.long 0x00 31. "ENABLED,Device enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 30. "TOTAL_TIMEOUT_EN,Total transfer timeout enable" "0,1"
|
|
hexmask.long.word 0x00 16.--29. 1. "TOTAL_TIMEOUT,Total transfer timeout in clk_mem cycles"
|
|
newline
|
|
bitfld.long 0x00 15. "MERGE_EN,Continous transfer merge enable: '0': Disabled" "0,1"
|
|
bitfld.long 0x00 12.--14. "MERGE_TIMEOUT,Continuous transfer merge timeout in clk_mem cycles" "0: Timeout after 1 clk_mem cycle,1: Timeout after 2^4 = 16 clk_mem cycles,2: Timeout after 2^8 = 256 clk_mem cycles,3: Timeout after 2^12 = 4096 clk_mem cycles,4: Timeout after 2^16 = 65536 clk_mem cycles,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
bitfld.long 0x00 8.--9. "DATA_SEL,Specifies the connection of the IP's data lines (spi_data[0] ... spi_data[7]) to the device's data lines (SI/IO0 SO/IO1 IO2 IO3 IO4 IO5 IO6 IO7): '0': spi_data[0] = IO0 spi_data[1] = IO1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4. "CRYPTO_EN,Cryptography on read/write accesses: '0': disabled" "0,1"
|
|
bitfld.long 0x00 0. "WR_EN,Write enable: '0': write transfers are not allowed to this device" "0,1"
|
|
group.long ($2+0x808)++0x03
|
|
line.long 0x00 "ADDR,Device region base address"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "ADDR,Specifies the base address of the device region"
|
|
group.long ($2+0x80C)++0x03
|
|
line.long 0x00 "MASK,Device region mask"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "MASK,Specifies the size of the device region"
|
|
group.long ($2+0x820)++0x03
|
|
line.long 0x00 "ADDR_CTL,Address control"
|
|
bitfld.long 0x00 8. "DIV2,Specifies if the AHB-Lite bus transfer address is divided by 2 or not: '0': No divide by 2" "0,1"
|
|
bitfld.long 0x00 0.--2. "SIZE3,N/A" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0x830)++0x03
|
|
line.long 0x00 "RD_STATUS,Read status"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FS_STATUS,Provides the Functional Safety Status Register of the memory received with the last read transfer"
|
|
group.long ($2+0x840)++0x03
|
|
line.long 0x00 "RD_CMD_CTL,Read command control"
|
|
bitfld.long 0x00 30.--31. "PRESENT2,Presence of command field: '0': not present '1': present (1 Byte) '2': present (2 Byte for OPI) Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') either the HB protocol needs to be selected (by ADDR_CTL.SIZE3='7') or this.." "0,1,2,3"
|
|
bitfld.long 0x00 18. "DDR_MODE,Mode of transfer rate: '0': SDR mode '1': DDR mode" "0,1"
|
|
bitfld.long 0x00 16.--17. "WIDTH,Width of data transfer: '0': 1 bit/cycle (single data transfer)" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CODEH,Command high byte code"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CODE,Command byte code"
|
|
group.long ($2+0x844)++0x03
|
|
line.long 0x00 "RD_ADDR_CTL,Read address control"
|
|
bitfld.long 0x00 18. "DDR_MODE,Mode of transfer rate" "0,1"
|
|
bitfld.long 0x00 16.--17. "WIDTH,Width of transfer" "0,1,2,3"
|
|
group.long ($2+0x848)++0x03
|
|
line.long 0x00 "RD_MODE_CTL,Read mode control"
|
|
bitfld.long 0x00 30.--31. "PRESENT2,Presence of mode field: '0': not present '1': present (1 Byte) '2': present (2 Byte for OPI) Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') this field needs to be set to PRESENT2='2' to generate a mode field (or to.." "0,1,2,3"
|
|
bitfld.long 0x00 18. "DDR_MODE,Mode of transfer rate" "0,1"
|
|
bitfld.long 0x00 16.--17. "WIDTH,Width of transfer" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CODEH,Mode high byte code"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CODE,Mode byte code"
|
|
group.long ($2+0x84C)++0x03
|
|
line.long 0x00 "RD_DUMMY_CTL,Read dummy control"
|
|
bitfld.long 0x00 30.--31. "PRESENT2,Presence of dummy cycles: '0': not present '1': present '2': present - Dummy cycles are doubled when RWDS refresh indicator is high during CA cycle" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "SIZE5,Number of dummy cycles (minus 1): '0': 1 cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long ($2+0x850)++0x03
|
|
line.long 0x00 "RD_DATA_CTL,Read data control"
|
|
bitfld.long 0x00 18. "DDR_MODE,Mode of transfer rate" "0,1"
|
|
bitfld.long 0x00 16.--17. "WIDTH,Width of transfer" "0,1,2,3"
|
|
group.long ($2+0x854)++0x03
|
|
line.long 0x00 "RD_CRC_CTL,Read Bus CRC control"
|
|
bitfld.long 0x00 31. "DATA_CRC_PRESENT,Presence of data CRC field: '0': not present '1': present Note: Width and data transfer mode (SDR or DDR) of read data CRC fields are the same as for the associated read data fields i.e" "0,1"
|
|
bitfld.long 0x00 30. "CMD_ADDR_CRC_PRESENT,Presence of command / address CRC field: '0': not present '1': present Note: For octal data transfer with DDR mode (RD_CRC_CTL.WIDTH='3' and RD_CRC_CTL.DDR_MODE='1') the command / address CRC byte is sent twice otherwise the command.." "0,1"
|
|
bitfld.long 0x00 28. "DATA_CRC_CHECK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "CMD_ADDR_CRC_INPUT,Specifies which fields are included in the command / address CRC generation" "0,1"
|
|
bitfld.long 0x00 26. "CMD_ADDR_CRC_DDR_MODE,Mode of transfer rate of command / address CRC field" "0,1"
|
|
bitfld.long 0x00 24.--25. "CMD_ADDR_CRC_WIDTH,Width of command / address CRC field" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_CRC_INPUT_SIZE,Number of input data bytes for CRC generation (minus 1) i.e"
|
|
hexmask.long.byte 0x00 8.--15. 1. "STATUS_ERROR_POL,Specifies the polarity of the Functional Safety Status field bits"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STATUS_CHECK_MASK,Specifies which of the Functional Safety Status field bits are checked"
|
|
group.long ($2+0x858)++0x03
|
|
line.long 0x00 "RD_BOUND_CTL,Read boundary control"
|
|
bitfld.long 0x00 31. "PRESENT,Presence of first page boundary latency cycles: '0': not present '1': present" "0,1"
|
|
bitfld.long 0x00 28. "SUBSEQ_BOUND_EN,Enable subsequent page boundary latency cycles" "0,1"
|
|
bitfld.long 0x00 20.--21. "SUB_PAGE_NR,Specifies the number of sub pages per page" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "SUB_PAGE_SIZE,Specifies the size of a memory sub page 'sub_page_size'" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "SIZE5,Number of base latency cycles (minus 1) used for calculating the number of fist page boundary crossing latency cycles: '0': base_latency = 1 cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long ($2+0x860)++0x03
|
|
line.long 0x00 "WR_CMD_CTL,Write command control"
|
|
bitfld.long 0x00 30.--31. "PRESENT2,Presence of command field: '0': not present '1': present (1 Byte) '2': present (2 Byte for OPI) Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') either the HB protocol needs to be selected (by ADDR_CTL.SIZE3='7') or this.." "0,1,2,3"
|
|
bitfld.long 0x00 18. "DDR_MODE,Mode of transfer rate" "0,1"
|
|
bitfld.long 0x00 16.--17. "WIDTH,Width of transfer" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CODEH,Command high byte code"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CODE,Command byte code"
|
|
group.long ($2+0x864)++0x03
|
|
line.long 0x00 "WR_ADDR_CTL,Write address control"
|
|
bitfld.long 0x00 18. "DDR_MODE,Mode of transfer rate" "0,1"
|
|
bitfld.long 0x00 16.--17. "WIDTH,Width of transfer" "0,1,2,3"
|
|
group.long ($2+0x868)++0x03
|
|
line.long 0x00 "WR_MODE_CTL,Write mode control"
|
|
bitfld.long 0x00 30.--31. "PRESENT2,Presence of mode field: '0': not present '1': present (1 Byte) '2': present (2 Byte for OPI) Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') this field needs to be set to PRESENT2='2' to generate a mode field (or to.." "0,1,2,3"
|
|
bitfld.long 0x00 18. "DDR_MODE,Mode of transfer rate" "0,1"
|
|
bitfld.long 0x00 16.--17. "WIDTH,Width of transfer" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CODEH,Mode high byte code"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CODE,Mode byte code"
|
|
group.long ($2+0x86C)++0x03
|
|
line.long 0x00 "WR_DUMMY_CTL,Write dummy control"
|
|
bitfld.long 0x00 30.--31. "PRESENT2,Presence of dummy cycles: '0': not present '1': present '2': present - Dummy cycles are doubled when RWDS refresh indicator is high during CA cycle" "0,1,2,3"
|
|
bitfld.long 0x00 17. "RWDS_EN,Read-Write-Data-Strobe Enable" "0,1"
|
|
bitfld.long 0x00 0.--4. "SIZE5,Number of dummy cycles (minus 1): '0': 1 cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long ($2+0x870)++0x03
|
|
line.long 0x00 "WR_DATA_CTL,Write data control"
|
|
bitfld.long 0x00 18. "DDR_MODE,Mode of transfer rate" "0,1"
|
|
bitfld.long 0x00 16.--17. "WIDTH,Width of transfer" "0,1,2,3"
|
|
group.long ($2+0x874)++0x03
|
|
line.long 0x00 "WR_CRC_CTL,Write Bus CRC control"
|
|
bitfld.long 0x00 31. "DATA_CRC_PRESENT,Presence of data CRC field: '0': not present '1': present Note: Width and data transfer mode (SDR or DDR) of read data CRC fields are the same as for the associated read data fields i.e" "0,1"
|
|
bitfld.long 0x00 30. "CMD_ADDR_CRC_PRESENT,Presence of command / address CRC field: '0': not present '1': present Note: For octal data transfer with DDR mode (RD_CRC_CTL.WIDTH='3' and RD_CRC_CTL.DDR_MODE='1') the command / address CRC byte is sent twice otherwise the command.." "0,1"
|
|
bitfld.long 0x00 27. "CMD_ADDR_CRC_INPUT,Specifies which fields are included in the command / address CRC generation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "CMD_ADDR_CRC_DDR_MODE,Mode of transfer rate of command / address CRC field" "0,1"
|
|
bitfld.long 0x00 24.--25. "CMD_ADDR_CRC_WIDTH,Width of command / address CRC field" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_CRC_INPUT_SIZE,Number of input data bytes for CRC generation (minus 1) i.e"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SRSS (SRSS Core Registers)"
|
|
base ad:0x40260000
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "PWR_LVD_STATUS,High Voltage / Low Voltage Detector (HVLVD) Status Register"
|
|
bitfld.long 0x00 0. "HVLVD1_OUT,HVLVD1 output" "0: below voltage threshold,1: above voltage threshold"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "PWR_LVD_STATUS2,High Voltage / Low Voltage Detector (HVLVD) Status Register #2"
|
|
bitfld.long 0x00 0. "HVLVD2_OUT,HVLVD2 output" "0: below voltage threshold,1: above voltage threshold"
|
|
repeat 16. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "CLK_DSI_SELECT[$1],Clock DSI Select Register $1"
|
|
bitfld.long 0x00 0.--4. "DSI_MUX,Selects a DSI source or low frequency clock for use in a clock path" "0: DSI0 - dsi_out[0],1: DSI1 - dsi_out[1],2: DSI2 - dsi_out[2],3: DSI3 - dsi_out[3],4: DSI4 - dsi_out[4],5: DSI5 - dsi_out[5],6: DSI6 - dsi_out[6],7: DSI7 - dsi_out[7],8: DSI8 - dsi_out[8],9: DSI9 - dsi_out[9],10: DSI10 - dsi_out[10],11: DSI11 - dsi_out[11],12: DSI12 - dsi_out[12],13: DSI13 - dsi_out[13],14: DSI14 - dsi_out[14],15: DSI15 - dsi_out[15],16: ILO0 - Internal Low-speed Oscillator #0,17: WCO - Watch-Crystal Oscillator,18: ALTLF - Alternate Low-Frequency Clock,19: PILO - Precision Internal Low-speed Oscillator,20: ILO1 - Internal Low-speed Oscillator #1 if..,?..."
|
|
repeat.end
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CLK_OUTPUT_FAST,Fast Clock Output Select Register"
|
|
bitfld.long 0x00 24.--27. "HFCLK_SEL1,Selects a HFCLK tree for use in fast clock output #1 logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PATH_SEL1,Selects a clock path to use in fast clock output #1 logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "FAST_SEL1,Select signal for fast clock output #1" "0: Disabled - output is 0,1: External Crystal Oscillator (ECO),2: External clock input (EXTCLK),3: Alternate High-Frequency (ALTHF) clock input..,4: Timer clock,5: Selects the clock path chosen by PATH_SEL1..,6: Selects the output of the HFCLK_SEL1 mux,7: Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "HFCLK_SEL0,Selects a HFCLK tree for use in fast clock output #0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PATH_SEL0,Selects a clock path to use in fast clock output #0 logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "FAST_SEL0,Select signal for fast clock output #0" "0: Disabled - output is 0,1: External Crystal Oscillator (ECO),2: External clock input (EXTCLK),3: Alternate High-Frequency (ALTHF) clock input..,4: Timer clock,5: Selects the clock path chosen by PATH_SEL0..,6: Selects the output of the HFCLK_SEL0 mux,7: Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0,?..."
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group.long 0x144++0x03
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line.long 0x00 "CLK_OUTPUT_SLOW,Slow Clock Output Select Register"
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bitfld.long 0x00 4.--7. "SLOW_SEL1,Select signal for slow clock output #1" "0: Disabled - output is 0,1: Internal Low Speed Oscillator (ILO),2: Watch-Crystal Oscillator (WCO),3: Root of the Backup domain clock tree (BAK),4: Alternate low-frequency clock input to SRSS..,5: Root of the low-speed clock tree (LFCLK),6: Internal Main Oscillator (IMO),7: Sleep Controller clock (SLPCTRL),8: Precision Internal Low Speed Oscillator (PILO),9: Internal Low Speed Oscillator (ILO1) if..,10: ECO Prescaler (ECO_PRESCALER),11: LPECO,12: LPECO Prescaler (LPECO_PRESCALER),?..."
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bitfld.long 0x00 0.--3. "SLOW_SEL0,Select signal for slow clock output #0" "0: Disabled - output is 0,1: Internal Low Speed Oscillator (ILO0),2: Watch-Crystal Oscillator (WCO),3: Root of the Backup domain clock tree (BAK),4: Alternate low-frequency clock input to SRSS..,5: Root of the low-speed clock tree (LFCLK),6: Internal Main Oscillator (IMO),7: Sleep Controller clock (SLPCTRL),8: Precision Internal Low Speed Oscillator (PILO),9: Internal Low Speed Oscillator (ILO1) if..,10: ECO Prescaler (ECO_PRESCALER),11: LPECO,12: LPECO Prescaler (LPECO_PRESCALER),?..."
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group.long 0x148++0x03
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line.long 0x00 "CLK_CAL_CNT1,Clock Calibration Counter 1"
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rbitfld.long 0x00 31. "CAL_COUNTER_DONE,Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up" "0,1"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAL_COUNTER1,Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST)"
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rgroup.long 0x14C++0x03
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line.long 0x00 "CLK_CAL_CNT2,Clock Calibration Counter 2"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAL_COUNTER2,Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST)"
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group.long 0x200++0x03
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line.long 0x00 "SRSS_INTR,SRSS Interrupt Register"
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bitfld.long 0x00 5. "CLK_CAL,Clock calibration counter is done" "0,1"
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bitfld.long 0x00 2. "HVLVD2,Interrupt for low voltage detector HVLVD2" "0,1"
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bitfld.long 0x00 1. "HVLVD1,Interrupt for low voltage detector HVLVD1" "0,1"
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group.long 0x204++0x03
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line.long 0x00 "SRSS_INTR_SET,SRSS Interrupt Set Register"
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bitfld.long 0x00 5. "CLK_CAL,Set interrupt for clock calibration counter done" "0,1"
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bitfld.long 0x00 2. "HVLVD2,Set interrupt for low voltage detector HVLVD2" "0,1"
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bitfld.long 0x00 1. "HVLVD1,Set interrupt for low voltage detector HVLVD1" "0,1"
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group.long 0x208++0x03
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line.long 0x00 "SRSS_INTR_MASK,SRSS Interrupt Mask Register"
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bitfld.long 0x00 5. "CLK_CAL,Mask for clock calibration done" "0,1"
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bitfld.long 0x00 2. "HVLVD2,Mask for low voltage detector HVLVD2" "0,1"
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bitfld.long 0x00 1. "HVLVD1,Mask for low voltage detector HVLVD1" "0,1"
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rgroup.long 0x20C++0x03
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line.long 0x00 "SRSS_INTR_MASKED,SRSS Interrupt Masked Register"
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bitfld.long 0x00 5. "CLK_CAL,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 2. "HVLVD2,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "HVLVD1,Logical and of corresponding request and mask bits" "0,1"
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rgroup.long 0x1000++0x03
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line.long 0x00 "PWR_CTL,Power Mode Control"
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bitfld.long 0x00 5. "LPM_READY,Indicates whether certain low power functions are ready" "0: If a low power circuit operation is requested..,1: Normal operation"
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bitfld.long 0x00 4. "DEBUG_SESSION,Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)" "0: No debug session active,1: Debug session is active"
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bitfld.long 0x00 0.--1. "POWER_MODE,Current power mode of the device" "0: System is resetting,1: At least one CPU is running,2: No CPUs are running,3: Main high-frequency clock is off low speed.."
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group.long 0x1004++0x03
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line.long 0x00 "PWR_CTL2,Power Mode Control 2"
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bitfld.long 0x00 31. "PLL_LS_BYPASS,Bypass level shifter inside the PLL" "0: Do not bypass the level shifter,1: Bypass the level shifter"
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bitfld.long 0x00 28. "BGREF_LPMODE,Control the circuit-level power mode of the Bandgap Reference circuits" "0: Bandgap Reference circuits operate in higher,1: Bandgap Reference circuits operate in low power"
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bitfld.long 0x00 27. "PORBOD_LPMODE,Control the power mode of the POR/BOD circuits" "0: POR/BOD circuits operate in normal mode,1: POR/BOD circuits operate in low power mode"
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bitfld.long 0x00 26. "REFI_LPMODE,Control the power mode of the reference current generator" "0: Current reference generator operates in normal,1: Current reference generator operates in low"
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rbitfld.long 0x00 25. "REFI_OK,Indicates that the current reference is ready" "0,1"
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bitfld.long 0x00 24. "REFI_DIS,N/A" "0,1"
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bitfld.long 0x00 22. "REFVBUF_LPMODE,Control the power mode of the 800mV voltage reference buffer" "0: Voltage Reference Buffer operates in normal..,1: Voltage Reference Buffer operates in low power"
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rbitfld.long 0x00 21. "REFVBUF_OK,Indicates that the voltage reference buffer is ready" "0,1"
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bitfld.long 0x00 20. "REFVBUF_DIS,Disable the voltage reference buffer" "0,1"
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rbitfld.long 0x00 17. "REFV_OK,Indicates that the normal mode of the voltage reference is ready" "0,1"
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bitfld.long 0x00 16. "REFV_DIS,N/A" "0,1"
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bitfld.long 0x00 12. "NWELL_REG_DIS,Explicitly disable the Nwell regulator" "0: Nwell Regulator is on,1: Nwell Regulator is explicitly disabled"
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bitfld.long 0x00 8. "RET_REG_DIS,Explicitly disable the Retention regulator" "0: Retention Regulator is not explicitly disabled,1: Retention Regulator is explicitly disabled"
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bitfld.long 0x00 4. "DPSLP_REG_DIS,Explicity disable the DeepSleep regulator including circuits shared with the Active Regulator" "0: DeepSleep Regulator is not explicitly disabled,1: DeepSleep Regulator is explicitly disabled"
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bitfld.long 0x00 2. "LINREG_LPMODE,Control the power mode of the Linear Regulator" "0: Linear Regulator operates in normal mode,1: Linear Regulator operates in low power mode"
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rbitfld.long 0x00 1. "LINREG_OK,Status of the linear Core Regulator" "0,1"
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bitfld.long 0x00 0. "LINREG_DIS,Explicitly disable the linear Core Regulator" "0: Linear Core Regulator is not explicitly..,1: Linear Core Regulator is explicitly disabled"
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group.long 0x1008++0x03
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line.long 0x00 "PWR_HIBERNATE,HIBERNATE Mode Register"
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bitfld.long 0x00 31. "HIBERNATE,Firmware sets this bit to enter HIBERNATE mode" "0,1"
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bitfld.long 0x00 30. "HIBERNATE_DISABLE,Hibernate disable bit" "0: Normal operation HIBERNATE works as described,1: Further writes to this register are ignored"
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bitfld.long 0x00 24.--27. "MASK_HIBPIN,When set HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "POLARITY_HIBPIN,Each bit sets the active polarity of the corresponding wakeup pin" "0: Pin input of 0 will wakeup the part from..,1: Pin input of 1 will wakeup the part from..,?..."
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bitfld.long 0x00 19. "MASK_HIBWDT,When set HIBERNATE will wakeup for WDT interrupt" "0,1"
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bitfld.long 0x00 18. "MASK_HIBALARM,When set HIBERNATE will wakeup for a RTC interrupt" "0,1"
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bitfld.long 0x00 17. "FREEZE,Firmware sets this bit to freeze the configuration mode and state of all GPIOs and SIOs in the system" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "UNLOCK,This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate"
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hexmask.long.byte 0x00 0.--7. 1. "TOKEN,Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event"
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group.long 0x1010++0x03
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line.long 0x00 "PWR_BUCK_CTL,Buck Control Register"
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bitfld.long 0x00 31. "BUCK_OUT1_EN,Enable for vccbuck1 output" "0,1"
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bitfld.long 0x00 30. "BUCK_EN,Master enable for buck converter" "0,1"
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bitfld.long 0x00 0.--2. "BUCK_OUT1_SEL,Voltage output selection for vccbuck1 output" "0: 0.85V,1: 0.875V,2: 0.90V,3: 0.95V,4: 1.05V,5: 1.10V,6: 1.15V,7: 1.20V"
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group.long 0x1014++0x03
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line.long 0x00 "PWR_BUCK_CTL2,Buck Control Register 2"
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bitfld.long 0x00 31. "BUCK_OUT2_EN,Enable for vccbuck2 output" "0,1"
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bitfld.long 0x00 30. "BUCK_OUT2_HW_SEL,Hardware control for vccbuck2 output" "0,1"
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bitfld.long 0x00 0.--2. "BUCK_OUT2_SEL,Voltage output selection for vccbuck2 output" "0: 1.15V,1: 1.20V,2: 1.25V,3: 1.30V,4: 1.35V,5: 1.40V,6: 1.45V,7: 1.50V"
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group.long 0x1018++0x03
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line.long 0x00 "PWR_SSV_CTL,Supply Supervision Control Register"
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bitfld.long 0x00 27. "OVDVCCD_ENABLE,Enable for OVD on vccd" "0,1"
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bitfld.long 0x00 24. "OVDVDDA_ENABLE,Enable for OVD on vdda" "0,1"
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bitfld.long 0x00 22.--23. "OVDVDDA_ACTION,Action taken when the OVD on vdda triggers" "0: No action,1: Generate a fault,2: Reset the chip,?..."
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bitfld.long 0x00 20. "OVDVDDA_VSEL,Selects the voltage threshold for OVD on vdda" "0: vddd>5.5V,1: vddd>5.0V"
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bitfld.long 0x00 19. "OVDVDDD_ENABLE,Enable for OVD on vddd" "0,1"
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bitfld.long 0x00 16. "OVDVDDD_VSEL,Selects the voltage threshold for OVD on vddd" "0: vddd>5.5V,1: vddd>5.0V"
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bitfld.long 0x00 11. "BODVCCD_ENABLE,Enable for BOD on vccd" "0,1"
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bitfld.long 0x00 8. "BODVDDA_ENABLE,Enable for BOD on vdda" "0,1"
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bitfld.long 0x00 6.--7. "BODVDDA_ACTION,Action taken when the BOD on vdda triggers" "0: No action,1: Generate a fault,2: Reset the chip,?..."
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bitfld.long 0x00 4. "BODVDDA_VSEL,Selects the voltage threshold for BOD on vdda" "0: vdda<2.7V,1: vdda<3.0V"
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bitfld.long 0x00 3. "BODVDDD_ENABLE,Enable for BOD on vddd" "0,1"
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bitfld.long 0x00 0. "BODVDDD_VSEL,Selects the voltage threshold for BOD on vddd" "0: vddd<2.7V,1: vddd<3.0V"
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rgroup.long 0x101C++0x03
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line.long 0x00 "PWR_SSV_STATUS,Supply Supervision Status Register"
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bitfld.long 0x00 17. "OCD_DPSLP_REG_OK,OCD indicates the current drawn from the linear DeepSleep Regulator is ok" "0,1"
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bitfld.long 0x00 16. "OCD_ACT_LINREG_OK,OCD indicates the current drawn from the linear Active Regulator is ok" "0,1"
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bitfld.long 0x00 10. "OVDVCCD_OK,OVD indicates vccd is ok" "0,1"
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bitfld.long 0x00 9. "OVDVDDA_OK,OVD indicates vdda is ok" "0,1"
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bitfld.long 0x00 8. "OVDVDDD_OK,OVD indicates vddd is ok" "0,1"
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bitfld.long 0x00 2. "BODVCCD_OK,BOD indicates vccd is ok" "0,1"
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bitfld.long 0x00 1. "BODVDDA_OK,BOD indicates vdda is ok" "0,1"
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bitfld.long 0x00 0. "BODVDDD_OK,BOD indicates vddd is ok" "0,1"
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group.long 0x1020++0x03
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line.long 0x00 "PWR_LVD_CTL,High Voltage / Low Voltage Detector (HVLVD) Configuration Register"
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bitfld.long 0x00 18. "HVLVD1_ACTION,Action taken when the threshold is crossed in the programmed directions(s)" "0: Generate an interrupt,1: Generate a fault"
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bitfld.long 0x00 16.--17. "HVLVD1_EDGE_SEL,Sets which edge(s) will trigger an action when the threshold is crossed" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
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bitfld.long 0x00 15. "HVLVD1_EN_HT,Enable HVLVD1 voltage monitor" "0,1"
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bitfld.long 0x00 14. "HVLVD1_DPSLP_EN_HT,Keep HVLVD1 voltage monitor enabled during DEEPSLEEP mode" "0,1"
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bitfld.long 0x00 8.--12. "HVLVD1_TRIPSEL_HT,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "HVLVD1_EN,Enable HVLVD1 voltage monitor" "0,1"
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bitfld.long 0x00 4.--6. "HVLVD1_SRCSEL,Source selection for HVLVD1" "0: Select VDDD,1: Select AMUXBUSA (VDDD branch),2: RSVD,3: VDDIO,4: Select AMUXBUSB (VDDD branch),?..."
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bitfld.long 0x00 0.--3. "HVLVD1_TRIPSEL,Threshold selection for HVLVD1" "0: rise=1.225V (nom) fall=1.2V (nom),1: rise=1.425V (nom) fall=1.4V (nom),2: rise=1.625V (nom) fall=1.6V (nom),3: rise=1.825V (nom) fall=1.8V (nom),4: rise=2.025V (nom) fall=2V (nom),5: rise=2.125V (nom) fall=2.1V (nom),6: rise=2.225V (nom) fall=2.2V (nom),7: rise=2.325V (nom) fall=2.3V (nom),8: rise=2.425V (nom) fall=2.4V (nom),9: rise=2.525V (nom) fall=2.5V (nom),10: rise=2.625V (nom) fall=2.6V (nom),11: rise=2.725V (nom) fall=2.7V (nom),12: rise=2.825V (nom) fall=2.8V (nom),13: rise=2.925V (nom) fall=2.9V (nom),14: rise=3.025V (nom) fall=3.0V (nom),15: rise=3.125V (nom) fall=3.1V (nom)"
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group.long 0x1024++0x03
|
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line.long 0x00 "PWR_LVD_CTL2,High Voltage / Low Voltage Detector (HVLVD) Configuration Register #2"
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bitfld.long 0x00 18. "HVLVD2_ACTION,Action taken when the threshold is crossed in the programmed directions(s)" "0: Generate an interrupt,1: Generate a fault"
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bitfld.long 0x00 16.--17. "HVLVD2_EDGE_SEL,Sets which edge(s) will trigger an action when the threshold is crossed" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
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bitfld.long 0x00 15. "HVLVD2_EN_HT,Enable HVLVD2 voltage monitor" "0,1"
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|
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bitfld.long 0x00 14. "HVLVD2_DPSLP_EN_HT,Keep HVLVD2 voltage monitor enabled during DEEPSLEEP mode" "0,1"
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|
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bitfld.long 0x00 8.--12. "HVLVD2_TRIPSEL_HT,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x1028++0x03
|
|
line.long 0x00 "PWR_REGHC_CTL,REGHC Control Register"
|
|
bitfld.long 0x00 31. "REGHC_CONFIGURED,Indicates the REGHC has been configured" "0,1"
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bitfld.long 0x00 30. "REGHC_TRANS_USE_OCD,N/A" "0,1"
|
|
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|
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hexmask.long.word 0x00 20.--29. 1. "REGHC_PMIC_STATUS_WAIT,Wait count in 4us steps after PMIC status ok"
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|
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bitfld.long 0x00 19. "REGHC_PMIC_STATUS_POLARITY,The polarity used to trigger a reset action based on the PMIC status input" "0,1"
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bitfld.long 0x00 18. "REGHC_PMIC_STATUS_INEN,Input buffer enable for PMIC status input" "0,1"
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|
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bitfld.long 0x00 17. "REGHC_PMIC_CTL_POLARITY,Polarity used to enable the PMIC" "0,1"
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bitfld.long 0x00 16. "REGHC_PMIC_CTL_OUTEN,Output enable for PMIC enable pin" "0,1"
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bitfld.long 0x00 12.--14. "REGHC_PMIC_RADJ,Reset voltage adjustment for PMIC as a factor (Vfbk/Vref) where Vfbk is the feedback voltage and Vref is the PMIC internal reference" "0: Vfbk/Vref=1.0000 Vreset=.800V@(Vref=0.8V),1: Vfbk/Vref=1.0556 Vreset=.844V@(Vref=0.8V),2: Vfbk/Vref=1.1111 Vreset=.889V@(Vref=0.8V),3: Vfbk/Vref=1.1250 Vreset=.900V@(Vref=0.8V),4: Vfbk/Vref=1.1667 Vreset=.933V@(Vref=0.8V),5: Vfbk/Vref=1.1875 Vreset=.950V@(Vref=0.8V),6: Vfbk/Vref=1.2500 Vreset=1.000V@(Vref=0.8V),7: Vfbk/Vref=1.3125 Vreset=1.050V@(Vref=0.8V)"
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bitfld.long 0x00 11. "REGHC_PMIC_USE_RADJ,Controls whether hardware sequencer enables reset voltage adjustment circuit when enabling a PMIC" "0,1"
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|
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bitfld.long 0x00 10. "REGHC_PMIC_USE_LINREG,For REGHC external PMIC mode controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd" "0: Internal Active Linear Regulator disabled after,1: Internal Active Linear Regulator kept enabled"
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bitfld.long 0x00 4.--8. "REGHC_VADJ,Regulator output trim according to the formula vadj=(1.020V + REGHC_VADJ*0.005V) plus an offset described below" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 2.--3. "REGHC_PMIC_DRV_VOUT,Setting for DRV_VOUT pin for PMIC mode" "0: DRV_VOUT=vccd*0.9/vadj,1: DRV_VOUT=vccd*0.8/vadj,2: DRV_VOUT=vccd*0.6/vadj,3: DRV_VOUT=vccd"
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|
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bitfld.long 0x00 0. "REGHC_MODE,REGHC control mode" "0: external transistor connected,1: external PMIC connected"
|
|
rgroup.long 0x102C++0x03
|
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line.long 0x00 "PWR_REGHC_STATUS,REGHC Status Register"
|
|
bitfld.long 0x00 31. "REGHC_SEQ_BUSY,Indicates the REGHC enable/disable sequencer is busy transitioning to/from REGHC" "0: Sequencer is not busy,1: Sequencer is busy either enabling or disabling"
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bitfld.long 0x00 12. "REGHC_PMIC_STATUS_OK,Indicates the PMIC status is ok" "0: PMIC status is not ok or PMIC input buffer is,1: PMIC status input buffer is enabled and"
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bitfld.long 0x00 9. "REGHC_OV_OUT,N/A" "0,1"
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|
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bitfld.long 0x00 8. "REGHC_UV_OUT,N/A" "0,1"
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|
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|
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bitfld.long 0x00 2. "REGHC_CKT_OK,Indicates the REGHC circuit is enabled and operating" "0: REGHC circuit is not ready,1: REGHC circuit is enabled and operating"
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|
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bitfld.long 0x00 1. "REGHC_OCD_OK,Indicates the over-current detector is operating and the current drawn from REGHC is within limits" "0: Current measurement exceeds limit or detector..,1: Current measurement within limit"
|
|
newline
|
|
bitfld.long 0x00 0. "REGHC_ENABLED,Indicates the state of the REGHC enable/disable sequencer" "0: REGHC sequencer indicates REGHC is disabled,1: REGHC sequencer indicates REGHC is enabled"
|
|
group.long 0x1030++0x03
|
|
line.long 0x00 "PWR_REGHC_CTL2,REGHC Control Register 2"
|
|
bitfld.long 0x00 31. "REGHC_EN,Enable REGHC" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "REGHC_PMIC_STATUS_TIMEOUT,Timeout while waiting for REGHC_PMIC_STATUS_OK==1 when switching to PMIC"
|
|
group.long 0x1038++0x03
|
|
line.long 0x00 "PWR_REGHC_CTL4,REGHC Control Register 4"
|
|
bitfld.long 0x00 31. "REGHC_PMIC_DPSLP,When operating in PMIC mode configures PMIC behavior during DEEPSLEEP" "0: Device operates from internal regulators during,1: DEEPSLEEP transition does not change PMIC.."
|
|
newline
|
|
bitfld.long 0x00 30. "REGHC_PMIC_VADJ_DIS,When operating in PMIC mode disables the VADJ circuitry" "0: Device generates VADJ when PMIC is enabled,1: Device does not generate VADJ and it must not.."
|
|
repeat 16. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x1040)++0x03
|
|
line.long 0x00 "PWR_HIB_DATA[$1],HIBERNATE Data Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "HIB_DATA,Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose"
|
|
repeat.end
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "PWR_PMIC_CTL,PMIC Control Register"
|
|
bitfld.long 0x00 31. "PMIC_CONFIGURED,Indicates the PMIC has been configured" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 20.--29. 1. "PMIC_STATUS_WAIT,Wait count in 4us steps after PMIC status ok"
|
|
newline
|
|
bitfld.long 0x00 19. "PMIC_STATUS_POLARITY,The polarity used to trigger a reset action based on the PMIC status input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "PMIC_STATUS_INEN,Input buffer enable for PMIC status input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "PMIC_CTL_POLARITY,Polarity used to enable the PMIC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "PMIC_CTL_OUTEN,Output enable for PMIC enable pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PMIC_VADJ_BUF_EN,Analog buffer enable on voltage adjust output" "0: Bypass buffer,1: Use analog buffer"
|
|
newline
|
|
bitfld.long 0x00 10. "PMIC_USE_LINREG,Controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd" "0: Internal Active Linear Regulator disabled after,1: Internal Active Linear Regulator kept enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--8. "PMIC_VADJ,Voltage adjustment output setting" "?,?,?,3: 1.040V,4: 1.049V,5: 1.057V,6: 1.066V,7: 1.074V,8: 1.083V,9: 1.091V,10: 1.099V,11: 1.108V,12: 1.116V,13: 1.125V,14: 1.133V,15: 1.142V,16: 1.150V,17: 1.158V,18: 1.167V,19: 1.175V,20: 1.184V,21: 1.192V,22: 1.201V,23: 1.209V,24: 1.218V,25: 1.226V,26: 1.234V,27: 1.243V,28: 1.251V others,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "PMIC_VREF,PMIC reference voltage setting" "0: Scale for vref=0.9V use PMIC_VADJ to set the,1: Scale for vref=0.8V use PMIC_VADJ to set the,2: Scale for vref=0.6V use PMIC_VADJ to set the,3: No scaling PMIC_VADJ has no effect"
|
|
rgroup.long 0x10C4++0x03
|
|
line.long 0x00 "PWR_PMIC_STATUS,PMIC Status Register"
|
|
bitfld.long 0x00 31. "PMIC_SEQ_BUSY,Indicates the PMIC enable/disable sequencer is busy transitioning to/from PMIC" "0: Sequencer is not busy,1: Sequencer is busy either enabling or disabling"
|
|
newline
|
|
bitfld.long 0x00 12. "PMIC_STATUS_OK,Indicates the PMIC status is ok" "0: PMIC status is not ok or PMIC input buffer is,1: PMIC status input buffer is enabled and"
|
|
newline
|
|
bitfld.long 0x00 0. "PMIC_ENABLED,Indicates the state of the PMIC enable/disable sequencer" "0: PMIC sequencer indicates PMIC is disabled,1: PMIC sequencer indicates PMIC is enabled"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "PWR_PMIC_CTL2,PMIC Control Register 2"
|
|
bitfld.long 0x00 31. "PMIC_EN,Enable PMIC" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PMIC_STATUS_TIMEOUT,Timeout while waiting for PMIC_STATUS_OK==1 when switching to PMIC"
|
|
group.long 0x10D0++0x03
|
|
line.long 0x00 "PWR_PMIC_CTL4,PMIC Control Register 4"
|
|
bitfld.long 0x00 31. "PMIC_DPSLP,Configures PMIC behavior during DEEPSLEEP" "0: Device operates from internal regulators during,1: DEEPSLEEP transition does not change PMIC.."
|
|
newline
|
|
bitfld.long 0x00 30. "PMIC_VADJ_DIS,Disables the VADJ circuitry" "0: Device generates VADJ when PMIC is enabled,1: Device does not generate VADJ and it must not.."
|
|
repeat 16. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x1200)++0x03
|
|
line.long 0x00 "CLK_PATH_SELECT[$1],Clock Path Select Register $1"
|
|
bitfld.long 0x00 0.--2. "PATH_MUX,Selects a source for clock PATH<i>" "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator,3: ALTHF - Alternate High-Frequency clock input..,4: DSI_MUX - Output of DSI mux for this path,5: LPECO - Low-Power External-Crystal Oscillator,?..."
|
|
repeat.end
|
|
repeat 16. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x1240)++0x03
|
|
line.long 0x00 "CLK_ROOT_SELECT[$1],Clock Root Select Register $1"
|
|
bitfld.long 0x00 31. "ENABLE,Enable for this clock root" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DIRECT_MUX,Direct selection mux that allows IMO to bypass most of the clock mux structure" "0: Select IMO,1: Select ROOT_MUX selection"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "ROOT_DIV,Selects predivider value for this clock root and DSI input" "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "ROOT_MUX,Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>" "0: Select PATH0 (can be configured for FLL),1: Select PATH1 (can be configured for PLL0 if..,2: Select PATH2 (can be configured for PLL1 if..,3: Select PATH3 (can be configured for PLL2 if..,4: Select PATH4 (can be configured for PLL3 if..,5: Select PATH5 (can be configured for PLL4 if..,6: Select PATH6 (can be configured for PLL5 if..,7: Select PATH7 (can be configured for PLL6 if..,8: Select PATH8 (can be configured for PLL7 if..,9: Select PATH9 (can be configured for PLL8 if..,10: Select PATH10 (can be configured for PLL9 if..,11: Select PATH11 (can be configured for PLL10..,12: Select PATH12 (can be configured for PLL11..,13: Select PATH13 (can be configured for PLL12..,14: Select PATH14 (can be configured for PLL13..,15: Select PATH15 (can be configured for PLL14.."
|
|
repeat.end
|
|
group.long 0x1500++0x03
|
|
line.long 0x00 "CLK_SELECT,Clock selection register"
|
|
bitfld.long 0x00 15. "PUMP_ENABLE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "PUMP_DIV,N/A" "0: NO_DIV,1: DIV_BY_2,2: DIV_BY_4,3: DIV_BY_8,4: DIV_BY_16,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PUMP_SEL,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "LFCLK_SEL,Select source for LFCLK" "0: ILO0 - Internal Low-speed Oscillator #0,1: WCO - Watch-Crystal Oscillator,2: ALTLF - Alternate Low-Frequency Clock,3: PILO - Precision ILO,4: ILO1 - Internal Low-speed Oscillator #1 if..,5: ECO_PRESCALER - External-Crystal Oscillator..,6: LPECO_PRESCALER - Low-Power External-Crystal..,?..."
|
|
group.long 0x1504++0x03
|
|
line.long 0x00 "CLK_TIMER_CTL,Timer Clock Control Register"
|
|
bitfld.long 0x00 31. "ENABLE,Obsolete" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "TIMER_DIV,Obsolete"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "TIMER_HF0_DIV,Obsolete" "0: Obsolete,1: Obsolete,2: Obsolete,3: Obsolete"
|
|
newline
|
|
bitfld.long 0x00 0. "TIMER_SEL,Obsolete" "0: Obsolete,1: Obsolete"
|
|
group.long 0x1508++0x03
|
|
line.long 0x00 "CLK_ILO0_CONFIG,ILO0 Configuration"
|
|
bitfld.long 0x00 31. "ENABLE,Master enable for ILO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "ILO0_MON_ENABLE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ILO0_BACKUP,This register indicates that ILO0 should stay enabled during XRES and HIBERNATE modes" "0: ILO0 turns off during XRES HIBERNATE and,1: ILO0 stays enabled as described above"
|
|
group.long 0x150C++0x03
|
|
line.long 0x00 "CLK_ILO1_CONFIG,ILO1 Configuration"
|
|
bitfld.long 0x00 31. "ENABLE,Master enable for ILO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "ILO1_MON_ENABLE,N/A" "0,1"
|
|
group.long 0x1518++0x03
|
|
line.long 0x00 "CLK_IMO_CONFIG,IMO Configuration"
|
|
bitfld.long 0x00 31. "ENABLE,Master enable for IMO oscillator" "0,1"
|
|
group.long 0x151C++0x03
|
|
line.long 0x00 "CLK_ECO_CONFIG,ECO Configuration Register"
|
|
bitfld.long 0x00 31. "ECO_EN,Master enable for ECO oscillator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "ECO_DIV_ENABLE,ECO prescaler enable command (mutually exclusive with ECO_DIV_DISABLE)" "0: Disable the divider using the ECO_DIV_DISABLE,1: Configure CLK_ECO_PRESCALE registers"
|
|
newline
|
|
bitfld.long 0x00 27. "ECO_DIV_DISABLE,ECO prescaler disable command (mutually exclusive with ECO_DIV_ENABLE)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "AGC_EN,Automatic Gain Control (AGC) enable" "0,1"
|
|
group.long 0x1520++0x03
|
|
line.long 0x00 "CLK_ECO_PRESCALE,ECO Prescaler Configuration Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "ECO_INT_DIV,10-bit integer value allows for ECO frequencies up to 33.55MHz"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "ECO_FRAC_DIV,8-bit fractional value sufficient to get prescaler output within the +/-65ppm calibration range"
|
|
newline
|
|
rbitfld.long 0x00 0. "ECO_DIV_ENABLED,ECO prescaler enabled" "0,1"
|
|
rgroup.long 0x1524++0x03
|
|
line.long 0x00 "CLK_ECO_STATUS,ECO Status Register"
|
|
bitfld.long 0x00 1. "ECO_READY,Indicates the ECO internal oscillator circuit has had enough time to fully stabilize" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ECO_OK,Indicates the ECO internal oscillator circuit has sufficient amplitude" "0,1"
|
|
group.long 0x1528++0x03
|
|
line.long 0x00 "CLK_PILO_CONFIG,Precision ILO Configuration Register"
|
|
bitfld.long 0x00 31. "PILO_EN,Enable PILO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "PILO_RESET_N,Reset the PILO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PILO_CLK_EN,Enable the PILO clock output" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "PILO_FFREQ,Fine frequency trim allowing +/-250ppm accuracy with periodic calibration"
|
|
group.long 0x1530++0x03
|
|
line.long 0x00 "CLK_FLL_CONFIG,FLL Configuration Register"
|
|
bitfld.long 0x00 31. "FLL_ENABLE,Master enable for FLL" "0: Block is powered off,1: Block is powered on"
|
|
newline
|
|
bitfld.long 0x00 24. "FLL_OUTPUT_DIV,Control bits for Output divider" "0: no division,1: divide by 2"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "FLL_MULT,Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref)"
|
|
group.long 0x1534++0x03
|
|
line.long 0x00 "CLK_FLL_CONFIG2,FLL Configuration Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "UPDATE_TOL,Update tolerance sets the error threshold for when the FLL will update the CCO frequency settings"
|
|
newline
|
|
abitfld.long 0x00 16.--23. "LOCK_TOL,Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input" "0x00=0: tolerate error of 1 count value,0x01=1: tolerate error of 2 count values,0xFF=255: tolerate error of 256 count values"
|
|
newline
|
|
abitfld.long 0x00 0.--12. "FLL_REF_DIV,Control bits for reference divider" "0x0000=0: illegal (undefined behavior),0x0001=1: divide by 1,0x1FFF=8191: divide by 8191"
|
|
group.long 0x1538++0x03
|
|
line.long 0x00 "CLK_FLL_CONFIG3,FLL Configuration Register 3"
|
|
bitfld.long 0x00 28.--29. "BYPASS_SEL,Bypass mux located just after FLL output" "0: Automatic using lock indicator,1: Similar to AUTO except the clock is gated off..,2: Select FLL reference input (bypass mode),3: Select FLL output"
|
|
newline
|
|
abitfld.long 0x00 8.--20. "SETTLING_COUNT,Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts" "0x0000=0: no settling time,0x0001=1: wait one reference clock cycle,0x1FFF=8191: wait 8191 reference clock cycles"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "FLL_LF_PGAIN,FLL Loop Filter Gain Setting #2" "0: 1/256,1: 1/128,2: 1/64,3: 1/32,4: 1/16,5: 1/8,6: 1/4,7: 1/2,8: 1.0,9: 2.0,10: 4.0,11: 8.0 >=12,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "FLL_LF_IGAIN,FLL Loop Filter Gain Setting #1" "0: 1/256,1: 1/128,2: 1/64,3: 1/32,4: 1/16,5: 1/8,6: 1/4,7: 1/2,8: 1.0,9: 2.0,10: 4.0,11: 8.0 >=12,?..."
|
|
group.long 0x153C++0x03
|
|
line.long 0x00 "CLK_FLL_CONFIG4,FLL Configuration Register 4"
|
|
bitfld.long 0x00 31. "CCO_ENABLE,Enable the CCO" "0: Block is powered off,1: Block is powered on"
|
|
newline
|
|
bitfld.long 0x00 30. "CCO_HW_UPDATE_DIS,Disable CCO frequency update by FLL hardware" "0: Hardware update of CCO settings is allowed,1: Hardware update of CCO settings is disabled"
|
|
newline
|
|
hexmask.long.word 0x00 16.--24. 1. "CCO_FREQ,CCO frequency code"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "CCO_RANGE,Frequency range of CCO" "0: Target frequency is in range [48 64) MHz,1: Target frequency is in range [64 85) MHz,2: Target frequency is in range [85 113) MHz,3: Target frequency is in range [113 150) MHz,4: Target frequency is in range [150 200] MHz,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CCO_LIMIT,Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)"
|
|
group.long 0x1540++0x03
|
|
line.long 0x00 "CLK_FLL_STATUS,FLL Status Register"
|
|
rbitfld.long 0x00 2. "CCO_READY,This indicates that the CCO is internally settled and ready to use" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "UNLOCK_OCCURRED,This bit sets whenever the FLL is enabled and goes out of lock" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "LOCKED,FLL Lock Indicator" "0,1"
|
|
group.long 0x1544++0x03
|
|
line.long 0x00 "CLK_ECO_CONFIG2,ECO Configuration Register 2"
|
|
bitfld.long 0x00 12.--14. "GTRIM,Gain Trim - Startup time" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "RTRIM,Feedback resistor Trim" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "FTRIM,Filter Trim - 3rd harmonic oscillation" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "ATRIM,Amplitude trim" "0: Vp < 0.35V,1: Vp < 0.40V,2: Vp < 0.45V,3: Vp < 0.50V,4: Vp < 0.55V,5: Vp < 0.60V,6: Vp < 0.65V,7: Vp < 0.70V,8: Vp < 0.75V,9: Vp < 0.80V,10: Vp < 0.85V,11: Vp < 0.90V,12: Vp < 0.95V,13: Vp < 1.00V,14: Vp < 1.05V,15: Vp < 1.10V when AGC_EN=1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "WDTRIM,Watch Dog Trim" "0: Vp > 0.05V,1: Vp > 0.10V,2: Vp > 0.15V,3: Vp > 0.20V,4: Vp > 0.25V,5: Vp > 0.30V,6: Vp > 0.35V,7: Vp > 0.40V"
|
|
repeat 15. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x1600)++0x03
|
|
line.long 0x00 "CLK_PLL_CONFIG[$1],PLL Configuration Register $1"
|
|
bitfld.long 0x00 31. "ENABLE,Master enable for PLL" "0: Block is disabled,1: Block is enabled"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output" "0: Automatic using lock indicator,1: Similar to AUTO except the clock is gated off..,2: Select PLL reference input (bypass mode),3: Select PLL output"
|
|
newline
|
|
bitfld.long 0x00 27. "PLL_LF_MODE,VCO frequency range selection" "0: VCO frequency is [200MHz 400MHz],1: VCO frequency is [170MHz 200MHz)"
|
|
newline
|
|
bitfld.long 0x00 25.--26. "LOCK_DELAY,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "OUTPUT_DIV,Control bits for Output divider" "0: illegal (undefined behavior),1: illegal (undefined behavior),2: divide by 2,?,?,?,?,?,?,?,?,?,?,?,?,?,16: divide by 16,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--12. "REFERENCE_DIV,Control bits for reference divider" "0: illegal (undefined behavior),1: divide by 1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,20: divide by 20 others,?..."
|
|
newline
|
|
abitfld.long 0x00 0.--6. "FEEDBACK_DIV,Control bits for feedback divider" "0x16=22: divide by 22,0x70=112: divide by 112 >112"
|
|
repeat.end
|
|
repeat 15. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x1640)++0x03
|
|
line.long 0x00 "CLK_PLL_STATUS[$1],PLL Status Register $1"
|
|
bitfld.long 0x00 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "LOCKED,PLL Lock Indicator" "0,1"
|
|
repeat.end
|
|
group.long 0x1700++0x03
|
|
line.long 0x00 "CSV_REF_SEL,Select CSV Reference clock for Active domain"
|
|
bitfld.long 0x00 0.--2. "REF_MUX,Selects a source for clock clk_ref_hf" "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator,3: ALTHF - Alternate High-Frequency clock input..,?..."
|
|
group.long 0x1800++0x03
|
|
line.long 0x00 "RES_CAUSE,Reset Cause Observation Register"
|
|
bitfld.long 0x00 30. "RESET_PORVDDD,Indicator that a POR occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RESET_STRUCT_XRES,Structural reset was asserted" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "RESET_PXRES,PXRES triggered" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "RESET_PMIC,PMIC status triggered a reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "RESET_OCD_REGHC,Overcurrent detection from REGHC (if present)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RESET_OCD_DPSLP_LINREG,Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RESET_OCD_ACT_LINREG,Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "RESET_OVDVCCD,Overvoltage detection on the internal core VCCD supply" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESET_OVDVDDA,Overvoltage detection on the external VDDA supply" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "RESET_OVDVDDD,Overvoltage detection on the external VDDD supply" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "RESET_BODVCCD,Internal VCCD core supply crossed the brown-out limit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "RESET_BODVDDA,External VDDA supply crossed the brown-out limit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "RESET_BODVDDD,External VDDD supply crossed brown-out limit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "RESET_XRES,External XRES pin was asserted" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RESET_MCWDT3,Multi-Counter Watchdog timer reset #3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RESET_MCWDT2,Multi-Counter Watchdog timer reset #2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RESET_MCWDT1,Multi-Counter Watchdog timer reset #1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RESET_MCWDT0,Multi-Counter Watchdog timer reset #0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RESET_SOFT,A CPU requested a system reset through it's SYSRESETREQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RESET_TC_DBGRESET,Test controller or debugger asserted reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RESET_DPSLP_FAULT,Fault logging system requested a reset from its DeepSleep logic" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RESET_ACT_FAULT,Fault logging system requested a reset from its Active logic" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESET_WDT,A basic WatchDog Timer (WDT) reset has occurred since last power cycle" "0,1"
|
|
group.long 0x1804++0x03
|
|
line.long 0x00 "RES_CAUSE2,Reset Cause Observation Register 2"
|
|
bitfld.long 0x00 16. "RESET_CSV_REF,Clock supervision logic requested a reset due to loss or frequency violation of the reference clock source that is used to monitor the other HF clock sources" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESET_CSV_HF,Clock supervision logic requested a reset due to loss or frequency violation of a high-frequency clock"
|
|
group.long 0x3014++0x03
|
|
line.long 0x00 "CLK_TRIM_ILO0_CTL,ILO0 Trim Register"
|
|
bitfld.long 0x00 8.--11. "ILO0_MONTRIM,ILO0 internal monitor trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ILO0_FTRIM,ILO0 frequency trims" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x3108++0x03
|
|
line.long 0x00 "PWR_TRIM_PWRSYS_CTL,Power System Trim Register"
|
|
bitfld.long 0x00 30.--31. "ACT_REG_BOOST,Controls the tradeoff between output current and internal operating current for the Active Regulator" "0: 50uA,1: 100uA,2: 150uA,3: 200uA The"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ACT_REG_TRIM,Trim for the Active-Regulator" "?,?,?,?,?,?,?,7: 900mV (nominal),?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,23: 1100mV (nominal),?..."
|
|
group.long 0x3114++0x03
|
|
line.long 0x00 "CLK_TRIM_PILO_CTL,PILO Trim Register"
|
|
bitfld.long 0x00 28.--30. "PILO_VTDIFF_TRIM,Trim for VT-DIFF output (internal power supply)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "PILO_ISLOPE_TRIM,Trim for beta-multiplier current slope" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--24. "PILO_RES_TRIM,Trim for beta-multiplier branch current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "PILO_NBIAS_TRIM,Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "PILO_COMP_TRIM,Trim for comparator bias current" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "PILO_OSC_TRIM,Trim for current in oscillator block" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PILO_CFREQ,Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x3118++0x03
|
|
line.long 0x00 "CLK_TRIM_PILO_CTL2,PILO Trim Register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PILO_IREF_TRIM,Trim for current reference"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "PILO_IREFBM_TRIM,Trim for beta-multiplier current reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PILO_VREF_TRIM,Trim for voltage reference"
|
|
group.long 0x311C++0x03
|
|
line.long 0x00 "CLK_TRIM_PILO_CTL3,PILO Trim Register 3"
|
|
abitfld.long 0x00 0.--15. "PILO_ENGOPT,Engineering options for PILO circuits" "0x0000=0: Short vdda to vpwr,0x0001=1: Beta,0x0002=2: Iref generation Ptat current addition,0x0003=3: Disable current path in secondary Beta,0x0004=4: Double oscillator current,0x0005=5: Switch between deep,0x0006=6: Spare,0x0007=7: Ptat component increase in Iref,0x0008=8: vpwr_rc and vpwr_dig_rc shorting..,0x0009=9: Switch b/w psub connection for cascode..,0x000A=10: Switch between sub"
|
|
group.long 0x3220++0x03
|
|
line.long 0x00 "CLK_TRIM_ILO1_CTL,ILO1 Trim Register"
|
|
bitfld.long 0x00 8.--11. "ILO1_MONTRIM,ILO1 internal monitor trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ILO1_FTRIM,ILO1 frequency trims" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree "CSV_HF"
|
|
repeat 8. (increment 0 1)(increment 0 0x10)
|
|
tree "CSV[$1]"
|
|
group.long ($2+0x1400)++0x03
|
|
line.long 0x00 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x00 31. "CSV_EN,Enables clock supervision both frequency and loss" "0,1"
|
|
bitfld.long 0x00 30. "CSV_ACTION,Specifies the action taken when an anomaly is detected on the monitored clock" "0: Do a Fault report,1: Cause a power reset"
|
|
hexmask.long.word 0x00 0.--15. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable or DeepSleep wakeup from reference clock start to monitored clock start"
|
|
group.long ($2+0x1404)++0x03
|
|
line.long 0x00 "REF_LIMIT,Clock Supervision Reference Limits"
|
|
hexmask.long.word 0x00 16.--31. 1. "UPPER,Cycle time upper limit"
|
|
hexmask.long.word 0x00 0.--15. 1. "LOWER,Cycle time lower limit"
|
|
group.long ($2+0x1408)++0x03
|
|
line.long 0x00 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.word 0x00 0.--15. 1. "PERIOD,Period time"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "CSV_REF"
|
|
tree "CSV"
|
|
group.long 0x1710++0x03
|
|
line.long 0x00 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x00 31. "CSV_EN,Enables clock supervision both frequency and loss" "0,1"
|
|
bitfld.long 0x00 30. "CSV_ACTION,Specifies the action taken when an anomaly is detected on the monitored clock" "0: Do a Fault report,1: Cause a power reset"
|
|
hexmask.long.word 0x00 0.--15. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable or DeepSleep wakeup from reference clock start to monitored clock start"
|
|
group.long 0x1714++0x03
|
|
line.long 0x00 "REF_LIMIT,Clock Supervision Reference Limits"
|
|
hexmask.long.word 0x00 16.--31. 1. "UPPER,Cycle time upper limit"
|
|
hexmask.long.word 0x00 0.--15. 1. "LOWER,Cycle time lower limit"
|
|
group.long 0x1718++0x03
|
|
line.long 0x00 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.word 0x00 0.--15. 1. "PERIOD,Period time"
|
|
tree.end
|
|
tree.end
|
|
tree "CSV_LF"
|
|
tree "CSV"
|
|
group.long 0x1720++0x03
|
|
line.long 0x00 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x00 31. "CSV_EN,Enables clock supervision both frequency and loss" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable from reference clock start to monitored clock start"
|
|
group.long 0x1724++0x03
|
|
line.long 0x00 "REF_LIMIT,Clock Supervision Reference Limits"
|
|
hexmask.long.byte 0x00 16.--23. 1. "UPPER,Cycle time upper limit"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LOWER,Cycle time lower limit"
|
|
group.long 0x1728++0x03
|
|
line.long 0x00 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PERIOD,Period time"
|
|
tree.end
|
|
tree.end
|
|
tree "CSV_ILO"
|
|
tree "CSV"
|
|
group.long 0x1730++0x03
|
|
line.long 0x00 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x00 31. "CSV_EN,Enables clock supervision both frequency and loss" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable from reference clock start to monitored clock start"
|
|
group.long 0x1734++0x03
|
|
line.long 0x00 "REF_LIMIT,Clock Supervision Reference Limits"
|
|
hexmask.long.byte 0x00 16.--23. 1. "UPPER,Cycle time upper limit"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LOWER,Cycle time lower limit"
|
|
group.long 0x1738++0x03
|
|
line.long 0x00 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PERIOD,Period time"
|
|
tree.end
|
|
tree.end
|
|
repeat 2. (increment 0 1)(increment 0 0x10)
|
|
tree "CLK_PLL400M[$1]"
|
|
group.long ($2+0x1900)++0x03
|
|
line.long 0x00 "CONFIG,400MHz PLL Configuration Register"
|
|
bitfld.long 0x00 31. "ENABLE,Master enable for PLL" "0: Block is disabled,1: Block is enabled"
|
|
bitfld.long 0x00 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output" "0: Automatic using lock indicator,1: Similar to AUTO except the clock is gated off..,2: Select PLL reference input (bypass mode),3: Select PLL output"
|
|
newline
|
|
bitfld.long 0x00 25.--26. "LOCK_DELAY,N/A" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "OUTPUT_DIV,Control bits for Output divider" "0: illegal (undefined behavior),1: illegal (undefined behavior),2: divide by 2,?,?,?,?,?,?,?,?,?,?,?,?,?,16: divide by 16,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--12. "REFERENCE_DIV,Control bits for reference divider" "0: illegal (undefined behavior),1: divide by 1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: divide by 16 others,?..."
|
|
abitfld.long 0x00 0.--7. "FEEDBACK_DIV,Control bits for feedback divider" "0x10=16: divide by 16,0xC8=200: divide by 200 >200"
|
|
group.long ($2+0x1904)++0x03
|
|
line.long 0x00 "CONFIG2,400MHz PLL Configuration Register 2"
|
|
bitfld.long 0x00 31. "FRAC_EN,Enables fractional division mode" "0,1"
|
|
bitfld.long 0x00 28.--30. "FRAC_DITHER_EN,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "FRAC_DIV,Control bits for fractional divider"
|
|
group.long ($2+0x1908)++0x03
|
|
line.long 0x00 "CONFIG3,400MHz PLL Configuration Register 3"
|
|
bitfld.long 0x00 31. "SSCG_EN,Enables spreading mode" "0,1"
|
|
bitfld.long 0x00 28. "SSCG_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "SSCG_DITHER_EN,N/A" "0,1"
|
|
bitfld.long 0x00 16.--18. "SSCG_RATE,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "SSCG_DEPTH,N/A"
|
|
group.long ($2+0x190C)++0x03
|
|
line.long 0x00 "STATUS,400MHz PLL Status Register"
|
|
bitfld.long 0x00 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware" "0,1"
|
|
rbitfld.long 0x00 0. "LOCKED,PLL Lock Indicator" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 3. (increment 0 1)(increment 0 0x6840)
|
|
tree "MCWDT[$1]"
|
|
group.long ($2+0x8040)++0x03
|
|
line.long 0x00 "CPU_SELECT,MCWDT CPU selection register"
|
|
bitfld.long 0x00 0.--1. "CPU_SEL,Assigns this MCWDT to a CPU" "0,1,2,3"
|
|
group.long ($2+0x8080)++0x03
|
|
line.long 0x00 "CTR2_CTL,MCWDT Subcounter 2 Control register"
|
|
bitfld.long 0x00 31. "ENABLE,Enable subcounter" "0: Counter is disabled (not clocked),1: Counter is enabled (counting up)"
|
|
rbitfld.long 0x00 0. "ENABLED,Indicates actual state of this subcounter" "0,1"
|
|
group.long ($2+0x8084)++0x03
|
|
line.long 0x00 "CTR2_CONFIG,MCWDT Subcounter 2 Configuration register"
|
|
bitfld.long 0x00 31. "DEBUG_RUN,Pauses/runs this counter while a debugger is connected" "0: When debugger connected counter pauses,1: When debugger connected counter increments"
|
|
bitfld.long 0x00 30. "SLEEPDEEP_PAUSE,Pauses/runs this counter when the corresponding processor is in SLEEPDEEP" "0: Counter runs normally regardless of processor..,1: Counter pauses when corresponding processor is"
|
|
newline
|
|
bitfld.long 0x00 28. "DEBUG_TRIGGER_EN,Enables the trigger input for this MCWDT to pause the counter during debug mode" "0: Pauses the counter whenever a debug probe is,1: Pauses the counter whenever a debug probe is"
|
|
bitfld.long 0x00 16.--20. "BITS,Bit to observe for a toggle" "0: Do ACTION after CNT[0] toggles (i.e. every..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Do ACTION after CNT[31] toggles (i.e. every.."
|
|
newline
|
|
bitfld.long 0x00 0. "ACTION,Action taken when the specified BIT toggles" "0: Do nothing,1: Trigger an interrupt"
|
|
group.long ($2+0x8088)++0x03
|
|
line.long 0x00 "CTR2_CNT,MCWDT Subcounter 2 Count Register"
|
|
hexmask.long 0x00 0.--31. 1. "CNT2,Current value of subcounter 2 for this MCWDT"
|
|
group.long ($2+0x8090)++0x03
|
|
line.long 0x00 "LOCK,MCWDT Lock Register"
|
|
bitfld.long 0x00 0.--1. "MCWDT_LOCK,Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions)" "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
|
|
group.long ($2+0x8094)++0x03
|
|
line.long 0x00 "SERVICE,MCWDT Service Register"
|
|
bitfld.long 0x00 1. "CTR1_SERVICE,Services subcounter 1" "0,1"
|
|
bitfld.long 0x00 0. "CTR0_SERVICE,Services subcounter 0" "0,1"
|
|
group.long ($2+0x80A0)++0x03
|
|
line.long 0x00 "INTR,MCWDT Interrupt Register"
|
|
bitfld.long 0x00 2. "CTR2_INT,MCWDT Interrupt Request for sub-counter 2" "0,1"
|
|
bitfld.long 0x00 1. "CTR1_INT,MCWDT Interrupt Request for sub-counter 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CTR0_INT,MCWDT Interrupt Request for sub-counter 0" "0,1"
|
|
group.long ($2+0x80A4)++0x03
|
|
line.long 0x00 "INTR_SET,MCWDT Interrupt Set Register"
|
|
bitfld.long 0x00 2. "CTR2_INT,Set interrupt for MCWDT_INT2" "0,1"
|
|
bitfld.long 0x00 1. "CTR1_INT,Set interrupt for MCWDT_INT1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CTR0_INT,Set interrupt for MCWDT_INT0" "0,1"
|
|
group.long ($2+0x80A8)++0x03
|
|
line.long 0x00 "INTR_MASK,MCWDT Interrupt Mask Register"
|
|
bitfld.long 0x00 2. "CTR2_INT,Mask for sub-counter 2" "0,1"
|
|
bitfld.long 0x00 1. "CTR1_INT,Mask for sub-counter 1 for warning interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CTR0_INT,Mask for sub-counter 0 for warning interrupt" "0,1"
|
|
rgroup.long ($2+0x80AC)++0x03
|
|
line.long 0x00 "INTR_MASKED,MCWDT Interrupt Masked Register"
|
|
bitfld.long 0x00 2. "CTR2_INT,Logical and of corresponding request and mask bits" "0,1"
|
|
bitfld.long 0x00 1. "CTR1_INT,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CTR0_INT,Logical and of corresponding request and mask bits" "0,1"
|
|
tree "CTR[0]"
|
|
group.long ($2+0x8000)++0x03
|
|
line.long 0x00 "CTL,MCWDT Subcounter Control Register"
|
|
bitfld.long 0x00 31. "ENABLE,Enable subcounter" "0: Counter is disabled (not clocked),1: Counter is enabled (counting up)"
|
|
rbitfld.long 0x00 0. "ENABLED,Indicates actual state of this subcounter" "0,1"
|
|
group.long ($2+0x8004)++0x03
|
|
line.long 0x00 "LOWER_LIMIT,MCWDT Subcounter Lower Limit Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "LOWER_LIMIT,Lower limit for this MCWDT subcounter"
|
|
group.long ($2+0x8008)++0x03
|
|
line.long 0x00 "UPPER_LIMIT,MCWDT Subcounter Upper Limit Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "UPPER_LIMIT,Upper limit for this MCWDT subcounter"
|
|
group.long ($2+0x800C)++0x03
|
|
line.long 0x00 "WARN_LIMIT,MCWDT Subcounter Warn Limit Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "WARN_LIMIT,Warn limit for this MCWDT subcounter"
|
|
group.long ($2+0x8010)++0x03
|
|
line.long 0x00 "CONFIG,MCWDT Subcounter Configuration Register"
|
|
bitfld.long 0x00 31. "DEBUG_RUN,Pauses/runs this counter while a debugger is connected" "0: When debugger connected counter pauses,1: When debugger connected counter increments"
|
|
bitfld.long 0x00 30. "SLEEPDEEP_PAUSE,Pauses/runs this counter when the corresponding processor is in SLEEPDEEP" "0: Counter runs normally regardless of processor..,1: Counter pauses when corresponding processor is"
|
|
newline
|
|
bitfld.long 0x00 28. "DEBUG_TRIGGER_EN,Enables the trigger input for this MCWDT to pause the counter during debug mode" "0: Pauses the counter whenever a debug probe is,1: Pauses the counter whenever a debug probe is"
|
|
bitfld.long 0x00 12. "AUTO_SERVICE,Automatically service when the count value reaches WARN_LIMIT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "WARN_ACTION,Action taken when the count value reaches WARN_LIMIT" "0: Do nothing,1: Trigger an interrupt"
|
|
bitfld.long 0x00 4.--5. "UPPER_ACTION,Action taken if this watchdog is not serviced before UPPER_LIMIT is reached" "0: Do nothing,1: Trigger a fault,2: Trigger a fault,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "LOWER_ACTION,Action taken if this watchdog is serviced before LOWER_LIMIT is reached" "0: Do nothing,1: Trigger a fault,2: Trigger a fault,?..."
|
|
group.long ($2+0x8014)++0x03
|
|
line.long 0x00 "CNT,MCWDT Subcounter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,Current value of subcounter for this MCWDT"
|
|
tree.end
|
|
tree "CTR[1]"
|
|
group.long ($2+0x8020)++0x03
|
|
line.long 0x00 "CTL,MCWDT Subcounter Control Register"
|
|
bitfld.long 0x00 31. "ENABLE,Enable subcounter" "0: Counter is disabled (not clocked),1: Counter is enabled (counting up)"
|
|
rbitfld.long 0x00 0. "ENABLED,Indicates actual state of this subcounter" "0,1"
|
|
group.long ($2+0x8024)++0x03
|
|
line.long 0x00 "LOWER_LIMIT,MCWDT Subcounter Lower Limit Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "LOWER_LIMIT,Lower limit for this MCWDT subcounter"
|
|
group.long ($2+0x8028)++0x03
|
|
line.long 0x00 "UPPER_LIMIT,MCWDT Subcounter Upper Limit Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "UPPER_LIMIT,Upper limit for this MCWDT subcounter"
|
|
group.long ($2+0x802C)++0x03
|
|
line.long 0x00 "WARN_LIMIT,MCWDT Subcounter Warn Limit Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "WARN_LIMIT,Warn limit for this MCWDT subcounter"
|
|
group.long ($2+0x8030)++0x03
|
|
line.long 0x00 "CONFIG,MCWDT Subcounter Configuration Register"
|
|
bitfld.long 0x00 31. "DEBUG_RUN,Pauses/runs this counter while a debugger is connected" "0: When debugger connected counter pauses,1: When debugger connected counter increments"
|
|
bitfld.long 0x00 30. "SLEEPDEEP_PAUSE,Pauses/runs this counter when the corresponding processor is in SLEEPDEEP" "0: Counter runs normally regardless of processor..,1: Counter pauses when corresponding processor is"
|
|
newline
|
|
bitfld.long 0x00 28. "DEBUG_TRIGGER_EN,Enables the trigger input for this MCWDT to pause the counter during debug mode" "0: Pauses the counter whenever a debug probe is,1: Pauses the counter whenever a debug probe is"
|
|
bitfld.long 0x00 12. "AUTO_SERVICE,Automatically service when the count value reaches WARN_LIMIT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "WARN_ACTION,Action taken when the count value reaches WARN_LIMIT" "0: Do nothing,1: Trigger an interrupt"
|
|
bitfld.long 0x00 4.--5. "UPPER_ACTION,Action taken if this watchdog is not serviced before UPPER_LIMIT is reached" "0: Do nothing,1: Trigger a fault,2: Trigger a fault,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "LOWER_ACTION,Action taken if this watchdog is serviced before LOWER_LIMIT is reached" "0: Do nothing,1: Trigger a fault,2: Trigger a fault,?..."
|
|
group.long ($2+0x8034)++0x03
|
|
line.long 0x00 "CNT,MCWDT Subcounter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,Current value of subcounter for this MCWDT"
|
|
tree.end
|
|
tree.end
|
|
repeat.end
|
|
tree "WDT"
|
|
group.long 0xC000++0x03
|
|
line.long 0x00 "CTL,WDT Control Register"
|
|
bitfld.long 0x00 31. "ENABLE,Enable watchdog" "0: Counter is disabled (not clocked),1: Counter is enabled (counting up)"
|
|
rbitfld.long 0x00 0. "ENABLED,Indicates actual state of watchdog" "0,1"
|
|
group.long 0xC004++0x03
|
|
line.long 0x00 "LOWER_LIMIT,WDT Lower Limit Register"
|
|
hexmask.long 0x00 0.--31. 1. "LOWER_LIMIT,Lower limit for watchdog"
|
|
group.long 0xC008++0x03
|
|
line.long 0x00 "UPPER_LIMIT,WDT Upper Limit Register"
|
|
hexmask.long 0x00 0.--31. 1. "UPPER_LIMIT,Upper limit for watchdog"
|
|
group.long 0xC00C++0x03
|
|
line.long 0x00 "WARN_LIMIT,WDT Warn Limit Register"
|
|
hexmask.long 0x00 0.--31. 1. "WARN_LIMIT,Warn limit for watchdog"
|
|
group.long 0xC010++0x03
|
|
line.long 0x00 "CONFIG,WDT Configuration Register"
|
|
bitfld.long 0x00 31. "DEBUG_RUN,Pauses/runs this counter while a debugger is connected" "0: When debugger connected counter pauses,1: When debugger connected counter increments"
|
|
bitfld.long 0x00 30. "HIB_PAUSE,Pauses/runs this counter when the system is in HIBERNATE" "0: Counter behaves normally during HIBERNATE,1: Counter pauses during HIBERNATE"
|
|
newline
|
|
bitfld.long 0x00 29. "DPSLP_PAUSE,Pauses/runs this counter when the system is in DEEPSLEEP" "0: Counter behaves normally during DEEPSLEEP,1: Counter pauses during DEEPSLEEP"
|
|
bitfld.long 0x00 28. "DEBUG_TRIGGER_EN,Enables the trigger input for WDT to pause the counter during debug mode" "0: Pauses the counter whenever a debug probe is,1: Pauses the counter whenever a debug probe is"
|
|
newline
|
|
bitfld.long 0x00 12. "AUTO_SERVICE,Automatically service when the count value reaches WARN_LIMIT" "0,1"
|
|
bitfld.long 0x00 8. "WARN_ACTION,Action taken when the count value reaches WARN_LIMIT" "0: Do nothing,1: Trigger an interrupt"
|
|
newline
|
|
bitfld.long 0x00 4. "UPPER_ACTION,Action taken if this watchdog is not serviced before UPPER_LIMIT is reached" "0: Do nothing,1: Trigger a reset"
|
|
bitfld.long 0x00 0. "LOWER_ACTION,Action taken if this watchdog is serviced before LOWER_LIMIT is reached" "0: Do nothing,1: Trigger a reset"
|
|
group.long 0xC014++0x03
|
|
line.long 0x00 "CNT,WDT Count Register"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,Current value of subcounter for this WDT"
|
|
group.long 0xC040++0x03
|
|
line.long 0x00 "LOCK,WDT Lock register"
|
|
bitfld.long 0x00 0.--1. "WDT_LOCK,Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions)" "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
|
|
group.long 0xC044++0x03
|
|
line.long 0x00 "SERVICE,WDT Service register"
|
|
bitfld.long 0x00 0. "SERVICE,Services the watchdog" "0,1"
|
|
group.long 0xC050++0x03
|
|
line.long 0x00 "INTR,WDT Interrupt Register"
|
|
bitfld.long 0x00 0. "WDT,WDT Interrupt Request" "0,1"
|
|
group.long 0xC054++0x03
|
|
line.long 0x00 "INTR_SET,WDT Interrupt Set Register"
|
|
bitfld.long 0x00 0. "WDT,Set interrupt" "0,1"
|
|
group.long 0xC058++0x03
|
|
line.long 0x00 "INTR_MASK,WDT Interrupt Mask Register"
|
|
bitfld.long 0x00 0. "WDT,Mask for watchdog timer" "0,1"
|
|
rgroup.long 0xC05C++0x03
|
|
line.long 0x00 "INTR_MASKED,WDT Interrupt Masked Register"
|
|
bitfld.long 0x00 0. "WDT,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "TCPWM (Timer/Counter/PWM)"
|
|
repeat 2. (list 0. 1.) (list ad:0x40380000 ad:0x40580000)
|
|
tree "TCPWM$1"
|
|
base $2
|
|
repeat 3. (increment 0 1)(increment 0 0x8000)
|
|
tree "GRP[$1]"
|
|
tree "CNT[0]"
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
|
|
newline
|
|
bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
|
|
newline
|
|
bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x04)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
|
bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x2C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x30)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x44)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x4C)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x54)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x70)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x74)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x78)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x7C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[1]"
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
newline
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
newline
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
newline
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x84)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
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newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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|
group.long ($2+0x88)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
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group.long ($2+0x90)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x94)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x98)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x9C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
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group.long ($2+0xA0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0xA4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0xA8)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
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group.long ($2+0xAC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0xB0)++0x03
|
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line.long 0x00 "DT,Counter PWM dead time register"
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|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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|
newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0xC0)++0x03
|
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0xC4)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0xC8)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0xCC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0xD0)++0x03
|
|
line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0xD4)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0xF0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0xF4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xF8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xFC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[2]"
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
|
|
newline
|
|
bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x104)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x108)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x110)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
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|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x114)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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|
group.long ($2+0x118)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x11C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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|
group.long ($2+0x120)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x124)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0x128)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x12C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x130)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x140)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x144)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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|
newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x148)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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|
newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x14C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x150)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x154)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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|
newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x170)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
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|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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|
group.long ($2+0x174)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x178)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x17C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[3]"
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x184)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x188)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x190)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x194)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x198)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x19C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x1A0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x1A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x1A8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x1AC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x1B0)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x1C0)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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|
group.long ($2+0x1C4)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0x1C8)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x1CC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
group.long ($2+0x1D4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1F0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1F4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x1F8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x1FC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[4]"
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group.long ($2+0x200)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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newline
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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|
newline
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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newline
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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newline
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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newline
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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newline
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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newline
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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newline
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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newline
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x204)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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newline
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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newline
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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|
newline
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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newline
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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newline
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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newline
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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newline
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x208)++0x03
|
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x210)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x214)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x218)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x21C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x220)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x224)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x228)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x22C)++0x03
|
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
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group.long ($2+0x230)++0x03
|
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x240)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x244)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x248)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0x24C)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x250)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x254)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x270)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x274)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x278)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x27C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[5]"
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
newline
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
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|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
|
|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
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|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
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|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
|
bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
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|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
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|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x284)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
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|
|
hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x288)++0x03
|
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line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x290)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x294)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x298)++0x03
|
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line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x29C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x2A0)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x2A4)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0x2A8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x2AC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x2B0)++0x03
|
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x2C0)++0x03
|
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x2C4)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0x2C8)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0x2CC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x2D0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x2D4)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x2F0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x2F4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x2F8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x2FC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[6]"
|
|
group.long ($2+0x300)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
|
|
newline
|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
|
|
newline
|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
|
|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x304)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x308)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x310)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x314)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x318)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x31C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x320)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x324)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0x328)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x32C)++0x03
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|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x330)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x340)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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|
newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x344)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
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|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x348)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x34C)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
group.long ($2+0x350)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x354)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x370)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x374)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x378)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x37C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[7]"
|
|
group.long ($2+0x380)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x384)++0x03
|
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x388)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x390)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x394)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x398)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x39C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x3A0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x3A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x3A8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x3AC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x3B0)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x3C0)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x3C4)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x3C8)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0x3CC)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x3D0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x3D4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x3F0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x3F4)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
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group.long ($2+0x3F8)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x3FC)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[8]"
|
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group.long ($2+0x400)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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|
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|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
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|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x404)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x408)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x410)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x414)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x418)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x41C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x420)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x424)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x428)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x42C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x430)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x440)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x444)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x448)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0x44C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x450)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x454)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x470)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x474)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x478)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x47C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[9]"
|
|
group.long ($2+0x480)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x484)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x488)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x490)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x494)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x498)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x49C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x4A0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x4A4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x4A8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x4AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x4B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x4C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x4C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x4C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x4CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x4D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x4D4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x4F0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x4F4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x4F8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x4FC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[10]"
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group.long ($2+0x500)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x504)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x508)++0x03
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line.long 0x00 "COUNTER,Counter count register"
|
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x510)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x514)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x518)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x51C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x520)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x524)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x528)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
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|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x52C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x530)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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|
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|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
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|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x540)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
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|
|
bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x544)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
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|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
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|
|
hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x548)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x54C)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
group.long ($2+0x550)++0x03
|
|
line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x554)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x570)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
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|
|
bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x574)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x578)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x57C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[11]"
|
|
group.long ($2+0x580)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x584)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x588)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x590)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x594)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x598)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x59C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x5A0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x5A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x5A8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x5AC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x5B0)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x5C0)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x5C4)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x5C8)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x5CC)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x5D0)++0x03
|
|
line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
group.long ($2+0x5D4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x5F0)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
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|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x5F4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x5F8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
rgroup.long ($2+0x5FC)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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|
tree.end
|
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tree "CNT[12]"
|
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group.long ($2+0x600)++0x03
|
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line.long 0x00 "CTRL,Counter control register"
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|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x604)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x608)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x610)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x614)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x618)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x61C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x620)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x624)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x628)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x62C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x630)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x640)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x644)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x648)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x64C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x650)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x654)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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|
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|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x670)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x674)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x678)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x67C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
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|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[13]"
|
|
group.long ($2+0x680)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
|
|
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x684)++0x03
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line.long 0x00 "STATUS,Counter status register"
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|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x688)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x690)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x694)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x698)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x69C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x6A0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x6A4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x6A8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x6AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x6B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x6C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x6C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x6C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x6CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x6D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x6D4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x6F0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x6F4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x6F8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x6FC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[14]"
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group.long ($2+0x700)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x704)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x708)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
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group.long ($2+0x710)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x714)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x718)++0x03
|
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line.long 0x00 "CC1,Counter compare/capture 1 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x71C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
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group.long ($2+0x720)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x724)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x728)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x72C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x730)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x740)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x744)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x748)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x74C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x750)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x754)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x770)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x774)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x778)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x77C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[15]"
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group.long ($2+0x780)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x784)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x788)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x790)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x794)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x798)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x79C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x7A0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x7A4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x7A8)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x7AC)++0x03
|
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x7B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x7C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x7C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0x7C8)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0x7CC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x7D0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x7D4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x7F0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x7F4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x7F8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x7FC)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
|
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tree "CNT[16]"
|
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group.long ($2+0x800)++0x03
|
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x804)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x808)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x810)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x814)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x818)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x81C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x820)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x824)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x828)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x82C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x830)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x840)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x844)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x848)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x84C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x850)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x854)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x870)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
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|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x874)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x878)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x87C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
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|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[17]"
|
|
group.long ($2+0x880)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
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|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
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|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
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|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
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|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
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|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x884)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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|
group.long ($2+0x888)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x890)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x894)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x898)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x89C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
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group.long ($2+0x8A0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x8A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0x8A8)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
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|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x8AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x8B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x8C0)++0x03
|
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x8C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x8C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x8CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x8D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x8D4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
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group.long ($2+0x8F0)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x8F4)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
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|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x8F8)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
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|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
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|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x8FC)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
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|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[18]"
|
|
group.long ($2+0x900)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
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|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
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|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
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|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
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|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
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|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x904)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x908)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x910)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x914)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x918)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x91C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x920)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x924)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x928)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x92C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x930)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x940)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x944)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x948)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x94C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x950)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x954)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x970)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x974)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x978)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x97C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[19]"
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group.long ($2+0x980)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x984)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x988)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x990)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x994)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x998)++0x03
|
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line.long 0x00 "CC1,Counter compare/capture 1 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x99C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
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group.long ($2+0x9A0)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
|
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x9A4)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x9A8)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x9AC)++0x03
|
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
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group.long ($2+0x9B0)++0x03
|
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x9C0)++0x03
|
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x9C4)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0x9C8)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x9CC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
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newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x9D0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x9D4)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x9F0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x9F4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x9F8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x9FC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
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tree "CNT[20]"
|
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group.long ($2+0xA00)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
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|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
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|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
|
bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
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|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0xA04)++0x03
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|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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|
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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|
group.long ($2+0xA08)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0xA10)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0xA14)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0xA18)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0xA1C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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|
group.long ($2+0xA20)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0xA24)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0xA28)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0xA2C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0xA30)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0xA40)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0xA44)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0xA48)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0xA4C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0xA50)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0xA54)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0xA70)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0xA74)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xA78)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xA7C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[21]"
|
|
group.long ($2+0xA80)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
newline
|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0xA84)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
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|
|
hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0xA88)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0xA90)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0xA94)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0xA98)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0xA9C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0xAA0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0xAA4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0xAA8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
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group.long ($2+0xAAC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xAB0)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
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group.long ($2+0xAC0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
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group.long ($2+0xAC4)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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|
newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0xAC8)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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|
group.long ($2+0xACC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
group.long ($2+0xAD0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0xAD4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0xAF0)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0xAF4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xAF8)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xAFC)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[22]"
|
|
group.long ($2+0xB00)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
newline
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0xB04)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0xB08)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0xB10)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0xB14)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0xB18)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0xB1C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0xB20)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0xB24)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0xB28)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0xB2C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xB30)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0xB40)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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|
newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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|
group.long ($2+0xB44)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0xB48)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0xB4C)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
group.long ($2+0xB50)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0xB54)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0xB70)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0xB74)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0xB78)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
rgroup.long ($2+0xB7C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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|
tree.end
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tree "CNT[23]"
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group.long ($2+0xB80)++0x03
|
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line.long 0x00 "CTRL,Counter control register"
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|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
newline
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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newline
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
newline
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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newline
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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newline
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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newline
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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newline
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0xB84)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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newline
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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newline
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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newline
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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newline
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0xB88)++0x03
|
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0xB90)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0xB94)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0xB98)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0xB9C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0xBA0)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0xBA4)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0xBA8)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
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group.long ($2+0xBAC)++0x03
|
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
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group.long ($2+0xBB0)++0x03
|
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0xBC0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0xBC4)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0xBC8)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0xBCC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
group.long ($2+0xBD0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0xBD4)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0xBF0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0xBF4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xBF8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xBFC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
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tree "CNT[24]"
|
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group.long ($2+0xC00)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
newline
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
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|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
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|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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|
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|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
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|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
|
bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0xC04)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0xC08)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0xC10)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0xC14)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0xC18)++0x03
|
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line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0xC1C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0xC20)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0xC24)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0xC28)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0xC2C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0xC30)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0xC40)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0xC44)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0xC48)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0xC4C)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0xC50)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0xC54)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0xC70)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0xC74)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xC78)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xC7C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[25]"
|
|
group.long ($2+0xC80)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
|
|
newline
|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0xC84)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
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|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0xC88)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0xC90)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0xC94)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0xC98)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0xC9C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0xCA0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0xCA4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0xCA8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0xCAC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xCB0)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0xCC0)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0xCC4)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
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|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0xCC8)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
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|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0xCCC)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0xCD0)++0x03
|
|
line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0xCD4)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0xCF0)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0xCF4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xCF8)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xCFC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
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|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[26]"
|
|
group.long ($2+0xD00)++0x03
|
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line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
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|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
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newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
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newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0xD04)++0x03
|
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0xD08)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0xD10)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0xD14)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0xD18)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0xD1C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0xD20)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0xD24)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0xD28)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0xD2C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xD30)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0xD40)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0xD44)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0xD48)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0xD4C)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
group.long ($2+0xD50)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0xD54)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0xD70)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0xD74)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0xD78)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0xD7C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[27]"
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group.long ($2+0xD80)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0xD84)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0xD88)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0xD90)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0xD94)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0xD98)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0xD9C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0xDA0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0xDA4)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0xDA8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0xDAC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0xDB0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0xDC0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0xDC4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0xDC8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0xDCC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0xDD0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0xDD4)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
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|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0xDF0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0xDF4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xDF8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xDFC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[28]"
|
|
group.long ($2+0xE00)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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|
rgroup.long ($2+0xE04)++0x03
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line.long 0x00 "STATUS,Counter status register"
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|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0xE08)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0xE10)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0xE14)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0xE18)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0xE1C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0xE20)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0xE24)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0xE28)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0xE2C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0xE30)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0xE40)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0xE44)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0xE48)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0xE4C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0xE50)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0xE54)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0xE70)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0xE74)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
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|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0xE78)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0xE7C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
|
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tree "CNT[29]"
|
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group.long ($2+0xE80)++0x03
|
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
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|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
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|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0xE84)++0x03
|
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0xE88)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0xE90)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0xE94)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0xE98)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0xE9C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0xEA0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0xEA4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0xEA8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0xEAC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xEB0)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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|
newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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|
newline
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0xEC0)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0xEC4)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0xEC8)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0xECC)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
group.long ($2+0xED0)++0x03
|
|
line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0xED4)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0xEF0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0xEF4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xEF8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xEFC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[30]"
|
|
group.long ($2+0xF00)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
newline
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
newline
|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0xF04)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0xF08)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0xF10)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0xF14)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0xF18)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0xF1C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0xF20)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0xF24)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0xF28)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0xF2C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xF30)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0xF40)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0xF44)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0xF48)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0xF4C)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0xF50)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0xF54)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0xF70)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0xF74)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0xF78)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0xF7C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[31]"
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group.long ($2+0xF80)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0xF84)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0xF88)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0xF90)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0xF94)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0xF98)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0xF9C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0xFA0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0xFA4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0xFA8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0xFAC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0xFB0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0xFC0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0xFC4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0xFC8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0xFCC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0xFD0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0xFD4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0xFF4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0xFF8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0xFFC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[32]"
|
|
group.long ($2+0x1000)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1004)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1008)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1010)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1014)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1018)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x101C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1020)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1024)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1028)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x102C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1030)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1040)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1044)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1048)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x104C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1050)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x1054)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1070)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1074)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x1078)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x107C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[33]"
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group.long ($2+0x1080)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1084)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1088)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1090)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1094)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1098)++0x03
|
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
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group.long ($2+0x109C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x10A0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x10A4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x10A8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x10AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x10B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x10C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x10C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x10C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x10CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x10D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x10D4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x10F0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x10F4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x10F8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x10FC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[34]"
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group.long ($2+0x1100)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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newline
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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newline
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1104)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1108)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1110)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1114)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1118)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x111C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1120)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1124)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1128)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x112C)++0x03
|
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1130)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1140)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1144)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0x1148)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0x114C)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1150)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x1154)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1170)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1174)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x1178)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x117C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
|
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tree "CNT[35]"
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group.long ($2+0x1180)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1184)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1188)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1190)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1194)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1198)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x119C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x11A0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x11A4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x11A8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x11AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x11B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x11C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x11C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x11C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x11CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x11D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x11D4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
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group.long ($2+0x11F0)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
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|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
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group.long ($2+0x11F4)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x11F8)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x11FC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
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|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[36]"
|
|
group.long ($2+0x1200)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
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|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
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|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x1204)++0x03
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1208)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1210)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1214)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1218)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x121C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1220)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1224)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1228)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x122C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1230)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1240)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1244)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1248)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x124C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1250)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x1254)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1270)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1274)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x1278)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x127C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
|
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tree "CNT[37]"
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group.long ($2+0x1280)++0x03
|
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
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|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
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|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x1284)++0x03
|
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x1288)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x1290)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1294)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x1298)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x129C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x12A0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x12A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x12A8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x12AC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x12B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x12C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x12C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x12C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x12CC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x12D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x12D4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x12F0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x12F4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x12F8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x12FC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[38]"
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group.long ($2+0x1300)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1304)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1308)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1310)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1314)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1318)++0x03
|
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line.long 0x00 "CC1,Counter compare/capture 1 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x131C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
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group.long ($2+0x1320)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
|
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
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group.long ($2+0x1324)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1328)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x132C)++0x03
|
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1330)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1340)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1344)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0x1348)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x134C)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1350)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x1354)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x1370)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x1374)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x1378)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x137C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
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tree.end
|
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tree "CNT[39]"
|
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group.long ($2+0x1380)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
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|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
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|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x1384)++0x03
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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|
group.long ($2+0x1388)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1390)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1394)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1398)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x139C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x13A0)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x13A4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x13A8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x13AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x13B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x13C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x13C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x13C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x13CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x13D0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x13D4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x13F0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x13F4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x13F8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x13FC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[40]"
|
|
group.long ($2+0x1400)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
newline
|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
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|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
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|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
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newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
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|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x1404)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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|
group.long ($2+0x1408)++0x03
|
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line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
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group.long ($2+0x1410)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1414)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1418)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
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group.long ($2+0x141C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1420)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1424)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1428)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x142C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1430)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1440)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1444)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0x1448)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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|
newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x144C)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1450)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x1454)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x1470)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x1474)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x1478)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x147C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[41]"
|
|
group.long ($2+0x1480)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x1484)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x1488)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x1490)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1494)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x1498)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x149C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x14A0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x14A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x14A8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x14AC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x14B0)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x14C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x14C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x14C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x14CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x14D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x14D4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x14F0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x14F4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x14F8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x14FC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[42]"
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group.long ($2+0x1500)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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newline
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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newline
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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newline
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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newline
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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newline
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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newline
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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newline
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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newline
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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newline
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1504)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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newline
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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newline
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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newline
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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newline
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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newline
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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newline
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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newline
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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newline
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1508)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1510)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1514)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1518)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x151C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1520)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1524)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1528)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x152C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1530)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1540)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1544)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1548)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x154C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1550)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x1554)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
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group.long ($2+0x1570)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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|
group.long ($2+0x1574)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
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|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x1578)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x157C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
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tree "CNT[43]"
|
|
group.long ($2+0x1580)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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newline
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
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|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x1584)++0x03
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|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
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newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x1588)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1590)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1594)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
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group.long ($2+0x1598)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
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group.long ($2+0x159C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
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group.long ($2+0x15A0)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
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group.long ($2+0x15A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0x15A8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x15AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x15B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x15C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x15C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x15C8)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x15CC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x15D0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x15D4)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x15F0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x15F4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x15F8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x15FC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[44]"
|
|
group.long ($2+0x1600)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
newline
|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
newline
|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x1604)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
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newline
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
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newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
newline
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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newline
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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newline
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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newline
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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|
newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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|
group.long ($2+0x1608)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
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group.long ($2+0x1610)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
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group.long ($2+0x1614)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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|
group.long ($2+0x1618)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
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group.long ($2+0x161C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1620)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
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group.long ($2+0x1624)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1628)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x162C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1630)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1640)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1644)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0x1648)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0x164C)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1650)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x1654)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x1670)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x1674)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x1678)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x167C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[45]"
|
|
group.long ($2+0x1680)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
newline
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
newline
|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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newline
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x1684)++0x03
|
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x1688)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x1690)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1694)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x1698)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x169C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x16A0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x16A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x16A8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x16AC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x16B0)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x16C0)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x16C4)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x16C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x16CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x16D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x16D4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x16F0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x16F4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x16F8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x16FC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[46]"
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group.long ($2+0x1700)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1704)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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newline
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1708)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1710)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1714)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1718)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x171C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1720)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1724)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1728)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x172C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1730)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1740)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1744)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1748)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x174C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1750)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x1754)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1770)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1774)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
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group.long ($2+0x1778)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x177C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
|
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tree "CNT[47]"
|
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group.long ($2+0x1780)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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|
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|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
newline
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
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rgroup.long ($2+0x1784)++0x03
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1788)++0x03
|
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1790)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1794)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1798)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x179C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x17A0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x17A4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x17A8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x17AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x17B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x17C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x17C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x17C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x17CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x17D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x17D4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
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group.long ($2+0x17F0)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x17F4)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
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group.long ($2+0x17F8)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
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rgroup.long ($2+0x17FC)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
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tree.end
|
|
tree "CNT[48]"
|
|
group.long ($2+0x1800)++0x03
|
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line.long 0x00 "CTRL,Counter control register"
|
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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newline
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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newline
|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
newline
|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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newline
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
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newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
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newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x1804)++0x03
|
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
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newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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newline
|
|
bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x1808)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x1810)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1814)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x1818)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x181C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x1820)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x1824)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x1828)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x182C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x1830)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
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|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
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|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x1840)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
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|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x1844)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x1848)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x184C)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
group.long ($2+0x1850)++0x03
|
|
line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x1854)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x1870)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x1874)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x1878)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x187C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[49]"
|
|
group.long ($2+0x1880)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
|
|
newline
|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
|
|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x1884)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x1888)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x1890)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1894)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x1898)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x189C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x18A0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x18A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x18A8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x18AC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x18B0)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x18C0)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x18C4)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x18C8)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x18CC)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x18D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x18D4)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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|
group.long ($2+0x18F0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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|
group.long ($2+0x18F4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
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group.long ($2+0x18F8)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x18FC)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[50]"
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group.long ($2+0x1900)++0x03
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line.long 0x00 "CTRL,Counter control register"
|
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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|
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|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1904)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1908)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1910)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1914)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1918)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x191C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1920)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1924)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1928)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x192C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1930)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1940)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1944)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1948)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x194C)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1950)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x1954)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x1970)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x1974)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x1978)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x197C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[51]"
|
|
group.long ($2+0x1980)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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newline
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1984)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1988)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1990)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1994)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1998)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x199C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x19A0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x19A4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x19A8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x19AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x19B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x19C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x19C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x19C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x19CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x19D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x19D4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x19F0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x19F4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x19F8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x19FC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
|
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tree "CNT[52]"
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group.long ($2+0x1A00)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
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rgroup.long ($2+0x1A04)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1A08)++0x03
|
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line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x1A10)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1A14)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x1A18)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1A1C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x1A20)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x1A24)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x1A28)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x1A2C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x1A30)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x1A40)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
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|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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|
newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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|
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|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x1A44)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
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|
|
hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
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|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x1A48)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x1A4C)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1A50)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x1A54)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x1A70)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
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|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x1A74)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x1A78)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x1A7C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[53]"
|
|
group.long ($2+0x1A80)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
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|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
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newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x1A84)++0x03
|
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x1A88)++0x03
|
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line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x1A90)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1A94)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x1A98)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1A9C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x1AA0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x1AA4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x1AA8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x1AAC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x1AB0)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x1AC0)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x1AC4)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x1AC8)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x1ACC)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
group.long ($2+0x1AD0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x1AD4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1AF0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1AF4)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x1AF8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x1AFC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
|
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tree "CNT[54]"
|
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group.long ($2+0x1B00)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1B04)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1B08)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1B10)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1B14)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1B18)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1B1C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1B20)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1B24)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1B28)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x1B2C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1B30)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1B40)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1B44)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1B48)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x1B4C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1B50)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x1B54)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x1B70)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x1B74)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x1B78)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x1B7C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[55]"
|
|
group.long ($2+0x1B80)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1B84)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1B88)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1B90)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1B94)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1B98)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1B9C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1BA0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1BA4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1BA8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x1BAC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1BB0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1BC0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1BC4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1BC8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x1BCC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1BD0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x1BD4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1BF0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1BF4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x1BF8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x1BFC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[56]"
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group.long ($2+0x1C00)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1C04)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1C08)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1C10)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1C14)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1C18)++0x03
|
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line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1C1C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1C20)++0x03
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line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x1C24)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1C28)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x1C2C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1C30)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1C40)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1C44)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1C48)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x1C4C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1C50)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x1C54)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1C70)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1C74)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x1C78)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x1C7C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[57]"
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group.long ($2+0x1C80)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1C84)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1C88)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1C90)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1C94)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1C98)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1C9C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1CA0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1CA4)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1CA8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x1CAC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1CB0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1CC0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1CC4)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1CC8)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0x1CCC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1CD0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
group.long ($2+0x1CD4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1CF0)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1CF4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
group.long ($2+0x1CF8)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x1CFC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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|
tree.end
|
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tree "CNT[58]"
|
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group.long ($2+0x1D00)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1D04)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1D08)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1D10)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1D14)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1D18)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1D1C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1D20)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1D24)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1D28)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x1D2C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1D30)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1D40)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1D44)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1D48)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x1D4C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1D50)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x1D54)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
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group.long ($2+0x1D70)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
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|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x1D74)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x1D78)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x1D7C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[59]"
|
|
group.long ($2+0x1D80)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
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|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
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|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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|
rgroup.long ($2+0x1D84)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1D88)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1D90)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1D94)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1D98)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1D9C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1DA0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1DA4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1DA8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x1DAC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1DB0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1DC0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1DC4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1DC8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x1DCC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1DD0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x1DD4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1DF0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1DF4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x1DF8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x1DFC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
|
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tree "CNT[60]"
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group.long ($2+0x1E00)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
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|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x1E04)++0x03
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line.long 0x00 "STATUS,Counter status register"
|
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
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|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x1E08)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x1E10)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1E14)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x1E18)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x1E1C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x1E20)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x1E24)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x1E28)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x1E2C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1E30)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1E40)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1E44)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1E48)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x1E4C)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1E50)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x1E54)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1E70)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1E74)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x1E78)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x1E7C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[61]"
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group.long ($2+0x1E80)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1E84)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1E88)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1E90)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1E94)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1E98)++0x03
|
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1E9C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1EA0)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
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group.long ($2+0x1EA4)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1EA8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x1EAC)++0x03
|
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1EB0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1EC0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1EC4)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0x1EC8)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x1ECC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1ED0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x1ED4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1EF0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1EF4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x1EF8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x1EFC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[62]"
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group.long ($2+0x1F00)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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|
newline
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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newline
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1F04)++0x03
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line.long 0x00 "STATUS,Counter status register"
|
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1F08)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1F10)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1F14)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1F18)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1F1C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1F20)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1F24)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1F28)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x1F2C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1F30)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1F40)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1F44)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1F48)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x1F4C)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1F50)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x1F54)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x1F70)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x1F74)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x1F78)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x1F7C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[63]"
|
|
group.long ($2+0x1F80)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
newline
|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x1F84)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x1F88)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x1F90)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1F94)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x1F98)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x1F9C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x1FA0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x1FA4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x1FA8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x1FAC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x1FB0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x1FC0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x1FC4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x1FC8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x1FCC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x1FD0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x1FD4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x1FF0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x1FF4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x1FF8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x1FFC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[64]"
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group.long ($2+0x2000)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x2004)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
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group.long ($2+0x2008)++0x03
|
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line.long 0x00 "COUNTER,Counter count register"
|
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x2010)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x2014)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x2018)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x201C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x2020)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x2024)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x2028)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
group.long ($2+0x202C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x2030)++0x03
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|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x2040)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x2044)++0x03
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|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x2048)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x204C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x2050)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x2054)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x2070)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x2074)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x2078)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x207C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[65]"
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group.long ($2+0x2080)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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newline
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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newline
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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newline
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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newline
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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newline
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x2084)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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newline
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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newline
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x2088)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x2090)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
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group.long ($2+0x2094)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x2098)++0x03
|
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line.long 0x00 "CC1,Counter compare/capture 1 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
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group.long ($2+0x209C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
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group.long ($2+0x20A0)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
|
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
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group.long ($2+0x20A4)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x20A8)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
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group.long ($2+0x20AC)++0x03
|
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x20B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x20C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x20C4)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
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newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0x20C8)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x20CC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
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newline
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x20D0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x20D4)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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|
group.long ($2+0x20F0)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
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|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x20F4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x20F8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x20FC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
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|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
|
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tree "CNT[66]"
|
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group.long ($2+0x2100)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
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|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
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|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
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|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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|
rgroup.long ($2+0x2104)++0x03
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
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group.long ($2+0x2108)++0x03
|
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line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x2110)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x2114)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x2118)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x211C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x2120)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x2124)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x2128)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x212C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x2130)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x2140)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x2144)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x2148)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x214C)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x2150)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x2154)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x2170)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x2174)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x2178)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x217C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[67]"
|
|
group.long ($2+0x2180)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
newline
|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
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|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
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newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
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|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x2184)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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|
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x2188)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x2190)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x2194)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x2198)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x219C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
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group.long ($2+0x21A0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x21A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0x21A8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x21AC)++0x03
|
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x21B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
|
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
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group.long ($2+0x21C0)++0x03
|
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
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group.long ($2+0x21C4)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0x21C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0x21CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x21D0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x21D4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x21F0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
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|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
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|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x21F4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x21F8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x21FC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[68]"
|
|
group.long ($2+0x2200)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
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|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x2204)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x2208)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x2210)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x2214)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x2218)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x221C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x2220)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x2224)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x2228)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x222C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x2230)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x2240)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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|
newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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|
newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x2244)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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|
newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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|
newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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|
group.long ($2+0x2248)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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|
newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x224C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x2250)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x2254)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x2270)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x2274)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x2278)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x227C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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newline
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[69]"
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group.long ($2+0x2280)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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newline
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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newline
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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newline
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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newline
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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newline
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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newline
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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newline
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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newline
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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newline
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x2284)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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newline
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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newline
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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newline
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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newline
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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newline
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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newline
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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newline
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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newline
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x2288)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x2290)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x2294)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x2298)++0x03
|
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x229C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x22A0)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x22A4)++0x03
|
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x22A8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x22AC)++0x03
|
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x22B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x22C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x22C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x22C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0x22CC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x22D0)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x22D4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x22F0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x22F4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x22F8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x22FC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[70]"
|
|
group.long ($2+0x2300)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
newline
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
newline
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x2304)++0x03
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
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newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x2308)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
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group.long ($2+0x2310)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x2314)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
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group.long ($2+0x2318)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x231C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x2320)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x2324)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0x2328)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
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group.long ($2+0x232C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x2330)++0x03
|
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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|
newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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|
newline
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x2340)++0x03
|
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x2344)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
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group.long ($2+0x2348)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0x234C)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
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newline
|
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
newline
|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x2350)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x2354)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x2370)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x2374)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x2378)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x237C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[71]"
|
|
group.long ($2+0x2380)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
|
|
newline
|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
|
|
newline
|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
|
|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x2384)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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|
newline
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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newline
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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|
newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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|
group.long ($2+0x2388)++0x03
|
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line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x2390)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x2394)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x2398)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x239C)++0x03
|
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x23A0)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
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group.long ($2+0x23A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0x23A8)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x23AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x23B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x23C0)++0x03
|
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x23C4)++0x03
|
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x23C8)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
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group.long ($2+0x23CC)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x23D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x23D4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x23F0)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x23F4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x23F8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x23FC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[72]"
|
|
group.long ($2+0x2400)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
newline
|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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newline
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x2404)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x2408)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x2410)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x2414)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x2418)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x241C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x2420)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x2424)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x2428)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x242C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x2430)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x2440)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x2444)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x2448)++0x03
|
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x244C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x2450)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x2454)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x2470)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x2474)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x2478)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x247C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[73]"
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group.long ($2+0x2480)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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newline
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x2484)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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newline
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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newline
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x2488)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x2490)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x2494)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x2498)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x249C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x24A0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x24A4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x24A8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x24AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x24B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x24C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x24C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x24C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x24CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x24D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x24D4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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|
newline
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x24F0)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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|
group.long ($2+0x24F4)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x24F8)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x24FC)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[74]"
|
|
group.long ($2+0x2500)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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newline
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x2504)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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|
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x2508)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
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group.long ($2+0x2510)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x2514)++0x03
|
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
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group.long ($2+0x2518)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
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group.long ($2+0x251C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x2520)++0x03
|
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
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group.long ($2+0x2524)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0x2528)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x252C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x2530)++0x03
|
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line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x2540)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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newline
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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newline
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x2544)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x2548)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x254C)++0x03
|
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x2550)++0x03
|
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
|
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
|
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x2554)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x2570)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x2574)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x2578)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x257C)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[75]"
|
|
group.long ($2+0x2580)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
newline
|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
newline
|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x2584)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x2588)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x2590)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x2594)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x2598)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x259C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x25A0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x25A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0x25A8)++0x03
|
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line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x25AC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x25B0)++0x03
|
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line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x25C0)++0x03
|
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line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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|
newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x25C4)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x25C8)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x25CC)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
group.long ($2+0x25D0)++0x03
|
|
line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
newline
|
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
|
group.long ($2+0x25D4)++0x03
|
|
line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x25F0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x25F4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x25F8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x25FC)++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[76]"
|
|
group.long ($2+0x2600)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
|
|
newline
|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
|
|
newline
|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
|
|
newline
|
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x2604)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
|
bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x2608)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x2610)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x2614)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x2618)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x261C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x2620)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x2624)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x2628)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x262C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x2630)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x2640)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x2644)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x2648)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x264C)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x2650)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x2654)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x2670)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x2674)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x2678)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x267C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[77]"
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group.long ($2+0x2680)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x2684)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x2688)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x2690)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x2694)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x2698)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x269C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x26A0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x26A4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x26A8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x26AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x26B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x26C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x26C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x26C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x26CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x26D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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|
newline
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x26D4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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newline
|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x26F0)++0x03
|
|
line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x26F4)++0x03
|
|
line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x26F8)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x26FC)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[78]"
|
|
group.long ($2+0x2700)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
|
|
newline
|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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newline
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x2704)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x2708)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x2710)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x2714)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x2718)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x271C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x2720)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x2724)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x2728)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x272C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x2730)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x2740)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x2744)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x2748)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x274C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x2750)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x2754)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x2770)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x2774)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x2778)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x277C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[79]"
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group.long ($2+0x2780)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
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rgroup.long ($2+0x2784)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x2788)++0x03
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line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x2790)++0x03
|
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line.long 0x00 "CC0,Counter compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
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group.long ($2+0x2794)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x2798)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x279C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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|
group.long ($2+0x27A0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x27A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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|
group.long ($2+0x27A8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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|
newline
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x27AC)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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|
group.long ($2+0x27B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x27C0)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
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|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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|
newline
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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|
newline
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x27C4)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
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|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x27C8)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x27CC)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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|
group.long ($2+0x27D0)++0x03
|
|
line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x27D4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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|
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
|
group.long ($2+0x27F0)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
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|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
|
group.long ($2+0x27F4)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x27F8)++0x03
|
|
line.long 0x00 "INTR_MASK,Interrupt mask register"
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|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
rgroup.long ($2+0x27FC)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
newline
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[80]"
|
|
group.long ($2+0x2800)++0x03
|
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line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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|
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|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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|
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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newline
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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newline
|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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newline
|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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newline
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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newline
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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|
newline
|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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|
newline
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x2804)++0x03
|
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line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
newline
|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
newline
|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
newline
|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x2808)++0x03
|
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line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x2810)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x2814)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x2818)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x281C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x2820)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x2824)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x2828)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
|
|
group.long ($2+0x282C)++0x03
|
|
line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x2830)++0x03
|
|
line.long 0x00 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
|
|
group.long ($2+0x2840)++0x03
|
|
line.long 0x00 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
|
|
group.long ($2+0x2844)++0x03
|
|
line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
|
|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
|
|
group.long ($2+0x2848)++0x03
|
|
line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
|
|
group.long ($2+0x284C)++0x03
|
|
line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
|
newline
|
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
|
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newline
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x2850)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x2854)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x2870)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x2874)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x2878)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x287C)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree "CNT[81]"
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group.long ($2+0x2880)++0x03
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line.long 0x00 "CTRL,Counter control register"
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
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rgroup.long ($2+0x2884)++0x03
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line.long 0x00 "STATUS,Counter status register"
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hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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group.long ($2+0x2888)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x2890)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x2894)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x2898)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x289C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x28A0)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x28A4)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x28A8)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x28AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x28B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x28C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x28C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x28C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x28CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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newline
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x28D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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newline
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
|
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group.long ($2+0x28D4)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
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group.long ($2+0x28F0)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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|
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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|
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|
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
|
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group.long ($2+0x28F4)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
|
group.long ($2+0x28F8)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
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|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x28FC)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
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|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[82]"
|
|
group.long ($2+0x2900)++0x03
|
|
line.long 0x00 "CTRL,Counter control register"
|
|
bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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|
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|
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
|
|
newline
|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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|
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
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|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
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|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
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|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x2904)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
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|
group.long ($2+0x2908)++0x03
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line.long 0x00 "COUNTER,Counter count register"
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hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
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group.long ($2+0x2910)++0x03
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line.long 0x00 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x2914)++0x03
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line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
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group.long ($2+0x2918)++0x03
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line.long 0x00 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
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group.long ($2+0x291C)++0x03
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line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
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group.long ($2+0x2920)++0x03
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line.long 0x00 "PERIOD,Counter period register"
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hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
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group.long ($2+0x2924)++0x03
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line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
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abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
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group.long ($2+0x2928)++0x03
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line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x292C)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x2930)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x2940)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x2944)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x2948)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x294C)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x2950)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x2954)++0x03
|
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
|
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
|
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group.long ($2+0x2970)++0x03
|
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x2974)++0x03
|
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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|
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|
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
|
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group.long ($2+0x2978)++0x03
|
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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|
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|
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
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|
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
|
|
rgroup.long ($2+0x297C)++0x03
|
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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|
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|
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
|
|
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|
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
|
|
tree.end
|
|
tree "CNT[83]"
|
|
group.long ($2+0x2980)++0x03
|
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line.long 0x00 "CTRL,Counter control register"
|
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bitfld.long 0x00 31. "ENABLED,Counter enable" "0,1"
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bitfld.long 0x00 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode" "0,1"
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|
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|
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bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,1: RSVD1,2: Capture mode,3: Quadrature mode Different encoding modes can..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode"
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bitfld.long 0x00 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode" "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode"
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
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|
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|
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bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
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bitfld.long 0x00 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped" "0: The behavior is the same is in previous..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x00 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
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|
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|
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bitfld.long 0x00 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
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|
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bitfld.long 0x00 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')" "0,1"
|
|
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|
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bitfld.long 0x00 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode" "0,1"
|
|
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|
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bitfld.long 0x00 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values" "0,1"
|
|
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|
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bitfld.long 0x00 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
|
|
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|
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bitfld.long 0x00 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values" "0,1"
|
|
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|
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bitfld.long 0x00 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values" "0,1"
|
|
rgroup.long ($2+0x2984)++0x03
|
|
line.long 0x00 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter"
|
|
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|
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hexmask.long.byte 0x00 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field"
|
|
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|
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bitfld.long 0x00 15. "RUNNING,When '0' the counter is NOT running" "0,1"
|
|
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|
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bitfld.long 0x00 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 10. "LINE_OUT,Indicates the actual level of the PWM line output signal" "0,1"
|
|
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|
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bitfld.long 0x00 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger" "0,1"
|
|
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|
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bitfld.long 0x00 8. "TR_START,Indicates the actual level of the selected start trigger" "0,1"
|
|
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|
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bitfld.long 0x00 7. "TR_STOP,Indicates the actual level of the selected stop trigger" "0,1"
|
|
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|
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bitfld.long 0x00 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger" "0,1"
|
|
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|
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bitfld.long 0x00 5. "TR_COUNT,Indicates the actual level of the selected count trigger" "0,1"
|
|
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|
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bitfld.long 0x00 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger" "0,1"
|
|
newline
|
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bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
|
|
group.long ($2+0x2988)++0x03
|
|
line.long 0x00 "COUNTER,Counter count register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNTER,16-bit / 32-bit counter value"
|
|
group.long ($2+0x2990)++0x03
|
|
line.long 0x00 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x2994)++0x03
|
|
line.long 0x00 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC register"
|
|
group.long ($2+0x2998)++0x03
|
|
line.long 0x00 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,In CAPTURE mode captures the counter value"
|
|
group.long ($2+0x299C)++0x03
|
|
line.long 0x00 "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "CC,Additional buffer for counter CC1 register"
|
|
group.long ($2+0x29A0)++0x03
|
|
line.long 0x00 "PERIOD,Counter period register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Period value: upper value of the counter"
|
|
group.long ($2+0x29A4)++0x03
|
|
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
|
|
abitfld.long 0x00 0.--31. "PERIOD,Additional buffer for counter PERIOD register" "0x00000001=1: taps 8 10 11 12 (realized in 8..,0x00000010=16: - Maximum length 16bit LFSR -..,0x0000002D=45: period is 2^16-1 = 65535 cycles -.."
|
|
group.long ($2+0x29A8)++0x03
|
|
line.long 0x00 "LINE_SEL,Counter line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by..,5: RSVD5,6: RSVD6,7: RSVD7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'" "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: RSVD5,6: RSVD6,7: RSVD7"
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group.long ($2+0x29AC)++0x03
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line.long 0x00 "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x00 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL" "0,1,2,3,4,5,6,7"
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group.long ($2+0x29B0)++0x03
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line.long 0x00 "DT,Counter PWM dead time register"
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hexmask.long.word 0x00 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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hexmask.long.byte 0x00 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain"
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group.long ($2+0x29C0)++0x03
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line.long 0x00 "TR_CMD,Counter trigger command register"
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bitfld.long 0x00 5. "CAPTURE1,SW capture 1 trigger" "0,1"
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bitfld.long 0x00 4. "START,SW start trigger" "0,1"
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bitfld.long 0x00 3. "STOP,SW stop trigger" "0,1"
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bitfld.long 0x00 2. "RELOAD,SW reload trigger" "0,1"
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bitfld.long 0x00 0. "CAPTURE0,SW capture 0 trigger" "0,1"
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group.long ($2+0x29C4)++0x03
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line.long 0x00 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x00 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger"
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hexmask.long.byte 0x00 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger"
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hexmask.long.byte 0x00 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger"
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hexmask.long.byte 0x00 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger"
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group.long ($2+0x29C8)++0x03
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line.long 0x00 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x00 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger"
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hexmask.long.byte 0x00 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger"
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group.long ($2+0x29CC)++0x03
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line.long 0x00 "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0x00 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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bitfld.long 0x00 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
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group.long ($2+0x29D0)++0x03
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line.long 0x00 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x00 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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bitfld.long 0x00 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
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group.long ($2+0x29D4)++0x03
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line.long 0x00 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x00 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1" "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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bitfld.long 0x00 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0" "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: RSVD6,7: Output trigger disabled"
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group.long ($2+0x29F0)++0x03
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line.long 0x00 "INTR,Interrupt request register"
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bitfld.long 0x00 2. "CC1_MATCH,Counter matches CC1 register event" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Counter matches CC0 register event" "0,1"
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bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
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group.long ($2+0x29F4)++0x03
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line.long 0x00 "INTR_SET,Interrupt set request register"
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bitfld.long 0x00 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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group.long ($2+0x29F8)++0x03
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line.long 0x00 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x00 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
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rgroup.long ($2+0x29FC)++0x03
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line.long 0x00 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x00 2. "CC1_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 1. "CC0_MATCH,Logical and of corresponding request and mask bits" "0,1"
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bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
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tree.end
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tree.end
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repeat.end
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tree.end
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repeat.end
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tree.end
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autoindent.off
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