33480 lines
1.5 MiB
33480 lines
1.5 MiB
; --------------------------------------------------------------------------------
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; @Title: TXZ4 On-Chip Peripherals
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; @Props: Released
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; @Author: KWI, PIW
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; @Changelog: 2020-03-06 KWI
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; 2022-01-29 PIW
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; @Manufacturer: TOSHIBA - Toshiba
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; @Doc: SVD generated
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; @Core: Cortex-M4F
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; @Chip: TMPM4G*, TMPM4K*, TMPM4L*
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pertxz4.per 17736 2024-04-08 09:26:07Z kwisniewski $
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
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line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
tree "DMACA (DMA Controller)"
|
|
base ad:0x40000000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "INTSTATUS,DMAC Interrupt Status Register"
|
|
bitfld.long 0x00 1. "INTSTATUS1,INTSTATUS1" "0,1"
|
|
bitfld.long 0x00 0. "INTSTATUS0,INTSTATUS0" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "INTTCSTATUS,DMAC Interrupt Terminal Count Status Register"
|
|
bitfld.long 0x00 1. "INTTCSTATUS1,INTTCSTATUS1" "0,1"
|
|
bitfld.long 0x00 0. "INTTCSTATUS0,INTTCSTATUS0" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "INTTCCLEAR,DMAC Interrupt Terminal Count Clear Register"
|
|
bitfld.long 0x00 1. "INTTCCLEAR1,INTTCCLEAR1" "0,1"
|
|
bitfld.long 0x00 0. "INTTCCLEAR0,INTTCCLEAR0" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "INTERRORSTATUS,DMAC Interrupt Error Status Register"
|
|
bitfld.long 0x00 1. "INTERRSTATUS1,INTERRSTATUS1" "0,1"
|
|
bitfld.long 0x00 0. "INTERRSTATUS0,INTERRSTATUS0" "0,1"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "INTERRCLR,DMAC Interrupt Error Clear Register"
|
|
bitfld.long 0x00 1. "INTERRCLR1,INTERRCLR1" "0,1"
|
|
bitfld.long 0x00 0. "INTERRCLR0,INTERRCLR0" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RAWINTTCSTATUS,DMAC Raw Interrupt Terminal Count Status Register"
|
|
bitfld.long 0x00 1. "RAMINTTCS1,RAMINTTCS1" "0,1"
|
|
bitfld.long 0x00 0. "RAMINTTCS0,RAMINTTCS0" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RAWINTERRORSTATUS,DMAC Raw Error Interrupt Status Register"
|
|
bitfld.long 0x00 1. "RAWINTERRS1,RAWINTERRS1" "0,1"
|
|
bitfld.long 0x00 0. "RAWINTERRS0,RAWINTERRS0" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ENBLDCHNS,DMAC Enabled Channel Register"
|
|
bitfld.long 0x00 1. "ENABLEDCH1,ENABLEDCH1" "0,1"
|
|
bitfld.long 0x00 0. "ENABLEDCH0,ENABLEDCH0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SOFTBREQ,DMAC Software Burst Request Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "SOFTBREQ,SOFTBREQ"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SOFTSREQ,DMAC Software Single Request Register"
|
|
bitfld.long 0x00 15. "SOFTSREQ15,SOFTSREQ15" "0,1"
|
|
bitfld.long 0x00 14. "SOFTSREQ14,SOFTSREQ14" "0,1"
|
|
bitfld.long 0x00 13. "SOFTSREQ13,SOFTSREQ13" "0,1"
|
|
bitfld.long 0x00 12. "SOFTSREQ12,SOFTSREQ12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "SOFTSREQ11,SOFTSREQ11" "0,1"
|
|
bitfld.long 0x00 10. "SOFTSREQ10,SOFTSREQ10" "0,1"
|
|
bitfld.long 0x00 9. "SOFTSREQ9,SOFTSREQ9" "0,1"
|
|
bitfld.long 0x00 8. "SOFTSREQ8,SOFTSREQ8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SOFTSREQ7,SOFTSREQ7" "0,1"
|
|
bitfld.long 0x00 6. "SOFTSREQ6,SOFTSREQ6" "0,1"
|
|
bitfld.long 0x00 5. "SOFTSREQ5,SOFTSREQ5" "0,1"
|
|
bitfld.long 0x00 4. "SOFTSREQ4,SOFTSREQ4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SOFTSREQ3,SOFTSREQ3" "0,1"
|
|
bitfld.long 0x00 2. "SOFTSREQ2,SOFTSREQ2" "0,1"
|
|
bitfld.long 0x00 1. "SOFTSREQ1,SOFTSREQ1" "0,1"
|
|
bitfld.long 0x00 0. "SOFTSREQ0,SOFTSREQ0" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CONFIGURATION,DMAC Configuration Register"
|
|
bitfld.long 0x00 0. "E,E" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "C0SRCADDR,DMAC Channel 0 Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCADDR,SRCADDR"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "C0DESTADDR,DMAC Channel 0 Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DESTADDR,DESTADDR"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "C0LLI,DMAC Channel 0 Linked List Item Register"
|
|
hexmask.long 0x00 2.--31. 1. "LLI,LLI"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "C0CONTROL,DMAC Channel 0 Control Register"
|
|
bitfld.long 0x00 31. "I,I" "0,1"
|
|
bitfld.long 0x00 27. "DI,DI" "0,1"
|
|
bitfld.long 0x00 26. "SI,SI" "0,1"
|
|
bitfld.long 0x00 21.--23. "DWIDTH,DWIDTH" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "SWIDTH,SWIDTH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "DBSIZE,DBSIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SBSIZE,SBSIZE" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--11. 1. "TRANSFERSIZE,TRANSFERSIZE"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "C0CONFIGURATION,DMAC Channel 0 Configuration Register"
|
|
bitfld.long 0x00 18. "HALT,HALT" "0,1"
|
|
rbitfld.long 0x00 17. "ACTIVE,ACTIVE" "0,1"
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x00 15. "ITC,ITC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "IE,IE" "0,1"
|
|
bitfld.long 0x00 11.--13. "FLOWCNTRL,FLOWCNTRL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--9. "DESTPERIPHERAL,DESTPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. "SRCPERIPHERAL,SRCPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "E,E" "0,1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "C1SRCADDR,DMAC Channel 1 Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCADDR,SRCADDR"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "C1DESTADDR,DMAC Channel 1 Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DESTADDR,DESTADDR"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "C1LLI,DMAC Channel 1 Linked List Item Register"
|
|
hexmask.long 0x00 2.--31. 1. "LLI,LLI"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "C1CONTROL,DMAC Channel 1 Control Register"
|
|
bitfld.long 0x00 31. "I,I" "0,1"
|
|
bitfld.long 0x00 27. "DI,DI" "0,1"
|
|
bitfld.long 0x00 26. "SI,SI" "0,1"
|
|
bitfld.long 0x00 21.--23. "DWIDTH,DWIDTH" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "SWIDTH,SWIDTH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "DBSIZE,DBSIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SBSIZE,SBSIZE" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--11. 1. "TRANSFERSIZE,TRANSFERSIZE"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "C1CONFIGURATION,DMAC Channel 1 Configuration Register"
|
|
bitfld.long 0x00 18. "HALT,HALT" "0,1"
|
|
rbitfld.long 0x00 17. "ACTIVE,ACTIVE" "0,1"
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x00 15. "ITC,ITC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "IE,IE" "0,1"
|
|
bitfld.long 0x00 11.--13. "FLOWCNTRL,FLOWCNTRL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--9. "DESTPERIPHERAL,DESTPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. "SRCPERIPHERAL,SRCPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "E,E" "0,1"
|
|
tree.end
|
|
tree "DMACB (DMA Controller)"
|
|
base ad:0x40001000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "INTSTATUS,DMAC Interrupt Status Register"
|
|
bitfld.long 0x00 1. "INTSTATUS1,INTSTATUS1" "0,1"
|
|
bitfld.long 0x00 0. "INTSTATUS0,INTSTATUS0" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "INTTCSTATUS,DMAC Interrupt Terminal Count Status Register"
|
|
bitfld.long 0x00 1. "INTTCSTATUS1,INTTCSTATUS1" "0,1"
|
|
bitfld.long 0x00 0. "INTTCSTATUS0,INTTCSTATUS0" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "INTTCCLEAR,DMAC Interrupt Terminal Count Clear Register"
|
|
bitfld.long 0x00 1. "INTTCCLEAR1,INTTCCLEAR1" "0,1"
|
|
bitfld.long 0x00 0. "INTTCCLEAR0,INTTCCLEAR0" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "INTERRORSTATUS,DMAC Interrupt Error Status Register"
|
|
bitfld.long 0x00 1. "INTERRSTATUS1,INTERRSTATUS1" "0,1"
|
|
bitfld.long 0x00 0. "INTERRSTATUS0,INTERRSTATUS0" "0,1"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "INTERRCLR,DMAC Interrupt Error Clear Register"
|
|
bitfld.long 0x00 1. "INTERRCLR1,INTERRCLR1" "0,1"
|
|
bitfld.long 0x00 0. "INTERRCLR0,INTERRCLR0" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RAWINTTCSTATUS,DMAC Raw Interrupt Terminal Count Status Register"
|
|
bitfld.long 0x00 1. "RAMINTTCS1,RAMINTTCS1" "0,1"
|
|
bitfld.long 0x00 0. "RAMINTTCS0,RAMINTTCS0" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RAWINTERRORSTATUS,DMAC Raw Error Interrupt Status Register"
|
|
bitfld.long 0x00 1. "RAWINTERRS1,RAWINTERRS1" "0,1"
|
|
bitfld.long 0x00 0. "RAWINTERRS0,RAWINTERRS0" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ENBLDCHNS,DMAC Enabled Channel Register"
|
|
bitfld.long 0x00 1. "ENABLEDCH1,ENABLEDCH1" "0,1"
|
|
bitfld.long 0x00 0. "ENABLEDCH0,ENABLEDCH0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SOFTBREQ,DMAC Software Burst Request Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "SOFTBREQ,SOFTBREQ"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SOFTSREQ,DMAC Software Single Request Register"
|
|
bitfld.long 0x00 15. "SOFTSREQ15,SOFTSREQ15" "0,1"
|
|
bitfld.long 0x00 14. "SOFTSREQ14,SOFTSREQ14" "0,1"
|
|
bitfld.long 0x00 13. "SOFTSREQ13,SOFTSREQ13" "0,1"
|
|
bitfld.long 0x00 12. "SOFTSREQ12,SOFTSREQ12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "SOFTSREQ11,SOFTSREQ11" "0,1"
|
|
bitfld.long 0x00 10. "SOFTSREQ10,SOFTSREQ10" "0,1"
|
|
bitfld.long 0x00 9. "SOFTSREQ9,SOFTSREQ9" "0,1"
|
|
bitfld.long 0x00 8. "SOFTSREQ8,SOFTSREQ8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SOFTSREQ7,SOFTSREQ7" "0,1"
|
|
bitfld.long 0x00 6. "SOFTSREQ6,SOFTSREQ6" "0,1"
|
|
bitfld.long 0x00 5. "SOFTSREQ5,SOFTSREQ5" "0,1"
|
|
bitfld.long 0x00 4. "SOFTSREQ4,SOFTSREQ4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SOFTSREQ3,SOFTSREQ3" "0,1"
|
|
bitfld.long 0x00 2. "SOFTSREQ2,SOFTSREQ2" "0,1"
|
|
bitfld.long 0x00 1. "SOFTSREQ1,SOFTSREQ1" "0,1"
|
|
bitfld.long 0x00 0. "SOFTSREQ0,SOFTSREQ0" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CONFIGURATION,DMAC Configuration Register"
|
|
bitfld.long 0x00 0. "E,E" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "C0SRCADDR,DMAC Channel 0 Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCADDR,SRCADDR"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "C0DESTADDR,DMAC Channel 0 Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DESTADDR,DESTADDR"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "C0LLI,DMAC Channel 0 Linked List Item Register"
|
|
hexmask.long 0x00 2.--31. 1. "LLI,LLI"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "C0CONTROL,DMAC Channel 0 Control Register"
|
|
bitfld.long 0x00 31. "I,I" "0,1"
|
|
bitfld.long 0x00 27. "DI,DI" "0,1"
|
|
bitfld.long 0x00 26. "SI,SI" "0,1"
|
|
bitfld.long 0x00 21.--23. "DWIDTH,DWIDTH" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "SWIDTH,SWIDTH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "DBSIZE,DBSIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SBSIZE,SBSIZE" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--11. 1. "TRANSFERSIZE,TRANSFERSIZE"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "C0CONFIGURATION,DMAC Channel 0 Configuration Register"
|
|
bitfld.long 0x00 18. "HALT,HALT" "0,1"
|
|
rbitfld.long 0x00 17. "ACTIVE,ACTIVE" "0,1"
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x00 15. "ITC,ITC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "IE,IE" "0,1"
|
|
bitfld.long 0x00 11.--13. "FLOWCNTRL,FLOWCNTRL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--9. "DESTPERIPHERAL,DESTPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. "SRCPERIPHERAL,SRCPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "E,E" "0,1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "C1SRCADDR,DMAC Channel 1 Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCADDR,SRCADDR"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "C1DESTADDR,DMAC Channel 1 Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DESTADDR,DESTADDR"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "C1LLI,DMAC Channel 1 Linked List Item Register"
|
|
hexmask.long 0x00 2.--31. 1. "LLI,LLI"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "C1CONTROL,DMAC Channel 1 Control Register"
|
|
bitfld.long 0x00 31. "I,I" "0,1"
|
|
bitfld.long 0x00 27. "DI,DI" "0,1"
|
|
bitfld.long 0x00 26. "SI,SI" "0,1"
|
|
bitfld.long 0x00 21.--23. "DWIDTH,DWIDTH" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "SWIDTH,SWIDTH" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "DBSIZE,DBSIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SBSIZE,SBSIZE" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--11. 1. "TRANSFERSIZE,TRANSFERSIZE"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "C1CONFIGURATION,DMAC Channel 1 Configuration Register"
|
|
bitfld.long 0x00 18. "HALT,HALT" "0,1"
|
|
rbitfld.long 0x00 17. "ACTIVE,ACTIVE" "0,1"
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0,1"
|
|
bitfld.long 0x00 15. "ITC,ITC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "IE,IE" "0,1"
|
|
bitfld.long 0x00 11.--13. "FLOWCNTRL,FLOWCNTRL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--9. "DESTPERIPHERAL,DESTPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. "SRCPERIPHERAL,SRCPERIPHERAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "E,E" "0,1"
|
|
tree.end
|
|
tree "SMI"
|
|
base ad:0x4000C000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MAP0,SMIF Flash Memory Map0 Register"
|
|
rbitfld.long 0x00 28.--31. "FBAH,FBAH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 6.--27. 1. "FBAL,FBAL"
|
|
bitfld.long 0x00 2.--5. "FDEN,FDEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "RE,RE" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MAP1,SMIF Flash Memory Map1 Register"
|
|
rbitfld.long 0x00 28.--31. "FBAH,FBAH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 6.--27. 1. "FBAL,FBAL"
|
|
bitfld.long 0x00 2.--5. "FDEN,FDEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "RE,RE" "0,1"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "DACR$1,SMIF Direct Access Control Register $1"
|
|
bitfld.long 0x00 16.--20. "SPR,SPR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SCSD,SCSD"
|
|
bitfld.long 0x00 6. "POLLWIP,POLLWIP" "0,1"
|
|
repeat.end
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "DRCR$1,SMIF Direct Read Control Register $1"
|
|
hexmask.long.byte 0x00 23.--30. 1. "CMDOP,CMDOP"
|
|
bitfld.long 0x00 12.--15. "DMYBC,DMYBC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DATIO,DATIO" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "DMYIO,DMYIO" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "ADRIO,ADRIO" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CMOIO,CMOIO" "0,1,2,3"
|
|
repeat.end
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "RACR0,SMIF Program Register Access Control Register 0"
|
|
bitfld.long 0x00 16.--20. "SPR,SPR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SCSD,SCSD"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "RACR1,SMIF Program Register Access Control Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUFBC,SBUFBC"
|
|
bitfld.long 0x00 16.--18. "PBUFBC,PBUFBC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "SBUFEN,SBUFEN" "0,1"
|
|
bitfld.long 0x00 4. "PBUFEN,PBUFEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CSNUM,CSNUM" "0,1"
|
|
bitfld.long 0x00 0. "CYCGO,CYCGO" "0,1"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "INT,SMIF Program Register Access Interrupt Enable Register"
|
|
bitfld.long 0x00 0. "INTEN,INTEN" "0,1"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "STAT,SMIF Program Register Access Status Register"
|
|
rbitfld.long 0x00 1. "CYCPROG,CYCPROG" "0,1"
|
|
bitfld.long 0x00 0. "CYCDONE,CYCDONE" "0,1"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "PBUF0,SMIF Program Register Primary Buffer Data Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PBUF3,PBUF3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PBUF2,PBUF2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "PBUF1,PBUF1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PBUF0,PBUF0"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "PBUF1,SMIF Program Register Primary Buffer Data Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PBUF7,PBUF7"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PBUF6,PBUF6"
|
|
hexmask.long.byte 0x00 8.--15. 1. "PBUF5,PBUF5"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PBUF4,PBUF4"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SBUF00,SMIF Program Register Secondary Buffer Data Register 00"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF3,SBUF3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF2,SBUF2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF1,SBUF1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF0,SBUF0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SBUF01,SMIF Program Register Secondary Buffer Data Register 01"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF7,SBUF7"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF6,SBUF6"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF5,SBUF5"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF4,SBUF4"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SBUF02,SMIF Program Register Secondary Buffer Data Register 02"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF11,SBUF11"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF10,SBUF10"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF9,SBUF9"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF8,SBUF8"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SBUF03,SMIF Program Register Secondary Buffer Data Register 03"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF15,SBUF15"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF14,SBUF14"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF13,SBUF13"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF12,SBUF12"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SBUF04,SMIF Program Register Secondary Buffer Data Register 04"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF19,SBUF19"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF18,SBUF18"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF17,SBUF17"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF16,SBUF16"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SBUF05,SMIF Program Register Secondary Buffer Data Register 05"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF23,SBUF23"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF22,SBUF22"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF21,SBUF21"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF20,SBUF20"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SBUF06,SMIF Program Register Secondary Buffer Data Register 06"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF27,SBUF27"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF26,SBUF26"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF25,SBUF25"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF24,SBUF24"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SBUF07,SMIF Program Register Secondary Buffer Data Register 07"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF31,SBUF31"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF30,SBUF30"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF29,SBUF29"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF28,SBUF28"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SBUF08,SMIF Program Register Secondary Buffer Data Register 08"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF35,SBUF35"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF34,SBUF34"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF33,SBUF33"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF32,SBUF32"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SBUF09,SMIF Program Register Secondary Buffer Data Register 09"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF39,SBUF39"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF38,SBUF38"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF37,SBUF37"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF36,SBUF36"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SBUF10,SMIF Program Register Secondary Buffer Data Register 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF43,SBUF43"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF42,SBUF42"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF41,SBUF41"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF40,SBUF40"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SBUF11,SMIF Program Register Secondary Buffer Data Register 11"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF47,SBUF47"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF46,SBUF46"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF45,SBUF45"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF44,SBUF44"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SBUF12,SMIF Program Register Secondary Buffer Data Register 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF51,SBUF51"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF50,SBUF50"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF49,SBUF49"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF48,SBUF48"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SBUF13,SMIF Program Register Secondary Buffer Data Register 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF55,SBUF55"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF54,SBUF54"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF53,SBUF53"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF52,SBUF52"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SBUF14,SMIF Program Register Secondary Buffer Data Register 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF59,SBUF59"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF58,SBUF58"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF57,SBUF57"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF56,SBUF56"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SBUF15,SMIF Program Register Secondary Buffer Data Register 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF63,SBUF63"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF62,SBUF62"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF61,SBUF61"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF60,SBUF60"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SBUF16,SMIF Program Register Secondary Buffer Data Register 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF67,SBUF67"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF66,SBUF66"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF65,SBUF65"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF64,SBUF64"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SBUF17,SMIF Program Register Secondary Buffer Data Register 17"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF71,SBUF71"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF70,SBUF70"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF69,SBUF69"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF68,SBUF68"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SBUF18,SMIF Program Register Secondary Buffer Data Register 18"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF75,SBUF75"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF74,SBUF74"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF73,SBUF73"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF72,SBUF72"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SBUF19,SMIF Program Register Secondary Buffer Data Register 19"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF79,SBUF79"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF78,SBUF78"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF77,SBUF77"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF76,SBUF76"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SBUF20,SMIF Program Register Secondary Buffer Data Register 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF83,SBUF83"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF82,SBUF82"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF81,SBUF81"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF80,SBUF80"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SBUF21,SMIF Program Register Secondary Buffer Data Register 21"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF87,SBUF87"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF86,SBUF86"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF85,SBUF85"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF84,SBUF84"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SBUF22,SMIF Program Register Secondary Buffer Data Register 22"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF91,SBUF91"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF90,SBUF90"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF89,SBUF89"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF88,SBUF88"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SBUF23,SMIF Program Register Secondary Buffer Data Register 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF95,SBUF95"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF94,SBUF94"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF93,SBUF93"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF92,SBUF92"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SBUF24,SMIF Program Register Secondary Buffer Data Register 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF99,SBUF99"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF98,SBUF98"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF97,SBUF97"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF96,SBUF96"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SBUF25,SMIF Program Register Secondary Buffer Data Register 25"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF103,SBUF103"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF102,SBUF102"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF101,SBUF101"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF100,SBUF100"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SBUF26,SMIF Program Register Secondary Buffer Data Register 26"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF107,SBUF107"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF106,SBUF106"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF105,SBUF105"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF104,SBUF104"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SBUF27,SMIF Program Register Secondary Buffer Data Register 27"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF111,SBUF111"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF110,SBUF110"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF109,SBUF109"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF108,SBUF108"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SBUF28,SMIF Program Register Secondary Buffer Data Register 28"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF115,SBUF115"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF114,SBUF114"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF113,SBUF113"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF112,SBUF112"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SBUF29,SMIF Program Register Secondary Buffer Data Register 29"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF119,SBUF119"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF118,SBUF118"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF117,SBUF117"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF116,SBUF116"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SBUF30,SMIF Program Register Secondary Buffer Data Register 30"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF123,SBUF123"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF122,SBUF122"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF121,SBUF121"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF120,SBUF120"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SBUF31,SMIF Program Register Secondary Buffer Data Register 31"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF127,SBUF127"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF126,SBUF126"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF125,SBUF125"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF124,SBUF124"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SBUF32,SMIF Program Register Secondary Buffer Data Register 32"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF131,SBUF131"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF130,SBUF130"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF129,SBUF129"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF128,SBUF128"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SBUF33,SMIF Program Register Secondary Buffer Data Register 33"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF135,SBUF135"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF134,SBUF134"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF133,SBUF133"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF132,SBUF132"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SBUF34,SMIF Program Register Secondary Buffer Data Register 34"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF139,SBUF139"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF138,SBUF138"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF137,SBUF137"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF136,SBUF136"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SBUF35,SMIF Program Register Secondary Buffer Data Register 35"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF143,SBUF143"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF142,SBUF142"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF141,SBUF141"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF140,SBUF140"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SBUF36,SMIF Program Register Secondary Buffer Data Register 36"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF147,SBUF147"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF146,SBUF146"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF145,SBUF145"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF144,SBUF144"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SBUF37,SMIF Program Register Secondary Buffer Data Register 37"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF151,SBUF151"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF150,SBUF150"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF149,SBUF149"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF148,SBUF148"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SBUF38,SMIF Program Register Secondary Buffer Data Register 38"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF155,SBUF155"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF154,SBUF154"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF153,SBUF153"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF152,SBUF152"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SBUF39,SMIF Program Register Secondary Buffer Data Register 39"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF159,SBUF159"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF158,SBUF158"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF157,SBUF157"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF156,SBUF156"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SBUF40,SMIF Program Register Secondary Buffer Data Register 40"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF163,SBUF163"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF162,SBUF162"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF161,SBUF161"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF160,SBUF160"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SBUF41,SMIF Program Register Secondary Buffer Data Register 41"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF167,SBUF167"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF166,SBUF166"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF165,SBUF165"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF164,SBUF164"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SBUF42,SMIF Program Register Secondary Buffer Data Register 42"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF171,SBUF171"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF170,SBUF170"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF169,SBUF169"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF168,SBUF168"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SBUF43,SMIF Program Register Secondary Buffer Data Register 43"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF175,SBUF175"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF174,SBUF174"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF173,SBUF173"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF172,SBUF172"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SBUF44,SMIF Program Register Secondary Buffer Data Register 44"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF179,SBUF179"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF178,SBUF178"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF177,SBUF177"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF176,SBUF176"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SBUF45,SMIF Program Register Secondary Buffer Data Register 45"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF183,SBUF183"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF182,SBUF182"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF181,SBUF181"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF180,SBUF180"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SBUF46,SMIF Program Register Secondary Buffer Data Register 46"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF187,SBUF187"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF186,SBUF186"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF185,SBUF185"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF184,SBUF184"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SBUF47,SMIF Program Register Secondary Buffer Data Register 47"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF191,SBUF191"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF190,SBUF190"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF189,SBUF189"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF188,SBUF188"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SBUF48,SMIF Program Register Secondary Buffer Data Register 48"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF195,SBUF195"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF194,SBUF194"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF193,SBUF193"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF192,SBUF192"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SBUF49,SMIF Program Register Secondary Buffer Data Register 49"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF199,SBUF199"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF198,SBUF198"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF197,SBUF197"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF196,SBUF196"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SBUF50,SMIF Program Register Secondary Buffer Data Register 50"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF203,SBUF203"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF202,SBUF202"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF201,SBUF201"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF200,SBUF200"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SBUF51,SMIF Program Register Secondary Buffer Data Register 51"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF207,SBUF207"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF206,SBUF206"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF205,SBUF205"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF204,SBUF204"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SBUF52,SMIF Program Register Secondary Buffer Data Register 52"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF211,SBUF211"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF210,SBUF210"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF209,SBUF209"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF208,SBUF208"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SBUF53,SMIF Program Register Secondary Buffer Data Register 53"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF215,SBUF215"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF214,SBUF214"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF213,SBUF213"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF212,SBUF212"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SBUF54,SMIF Program Register Secondary Buffer Data Register 54"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF219,SBUF219"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF218,SBUF218"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF217,SBUF217"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF216,SBUF216"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SBUF55,SMIF Program Register Secondary Buffer Data Register 55"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF223,SBUF223"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF222,SBUF222"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF221,SBUF221"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF220,SBUF220"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SBUF56,SMIF Program Register Secondary Buffer Data Register 56"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF227,SBUF227"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF226,SBUF226"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF225,SBUF225"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF224,SBUF224"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SBUF57,SMIF Program Register Secondary Buffer Data Register 57"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF231,SBUF231"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF230,SBUF230"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF229,SBUF229"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF228,SBUF228"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SBUF58,SMIF Program Register Secondary Buffer Data Register 58"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF235,SBUF235"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF234,SBUF234"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF233,SBUF233"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF232,SBUF232"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SBUF59,SMIF Program Register Secondary Buffer Data Register 59"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF239,SBUF239"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF238,SBUF238"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF237,SBUF237"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF236,SBUF236"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SBUF60,SMIF Program Register Secondary Buffer Data Register 60"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF243,SBUF243"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF242,SBUF242"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF241,SBUF241"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF240,SBUF240"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SBUF61,SMIF Program Register Secondary Buffer Data Register 61"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF247,SBUF247"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF246,SBUF246"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF245,SBUF245"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF244,SBUF244"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SBUF62,SMIF Program Register Secondary Buffer Data Register 62"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF251,SBUF251"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF250,SBUF250"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF249,SBUF249"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF248,SBUF248"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SBUF63,SMIF Program Register Secondary Buffer Data Register 63"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SBUF255,SBUF255"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SBUF254,SBUF254"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SBUF253,SBUF253"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SBUF252,SBUF252"
|
|
tree.end
|
|
endif
|
|
tree "IA (Interrupt control A Register)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x4003E000
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "NIC00,Non makeable Interrupt Control(A) 00"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "INC00,Non Maskable Interrupu Mode Control Register A 00"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "NIC00,Non Maskable interrupt Mode Control Register A 00"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "IMC00,Interrupu Mode Control Register A 00"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "IMC00,Interrupu Mode Control Register(A) 00"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "IMC01,Interrupu Mode Control Register A 01"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
repeat 2. (strings "01" "02" )(list 0x0 0x1 )
|
|
group.byte ($2+0x21)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register(A $1"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 2. (strings "02" "03" )(list 0x0 0x1 )
|
|
group.byte ($2+0x22)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register A $1"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "IMC03,Interrupu Mode Control Register(A) 03"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 16. (strings "04" "05" "06" "07" "08" "09" "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x24)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register A $1"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
repeat 12. (strings "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB )
|
|
group.byte ($2+0x34)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register A $1"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
repeat 4. (strings "32" "33" "34" "35" )(list 0x0 0x1 0x2 0x3 )
|
|
group.byte ($2+0x40)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register(A $1"
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 9. (strings "49" "50" "51" "52" "53" "54" "55" "56" "57" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 )
|
|
group.byte ($2+0x51)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register A $1"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x4003E000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "NIC00,Non Maskable Interrupt Control Register(A) 00"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "RLM (Reset Low power Managiment Register)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x4003E400
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "LOSCCR,Low OSC and IHOSC2 clock supply Control Register"
|
|
rbitfld.byte 0x00 5. "POSCF,POSCF" "0,1"
|
|
bitfld.byte 0x00 4. "POSCEN,POSCEN" "0,1"
|
|
bitfld.byte 0x00 1. "DRCOSCL,DRCOSCL" "0,1"
|
|
bitfld.byte 0x00 0. "XTEN,XTEN" "0,1"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "SHTDNOP,Power Shut Down Control Register"
|
|
bitfld.byte 0x00 0. "PTKEEP,PTKEEP" "0,1"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "RSTFLG0,Reset flag register 0"
|
|
bitfld.byte 0x00 4. "STOP2RSTF,STOP2RSTF" "0,1"
|
|
bitfld.byte 0x00 3. "PINRSTF,PINRSTF" "0,1"
|
|
bitfld.byte 0x00 0. "PORSTF0,PORSTF0" "0,1"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "RSTFLG1,Reset flag register 1"
|
|
bitfld.byte 0x00 3. "OFDRSTF,OFDRSTF" "0,1"
|
|
bitfld.byte 0x00 2. "WDTRSTF,WDTRSTF" "0,1"
|
|
bitfld.byte 0x00 0. "SYSRSTF,SYSRSTF" "0,1"
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "PROTECT,Protect Register"
|
|
hexmask.byte 0x00 0.--7. 1. "PROTECT,PROTECT"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x4003E400
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x4003E400
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "RSTFLG0,Reset flag register 0"
|
|
bitfld.byte 0x00 5. "LVDRSTF,LVDRSTF" "0,1"
|
|
bitfld.byte 0x00 3. "PINRSTF,PINRSTF" "0,1"
|
|
bitfld.byte 0x00 0. "PORSTF,PORSTF" "0,1"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "RSTFLG1,Reset flag register 1"
|
|
bitfld.byte 0x00 3. "OFDRSTF,OFDRSTF" "0,1"
|
|
bitfld.byte 0x00 2. "WDTRSTF,WDTRSTF" "0,1"
|
|
bitfld.byte 0x00 1. "LOCKRSTF,LOCKRSTF" "0,1"
|
|
bitfld.byte 0x00 0. "SYSRSTF,SYSRSTF" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x4003E400
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "RSTFLG0,Reset flag register 0"
|
|
bitfld.byte 0x00 5.--7. "LVDRSTF,LVDRSTF" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 3. "PINRSTF,PINRSTF" "0,1"
|
|
bitfld.byte 0x00 0. "PORSTF,PORSTF" "0,1"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "RSTFLG1,Reset flag register 1"
|
|
bitfld.byte 0x00 3. "OFDRSTF,OFDRSTF" "0,1"
|
|
bitfld.byte 0x00 2. "WDTRSTF,WDTRSTF" "0,1"
|
|
bitfld.byte 0x00 1. "LOCKRSTF,LOCKRSTF" "0,1"
|
|
bitfld.byte 0x00 0. "SYSRSTF,SYSRSTF" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "LVD (LVD0)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x4003EC00
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR,LVD Control register"
|
|
rbitfld.byte 0x00 7. "ST,ST" "0,1"
|
|
bitfld.byte 0x00 4.--6. "LVL,LVL" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 2. "SEL,SEL" "0,1"
|
|
bitfld.byte 0x00 1. "OUTEN,OUTEN" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EN,EN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR1,LVD Control register1"
|
|
bitfld.byte 0x00 7. "SELVD,SELVD" "0,1"
|
|
bitfld.byte 0x00 4. "LVDSEL,LVDSEL" "0,1"
|
|
bitfld.byte 0x00 1. "LVSDEN,LVSDEN" "0,1"
|
|
bitfld.byte 0x00 0. "LVDNEN,LVDNEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR,LVD Control register1"
|
|
rbitfld.byte 0x00 7. "ST,ST" "0,1"
|
|
bitfld.byte 0x00 4.--6. "LVL,LVL" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 2. "SEL,SEL" "0,1"
|
|
bitfld.byte 0x00 1. "OUTEN,OUTEN" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EN,EN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "CR2,LVD Control register2"
|
|
bitfld.byte 0x00 0. "LVDOEN,LVDOEN" "0,1"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "LVL1,LVD detection voltage select register 1"
|
|
bitfld.byte 0x00 0.--3. "LVDNLVL,LVDNLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "LVL2,LVD detection voltage select register 2"
|
|
bitfld.byte 0x00 0.--3. "LVDSLVL,LVDSLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "SR,LVD status register"
|
|
bitfld.byte 0x00 1. "LVDSS,LVDSS" "0,1"
|
|
bitfld.byte 0x00 0. "LVDNS,LVDNS" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x4003EC00
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR,LVD Control register"
|
|
rbitfld.byte 0x00 7. "ST,ST" "0,1"
|
|
bitfld.byte 0x00 4.--6. "LVL,LVL" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 2. "SEL,SEL" "0,1"
|
|
bitfld.byte 0x00 1. "OUTEN,OUTEN" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EN,EN" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "TSEL (TRGSEL)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400A0400
|
|
elif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400BB800
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40040400
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TRGSEL Control register 0"
|
|
bitfld.long 0x00 28.--30. "INSEL3,INSEL3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN3,UPDN3" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL3,OUTSEL3" "0,1"
|
|
bitfld.long 0x00 24. "EN3,EN3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL2,INSEL2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN2,UPDN2" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL2,OUTSEL2" "0,1"
|
|
bitfld.long 0x00 16. "EN2,EN2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL1,INSEL1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN1,UPDN1" "0,1"
|
|
bitfld.long 0x00 8. "EN1,EN1" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL1,OUTSEL1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL0,INSEL0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN0,UPDN0" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL0,OUTSEL0" "0,1"
|
|
bitfld.long 0x00 0. "EN0,EN0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TRGSEL Control register 0"
|
|
bitfld.long 0x00 28.--30. "INSEL3,INSEL3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN3,UPDN3" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL3,OUTSEL3" "0,1"
|
|
bitfld.long 0x00 24. "EN3,EN3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL2,INSEL2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN2,UPDN2" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL2,OUTSEL2" "0,1"
|
|
bitfld.long 0x00 16. "EN2,EN2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL1,INSEL1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN1,UPDN1" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL1,OUTSEL1" "0,1"
|
|
bitfld.long 0x00 8. "EN1,EN1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL0,INSEL0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN0,UPDN0" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL0,OUTSEL0" "0,1"
|
|
bitfld.long 0x00 0. "EN0,EN0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TRGSEL Control register 0"
|
|
bitfld.long 0x00 28.--30. "INSEL3,INSEL3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24. "EN3,EN3" "0,1"
|
|
bitfld.long 0x00 20.--22. "INSEL2,INSEL2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. "EN2,EN2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL1,INSEL1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. "EN1,EN1" "0,1"
|
|
bitfld.long 0x00 4.--6. "INSEL0,INSEL0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "EN0,EN0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TRGSEL Control register 1"
|
|
bitfld.long 0x00 28.--30. "INSEL7,INSEL7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN7,UPDN7" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL7,OUTSEL7" "0,1"
|
|
bitfld.long 0x00 24. "EN7,EN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL6,INSEL6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN6,UPDN6" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL6,OUTSEL6" "0,1"
|
|
bitfld.long 0x00 16. "EN6,EN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL5,INSEL5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN5,UPDN5" "0,1"
|
|
bitfld.long 0x00 8. "EN5,EN5" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL5,OUTSEL5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL4,INSEL4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN4,UPDN4" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL4,OUTSEL4" "0,1"
|
|
bitfld.long 0x00 0. "EN4,EN4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TRGSEL Control register 1"
|
|
bitfld.long 0x00 28.--30. "INSEL7,INSEL7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN7,UPDN7" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL7,OUTSEL7" "0,1"
|
|
bitfld.long 0x00 24. "EN7,EN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL6,INSEL6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN6,UPDN6" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL6,OUTSEL6" "0,1"
|
|
bitfld.long 0x00 16. "EN6,EN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL5,INSEL5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN5,UPDN5" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL5,OUTSEL5" "0,1"
|
|
bitfld.long 0x00 8. "EN5,EN5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL4,INSEL4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN4,UPDN4" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL4,OUTSEL4" "0,1"
|
|
bitfld.long 0x00 0. "EN4,EN4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TRGSEL Control register 1"
|
|
bitfld.long 0x00 28.--30. "INSEL7,INSEL7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24. "EN7,EN7" "0,1"
|
|
bitfld.long 0x00 20.--22. "INSEL6,INSEL6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. "EN6,EN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL5,INSEL5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. "EN5,EN5" "0,1"
|
|
bitfld.long 0x00 4.--6. "INSEL4,INSEL4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "EN4,EN4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSEL Control register 2"
|
|
bitfld.long 0x00 28.--30. "INSEL11,INSEL11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN11,UPDN11" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL11,OUTSEL11" "0,1"
|
|
bitfld.long 0x00 24. "EN11,EN11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL10,INSEL10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN10,UPDN10" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL10,OUTSEL10" "0,1"
|
|
bitfld.long 0x00 16. "EN10,EN10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL9,INSEL9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN9,UPDN9" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL9,OUTSEL9" "0,1"
|
|
bitfld.long 0x00 8. "EN9,EN9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL8,INSEL8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN8,UPDN8" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL8,OUTSEL8" "0,1"
|
|
bitfld.long 0x00 0. "EN8,EN8" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSEL Control register 2"
|
|
bitfld.long 0x00 28.--30. "INSEL11,INSEL11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN11,UPDN11" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL11,OUTSEL11" "0,1"
|
|
bitfld.long 0x00 24. "EN11,EN11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL10,INSEL10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN10,UPDN10" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL10,OUTSEL10" "0,1"
|
|
bitfld.long 0x00 16. "EN10,EN10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL9,INSEL9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN9,UPDN9" "0,1"
|
|
bitfld.long 0x00 8. "EN9,EN9" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL9,OUTSEL9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL8,INSEL8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN8,UPDN8" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL8,OUTSEL8" "0,1"
|
|
bitfld.long 0x00 0. "EN8,EN8" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSEL Control register 2"
|
|
bitfld.long 0x00 28.--30. "INSEL11,INSEL11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24. "EN11,EN11" "0,1"
|
|
bitfld.long 0x00 20.--22. "INSEL10,INSEL10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. "EN10,EN10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL9,INSEL9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. "EN9,EN9" "0,1"
|
|
bitfld.long 0x00 4.--6. "INSEL8,INSEL8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "EN8,EN8" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TRGSEL Control register 3"
|
|
bitfld.long 0x00 28.--30. "INSEL15,INSEL15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN15,UPDN15" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL15,OUTSEL15" "0,1"
|
|
bitfld.long 0x00 24. "EN15,EN15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL14,INSEL14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN14,UPDN14" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL14,OUTSEL14" "0,1"
|
|
bitfld.long 0x00 16. "EN14,EN14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL13,INSEL13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN13,UPDN13" "0,1"
|
|
bitfld.long 0x00 8. "EN13,EN13" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL13,OUTSEL13" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL12,INSEL12" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN12,UPDN12" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL12,OUTSEL12" "0,1"
|
|
bitfld.long 0x00 0. "EN12,EN12" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TRGSEL Control register 3"
|
|
bitfld.long 0x00 28.--30. "INSEL15,INSEL15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN15,UPDN15" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL15,OUTSEL15" "0,1"
|
|
bitfld.long 0x00 24. "EN15,EN15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL14,INSEL14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN14,UPDN14" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL14,OUTSEL14" "0,1"
|
|
bitfld.long 0x00 16. "EN14,EN14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL13,INSEL13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN13,UPDN13" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL13,OUTSEL13" "0,1"
|
|
bitfld.long 0x00 8. "EN13,EN13" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL12,INSEL12" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN12,UPDN12" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL12,OUTSEL12" "0,1"
|
|
bitfld.long 0x00 0. "EN12,EN12" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TRGSEL Control register 3"
|
|
bitfld.long 0x00 28.--30. "INSEL15,INSEL15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24. "EN15,EN15" "0,1"
|
|
bitfld.long 0x00 20.--22. "INSEL14,INSEL14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. "EN14,EN14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL13,INSEL13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. "EN13,EN13" "0,1"
|
|
bitfld.long 0x00 4.--6. "INSEL12,INSEL12" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "EN12,EN12" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR4,TRGSEL Control register 4"
|
|
bitfld.long 0x00 28.--30. "INSEL19,INSEL19" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN19,UPDN19" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL19,OUTSEL19" "0,1"
|
|
bitfld.long 0x00 24. "EN19,EN19" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL18,INSEL18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN18,UPDN18" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL18,OUTSEL18" "0,1"
|
|
bitfld.long 0x00 16. "EN18,EN18" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL17,INSEL17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN17,UPDN17" "0,1"
|
|
bitfld.long 0x00 8. "EN17,EN17" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL17,OUTSEL17" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL16,INSEL16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN16,UPDN16" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL16,OUTSEL16" "0,1"
|
|
bitfld.long 0x00 0. "EN16,EN16" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR4,TRGSEL Control register 4"
|
|
bitfld.long 0x00 28.--30. "INSEL19,INSEL19" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN19,UPDN19" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL19,OUTSEL19" "0,1"
|
|
bitfld.long 0x00 24. "EN19,EN19" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL18,INSEL18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN18,UPDN18" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL18,OUTSEL18" "0,1"
|
|
bitfld.long 0x00 16. "EN18,EN18" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL17,INSEL17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN17,UPDN17" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL17,OUTSEL17" "0,1"
|
|
bitfld.long 0x00 8. "EN17,EN17" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL16,INSEL16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN16,UPDN16" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL16,OUTSEL16" "0,1"
|
|
bitfld.long 0x00 0. "EN16,EN16" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CR5,TRGSEL Control register 5"
|
|
bitfld.long 0x00 28.--30. "INSEL23,INSEL23" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN23,UPDN23" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL23,OUTSEL23" "0,1"
|
|
bitfld.long 0x00 24. "EN23,EN23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL22,INSEL22" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN22,UPDN22" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL22,OUTSEL22" "0,1"
|
|
bitfld.long 0x00 16. "EN22,EN22" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL21,INSEL21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN21,UPDN21" "0,1"
|
|
bitfld.long 0x00 8. "EN21,EN21" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL21,OUTSEL21" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL20,INSEL20" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN20,UPDN20" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL20,OUTSEL20" "0,1"
|
|
bitfld.long 0x00 0. "EN20,EN20" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CR5,TRGSEL Control register 5"
|
|
bitfld.long 0x00 28.--30. "INSEL23,INSEL23" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN23,UPDN23" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL23,OUTSEL23" "0,1"
|
|
bitfld.long 0x00 24. "EN23,EN23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL22,INSEL22" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN22,UPDN22" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL22,OUTSEL22" "0,1"
|
|
bitfld.long 0x00 16. "EN22,EN22" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL21,INSEL21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN21,UPDN21" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL21,OUTSEL21" "0,1"
|
|
bitfld.long 0x00 8. "EN21,EN21" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL20,INSEL20" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN20,UPDN20" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL20,OUTSEL20" "0,1"
|
|
bitfld.long 0x00 0. "EN20,EN20" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CR6,TRGSEL Control register 6"
|
|
bitfld.long 0x00 28.--30. "INSEL27,INSEL27" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN27,UPDN27" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL27,OUTSEL27" "0,1"
|
|
bitfld.long 0x00 24. "EN27,EN27" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL26,INSEL26" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN26,UPDN26" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL26,OUTSEL26" "0,1"
|
|
bitfld.long 0x00 16. "EN26,EN26" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL25,INSEL25" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN25,UPDN25" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL25,OUTSEL25" "0,1"
|
|
bitfld.long 0x00 8. "EN25,EN25" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL24,INSEL24" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN24,UPDN24" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL24,OUTSEL24" "0,1"
|
|
bitfld.long 0x00 0. "EN24,EN24" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CR6,TRGSEL Control register 6"
|
|
bitfld.long 0x00 28.--30. "INSEL27,INSEL27" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN27,UPDN27" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL27,OUTSEL27" "0,1"
|
|
bitfld.long 0x00 24. "EN27,EN27" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL26,INSEL26" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN26,UPDN26" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL26,OUTSEL26" "0,1"
|
|
bitfld.long 0x00 16. "EN26,EN26" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL25,INSEL25" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN25,UPDN25" "0,1"
|
|
bitfld.long 0x00 8. "EN25,EN25" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL25,OUTSEL25" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL24,INSEL24" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN24,UPDN24" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL24,OUTSEL24" "0,1"
|
|
bitfld.long 0x00 0. "EN24,EN24" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CR7,TRGSEL Control register 7"
|
|
bitfld.long 0x00 28.--30. "INSEL31,INSEL31" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN31,UPDN31" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL31,OUTSEL31" "0,1"
|
|
bitfld.long 0x00 24. "EN31,EN31" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL30,INSEL30" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN30,UPDN30" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL30,OUTSEL30" "0,1"
|
|
bitfld.long 0x00 16. "EN30,EN30" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL29,INSEL29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN29,UPDN29" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL29,OUTSEL29" "0,1"
|
|
bitfld.long 0x00 8. "EN29,EN29" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL28,INSEL28" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN28,UPDN28" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL28,OUTSEL28" "0,1"
|
|
bitfld.long 0x00 0. "EN28,EN28" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CR7,TRGSEL Control register 7"
|
|
bitfld.long 0x00 28.--30. "INSEL31,INSEL31" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN31,UPDN31" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL31,OUTSEL31" "0,1"
|
|
bitfld.long 0x00 24. "EN31,EN31" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL30,INSEL30" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN30,UPDN30" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL30,OUTSEL30" "0,1"
|
|
bitfld.long 0x00 16. "EN30,EN30" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL29,INSEL29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN29,UPDN29" "0,1"
|
|
bitfld.long 0x00 8. "EN29,EN29" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL29,OUTSEL29" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL28,INSEL28" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN28,UPDN28" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL28,OUTSEL28" "0,1"
|
|
bitfld.long 0x00 0. "EN28,EN28" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CR8,TRGSEL Control register 8"
|
|
bitfld.long 0x00 28.--30. "INSEL35,INSEL35" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN35,UPDN35" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL35,OUTSEL35" "0,1"
|
|
bitfld.long 0x00 24. "EN35,EN35" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL34,INSEL34" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN34,UPDN34" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL34,OUTSEL34" "0,1"
|
|
bitfld.long 0x00 16. "EN34,EN34" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL33,INSEL33" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN33,UPDN33" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL33,OUTSEL33" "0,1"
|
|
bitfld.long 0x00 8. "EN33,EN33" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL32,INSEL32" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN32,UPDN32" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL32,OUTSEL32" "0,1"
|
|
bitfld.long 0x00 0. "EN32,EN32" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CR8,TRGSEL Control register 8"
|
|
bitfld.long 0x00 28.--30. "INSEL35,INSEL35" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN35,UPDN35" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL35,OUTSEL35" "0,1"
|
|
bitfld.long 0x00 24. "EN35,EN35" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL34,INSEL34" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN34,UPDN34" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL34,OUTSEL34" "0,1"
|
|
bitfld.long 0x00 16. "EN34,EN34" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL33,INSEL33" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN33,UPDN33" "0,1"
|
|
bitfld.long 0x00 8. "EN33,EN33" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL33,OUTSEL33" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL32,INSEL32" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN32,UPDN32" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL32,OUTSEL32" "0,1"
|
|
bitfld.long 0x00 0. "EN32,EN32" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CR9,TRGSEL Control register 9"
|
|
bitfld.long 0x00 28.--30. "INSEL39,INSEL39" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN39,UPDN39" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL39,OUTSEL39" "0,1"
|
|
bitfld.long 0x00 24. "EN39,EN39" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL38,INSEL38" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN38,UPDN38" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL38,OUTSEL38" "0,1"
|
|
bitfld.long 0x00 16. "EN38,EN38" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL37,INSEL37" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN37,UPDN37" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL37,OUTSEL37" "0,1"
|
|
bitfld.long 0x00 8. "EN37,EN37" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL36,INSEL36" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN36,UPDN36" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL36,OUTSEL36" "0,1"
|
|
bitfld.long 0x00 0. "EN36,EN36" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CR9,TRGSEL Control register 9"
|
|
bitfld.long 0x00 28.--30. "INSEL39,INSEL39" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN39,UPDN39" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL39,OUTSEL39" "0,1"
|
|
bitfld.long 0x00 24. "EN39,EN39" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL38,INSEL38" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN38,UPDN38" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL38,OUTSEL38" "0,1"
|
|
bitfld.long 0x00 16. "EN38,EN38" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL37,INSEL37" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN37,UPDN37" "0,1"
|
|
bitfld.long 0x00 8. "EN37,EN37" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL37,OUTSEL37" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL36,INSEL36" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN36,UPDN36" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL36,OUTSEL36" "0,1"
|
|
bitfld.long 0x00 0. "EN36,EN36" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CR10,TRGSEL Control register 10"
|
|
bitfld.long 0x00 4.--6. "INSEL40,INSEL40" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN40,UPDN40" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL40,OUTSEL40" "0,1"
|
|
bitfld.long 0x00 0. "EN40,EN40" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CR10,TRGSEL Control register 10"
|
|
bitfld.long 0x00 28.--30. "INSEL43,INSEL43" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN43,UPDN43" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL43,OUTSEL43" "0,1"
|
|
bitfld.long 0x00 24. "EN43,EN43" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL42,INSEL42" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN42,UPDN42" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL42,OUTSEL42" "0,1"
|
|
bitfld.long 0x00 16. "EN42,EN42" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL41,INSEL41" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN41,UPDN41" "0,1"
|
|
bitfld.long 0x00 8. "EN41,EN41" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL41,OUTSEL41" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL40,INSEL40" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN40,UPDN40" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL40,OUTSEL40" "0,1"
|
|
bitfld.long 0x00 0. "EN40,EN40" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CR11,TRGSEL Control register 11"
|
|
bitfld.long 0x00 28.--30. "INSEL47,INSEL47" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN47,UPDN47" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL47,OUTSEL47" "0,1"
|
|
bitfld.long 0x00 24. "EN47,EN47" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL46,INSEL46" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN46,UPDN46" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL46,OUTSEL46" "0,1"
|
|
bitfld.long 0x00 16. "EN46,EN46" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL45,INSEL45" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN45,UPDN45" "0,1"
|
|
bitfld.long 0x00 8. "EN45,EN45" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL45,OUTSEL45" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL44,INSEL44" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN44,UPDN44" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL44,OUTSEL44" "0,1"
|
|
bitfld.long 0x00 0. "EN44,EN44" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CR12,TRGSEL Control register 12"
|
|
bitfld.long 0x00 28.--30. "INSEL51,INSEL51" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN51,UPDN51" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL51,OUTSEL51" "0,1"
|
|
bitfld.long 0x00 24. "EN51,EN51" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL50,INSEL50" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN50,UPDN50" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL50,OUTSEL50" "0,1"
|
|
bitfld.long 0x00 16. "EN50,EN50" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL49,INSEL49" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN49,UPDN49" "0,1"
|
|
bitfld.long 0x00 8. "EN49,EN49" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL49,OUTSEL49" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL48,INSEL48" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN48,UPDN48" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL48,OUTSEL48" "0,1"
|
|
bitfld.long 0x00 0. "EN48,EN48" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CR13,TRGSEL Control register 13"
|
|
bitfld.long 0x00 28.--30. "INSEL55,INSEL55" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN55,UPDN55" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL55,OUTSEL55" "0,1"
|
|
bitfld.long 0x00 24. "EN55,EN55" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL54,INSEL54" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN54,UPDN54" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL54,OUTSEL54" "0,1"
|
|
bitfld.long 0x00 16. "EN54,EN54" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL53,INSEL53" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN53,UPDN53" "0,1"
|
|
bitfld.long 0x00 8. "EN53,EN53" "0,1"
|
|
bitfld.long 0x00 7. "OUTSEL53,OUTSEL53" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL52,INSEL52" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN52,UPDN52" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL52,OUTSEL52" "0,1"
|
|
bitfld.long 0x00 0. "EN52,EN52" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400A0400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TRGSEL Control register 0"
|
|
bitfld.long 0x00 28.--30. "INSEL3,INSEL3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN3,UPDN3" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL3,OUTSEL3" "0,1"
|
|
bitfld.long 0x00 24. "EN3,EN3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL2,INSEL2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN2,UPDN2" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL2,OUTSEL2" "0,1"
|
|
bitfld.long 0x00 16. "EN2,EN2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL1,INSEL1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN1,UPDN1" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL1,OUTSEL1" "0,1"
|
|
bitfld.long 0x00 8. "EN1,EN1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL0,INSEL0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN0,UPDN0" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL0,OUTSEL0" "0,1"
|
|
bitfld.long 0x00 0. "EN0,EN0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TRGSEL Control register 1"
|
|
bitfld.long 0x00 28.--30. "INSEL7,INSEL7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN7,UPDN7" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL7,OUTSEL7" "0,1"
|
|
bitfld.long 0x00 24. "EN7,EN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL6,INSEL6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN6,UPDN6" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL6,OUTSEL6" "0,1"
|
|
bitfld.long 0x00 16. "EN6,EN6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL5,INSEL5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN5,UPDN5" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL5,OUTSEL5" "0,1"
|
|
bitfld.long 0x00 8. "EN5,EN5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL4,INSEL4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN4,UPDN4" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL4,OUTSEL4" "0,1"
|
|
bitfld.long 0x00 0. "EN4,EN4" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TRGSEL Control register 2"
|
|
bitfld.long 0x00 28.--30. "INSEL11,INSEL11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN11,UPDN11" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL11,OUTSEL11" "0,1"
|
|
bitfld.long 0x00 24. "EN11,EN11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL10,INSEL10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN10,UPDN10" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL10,OUTSEL10" "0,1"
|
|
bitfld.long 0x00 16. "EN10,EN10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL9,INSEL9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN9,UPDN9" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL9,OUTSEL9" "0,1"
|
|
bitfld.long 0x00 8. "EN9,EN9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL8,INSEL8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN8,UPDN8" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL8,OUTSEL8" "0,1"
|
|
bitfld.long 0x00 0. "EN8,EN8" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TRGSEL Control register 3"
|
|
bitfld.long 0x00 28.--30. "INSEL15,INSEL15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN15,UPDN15" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL15,OUTSEL15" "0,1"
|
|
bitfld.long 0x00 24. "EN15,EN15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL14,INSEL14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN14,UPDN14" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL14,OUTSEL14" "0,1"
|
|
bitfld.long 0x00 16. "EN14,EN14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL13,INSEL13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN13,UPDN13" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL13,OUTSEL13" "0,1"
|
|
bitfld.long 0x00 8. "EN13,EN13" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL12,INSEL12" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN12,UPDN12" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL12,OUTSEL12" "0,1"
|
|
bitfld.long 0x00 0. "EN12,EN12" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR4,TRGSEL Control register 4"
|
|
bitfld.long 0x00 28.--30. "INSEL19,INSEL19" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN19,UPDN19" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL19,OUTSEL19" "0,1"
|
|
bitfld.long 0x00 24. "EN19,EN19" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL18,INSEL18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN18,UPDN18" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL18,OUTSEL18" "0,1"
|
|
bitfld.long 0x00 16. "EN18,EN18" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL17,INSEL17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN17,UPDN17" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL17,OUTSEL17" "0,1"
|
|
bitfld.long 0x00 8. "EN17,EN17" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL16,INSEL16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN16,UPDN16" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL16,OUTSEL16" "0,1"
|
|
bitfld.long 0x00 0. "EN16,EN16" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CR5,TRGSEL Control register 5"
|
|
bitfld.long 0x00 28.--30. "INSEL23,INSEL23" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN23,UPDN23" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL23,OUTSEL23" "0,1"
|
|
bitfld.long 0x00 24. "EN23,EN23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL22,INSEL22" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN22,UPDN22" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL22,OUTSEL22" "0,1"
|
|
bitfld.long 0x00 16. "EN22,EN22" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL21,INSEL21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN21,UPDN21" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL21,OUTSEL21" "0,1"
|
|
bitfld.long 0x00 8. "EN21,EN21" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL20,INSEL20" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN20,UPDN20" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL20,OUTSEL20" "0,1"
|
|
bitfld.long 0x00 0. "EN20,EN20" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CR6,TRGSEL Control register 6"
|
|
bitfld.long 0x00 28.--30. "INSEL27,INSEL27" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN27,UPDN27" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL27,OUTSEL27" "0,1"
|
|
bitfld.long 0x00 24. "EN27,EN27" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL26,INSEL26" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN26,UPDN26" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL26,OUTSEL26" "0,1"
|
|
bitfld.long 0x00 16. "EN26,EN26" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL25,INSEL25" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN25,UPDN25" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL25,OUTSEL25" "0,1"
|
|
bitfld.long 0x00 8. "EN25,EN25" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL24,INSEL24" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN24,UPDN24" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL24,OUTSEL24" "0,1"
|
|
bitfld.long 0x00 0. "EN24,EN24" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CR7,TRGSEL Control register 7"
|
|
bitfld.long 0x00 28.--30. "INSEL31,INSEL31" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN31,UPDN31" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL31,OUTSEL31" "0,1"
|
|
bitfld.long 0x00 24. "EN31,EN31" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL30,INSEL30" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN30,UPDN30" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL30,OUTSEL30" "0,1"
|
|
bitfld.long 0x00 16. "EN30,EN30" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL29,INSEL29" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN29,UPDN29" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL29,OUTSEL29" "0,1"
|
|
bitfld.long 0x00 8. "EN29,EN29" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL28,INSEL28" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN28,UPDN28" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL28,OUTSEL28" "0,1"
|
|
bitfld.long 0x00 0. "EN28,EN28" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CR8,TRGSEL Control register 8"
|
|
bitfld.long 0x00 28.--30. "INSEL35,INSEL35" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN35,UPDN35" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL35,OUTSEL35" "0,1"
|
|
bitfld.long 0x00 24. "EN35,EN35" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL34,INSEL34" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN34,UPDN34" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL34,OUTSEL34" "0,1"
|
|
bitfld.long 0x00 16. "EN34,EN34" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL33,INSEL33" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN33,UPDN33" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL33,OUTSEL33" "0,1"
|
|
bitfld.long 0x00 8. "EN33,EN33" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL32,INSEL32" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN32,UPDN32" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL32,OUTSEL32" "0,1"
|
|
bitfld.long 0x00 0. "EN32,EN32" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CR9,TRGSEL Control register 9"
|
|
bitfld.long 0x00 28.--30. "INSEL39,INSEL39" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26. "UPDN39,UPDN39" "0,1"
|
|
bitfld.long 0x00 25. "OUTSEL39,OUTSEL39" "0,1"
|
|
bitfld.long 0x00 24. "EN39,EN39" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "INSEL38,INSEL38" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN38,UPDN38" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL38,OUTSEL38" "0,1"
|
|
bitfld.long 0x00 16. "EN38,EN38" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL37,INSEL37" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN37,UPDN37" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL37,OUTSEL37" "0,1"
|
|
bitfld.long 0x00 8. "EN37,EN37" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL36,INSEL36" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN36,UPDN36" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL36,OUTSEL36" "0,1"
|
|
bitfld.long 0x00 0. "EN36,EN36" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CR10,TRGSEL Control register 10"
|
|
bitfld.long 0x00 20.--22. "INSEL42,INSEL42" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18. "UPDN42,UPDN42" "0,1"
|
|
bitfld.long 0x00 17. "OUTSEL42,OUTSEL42" "0,1"
|
|
bitfld.long 0x00 16. "EN42,EN42" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "INSEL41,INSEL41" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "UPDN41,UPDN41" "0,1"
|
|
bitfld.long 0x00 9. "OUTSEL41,OUTSEL41" "0,1"
|
|
bitfld.long 0x00 8. "EN41,EN41" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "INSEL40,INSEL40" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "UPDN40,UPDN40" "0,1"
|
|
bitfld.long 0x00 1. "OUTSEL40,OUTSEL40" "0,1"
|
|
bitfld.long 0x00 0. "EN40,EN40" "0,1"
|
|
endif
|
|
tree.end
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
tree "LTT (Long Term Timer(LTTMR))"
|
|
base ad:0x4003FF00
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CR0,Long Term Control Register"
|
|
bitfld.byte 0x00 1. "TRUN,TRUN" "0,1"
|
|
bitfld.byte 0x00 0. "OSCE,OSCE" "0,1"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "VALL,Long Term Setting Register"
|
|
hexmask.byte 0x00 0.--7. 1. "TMRVALL,TMRVALL"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "VALH,Long Term Setting Register"
|
|
hexmask.byte 0x00 0.--7. 1. "TMRVALH,TMRVALH"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G8*")
|
|
tree "TSPI (Serial Interface (TSPI))"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "TSPI0"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x4006A000
|
|
elif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x40098000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TSPI Control Register 0"
|
|
bitfld.long 0x00 6.--7. "SWRST,SWRST" "0,1,2,3"
|
|
bitfld.long 0x00 0. "TSPIE,TSPIE" "0,1"
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 15. "TRGEN,TRGEN" "0,1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "RXDLY,RXDLY" "0,1"
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TSPI Control Register 3"
|
|
bitfld.long 0x00 1. "TFEMPCLR,TFEMPCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFFLLCLR,RFFLLCLR" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BR,TSPI Baud Rate Generator Control Register"
|
|
bitfld.long 0x00 4.--7. "BRCK,BRCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "BRS,BRS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
rbitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
bitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FMTR1,TSPI Format Control Register 1"
|
|
bitfld.long 0x00 4.--6. "EHOLD,EHOLD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "VPE,VPE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "VPM,VPM" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DR,TSPI Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSPIDR,TSPIDR"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SR,TSPI Status Register"
|
|
rbitfld.long 0x00 31. "TSPISUE,TSPISUE" "0,1"
|
|
rbitfld.long 0x00 23. "TXRUN,TXRUN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 21. "INTTXWF,INTTXWF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "TFEMP,TFEMP" "0,1"
|
|
rbitfld.long 0x00 16.--19. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFF,INTRXFF" "0,1"
|
|
rbitfld.long 0x00 4. "RFFLL,RFFLL" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 3. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 0. "PERR,PERR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 3. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
rbitfld.long 0x00 0. "PERR,PERR" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
repeat 2. (list 0. 1.) (list ad:0x400CA000 ad:0x400CA400)
|
|
tree "TSPI$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TSPI Control Register 0"
|
|
bitfld.long 0x00 6.--7. "SWRST,SWRST" "0,1,2,3"
|
|
bitfld.long 0x00 0. "TSPIE,TSPIE" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 15. "TRGEN,TRGEN" "0,1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
bitfld.long 0x00 16. "RXDLY,RXDLY" "0,1"
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TSPI Control Register 3"
|
|
bitfld.long 0x00 1. "TFEMPCLR,TFEMPCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFFLLCLR,RFFLLCLR" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BR,TSPI Baud Rate Generator Control Register"
|
|
bitfld.long 0x00 4.--7. "BRCK,BRCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "BRS,BRS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
bitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FMTR1,TSPI Format Control Register 1"
|
|
bitfld.long 0x00 4.--6. "EHOLD,EHOLD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "VPE,VPE" "0,1"
|
|
bitfld.long 0x00 0. "VPM,VPM" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DR,TSPI Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSPIDR,TSPIDR"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SR,TSPI Status Register"
|
|
rbitfld.long 0x00 31. "TSPISUE,TSPISUE" "0,1"
|
|
rbitfld.long 0x00 23. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 22. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 21. "INTTXWF,INTTXWF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "TFEMP,TFEMP" "0,1"
|
|
rbitfld.long 0x00 16.--19. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFF,INTRXFF" "0,1"
|
|
rbitfld.long 0x00 4. "RFFLL,RFFLL" "0,1"
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 3. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 0. "PERR,PERR" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "TSPI1"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x4006A400
|
|
elif cpuis("TMPM4K4A*")
|
|
base ad:0x40099000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TSPI Control Register 0"
|
|
bitfld.long 0x00 6.--7. "SWRST,SWRST" "0,1,2,3"
|
|
bitfld.long 0x00 0. "TSPIE,TSPIE" "0,1"
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 15. "TRGEN,TRGEN" "0,1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "RXDLY,RXDLY" "0,1"
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TSPI Control Register 3"
|
|
bitfld.long 0x00 1. "TFEMPCLR,TFEMPCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFFLLCLR,RFFLLCLR" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BR,TSPI Baud Rate Generator Control Register"
|
|
bitfld.long 0x00 4.--7. "BRCK,BRCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "BRS,BRS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
rbitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
bitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FMTR1,TSPI Format Control Register 1"
|
|
bitfld.long 0x00 4.--6. "EHOLD,EHOLD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "VPE,VPE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "VPM,VPM" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DR,TSPI Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSPIDR,TSPIDR"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SR,TSPI Status Register"
|
|
rbitfld.long 0x00 31. "TSPISUE,TSPISUE" "0,1"
|
|
rbitfld.long 0x00 23. "TXRUN,TXRUN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 21. "INTTXWF,INTTXWF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "TFEMP,TFEMP" "0,1"
|
|
rbitfld.long 0x00 16.--19. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFF,INTRXFF" "0,1"
|
|
rbitfld.long 0x00 4. "RFFLL,RFFLL" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 3. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 0. "PERR,PERR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 3. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
rbitfld.long 0x00 0. "PERR,PERR" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "TSPI2"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x4006A800
|
|
elif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x4009A000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TSPI Control Register 0"
|
|
bitfld.long 0x00 6.--7. "SWRST,SWRST" "0,1,2,3"
|
|
bitfld.long 0x00 0. "TSPIE,TSPIE" "0,1"
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 15. "TRGEN,TRGEN" "0,1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "RXDLY,RXDLY" "0,1"
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TSPI Control Register 3"
|
|
bitfld.long 0x00 1. "TFEMPCLR,TFEMPCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFFLLCLR,RFFLLCLR" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BR,TSPI Baud Rate Generator Control Register"
|
|
bitfld.long 0x00 4.--7. "BRCK,BRCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "BRS,BRS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
rbitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
bitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FMTR1,TSPI Format Control Register 1"
|
|
bitfld.long 0x00 4.--6. "EHOLD,EHOLD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "VPE,VPE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "VPM,VPM" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DR,TSPI Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSPIDR,TSPIDR"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SR,TSPI Status Register"
|
|
rbitfld.long 0x00 31. "TSPISUE,TSPISUE" "0,1"
|
|
rbitfld.long 0x00 23. "TXRUN,TXRUN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 21. "INTTXWF,INTTXWF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "TFEMP,TFEMP" "0,1"
|
|
rbitfld.long 0x00 16.--19. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFF,INTRXFF" "0,1"
|
|
rbitfld.long 0x00 4. "RFFLL,RFFLL" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 3. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 0. "PERR,PERR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 3. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
rbitfld.long 0x00 0. "PERR,PERR" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K4A*")
|
|
tree "TSPI3"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x4006AC00
|
|
elif cpuis("TMPM4K4A*")
|
|
base ad:0x4009B000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TSPI Control Register 0"
|
|
bitfld.long 0x00 6.--7. "SWRST,SWRST" "0,1,2,3"
|
|
bitfld.long 0x00 0. "TSPIE,TSPIE" "0,1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 15. "TRGEN,TRGEN" "0,1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "RXDLY,RXDLY" "0,1"
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TSPI Control Register 3"
|
|
bitfld.long 0x00 1. "TFEMPCLR,TFEMPCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFFLLCLR,RFFLLCLR" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BR,TSPI Baud Rate Generator Control Register"
|
|
bitfld.long 0x00 4.--7. "BRCK,BRCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "BRS,BRS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
rbitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
bitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FMTR1,TSPI Format Control Register 1"
|
|
bitfld.long 0x00 4.--6. "EHOLD,EHOLD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "VPE,VPE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "VPM,VPM" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DR,TSPI Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSPIDR,TSPIDR"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SR,TSPI Status Register"
|
|
rbitfld.long 0x00 31. "TSPISUE,TSPISUE" "0,1"
|
|
rbitfld.long 0x00 23. "TXRUN,TXRUN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 21. "INTTXWF,INTTXWF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "TFEMP,TFEMP" "0,1"
|
|
rbitfld.long 0x00 16.--19. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFF,INTRXFF" "0,1"
|
|
rbitfld.long 0x00 4. "RFFLL,RFFLL" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 3. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 0. "PERR,PERR" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
tree "TSPI4"
|
|
base ad:0x4006B000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TSPI Control Register 0"
|
|
bitfld.long 0x00 6.--7. "SWRST,SWRST" "0,1,2,3"
|
|
bitfld.long 0x00 0. "TSPIE,TSPIE" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TSPI Control Register 3"
|
|
bitfld.long 0x00 1. "TFEMPCLR,TFEMPCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFFLLCLR,RFFLLCLR" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BR,TSPI Baud Rate Generator Control Register"
|
|
bitfld.long 0x00 4.--7. "BRCK,BRCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "BRS,BRS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
rbitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FMTR1,TSPI Format Control Register 1"
|
|
bitfld.long 0x00 4.--6. "EHOLD,EHOLD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "VPE,VPE" "0,1"
|
|
bitfld.long 0x00 0. "VPM,VPM" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DR,TSPI Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSPIDR,TSPIDR"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SR,TSPI Status Register"
|
|
rbitfld.long 0x00 31. "TSPISUE,TSPISUE" "0,1"
|
|
rbitfld.long 0x00 23. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 22. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 21. "INTTXWF,INTTXWF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "TFEMP,TFEMP" "0,1"
|
|
rbitfld.long 0x00 16.--19. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFF,INTRXFF" "0,1"
|
|
rbitfld.long 0x00 4. "RFFLL,RFFLL" "0,1"
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 2. (list 5. 6.) (list ad:0x4006B400 ad:0x400CB800)
|
|
tree "TSPI$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TSPI Control Register 0"
|
|
bitfld.long 0x00 6.--7. "SWRST,SWRST" "0,1,2,3"
|
|
bitfld.long 0x00 0. "TSPIE,TSPIE" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TSPI Control Register 3"
|
|
bitfld.long 0x00 1. "TFEMPCLR,TFEMPCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFFLLCLR,RFFLLCLR" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BR,TSPI Baud Rate Generator Control Register"
|
|
bitfld.long 0x00 4.--7. "BRCK,BRCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "BRS,BRS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
rbitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FMTR1,TSPI Format Control Register 1"
|
|
bitfld.long 0x00 4.--6. "EHOLD,EHOLD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "VPE,VPE" "0,1"
|
|
bitfld.long 0x00 0. "VPM,VPM" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DR,TSPI Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSPIDR,TSPIDR"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SR,TSPI Status Register"
|
|
rbitfld.long 0x00 31. "TSPISUE,TSPISUE" "0,1"
|
|
rbitfld.long 0x00 23. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 22. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 21. "INTTXWF,INTTXWF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "TFEMP,TFEMP" "0,1"
|
|
rbitfld.long 0x00 16.--19. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFF,INTRXFF" "0,1"
|
|
rbitfld.long 0x00 4. "RFFLL,RFFLL" "0,1"
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
repeat 2. (list 7. 8.) (list ad:0x400CBC00 ad:0x400CC000)
|
|
tree "TSPI$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TSPI Control Register 0"
|
|
bitfld.long 0x00 6.--7. "SWRST,SWRST" "0,1,2,3"
|
|
bitfld.long 0x00 0. "TSPIE,TSPIE" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TSPI Control Register 3"
|
|
bitfld.long 0x00 1. "TFEMPCLR,TFEMPCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFFLLCLR,RFFLLCLR" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BR,TSPI Baud Rate Generator Control Register"
|
|
bitfld.long 0x00 4.--7. "BRCK,BRCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "BRS,BRS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
rbitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FMTR1,TSPI Format Control Register 1"
|
|
bitfld.long 0x00 4.--6. "EHOLD,EHOLD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "VPE,VPE" "0,1"
|
|
bitfld.long 0x00 0. "VPM,VPM" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DR,TSPI Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSPIDR,TSPIDR"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SR,TSPI Status Register"
|
|
rbitfld.long 0x00 31. "TSPISUE,TSPISUE" "0,1"
|
|
rbitfld.long 0x00 23. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 22. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 21. "INTTXWF,INTTXWF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "TFEMP,TFEMP" "0,1"
|
|
rbitfld.long 0x00 16.--19. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFF,INTRXFF" "0,1"
|
|
rbitfld.long 0x00 4. "RFFLL,RFFLL" "0,1"
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
tree "EXB (External Bus Interface(EXB))"
|
|
base ad:0x40076000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,External Bus Mode Control Register"
|
|
bitfld.long 0x00 1.--2. "EXBWAIT,EXBWAIT" "0,1,2,3"
|
|
bitfld.long 0x00 0. "EXBSEL,EXBSEL" "0,1"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "AS$1,External Bus Base Address and CS Space setting Register $1"
|
|
hexmask.long.word 0x00 16.--31. 1. "SA,SA"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EXAR,EXAR"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "CS$1,Chip Select and Wait Controller Register $1"
|
|
bitfld.long 0x00 30.--31. "CSR,CSR" "0,1,2,3"
|
|
bitfld.long 0x00 27.--29. "WRR,WRR" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "RDR,RDR" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--21. "ALEW,ALEW" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "WRS,WRS" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "RDS,RDS" "0,1,2,3"
|
|
bitfld.long 0x00 13. "WSEL,WSEL" "0,1"
|
|
bitfld.long 0x00 12. "WAIT,WAIT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "CSIW,CSIW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--2. "CSW,CSW" "0,1,2,3"
|
|
bitfld.long 0x00 0. "CSW0,CSW0" "0,1"
|
|
repeat.end
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CLKCTL,Clock output controlRegister"
|
|
bitfld.long 0x00 1.--2. "CLKDIV,CLKDIV" "0,1,2,3"
|
|
bitfld.long 0x00 0. "CLKEN,CLKEN" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "CG (Clock Generator (CG))"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40083000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PROTECT,Protect Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PROTECT,PROTECT"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OSCCR,Oscillation Control Register"
|
|
rbitfld.long 0x00 16. "IHOSC1F,IHOSC1F" "0,1"
|
|
rbitfld.long 0x00 9. "OSCF,OSCF" "0,1"
|
|
bitfld.long 0x00 8. "OSCSEL,OSCSEL" "0,1"
|
|
rbitfld.long 0x00 1.--2. "EOSCEN,EOSCEN" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "IHOSC1N,IHOSC1N" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OSCCR,Oscillation Control Register"
|
|
rbitfld.long 0x00 16. "IHOSC1F,IHOSC1F" "0,1"
|
|
rbitfld.long 0x00 9. "OSCF,OSCF" "0,1"
|
|
bitfld.long 0x00 8. "OSCSEL,OSCSEL" "0,1"
|
|
bitfld.long 0x00 3. "IHOSC2EN,IHOSC2EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "EOSCEN,EOSCEN" "0,1,2,3"
|
|
bitfld.long 0x00 0. "IHOSC1EN,IHOSC1EN" "0,1"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SYSCR,System Clock Control Register"
|
|
rbitfld.long 0x00 24.--27. "PRCKST,PRCKST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 16.--18. "GEARST,GEARST" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "PRCK,PRCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "GEAR,GEAR" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "STBYCR,Standby Control Register"
|
|
bitfld.long 0x00 0.--1. "STBY,STBY" "0,1,2,3"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "OCR,SCOUT Output Control Register"
|
|
bitfld.long 0x00 4.--6. "SCODIV,SCODIV" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1.--3. "SCOSEL,SCOSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "SCOEN,SCOEN" "0,1"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PLL0SEL,PLL Selection Register 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "PLL0SET,PLL0SET"
|
|
rbitfld.long 0x00 2. "PLL0ST,PLL0ST" "0,1"
|
|
bitfld.long 0x00 1. "PLL0SEL,PLL0SEL" "0,1"
|
|
bitfld.long 0x00 0. "PLL0ON,PLL0ON" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "WUPHCR,High OSC Warming-up Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "WUPT,WUPT"
|
|
bitfld.long 0x00 8. "WUCLK,WUCLK" "0,1"
|
|
rbitfld.long 0x00 1. "WUEF,WUEF" "0,1"
|
|
bitfld.long 0x00 0. "WUON,WUON" "0,1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "WUPLCR,Low OSC Warming-up Register"
|
|
hexmask.long.tbyte 0x00 8.--26. 1. "WUPTL,WUPTL"
|
|
rbitfld.long 0x00 1. "WULEF,WULEF" "0,1"
|
|
bitfld.long 0x00 0. "WULON,WULON" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FSYSMENA,Middle fsys Supply Stop Register A"
|
|
bitfld.long 0x00 31. "IPMENA31,IPMENA31" "0,1"
|
|
bitfld.long 0x00 30. "IPMENA30,IPMENA30" "0,1"
|
|
bitfld.long 0x00 29. "IPMENA29,IPMENA29" "0,1"
|
|
bitfld.long 0x00 28. "IPMENA28,IPMENA28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "IPMENA27,IPMENA27" "0,1"
|
|
bitfld.long 0x00 26. "IPMENA26,IPMENA26" "0,1"
|
|
bitfld.long 0x00 25. "IPMENA25,IPMENA25" "0,1"
|
|
bitfld.long 0x00 24. "IPMENA24,IPMENA24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "IPMENA23,IPMENA23" "0,1"
|
|
bitfld.long 0x00 22. "IPMENA22,IPMENA22" "0,1"
|
|
bitfld.long 0x00 21. "IPMENA21,IPMENA21" "0,1"
|
|
bitfld.long 0x00 20. "IPMENA20,IPMENA20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "IPMENA19,IPMENA19" "0,1"
|
|
bitfld.long 0x00 18. "IPMENA18,IPMENA18" "0,1"
|
|
bitfld.long 0x00 17. "IPMENA17,IPMENA17" "0,1"
|
|
bitfld.long 0x00 16. "IPMENA16,IPMENA16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IPMENA15,IPMENA15" "0,1"
|
|
bitfld.long 0x00 14. "IPMENA14,IPMENA14" "0,1"
|
|
bitfld.long 0x00 13. "IPMENA13,IPMENA13" "0,1"
|
|
bitfld.long 0x00 12. "IPMENA12,IPMENA12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IPMENA11,IPMENA11" "0,1"
|
|
bitfld.long 0x00 10. "IPMENA10,IPMENA10" "0,1"
|
|
bitfld.long 0x00 9. "IPMENA09,IPMENA09" "0,1"
|
|
bitfld.long 0x00 8. "IPMENA08,IPMENA08" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IPMENA07,IPMENA07" "0,1"
|
|
bitfld.long 0x00 6. "IPMENA06,IPMENA06" "0,1"
|
|
bitfld.long 0x00 5. "IPMENA05,IPMENA05" "0,1"
|
|
bitfld.long 0x00 4. "IPMENA04,IPMENA04" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IPMENA03,IPMENA03" "0,1"
|
|
bitfld.long 0x00 2. "IPMENA02,IPMENA02" "0,1"
|
|
bitfld.long 0x00 1. "IPMENA01,IPMENA01" "0,1"
|
|
bitfld.long 0x00 0. "IPMENA00,IPMENA00" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FSYSMENB,Middle fsys Supply Stop Register A"
|
|
bitfld.long 0x00 31. "IPMENB31,IPMENB31" "0,1"
|
|
bitfld.long 0x00 30. "IPMENB30,IPMENB30" "0,1"
|
|
bitfld.long 0x00 29. "IPMENB29,IPMENB29" "0,1"
|
|
bitfld.long 0x00 28. "IPMENB28,IPMENB28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "IPMENB27,IPMENB27" "0,1"
|
|
bitfld.long 0x00 26. "IPMENB26,IPMENB26" "0,1"
|
|
bitfld.long 0x00 25. "IPMENB25,IPMENB25" "0,1"
|
|
bitfld.long 0x00 24. "IPMENB24,IPMENB24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "IPMENB23,IPMENB23" "0,1"
|
|
bitfld.long 0x00 22. "IPMENB22,IPMENB22" "0,1"
|
|
bitfld.long 0x00 21. "IPMENB21,IPMENB21" "0,1"
|
|
bitfld.long 0x00 20. "IPMENB20,IPMENB20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "IPMENB19,IPMENB19" "0,1"
|
|
bitfld.long 0x00 18. "IPMENB18,IPMENB18" "0,1"
|
|
bitfld.long 0x00 17. "IPMENB17,IPMENB17" "0,1"
|
|
bitfld.long 0x00 16. "IPMENB16,IPMENB16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IPMENB15,IPMENB15" "0,1"
|
|
bitfld.long 0x00 14. "IPMENB14,IPMENB14" "0,1"
|
|
bitfld.long 0x00 13. "IPMENB13,IPMENB13" "0,1"
|
|
bitfld.long 0x00 12. "IPMENB12,IPMENB12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IPMENB11,IPMENB11" "0,1"
|
|
bitfld.long 0x00 10. "IPMENB10,IPMENB10" "0,1"
|
|
bitfld.long 0x00 9. "IPMENB09,IPMENB09" "0,1"
|
|
bitfld.long 0x00 8. "IPMENB08,IPMENB08" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IPMENB07,IPMENB07" "0,1"
|
|
bitfld.long 0x00 6. "IPMENB06,IPMENB06" "0,1"
|
|
bitfld.long 0x00 5. "IPMENB05,IPMENB05" "0,1"
|
|
bitfld.long 0x00 4. "IPMENB04,IPMENB04" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IPMENB03,IPMENB03" "0,1"
|
|
bitfld.long 0x00 2. "IPMENB02,IPMENB02" "0,1"
|
|
bitfld.long 0x00 1. "IPMENB01,IPMENB01" "0,1"
|
|
bitfld.long 0x00 0. "IPMENB00,IPMENB00" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FSYSENA,High fsys Supply Stop Register A"
|
|
bitfld.long 0x00 9. "IPENA09,IPENA09" "0,1"
|
|
bitfld.long 0x00 8. "IPENA08,IPENA08" "0,1"
|
|
bitfld.long 0x00 7. "IPENA07,IPENA07" "0,1"
|
|
bitfld.long 0x00 6. "IPENA06,IPENA06" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IPENA05,IPENA05" "0,1"
|
|
bitfld.long 0x00 4. "IPENA04,IPENA04" "0,1"
|
|
bitfld.long 0x00 3. "IPENA03,IPENA03" "0,1"
|
|
bitfld.long 0x00 2. "IPENA02,IPENA02" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IPENA01,IPENA01" "0,1"
|
|
bitfld.long 0x00 0. "IPENA00,IPENA00" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FSYSENA,High fsys Supply Stop Register A"
|
|
bitfld.long 0x00 31. "IPENA31,IPENA31" "0,1"
|
|
bitfld.long 0x00 30. "IPENA30,IPENA30" "0,1"
|
|
bitfld.long 0x00 29. "IPENA29,IPENA29" "0,1"
|
|
bitfld.long 0x00 28. "IPENA28,IPENA28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "IPENA27,IPENA27" "0,1"
|
|
bitfld.long 0x00 26. "IPENA26,IPENA26" "0,1"
|
|
bitfld.long 0x00 25. "IPENA25,IPENA25" "0,1"
|
|
bitfld.long 0x00 24. "IPENA24,IPENA24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "IPENA23,IPENA23" "0,1"
|
|
bitfld.long 0x00 22. "IPENA22,IPENA22" "0,1"
|
|
bitfld.long 0x00 21. "IPENA21,IPENA21" "0,1"
|
|
bitfld.long 0x00 20. "IPENA20,IPENA20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "IPENA19,IPENA19" "0,1"
|
|
bitfld.long 0x00 18. "IPENA18,IPENA18" "0,1"
|
|
bitfld.long 0x00 17. "IPENA17,IPENA17" "0,1"
|
|
bitfld.long 0x00 16. "IPENA16,IPENA16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IPENA15,IPENA15" "0,1"
|
|
bitfld.long 0x00 14. "IPENA14,IPENA14" "0,1"
|
|
bitfld.long 0x00 13. "IPENA13,IPENA13" "0,1"
|
|
bitfld.long 0x00 12. "IPENA12,IPENA12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IPENA11,IPENA11" "0,1"
|
|
bitfld.long 0x00 10. "IPENA10,IPENA10" "0,1"
|
|
bitfld.long 0x00 9. "IPENA09,IPENA09" "0,1"
|
|
bitfld.long 0x00 8. "IPENA08,IPENA08" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IPENA07,IPENA07" "0,1"
|
|
bitfld.long 0x00 6. "IPENA06,IPENA06" "0,1"
|
|
bitfld.long 0x00 5. "IPENA05,IPENA05" "0,1"
|
|
bitfld.long 0x00 4. "IPENA04,IPENA04" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IPENA03,IPENA03" "0,1"
|
|
bitfld.long 0x00 2. "IPENA02,IPENA02" "0,1"
|
|
bitfld.long 0x00 1. "IPENA01,IPENA01" "0,1"
|
|
bitfld.long 0x00 0. "IPENA00,IPENA00" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCEN,FC Supply Stop Register"
|
|
bitfld.long 0x00 1. "FCIPEN01,FCIPEN01" "0,1"
|
|
bitfld.long 0x00 0. "FCIPEN00,FCIPEN00" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SPCLKEN,ADC TRACE Clock Supply Stop Register"
|
|
bitfld.long 0x00 16. "ADCKEN0,ADCKEN0" "0,1"
|
|
bitfld.long 0x00 0. "TRCKEN,TRCKEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SPCLKEN,ADC TRACE Clock Supply Stop Register"
|
|
bitfld.long 0x00 16. "ADCKEN,ADCKEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "EXTEND2,Extend for MDMAC Register"
|
|
bitfld.long 0x00 2. "REV22,REV22" "0,1"
|
|
bitfld.long 0x00 1. "REV21,REV21" "0,1"
|
|
bitfld.long 0x00 0. "REV20,REV20" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400F3000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PROTECT,CG Protect Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PROTECT,PROTECT"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OSCCR,CG Oscillation Control Register"
|
|
rbitfld.long 0x00 19. "IHOSC2F,IHOSC2F" "0,1"
|
|
rbitfld.long 0x00 16. "IHOSC1F,IHOSC1F" "0,1"
|
|
rbitfld.long 0x00 9. "OSCF,OSCF" "0,1"
|
|
bitfld.long 0x00 8. "OSCSEL,OSCSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IHOSC2EN,IHOSC2EN" "0,1"
|
|
bitfld.long 0x00 1.--2. "EOSCEN,EOSCEN" "0,1,2,3"
|
|
bitfld.long 0x00 0. "IHOSC1EN,IHOSC1EN" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SYSCR,CG System clock control register"
|
|
rbitfld.long 0x00 24.--27. "PRCKST,PRCKST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 16.--18. "GEARST,GEARST" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "PRCK,PRCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "GEAR,GEAR" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "STBYCR,CG Standby Control Register"
|
|
bitfld.long 0x00 0.--1. "STBY,STBY" "0,1,2,3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SCOCR,CG SCOUT Control Register"
|
|
bitfld.long 0x00 4.--6. "SCODIV,SCODIV" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1.--3. "SCOSEL,SCOSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "SCOEN,SCOEN" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PLL0SEL,CG PLL select register for fsys"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "PLL0SET,PLL0SET"
|
|
rbitfld.long 0x00 2. "PLL0ST,PLL0ST" "0,1"
|
|
bitfld.long 0x00 1. "PLL0SEL,PLL0SEL" "0,1"
|
|
bitfld.long 0x00 0. "PLL0ON,PLL0ON" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PLL1SEL,CG PLL select register for ADCLK"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "PLL1SET,PLL1SET"
|
|
bitfld.long 0x00 1. "PLL1SEL,PLL1SEL" "0,1"
|
|
bitfld.long 0x00 0. "PLL1ON,PLL1ON" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "WUPHCR,CG Warmup register for HOSC"
|
|
hexmask.long.word 0x00 16.--31. 1. "WUPT,WUPT"
|
|
bitfld.long 0x00 8. "WUCLK,WUCLK" "0,1"
|
|
rbitfld.long 0x00 1. "WUEF,WUEF" "0,1"
|
|
bitfld.long 0x00 0. "WUON,WUON" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FSYSENA,CG output control register A for fsys clock"
|
|
bitfld.long 0x00 31. "IPENA31,IPENA31" "0,1"
|
|
bitfld.long 0x00 30. "IPENA30,IPENA30" "0,1"
|
|
bitfld.long 0x00 29. "IPENA29,IPENA29" "0,1"
|
|
bitfld.long 0x00 28. "IPENA28,IPENA28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "IPENA27,IPENA27" "0,1"
|
|
bitfld.long 0x00 26. "IPENA26,IPENA26" "0,1"
|
|
bitfld.long 0x00 25. "IPENA25,IPENA25" "0,1"
|
|
bitfld.long 0x00 24. "IPENA24,IPENA24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "IPENA23,IPENA23" "0,1"
|
|
bitfld.long 0x00 22. "IPENA22,IPENA22" "0,1"
|
|
bitfld.long 0x00 21. "IPENA21,IPENA21" "0,1"
|
|
bitfld.long 0x00 20. "IPENA20,IPENA20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "IPENA19,IPENA19" "0,1"
|
|
bitfld.long 0x00 18. "IPENA18,IPENA18" "0,1"
|
|
bitfld.long 0x00 17. "IPENA17,IPENA17" "0,1"
|
|
bitfld.long 0x00 16. "IPENA16,IPENA16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IPENA15,IPENA15" "0,1"
|
|
bitfld.long 0x00 14. "IPENA14,IPENA14" "0,1"
|
|
bitfld.long 0x00 13. "IPENA13,IPENA13" "0,1"
|
|
bitfld.long 0x00 12. "IPENA12,IPENA12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IPENA11,IPENA11" "0,1"
|
|
bitfld.long 0x00 10. "IPENA10,IPENA10" "0,1"
|
|
bitfld.long 0x00 9. "IPENA09,IPENA09" "0,1"
|
|
bitfld.long 0x00 8. "IPENA08,IPENA08" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IPENA07,IPENA07" "0,1"
|
|
bitfld.long 0x00 6. "IPENA06,IPENA06" "0,1"
|
|
bitfld.long 0x00 5. "IPENA05,IPENA05" "0,1"
|
|
bitfld.long 0x00 4. "IPENA04,IPENA04" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IPENA03,IPENA03" "0,1"
|
|
bitfld.long 0x00 2. "IPENA02,IPENA02" "0,1"
|
|
bitfld.long 0x00 1. "IPENA01,IPENA01" "0,1"
|
|
bitfld.long 0x00 0. "IPENA00,IPENA00" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FSYSENB,CG output control register B for fsys clock"
|
|
bitfld.long 0x00 31. "IPENB31,IPENB31" "0,1"
|
|
bitfld.long 0x00 30. "IPENB30,IPENB30" "0,1"
|
|
bitfld.long 0x00 29. "IPENB29,IPENB29" "0,1"
|
|
bitfld.long 0x00 28. "IPENB28,IPENB28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "IPENB27,IPENB27" "0,1"
|
|
bitfld.long 0x00 26. "IPENB26,IPENB26" "0,1"
|
|
bitfld.long 0x00 25. "IPENB25,IPENB25" "0,1"
|
|
bitfld.long 0x00 24. "IPENB24,IPENB24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "IPENB23,IPENB23" "0,1"
|
|
bitfld.long 0x00 22. "IPENB22,IPENB22" "0,1"
|
|
bitfld.long 0x00 21. "IPENB21,IPENB21" "0,1"
|
|
bitfld.long 0x00 20. "IPENB20,IPENB20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "IPENB19,IPENB19" "0,1"
|
|
bitfld.long 0x00 18. "IPENB18,IPENB18" "0,1"
|
|
bitfld.long 0x00 17. "IPENB17,IPENB17" "0,1"
|
|
bitfld.long 0x00 16. "IPENB16,IPENB16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IPENB15,IPENB15" "0,1"
|
|
bitfld.long 0x00 14. "IPENB14,IPENB14" "0,1"
|
|
bitfld.long 0x00 13. "IPENB13,IPENB13" "0,1"
|
|
bitfld.long 0x00 12. "IPENB12,IPENB12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IPENB11,IPENB11" "0,1"
|
|
bitfld.long 0x00 10. "IPENB10,IPENB10" "0,1"
|
|
bitfld.long 0x00 9. "IPENB09,IPENB09" "0,1"
|
|
bitfld.long 0x00 8. "IPENB08,IPENB08" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IPENB07,IPENB07" "0,1"
|
|
bitfld.long 0x00 6. "IPENB06,IPENB06" "0,1"
|
|
bitfld.long 0x00 5. "IPENB05,IPENB05" "0,1"
|
|
bitfld.long 0x00 4. "IPENB04,IPENB04" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IPENB03,IPENB03" "0,1"
|
|
bitfld.long 0x00 2. "IPENB02,IPENB02" "0,1"
|
|
bitfld.long 0x00 1. "IPENB01,IPENB01" "0,1"
|
|
bitfld.long 0x00 0. "IPENB00,IPENB00" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCEN,CG output control register for fc clock"
|
|
bitfld.long 0x00 7. "DNFCKEN,DNFCKEN" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SPCLKEN,CG Output control register for ADC AND TRACE CLOCK"
|
|
bitfld.long 0x00 16. "ADCKEN,ADCKEN" "0,1"
|
|
bitfld.long 0x00 0. "TRCKEN,TRCKEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x40083000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PROTECT,Protect Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PROTECT,PROTECT"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OSCCR,Oscillation Control Register"
|
|
rbitfld.long 0x00 19. "IHOSC2F,IHOSC2F" "0,1"
|
|
rbitfld.long 0x00 16. "IHOSC1F,IHOSC1F" "0,1"
|
|
rbitfld.long 0x00 9. "OSCF,OSCF" "0,1"
|
|
bitfld.long 0x00 8. "OSCSEL,OSCSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "EOSCEN,EOSCEN" "0,1,2,3"
|
|
bitfld.long 0x00 0. "IHOSC1EN,IHOSC1EN" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SYSCR,System Clock Control Register"
|
|
rbitfld.long 0x00 24.--27. "PRCKST,PRCKST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 22.--23. "MCKSELGST,MCKSELGST" "0,1,2,3"
|
|
rbitfld.long 0x00 16.--18. "GEARST,GEARST" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "PRCK,PRCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "MCKSEL,MCKSEL" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "GEAR,GEAR" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "STBYCR,Standby Control Register"
|
|
bitfld.long 0x00 0.--1. "STBY,STBY" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PLL0SEL,PLL Selection Register 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "PLL0SET,PLL0SET"
|
|
rbitfld.long 0x00 2. "PLL0ST,PLL0ST" "0,1"
|
|
bitfld.long 0x00 1. "PLL0SEL,PLL0SEL" "0,1"
|
|
bitfld.long 0x00 0. "PLL0ON,PLL0ON" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "WUPHCR,High speed OSC Warming-up Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "WUPT,WUPT"
|
|
bitfld.long 0x00 8. "WUCLK,WUCLK" "0,1"
|
|
rbitfld.long 0x00 1. "WUEF,WUEF" "0,1"
|
|
bitfld.long 0x00 0. "WUON,WUON" "0,1"
|
|
sif cpuis("TMPM4KP*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FSYSMENA,Middle fsys Supply Stop Register A"
|
|
bitfld.long 0x00 31. "IPMENA31,IPMENA31" "0,1"
|
|
bitfld.long 0x00 30. "IPMENA30,IPMENA30" "0,1"
|
|
bitfld.long 0x00 29. "IPMENA29,IPMENA29" "0,1"
|
|
bitfld.long 0x00 28. "IPMENA28,IPMENA28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "IPMENA27,IPMENA27" "0,1"
|
|
bitfld.long 0x00 26. "IPMENA26,IPMENA26" "0,1"
|
|
bitfld.long 0x00 25. "IPMENA25,IPMENA25" "0,1"
|
|
bitfld.long 0x00 24. "IPMENA24,IPMENA24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "IPMENA23,IPMENA23" "0,1"
|
|
bitfld.long 0x00 22. "IPMENA22,IPMENA22" "0,1"
|
|
bitfld.long 0x00 21. "IPMENA21,IPMENA21" "0,1"
|
|
bitfld.long 0x00 20. "IPMENA20,IPMENA20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "IPMENA19,IPMENA19" "0,1"
|
|
bitfld.long 0x00 17. "IPMENA17,IPMENA17" "0,1"
|
|
bitfld.long 0x00 16. "IPMENA16,IPMENA16" "0,1"
|
|
bitfld.long 0x00 15. "IPMENA15,IPMENA15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "IPMENA13,IPMENA13" "0,1"
|
|
bitfld.long 0x00 12. "IPMENA12,IPMENA12" "0,1"
|
|
bitfld.long 0x00 11. "IPMENA11,IPMENA11" "0,1"
|
|
bitfld.long 0x00 10. "IPMENA10,IPMENA10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "IPMENA09,IPMENA09" "0,1"
|
|
bitfld.long 0x00 8. "IPMENA08,IPMENA08" "0,1"
|
|
bitfld.long 0x00 7. "IPMENA07,IPMENA07" "0,1"
|
|
bitfld.long 0x00 6. "IPMENA06,IPMENA06" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IPMENA05,IPMENA05" "0,1"
|
|
bitfld.long 0x00 4. "IPMENA04,IPMENA04" "0,1"
|
|
bitfld.long 0x00 3. "IPMENA03,IPMENA03" "0,1"
|
|
bitfld.long 0x00 2. "IPMENA02,IPMENA02" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IPMENA01,IPMENA01" "0,1"
|
|
bitfld.long 0x00 0. "IPMENA00,IPMENA00" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FSYSMENA,Middle fsys Supply Stop Register A"
|
|
bitfld.long 0x00 31. "IPMENA31,IPMENA31" "0,1"
|
|
bitfld.long 0x00 30. "IPMENA30,IPMENA30" "0,1"
|
|
bitfld.long 0x00 29. "IPMENA29,IPMENA29" "0,1"
|
|
bitfld.long 0x00 28. "IPMENA28,IPMENA28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "IPMENA27,IPMENA27" "0,1"
|
|
bitfld.long 0x00 26. "IPMENA26,IPMENA26" "0,1"
|
|
bitfld.long 0x00 25. "IPMENA25,IPMENA25" "0,1"
|
|
bitfld.long 0x00 23. "IPMENA23,IPMENA23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "IPMENA22,IPMENA22" "0,1"
|
|
bitfld.long 0x00 21. "IPMENA21,IPMENA21" "0,1"
|
|
bitfld.long 0x00 20. "IPMENA20,IPMENA20" "0,1"
|
|
bitfld.long 0x00 19. "IPMENA19,IPMENA19" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "IPMENA16,IPMENA16" "0,1"
|
|
bitfld.long 0x00 10. "IPMENA10,IPMENA10" "0,1"
|
|
bitfld.long 0x00 9. "IPMENA09,IPMENA09" "0,1"
|
|
bitfld.long 0x00 8. "IPMENA08,IPMENA08" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IPMENA07,IPMENA07" "0,1"
|
|
bitfld.long 0x00 6. "IPMENA06,IPMENA06" "0,1"
|
|
bitfld.long 0x00 5. "IPMENA05,IPMENA05" "0,1"
|
|
bitfld.long 0x00 4. "IPMENA04,IPMENA04" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "IPMENA02,IPMENA02" "0,1"
|
|
bitfld.long 0x00 1. "IPMENA01,IPMENA01" "0,1"
|
|
bitfld.long 0x00 0. "IPMENA00,IPMENA00" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FSYSMENA,Middle fsys Supply Stop Register A"
|
|
bitfld.long 0x00 31. "IPMENA31,IPMENA31" "0,1"
|
|
bitfld.long 0x00 30. "IPMENA30,IPMENA30" "0,1"
|
|
bitfld.long 0x00 29. "IPMENA29,IPMENA29" "0,1"
|
|
bitfld.long 0x00 28. "IPMENA28,IPMENA28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "IPMENA27,IPMENA27" "0,1"
|
|
bitfld.long 0x00 26. "IPMENA26,IPMENA26" "0,1"
|
|
bitfld.long 0x00 25. "IPMENA25,IPMENA25" "0,1"
|
|
bitfld.long 0x00 24. "IPMENA24,IPMENA24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "IPMENA23,IPMENA23" "0,1"
|
|
bitfld.long 0x00 22. "IPMENA22,IPMENA22" "0,1"
|
|
bitfld.long 0x00 21. "IPMENA21,IPMENA21" "0,1"
|
|
bitfld.long 0x00 20. "IPMENA20,IPMENA20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "IPMENA19,IPMENA19" "0,1"
|
|
bitfld.long 0x00 17. "IPMENA17,IPMENA17" "0,1"
|
|
bitfld.long 0x00 16. "IPMENA16,IPMENA16" "0,1"
|
|
bitfld.long 0x00 12. "IPMENA12,IPMENA12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IPMENA11,IPMENA11" "0,1"
|
|
bitfld.long 0x00 10. "IPMENA10,IPMENA10" "0,1"
|
|
bitfld.long 0x00 9. "IPMENA09,IPMENA09" "0,1"
|
|
bitfld.long 0x00 8. "IPMENA08,IPMENA08" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IPMENA07,IPMENA07" "0,1"
|
|
bitfld.long 0x00 6. "IPMENA06,IPMENA06" "0,1"
|
|
bitfld.long 0x00 5. "IPMENA05,IPMENA05" "0,1"
|
|
bitfld.long 0x00 4. "IPMENA04,IPMENA04" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IPMENA03,IPMENA03" "0,1"
|
|
bitfld.long 0x00 2. "IPMENA02,IPMENA02" "0,1"
|
|
bitfld.long 0x00 1. "IPMENA01,IPMENA01" "0,1"
|
|
bitfld.long 0x00 0. "IPMENA00,IPMENA00" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KQ*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FSYSMENA,Middle fsys Supply Stop Register A"
|
|
bitfld.long 0x00 31. "IPMENA31,IPMENA31" "0,1"
|
|
bitfld.long 0x00 30. "IPMENA30,IPMENA30" "0,1"
|
|
bitfld.long 0x00 29. "IPMENA29,IPMENA29" "0,1"
|
|
bitfld.long 0x00 28. "IPMENA28,IPMENA28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "IPMENA27,IPMENA27" "0,1"
|
|
bitfld.long 0x00 26. "IPMENA26,IPMENA26" "0,1"
|
|
bitfld.long 0x00 25. "IPMENA25,IPMENA25" "0,1"
|
|
bitfld.long 0x00 24. "IPMENA24,IPMENA24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "IPMENA23,IPMENA23" "0,1"
|
|
bitfld.long 0x00 22. "IPMENA22,IPMENA22" "0,1"
|
|
bitfld.long 0x00 21. "IPMENA21,IPMENA21" "0,1"
|
|
bitfld.long 0x00 20. "IPMENA20,IPMENA20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "IPMENA19,IPMENA19" "0,1"
|
|
bitfld.long 0x00 18. "IPMENA18,IPMENA18" "0,1"
|
|
bitfld.long 0x00 17. "IPMENA17,IPMENA17" "0,1"
|
|
bitfld.long 0x00 16. "IPMENA16,IPMENA16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IPMENA15,IPMENA15" "0,1"
|
|
bitfld.long 0x00 14. "IPMENA14,IPMENA14" "0,1"
|
|
bitfld.long 0x00 13. "IPMENA13,IPMENA13" "0,1"
|
|
bitfld.long 0x00 12. "IPMENA12,IPMENA12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IPMENA11,IPMENA11" "0,1"
|
|
bitfld.long 0x00 10. "IPMENA10,IPMENA10" "0,1"
|
|
bitfld.long 0x00 9. "IPMENA09,IPMENA09" "0,1"
|
|
bitfld.long 0x00 8. "IPMENA08,IPMENA08" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IPMENA07,IPMENA07" "0,1"
|
|
bitfld.long 0x00 6. "IPMENA06,IPMENA06" "0,1"
|
|
bitfld.long 0x00 5. "IPMENA05,IPMENA05" "0,1"
|
|
bitfld.long 0x00 4. "IPMENA04,IPMENA04" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IPMENA03,IPMENA03" "0,1"
|
|
bitfld.long 0x00 2. "IPMENA02,IPMENA02" "0,1"
|
|
bitfld.long 0x00 1. "IPMENA01,IPMENA01" "0,1"
|
|
bitfld.long 0x00 0. "IPMENA00,IPMENA00" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FSYSMENA,Middle fsys Supply Stop Register A"
|
|
bitfld.long 0x00 31. "IPMENA31,IPMENA31" "0,1"
|
|
bitfld.long 0x00 30. "IPMENA30,IPMENA30" "0,1"
|
|
bitfld.long 0x00 29. "IPMENA29,IPMENA29" "0,1"
|
|
bitfld.long 0x00 28. "IPMENA28,IPMENA28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "IPMENA27,IPMENA27" "0,1"
|
|
bitfld.long 0x00 26. "IPMENA26,IPMENA26" "0,1"
|
|
bitfld.long 0x00 25. "IPMENA25,IPMENA25" "0,1"
|
|
bitfld.long 0x00 24. "IPMENA24,IPMENA24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "IPMENA23,IPMENA23" "0,1"
|
|
bitfld.long 0x00 22. "IPMENA22,IPMENA22" "0,1"
|
|
bitfld.long 0x00 21. "IPMENA21,IPMENA21" "0,1"
|
|
bitfld.long 0x00 20. "IPMENA20,IPMENA20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "IPMENA19,IPMENA19" "0,1"
|
|
bitfld.long 0x00 16. "IPMENA16,IPMENA16" "0,1"
|
|
bitfld.long 0x00 12. "IPMENA12,IPMENA12" "0,1"
|
|
bitfld.long 0x00 10. "IPMENA10,IPMENA10" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "IPMENA09,IPMENA09" "0,1"
|
|
bitfld.long 0x00 8. "IPMENA08,IPMENA08" "0,1"
|
|
bitfld.long 0x00 7. "IPMENA07,IPMENA07" "0,1"
|
|
bitfld.long 0x00 6. "IPMENA06,IPMENA06" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IPMENA05,IPMENA05" "0,1"
|
|
bitfld.long 0x00 4. "IPMENA04,IPMENA04" "0,1"
|
|
bitfld.long 0x00 2. "IPMENA02,IPMENA02" "0,1"
|
|
bitfld.long 0x00 1. "IPMENA01,IPMENA01" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IPMENA00,IPMENA00" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FSYSMENB,Middle fsys Supply Stop Register B"
|
|
bitfld.long 0x00 31. "IPMENB31,IPMENB31" "0,1"
|
|
bitfld.long 0x00 29. "IPMENB29,IPMENB29" "0,1"
|
|
bitfld.long 0x00 17. "IPMENB17,IPMENB17" "0,1"
|
|
bitfld.long 0x00 16. "IPMENB16,IPMENB16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IPMENB15,IPMENB15" "0,1"
|
|
bitfld.long 0x00 14. "IPMENB14,IPMENB14" "0,1"
|
|
bitfld.long 0x00 13. "IPMENB13,IPMENB13" "0,1"
|
|
bitfld.long 0x00 12. "IPMENB12,IPMENB12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IPMENB11,IPMENB11" "0,1"
|
|
bitfld.long 0x00 10. "IPMENB10,IPMENB10" "0,1"
|
|
bitfld.long 0x00 9. "IPMENB09,IPMENB09" "0,1"
|
|
bitfld.long 0x00 8. "IPMENB08,IPMENB08" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IPMENB07,IPMENB07" "0,1"
|
|
bitfld.long 0x00 6. "IPMENB06,IPMENB06" "0,1"
|
|
bitfld.long 0x00 5. "IPMENB05,IPMENB05" "0,1"
|
|
bitfld.long 0x00 4. "IPMENB04,IPMENB04" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IPMENB03,IPMENB03" "0,1"
|
|
bitfld.long 0x00 2. "IPMENB02,IPMENB02" "0,1"
|
|
bitfld.long 0x00 1. "IPMENB01,IPMENB01" "0,1"
|
|
bitfld.long 0x00 0. "IPMENB00,IPMENB00" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FSYSMENB,Middle fsys Supply Stop Register B"
|
|
bitfld.long 0x00 31. "IPMENB31,IPMENB31" "0,1"
|
|
bitfld.long 0x00 29. "IPMENB29,IPMENB29" "0,1"
|
|
bitfld.long 0x00 17. "IPMENB17,IPMENB17" "0,1"
|
|
bitfld.long 0x00 16. "IPMENB16,IPMENB16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IPMENB15,IPMENB15" "0,1"
|
|
bitfld.long 0x00 14. "IPMENB14,IPMENB14" "0,1"
|
|
bitfld.long 0x00 13. "IPMENB13,IPMENB13" "0,1"
|
|
bitfld.long 0x00 12. "IPMENB12,IPMENB12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IPMENB11,IPMENB11" "0,1"
|
|
bitfld.long 0x00 10. "IPMENB10,IPMENB10" "0,1"
|
|
bitfld.long 0x00 9. "IPMENB09,IPMENB09" "0,1"
|
|
bitfld.long 0x00 8. "IPMENB08,IPMENB08" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IPMENB05,IPMENB05" "0,1"
|
|
bitfld.long 0x00 4. "IPMENB04,IPMENB04" "0,1"
|
|
bitfld.long 0x00 3. "IPMENB03,IPMENB03" "0,1"
|
|
bitfld.long 0x00 2. "IPMENB02,IPMENB02" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IPMENB01,IPMENB01" "0,1"
|
|
bitfld.long 0x00 0. "IPMENB00,IPMENB00" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FSYSMENB,Middle fsys Supply Stop Register B"
|
|
bitfld.long 0x00 31. "IPMENB31,IPMENB31" "0,1"
|
|
bitfld.long 0x00 30. "IPMENB30,IPMENB30" "0,1"
|
|
bitfld.long 0x00 29. "IPMENB29,IPMENB29" "0,1"
|
|
bitfld.long 0x00 17. "IPMENB17,IPMENB17" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "IPMENB16,IPMENB16" "0,1"
|
|
bitfld.long 0x00 15. "IPMENB15,IPMENB15" "0,1"
|
|
bitfld.long 0x00 14. "IPMENB14,IPMENB14" "0,1"
|
|
bitfld.long 0x00 13. "IPMENB13,IPMENB13" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "IPMENB12,IPMENB12" "0,1"
|
|
bitfld.long 0x00 11. "IPMENB11,IPMENB11" "0,1"
|
|
bitfld.long 0x00 10. "IPMENB10,IPMENB10" "0,1"
|
|
bitfld.long 0x00 9. "IPMENB09,IPMENB09" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "IPMENB08,IPMENB08" "0,1"
|
|
bitfld.long 0x00 7. "IPMENB07,IPMENB07" "0,1"
|
|
bitfld.long 0x00 6. "IPMENB06,IPMENB06" "0,1"
|
|
bitfld.long 0x00 5. "IPMENB05,IPMENB05" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "IPMENB04,IPMENB04" "0,1"
|
|
bitfld.long 0x00 3. "IPMENB03,IPMENB03" "0,1"
|
|
bitfld.long 0x00 2. "IPMENB02,IPMENB02" "0,1"
|
|
bitfld.long 0x00 1. "IPMENB01,IPMENB01" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IPMENB00,IPMENB00" "0,1"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FSYSENA,High fsys Supply Stop Register A"
|
|
bitfld.long 0x00 1. "IPENA01,IPENA01" "0,1"
|
|
bitfld.long 0x00 0. "IPENA00,IPENA00" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCEN,FC Supply Stop Register"
|
|
bitfld.long 0x00 28. "FCIPEN28,FCIPEN28" "0,1"
|
|
bitfld.long 0x00 27. "FCIPEN27,FCIPEN27" "0,1"
|
|
bitfld.long 0x00 26. "FCIPEN26,FCIPEN26" "0,1"
|
|
bitfld.long 0x00 23. "FCIPEN23,FCIPEN23" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SPCLKEN,ADC_TRACE Clock Supply Stop Register"
|
|
bitfld.long 0x00 19. "ADCKEN3,ADCKEN3" "0,1"
|
|
bitfld.long 0x00 18. "ADCKEN2,ADCKEN2" "0,1"
|
|
bitfld.long 0x00 17. "ADCKEN1,ADCKEN1" "0,1"
|
|
bitfld.long 0x00 16. "ADCKEN0,ADCKEN0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRCKEN,TRCKEN" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "IB (Interrupt Control B Register)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40083200
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "NIC00,Non maskable Interrupu Control Register 00"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
bitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "NIC00,Non maskable interrupt Control Register 00"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
group.byte 0x60++0x00
|
|
line.byte 0x00 "IMC000,interrupt Mode Control Register 000"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x60++0x00
|
|
line.byte 0x00 "IMC000,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x61++0x00
|
|
line.byte 0x00 "IMC001,interrupt Mode Control Register 001"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
rbitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x61++0x00
|
|
line.byte 0x00 "IMC001,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x62++0x00
|
|
line.byte 0x00 "IMC002,interrupt Mode Control Register 002"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
rbitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x62++0x00
|
|
line.byte 0x00 "IMC002,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x63++0x00
|
|
line.byte 0x00 "IMC003,interrupt Mode Control Register 003"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
rbitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x63++0x00
|
|
line.byte 0x00 "IMC003,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x64++0x00
|
|
line.byte 0x00 "IMC004,interrupt Mode Control Register 004"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
rbitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x64++0x00
|
|
line.byte 0x00 "IMC004,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x65++0x00
|
|
line.byte 0x00 "IMC005,interrupt Mode Control Register 005"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
rbitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 2. (strings "005" "006" )(list 0x0 0x1 )
|
|
group.byte ($2+0x65)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x66++0x00
|
|
line.byte 0x00 "IMC006,interrupt Mode Control Register 006"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
rbitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x67++0x00
|
|
line.byte 0x00 "IMC007,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.byte 0x67++0x00
|
|
line.byte 0x00 "IMC007,interrupt Mode Control Register 007"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
rbitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x68++0x00
|
|
line.byte 0x00 "IMC008,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x68++0x00
|
|
line.byte 0x00 "IMC008,interrupt Mode Control Register 008"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x69++0x00
|
|
line.byte 0x00 "IMC009,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x69++0x00
|
|
line.byte 0x00 "IMC009,interrupt Mode Control Register 009"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x6A++0x00
|
|
line.byte 0x00 "IMC010,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x6A++0x00
|
|
line.byte 0x00 "IMC010,interrupt Mode Control Register 010"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x6B++0x00
|
|
line.byte 0x00 "IMC011,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x6B++0x00
|
|
line.byte 0x00 "IMC011,interrupt Mode Control Register 011"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x6C++0x00
|
|
line.byte 0x00 "IMC012,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
repeat 2. (strings "012" "013" )(list 0x0 0x1 )
|
|
group.byte ($2+0x6C)++0x00
|
|
line.byte 0x00 "IMC$1,interrupt Mode Control Register $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 2. (strings "013" "014" )(list 0x0 0x1 )
|
|
group.byte ($2+0x6D)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
repeat 2. (strings "014" "015" )(list 0x0 0x1 )
|
|
group.byte ($2+0x6E)++0x00
|
|
line.byte 0x00 "IMC$1,interrupt Mode Control Register $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 2. (strings "015" "016" )(list 0x0 0x1 )
|
|
group.byte ($2+0x6F)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
repeat 2. (strings "016" "017" )(list 0x0 0x1 )
|
|
group.byte ($2+0x70)++0x00
|
|
line.byte 0x00 "IMC$1,interrupt Mode Control Register $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 2. (strings "017" "018" )(list 0x0 0x1 )
|
|
group.byte ($2+0x71)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x72++0x00
|
|
line.byte 0x00 "IMC018,interrupt Mode Control Register 018"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x73++0x00
|
|
line.byte 0x00 "IMC019,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
repeat 2. (strings "019" "020" )(list 0x0 0x1 )
|
|
group.byte ($2+0x73)++0x00
|
|
line.byte 0x00 "IMC$1,interrupt Mode Control Register $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 2. (strings "020" "021" )(list 0x0 0x1 )
|
|
group.byte ($2+0x74)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x75++0x00
|
|
line.byte 0x00 "IMC021,interrupt Mode Control Register 021"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x76++0x00
|
|
line.byte 0x00 "IMC022,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
repeat 2. (strings "022" "023" )(list 0x0 0x1 )
|
|
group.byte ($2+0x76)++0x00
|
|
line.byte 0x00 "IMC$1,interrupt Mode Control Register $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x77++0x00
|
|
line.byte 0x00 "IMC023,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x78++0x00
|
|
line.byte 0x00 "IMC024,interrupt Mode Control Register 024"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x78++0x00
|
|
line.byte 0x00 "IMC024,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x79++0x00
|
|
line.byte 0x00 "IMC025,interrupt Mode Control Register 025"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x79++0x00
|
|
line.byte 0x00 "IMC025,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x7A++0x00
|
|
line.byte 0x00 "IMC026,interrupt Mode Control Register 026"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 2. (strings "026" "027" )(list 0x0 0x1 )
|
|
group.byte ($2+0x7A)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
repeat 2. (strings "027" "028" )(list 0x0 0x1 )
|
|
group.byte ($2+0x7B)++0x00
|
|
line.byte 0x00 "IMC$1,interrupt Mode Control Register $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 2. (strings "028" "029" )(list 0x0 0x1 )
|
|
group.byte ($2+0x7C)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x7D++0x00
|
|
line.byte 0x00 "IMC029,interrupt Mode Control Register 029"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x7E++0x00
|
|
line.byte 0x00 "IMC030,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x7E++0x00
|
|
line.byte 0x00 "IMC030,interrupt Mode Control Register 030"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x7F++0x00
|
|
line.byte 0x00 "IMC031,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x7F++0x00
|
|
line.byte 0x00 "IMC031,interrupt Mode Control Register 031"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "IMC032,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
repeat 2. (strings "032" "033" )(list 0x0 0x1 )
|
|
group.byte ($2+0x80)++0x00
|
|
line.byte 0x00 "IMC$1,interrupt Mode Control Register $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x81++0x00
|
|
line.byte 0x00 "IMC033,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x82++0x00
|
|
line.byte 0x00 "IMC034,interrupt Mode Control Register 034"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x82++0x00
|
|
line.byte 0x00 "IMC034,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x83++0x00
|
|
line.byte 0x00 "IMC035,interrupt Mode Control Register 035"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 2. (strings "035" "036" )(list 0x0 0x1 )
|
|
group.byte ($2+0x83)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "IMC036,interrupt Mode Control Register 036"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x85++0x00
|
|
line.byte 0x00 "IMC037,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
repeat 2. (strings "037" "038" )(list 0x0 0x1 )
|
|
group.byte ($2+0x85)++0x00
|
|
line.byte 0x00 "IMC$1,interrupt Mode Control Register $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 2. (strings "038" "039" )(list 0x0 0x1 )
|
|
group.byte ($2+0x86)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x87++0x00
|
|
line.byte 0x00 "IMC039,interrupt Mode Control Register 039"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "IMC040,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "IMC040,interrupt Mode Control Register 040"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x89++0x00
|
|
line.byte 0x00 "IMC041,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.byte 0x89++0x00
|
|
line.byte 0x00 "IMC041,interrupt Mode Control Register 041"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.byte 0x8A++0x00
|
|
line.byte 0x00 "IMC042,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
repeat 2. (strings "042" "043" )(list 0x0 0x1 )
|
|
group.byte ($2+0x8A)++0x00
|
|
line.byte 0x00 "IMC$1,interrupt Mode Control Register $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 16. (strings "043" "044" "045" "046" "047" "048" "049" "050" "051" "052" "053" "054" "055" "056" "057" "058" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x8B)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
repeat 16. (strings "059" "060" "061" "062" "063" "064" "065" "066" "067" "068" "069" "070" "071" "072" "073" "074" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x9B)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
repeat 16. (strings "075" "076" "077" "078" "079" "080" "081" "082" "083" "084" "085" "086" "087" "088" "089" "090" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0xAB)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
repeat 16. (strings "091" "092" "093" "094" "095" "096" "097" "098" "099" "100" "101" "102" "103" "104" "105" "106" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0xBB)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
repeat 16. (strings "107" "108" "109" "110" "111" "112" "113" "114" "115" "116" "117" "118" "119" "120" "121" "122" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0xCB)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
repeat 16. (strings "123" "124" "125" "126" "127" "128" "129" "130" "131" "132" "133" "134" "135" "136" "137" "138" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0xDB)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
repeat 3. (strings "139" "140" "141" )(list 0x0 0x1 0x2 )
|
|
group.byte ($2+0xEB)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register 000"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400F4E00
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "NIC00,Non makeable Interrupt Control(B) 00"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
repeat 16. (strings "000" "001" "002" "003" "004" "005" "006" "007" "008" "009" "010" "011" "012" "013" "014" "015" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x60)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register(B $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
repeat.end
|
|
repeat 16. (strings "016" "017" "018" "019" "020" "021" "022" "023" "024" "025" "026" "027" "028" "029" "030" "031" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x70)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupu Mode Control Register(B $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
repeat.end
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "IMC032,Interrupu Mode Control Register(B) 032"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
repeat 8. (strings "033" "034" "035" "036" "037" "038" "039" "040" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )
|
|
group.byte ($2+0x81)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupt Mode Control Register(B $1"
|
|
sif cpuis("TMPM4K4A*")
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x40083200
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "NIC00,Non maskable Interrupt Control Register(B) 00"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
repeat 16. (strings "000" "001" "002" "003" "004" "005" "006" "007" "008" "009" "010" "011" "012" "013" "014" "015" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x60)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupt Mode Control Register(B $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
repeat.end
|
|
repeat 16. (strings "016" "017" "018" "019" "020" "021" "022" "023" "024" "025" "026" "027" "028" "029" "030" "031" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x70)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupt Mode Control Register(B $1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
repeat.end
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "IMC032,Interrupt Mode Control Register(B) 032"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
repeat 16. (strings "033" "034" "035" "036" "037" "038" "039" "040" "041" "042" "043" "044" "045" "046" "047" "048" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x81)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupt Mode Control Register(B $1"
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
repeat.end
|
|
repeat 16. (strings "049" "050" "051" "052" "053" "054" "055" "056" "057" "058" "059" "060" "061" "062" "063" "064" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x91)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupt Mode Control Register(B $1"
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
repeat.end
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
repeat 5. (strings "065" "066" "067" "068" "069" )(list 0x0 0x1 0x2 0x3 0x4 )
|
|
group.byte ($2+0xA1)++0x00
|
|
line.byte 0x00 "IMC$1,Interrupt Mode Control Register(B $1"
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
bitfld.byte 0x00 7. "INTNCLR,INTNCLR" "0,1"
|
|
bitfld.byte 0x00 6. "INTPCLR,INTPCLR" "0,1"
|
|
rbitfld.byte 0x00 5. "INTNFLG,INTNFLG" "0,1"
|
|
rbitfld.byte 0x00 4. "INTPFLG,INTPFLG" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1.--3. "INTMODE,INTMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "INTEN,INTEN" "0,1"
|
|
endif
|
|
repeat.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "IMN (Interrupt Monitor Register)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40083300
|
|
elif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400F4F00
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "FLGNMI,NMI Interrupt Monitor Flag 0"
|
|
bitfld.long 0x00 16. "INT016FLG,INT016FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT000FLG,INT000FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "FLGNMI,Interrupt Monitor Flag 0"
|
|
bitfld.long 0x00 16. "INT016FLG,INT016FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT000FLG,INT000FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FLG1,Interrupt Monitor Flag 1 (032 - 063)"
|
|
bitfld.long 0x00 31. "INT063FLG,INT063FLG" "0,1"
|
|
bitfld.long 0x00 30. "INT062FLG,INT062FLG" "0,1"
|
|
bitfld.long 0x00 29. "INT061FLG,INT061FLG" "0,1"
|
|
bitfld.long 0x00 28. "INT060FLG,INT060FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "INT059FLG,INT059FLG" "0,1"
|
|
bitfld.long 0x00 26. "INT058FLG,INT058FLG" "0,1"
|
|
bitfld.long 0x00 25. "INT057FLG,INT057FLG" "0,1"
|
|
bitfld.long 0x00 24. "INT056FLG,INT056FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "INT055FLG,INT055FLG" "0,1"
|
|
bitfld.long 0x00 22. "INT054FLG,INT054FLG" "0,1"
|
|
bitfld.long 0x00 21. "INT053FLG,INT053FLG" "0,1"
|
|
bitfld.long 0x00 20. "INT052FLG,INT052FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "INT051FLG,INT051FLG" "0,1"
|
|
bitfld.long 0x00 18. "INT050FLG,INT050FLG" "0,1"
|
|
bitfld.long 0x00 17. "INT049FLG,INT049FLG" "0,1"
|
|
bitfld.long 0x00 16. "INT048FLG,INT048FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "INT047FLG,INT047FLG" "0,1"
|
|
bitfld.long 0x00 14. "INT046FLG,INT046FLG" "0,1"
|
|
bitfld.long 0x00 13. "INT045FLG,INT045FLG" "0,1"
|
|
bitfld.long 0x00 12. "INT044FLG,INT044FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "INT043FLG,INT043FLG" "0,1"
|
|
bitfld.long 0x00 10. "INT042FLG,INT042FLG" "0,1"
|
|
bitfld.long 0x00 9. "INT041FLG,INT041FLG" "0,1"
|
|
bitfld.long 0x00 8. "INT040FLG,INT040FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "INT039FLG,INT039FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT038FLG,INT038FLG" "0,1"
|
|
bitfld.long 0x00 5. "INT037FLG,INT037FLG" "0,1"
|
|
bitfld.long 0x00 4. "INT036FLG,INT036FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INT035FLG,INT035FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT034FLG,INT034FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT033FLG,INT033FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT032FLG,INT032FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FLG1,Interrupt Monitor Flag 1"
|
|
bitfld.long 0x00 2. "INT034FLG,INT034FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT033FLG,INT033FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT032FLG,INT032FLG" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "FLG2,Interrupt Monitor Flag 2"
|
|
bitfld.long 0x00 3. "INT067FLG,INT067FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT066FLG,INT066FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT065FLG,INT065FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT064FLG,INT064FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "FLG2,Interrupt Monitor Flag 2 (064 - 095)"
|
|
bitfld.long 0x00 25. "INT089FLG,INT089FLG" "0,1"
|
|
bitfld.long 0x00 24. "INT088FLG,INT088FLG" "0,1"
|
|
bitfld.long 0x00 23. "INT087FLG,INT087FLG" "0,1"
|
|
bitfld.long 0x00 22. "INT086FLG,INT086FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "INT085FLG,INT085FLG" "0,1"
|
|
bitfld.long 0x00 20. "INT084FLG,INT084FLG" "0,1"
|
|
bitfld.long 0x00 19. "INT083FLG,INT083FLG" "0,1"
|
|
bitfld.long 0x00 18. "INT082FLG,INT082FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "INT081FLG,INT081FLG" "0,1"
|
|
bitfld.long 0x00 16. "INT080FLG,INT080FLG" "0,1"
|
|
bitfld.long 0x00 15. "INT079FLG,INT079FLG" "0,1"
|
|
bitfld.long 0x00 14. "INT078FLG,INT078FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "INT077FLG,INT077FLG" "0,1"
|
|
bitfld.long 0x00 12. "INT076FLG,INT076FLG" "0,1"
|
|
bitfld.long 0x00 11. "INT075FLG,INT075FLG" "0,1"
|
|
bitfld.long 0x00 10. "INT074FLG,INT074FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "INT073FLG,INT073FLG" "0,1"
|
|
bitfld.long 0x00 8. "INT072FLG,INT072FLG" "0,1"
|
|
bitfld.long 0x00 7. "INT071FLG,INT071FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT070FLG,INT070FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INT069FLG,INT069FLG" "0,1"
|
|
bitfld.long 0x00 4. "INT068FLG,INT068FLG" "0,1"
|
|
bitfld.long 0x00 3. "INT067FLG,INT067FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT066FLG,INT066FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "INT065FLG,INT065FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT064FLG,INT064FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
repeat 2. (strings "3" "3" )(list 0x0 0x0 )
|
|
rgroup.long ($2+0x0C)++0x03
|
|
line.long 0x00 "FLG$1,Interrupt Monitor Flag 3 (096 - 127)"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
bitfld.long 0x00 31. "INT127FLG,INT127FLG" "0,1"
|
|
bitfld.long 0x00 30. "INT126FLG,INT126FLG" "0,1"
|
|
bitfld.long 0x00 29. "INT125FLG,INT125FLG" "0,1"
|
|
bitfld.long 0x00 28. "INT124FLG,INT124FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "INT123FLG,INT123FLG" "0,1"
|
|
bitfld.long 0x00 26. "INT122FLG,INT122FLG" "0,1"
|
|
bitfld.long 0x00 25. "INT121FLG,INT121FLG" "0,1"
|
|
bitfld.long 0x00 24. "INT120FLG,INT120FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "INT119FLG,INT119FLG" "0,1"
|
|
bitfld.long 0x00 22. "INT118FLG,INT118FLG" "0,1"
|
|
bitfld.long 0x00 21. "INT117FLG,INT117FLG" "0,1"
|
|
bitfld.long 0x00 20. "INT116FLG,INT116FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "INT115FLG,INT115FLG" "0,1"
|
|
bitfld.long 0x00 18. "INT114FLG,INT114FLG" "0,1"
|
|
bitfld.long 0x00 17. "INT113FLG,INT113FLG" "0,1"
|
|
bitfld.long 0x00 16. "INT112FLG,INT112FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "INT111FLG,INT111FLG" "0,1"
|
|
bitfld.long 0x00 14. "INT110FLG,INT110FLG" "0,1"
|
|
bitfld.long 0x00 13. "INT109FLG,INT109FLG" "0,1"
|
|
bitfld.long 0x00 12. "INT108FLG,INT108FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "INT107FLG,INT107FLG" "0,1"
|
|
bitfld.long 0x00 10. "INT106FLG,INT106FLG" "0,1"
|
|
bitfld.long 0x00 9. "INT105FLG,INT105FLG" "0,1"
|
|
bitfld.long 0x00 8. "INT104FLG,INT104FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "INT103FLG,INT103FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT102FLG,INT102FLG" "0,1"
|
|
bitfld.long 0x00 5. "INT101FLG,INT101FLG" "0,1"
|
|
bitfld.long 0x00 4. "INT100FLG,INT100FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INT099FLG,INT099FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT098FLG,INT098FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT097FLG,INT097FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT096FLG,INT096FLG" "0,1"
|
|
endif
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLG4,NMI Interrupt Monitor Flag 4"
|
|
bitfld.long 0x00 8. "INT136FLG,INT136FLG" "0,1"
|
|
bitfld.long 0x00 7. "INT135FLG,INT135FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT134FLG,INT134FLG" "0,1"
|
|
bitfld.long 0x00 5. "INT133FLG,INT133FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "INT132FLG,INT132FLG" "0,1"
|
|
bitfld.long 0x00 3. "INT131FLG,INT131FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT130FLG,INT130FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT129FLG,INT129FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INT128FLG,INT128FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLG4,Interrupt Monitor Flag 4 (128 - 159)"
|
|
bitfld.long 0x00 31. "INT159FLG,INT159FLG" "0,1"
|
|
bitfld.long 0x00 30. "INT158FLG,INT158FLG" "0,1"
|
|
bitfld.long 0x00 29. "INT157FLG,INT157FLG" "0,1"
|
|
bitfld.long 0x00 28. "INT156FLG,INT156FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "INT155FLG,INT155FLG" "0,1"
|
|
bitfld.long 0x00 26. "INT154FLG,INT154FLG" "0,1"
|
|
bitfld.long 0x00 25. "INT153FLG,INT153FLG" "0,1"
|
|
bitfld.long 0x00 24. "INT152FLG,INT152FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "INT151FLG,INT151FLG" "0,1"
|
|
bitfld.long 0x00 22. "INT150FLG,INT150FLG" "0,1"
|
|
bitfld.long 0x00 21. "INT149FLG,INT149FLG" "0,1"
|
|
bitfld.long 0x00 20. "INT148FLG,INT148FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "INT147FLG,INT147FLG" "0,1"
|
|
bitfld.long 0x00 18. "INT146FLG,INT146FLG" "0,1"
|
|
bitfld.long 0x00 17. "INT145FLG,INT145FLG" "0,1"
|
|
bitfld.long 0x00 16. "INT144FLG,INT144FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "INT143FLG,INT143FLG" "0,1"
|
|
bitfld.long 0x00 14. "INT142FLG,INT142FLG" "0,1"
|
|
bitfld.long 0x00 13. "INT141FLG,INT141FLG" "0,1"
|
|
bitfld.long 0x00 12. "INT140FLG,INT140FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "INT139FLG,INT139FLG" "0,1"
|
|
bitfld.long 0x00 10. "INT138FLG,INT138FLG" "0,1"
|
|
bitfld.long 0x00 9. "INT137FLG,INT137FLG" "0,1"
|
|
bitfld.long 0x00 8. "INT136FLG,INT136FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "INT135FLG,INT135FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT134FLG,INT134FLG" "0,1"
|
|
bitfld.long 0x00 5. "INT133FLG,INT133FLG" "0,1"
|
|
bitfld.long 0x00 4. "INT132FLG,INT132FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INT131FLG,INT131FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT130FLG,INT130FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT129FLG,INT129FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT128FLG,INT128FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLG4,Interrupt Monitor Flag 4 (128 - 159)"
|
|
bitfld.long 0x00 11. "INT139FLG,INT139FLG" "0,1"
|
|
bitfld.long 0x00 10. "INT138FLG,INT138FLG" "0,1"
|
|
bitfld.long 0x00 9. "INT137FLG,INT137FLG" "0,1"
|
|
bitfld.long 0x00 8. "INT136FLG,INT136FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "INT135FLG,INT135FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT134FLG,INT134FLG" "0,1"
|
|
bitfld.long 0x00 5. "INT133FLG,INT133FLG" "0,1"
|
|
bitfld.long 0x00 4. "INT132FLG,INT132FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INT131FLG,INT131FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT130FLG,INT130FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT129FLG,INT129FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT128FLG,INT128FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "FLG5,Interrupt Monitor Flag 5 (160 - 191)"
|
|
bitfld.long 0x00 31. "INT191FLG,INT191FLG" "0,1"
|
|
bitfld.long 0x00 30. "INT190FLG,INT190FLG" "0,1"
|
|
bitfld.long 0x00 29. "INT189FLG,INT189FLG" "0,1"
|
|
bitfld.long 0x00 28. "INT188FLG,INT188FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "INT187FLG,INT187FLG" "0,1"
|
|
bitfld.long 0x00 26. "INT186FLG,INT186FLG" "0,1"
|
|
bitfld.long 0x00 25. "INT185FLG,INT185FLG" "0,1"
|
|
bitfld.long 0x00 24. "INT184FLG,INT184FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "INT183FLG,INT183FLG" "0,1"
|
|
bitfld.long 0x00 22. "INT182FLG,INT182FLG" "0,1"
|
|
bitfld.long 0x00 21. "INT181FLG,INT181FLG" "0,1"
|
|
bitfld.long 0x00 20. "INT180FLG,INT180FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "INT179FLG,INT179FLG" "0,1"
|
|
bitfld.long 0x00 18. "INT178FLG,INT178FLG" "0,1"
|
|
bitfld.long 0x00 17. "INT177FLG,INT177FLG" "0,1"
|
|
bitfld.long 0x00 16. "INT176FLG,INT176FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "INT175FLG,INT175FLG" "0,1"
|
|
bitfld.long 0x00 14. "INT174FLG,INT174FLG" "0,1"
|
|
bitfld.long 0x00 13. "INT173FLG,INT173FLG" "0,1"
|
|
bitfld.long 0x00 12. "INT172FLG,INT172FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "INT171FLG,INT171FLG" "0,1"
|
|
bitfld.long 0x00 10. "INT170FLG,INT170FLG" "0,1"
|
|
bitfld.long 0x00 9. "INT169FLG,INT169FLG" "0,1"
|
|
bitfld.long 0x00 8. "INT168FLG,INT168FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "INT167FLG,INT167FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT166FLG,INT166FLG" "0,1"
|
|
bitfld.long 0x00 5. "INT165FLG,INT165FLG" "0,1"
|
|
bitfld.long 0x00 4. "INT164FLG,INT164FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INT163FLG,INT163FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT162FLG,INT162FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT161FLG,INT161FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT160FLG,INT160FLG" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "FLG6,Interrupt Monitor Flag 6 (192 - 223)"
|
|
bitfld.long 0x00 31. "INT223FLG,INT223FLG" "0,1"
|
|
bitfld.long 0x00 30. "INT222FLG,INT222FLG" "0,1"
|
|
bitfld.long 0x00 29. "INT221FLG,INT221FLG" "0,1"
|
|
bitfld.long 0x00 28. "INT220FLG,INT220FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "INT219FLG,INT219FLG" "0,1"
|
|
bitfld.long 0x00 26. "INT218FLG,INT218FLG" "0,1"
|
|
bitfld.long 0x00 25. "INT217FLG,INT217FLG" "0,1"
|
|
bitfld.long 0x00 24. "INT216FLG,INT216FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "INT215FLG,INT215FLG" "0,1"
|
|
bitfld.long 0x00 22. "INT214FLG,INT214FLG" "0,1"
|
|
bitfld.long 0x00 21. "INT213FLG,INT213FLG" "0,1"
|
|
bitfld.long 0x00 20. "INT212FLG,INT212FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "INT211FLG,INT211FLG" "0,1"
|
|
bitfld.long 0x00 18. "INT210FLG,INT210FLG" "0,1"
|
|
bitfld.long 0x00 17. "INT209FLG,INT209FLG" "0,1"
|
|
bitfld.long 0x00 16. "INT208FLG,INT208FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "INT207FLG,INT207FLG" "0,1"
|
|
bitfld.long 0x00 14. "INT206FLG,INT206FLG" "0,1"
|
|
bitfld.long 0x00 13. "INT205FLG,INT205FLG" "0,1"
|
|
bitfld.long 0x00 12. "INT204FLG,INT204FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "INT203FLG,INT203FLG" "0,1"
|
|
bitfld.long 0x00 10. "INT202FLG,INT202FLG" "0,1"
|
|
bitfld.long 0x00 9. "INT201FLG,INT201FLG" "0,1"
|
|
bitfld.long 0x00 8. "INT200FLG,INT200FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "INT199FLG,INT199FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT198FLG,INT198FLG" "0,1"
|
|
bitfld.long 0x00 5. "INT197FLG,INT197FLG" "0,1"
|
|
bitfld.long 0x00 4. "INT196FLG,INT196FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INT195FLG,INT195FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT194FLG,INT194FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT193FLG,INT193FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT192FLG,INT192FLG" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "FLG7,Interrupt Monitor Flag 7 (224 - 225)"
|
|
bitfld.long 0x00 11. "INT235FLG,INT235FLG" "0,1"
|
|
bitfld.long 0x00 10. "INT234FLG,INT234FLG" "0,1"
|
|
bitfld.long 0x00 9. "INT233FLG,INT233FLG" "0,1"
|
|
bitfld.long 0x00 8. "INT232FLG,INT232FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "INT231FLG,INT231FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT230FLG,INT230FLG" "0,1"
|
|
bitfld.long 0x00 5. "INT229FLG,INT229FLG" "0,1"
|
|
bitfld.long 0x00 4. "INT228FLG,INT228FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INT227FLG,INT227FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT226FLG,INT226FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT225FLG,INT225FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT224FLG,INT224FLG" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x40083300
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "FLGNMI,NMI Interrupt Monitor Flag"
|
|
bitfld.long 0x00 16. "INT016FLG,INT016FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT000FLG,INT000FLG" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "FLG3,Interrupt Monitor Flag 3 (096 - 127)"
|
|
bitfld.long 0x00 31. "INT127FLG,INT127FLG" "0,1"
|
|
bitfld.long 0x00 30. "INT126FLG,INT126FLG" "0,1"
|
|
bitfld.long 0x00 29. "INT125FLG,INT125FLG" "0,1"
|
|
bitfld.long 0x00 28. "INT124FLG,INT124FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "INT123FLG,INT123FLG" "0,1"
|
|
bitfld.long 0x00 26. "INT122FLG,INT122FLG" "0,1"
|
|
bitfld.long 0x00 25. "INT121FLG,INT121FLG" "0,1"
|
|
bitfld.long 0x00 24. "INT120FLG,INT120FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "INT119FLG,INT119FLG" "0,1"
|
|
bitfld.long 0x00 22. "INT118FLG,INT118FLG" "0,1"
|
|
bitfld.long 0x00 21. "INT117FLG,INT117FLG" "0,1"
|
|
bitfld.long 0x00 20. "INT116FLG,INT116FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "INT115FLG,INT115FLG" "0,1"
|
|
bitfld.long 0x00 18. "INT114FLG,INT114FLG" "0,1"
|
|
bitfld.long 0x00 17. "INT113FLG,INT113FLG" "0,1"
|
|
bitfld.long 0x00 16. "INT112FLG,INT112FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "INT111FLG,INT111FLG" "0,1"
|
|
bitfld.long 0x00 14. "INT110FLG,INT110FLG" "0,1"
|
|
bitfld.long 0x00 13. "INT109FLG,INT109FLG" "0,1"
|
|
bitfld.long 0x00 12. "INT108FLG,INT108FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "INT107FLG,INT107FLG" "0,1"
|
|
bitfld.long 0x00 10. "INT106FLG,INT106FLG" "0,1"
|
|
bitfld.long 0x00 9. "INT105FLG,INT105FLG" "0,1"
|
|
bitfld.long 0x00 8. "INT104FLG,INT104FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "INT103FLG,INT103FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT102FLG,INT102FLG" "0,1"
|
|
bitfld.long 0x00 5. "INT101FLG,INT101FLG" "0,1"
|
|
bitfld.long 0x00 4. "INT100FLG,INT100FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INT099FLG,INT099FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT098FLG,INT098FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT097FLG,INT097FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT096FLG,INT096FLG" "0,1"
|
|
sif cpuis("TMPM4L*")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLG4,Interrupt Monitor Flag 4 (128 - 159)"
|
|
bitfld.long 0x00 23. "INT151FLG,INT151FLG" "0,1"
|
|
bitfld.long 0x00 22. "INT150FLG,INT150FLG" "0,1"
|
|
bitfld.long 0x00 21. "INT149FLG,INT149FLG" "0,1"
|
|
bitfld.long 0x00 20. "INT148FLG,INT148FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "INT147FLG,INT147FLG" "0,1"
|
|
bitfld.long 0x00 18. "INT146FLG,INT146FLG" "0,1"
|
|
bitfld.long 0x00 17. "INT145FLG,INT145FLG" "0,1"
|
|
bitfld.long 0x00 16. "INT144FLG,INT144FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "INT143FLG,INT143FLG" "0,1"
|
|
bitfld.long 0x00 14. "INT142FLG,INT142FLG" "0,1"
|
|
bitfld.long 0x00 12. "INT140FLG,INT140FLG" "0,1"
|
|
bitfld.long 0x00 11. "INT139FLG,INT139FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "INT138FLG,INT138FLG" "0,1"
|
|
bitfld.long 0x00 9. "INT137FLG,INT137FLG" "0,1"
|
|
bitfld.long 0x00 8. "INT136FLG,INT136FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT134FLG,INT134FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "INT132FLG,INT132FLG" "0,1"
|
|
bitfld.long 0x00 3. "INT131FLG,INT131FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT130FLG,INT130FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT129FLG,INT129FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INT128FLG,INT128FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLG4,Interrupt Monitor Flag 4 (128 - 159)"
|
|
bitfld.long 0x00 28. "INT156FLG,INT156FLG" "0,1"
|
|
bitfld.long 0x00 27. "INT155FLG,INT155FLG" "0,1"
|
|
bitfld.long 0x00 26. "INT154FLG,INT154FLG" "0,1"
|
|
bitfld.long 0x00 24. "INT152FLG,INT152FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "INT151FLG,INT151FLG" "0,1"
|
|
bitfld.long 0x00 22. "INT150FLG,INT150FLG" "0,1"
|
|
bitfld.long 0x00 21. "INT149FLG,INT149FLG" "0,1"
|
|
bitfld.long 0x00 20. "INT148FLG,INT148FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "INT147FLG,INT147FLG" "0,1"
|
|
bitfld.long 0x00 18. "INT146FLG,INT146FLG" "0,1"
|
|
bitfld.long 0x00 17. "INT145FLG,INT145FLG" "0,1"
|
|
bitfld.long 0x00 16. "INT144FLG,INT144FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "INT143FLG,INT143FLG" "0,1"
|
|
bitfld.long 0x00 14. "INT142FLG,INT142FLG" "0,1"
|
|
bitfld.long 0x00 12. "INT140FLG,INT140FLG" "0,1"
|
|
bitfld.long 0x00 11. "INT139FLG,INT139FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "INT138FLG,INT138FLG" "0,1"
|
|
bitfld.long 0x00 9. "INT137FLG,INT137FLG" "0,1"
|
|
bitfld.long 0x00 8. "INT136FLG,INT136FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT134FLG,INT134FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "INT132FLG,INT132FLG" "0,1"
|
|
bitfld.long 0x00 3. "INT131FLG,INT131FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT130FLG,INT130FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT129FLG,INT129FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INT128FLG,INT128FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLG4,Interrupt Monitor Flag 4 (128 - 159)"
|
|
bitfld.long 0x00 31. "INT159FLG,INT159FLG" "0,1"
|
|
bitfld.long 0x00 30. "INT158FLG,INT158FLG" "0,1"
|
|
bitfld.long 0x00 29. "INT157FLG,INT157FLG" "0,1"
|
|
bitfld.long 0x00 28. "INT156FLG,INT156FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "INT155FLG,INT155FLG" "0,1"
|
|
bitfld.long 0x00 26. "INT154FLG,INT154FLG" "0,1"
|
|
bitfld.long 0x00 25. "INT153FLG,INT153FLG" "0,1"
|
|
bitfld.long 0x00 24. "INT152FLG,INT152FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "INT151FLG,INT151FLG" "0,1"
|
|
bitfld.long 0x00 22. "INT150FLG,INT150FLG" "0,1"
|
|
bitfld.long 0x00 21. "INT149FLG,INT149FLG" "0,1"
|
|
bitfld.long 0x00 20. "INT148FLG,INT148FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "INT147FLG,INT147FLG" "0,1"
|
|
bitfld.long 0x00 18. "INT146FLG,INT146FLG" "0,1"
|
|
bitfld.long 0x00 17. "INT145FLG,INT145FLG" "0,1"
|
|
bitfld.long 0x00 16. "INT144FLG,INT144FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "INT143FLG,INT143FLG" "0,1"
|
|
bitfld.long 0x00 14. "INT142FLG,INT142FLG" "0,1"
|
|
bitfld.long 0x00 13. "INT141FLG,INT141FLG" "0,1"
|
|
bitfld.long 0x00 12. "INT140FLG,INT140FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "INT139FLG,INT139FLG" "0,1"
|
|
bitfld.long 0x00 10. "INT138FLG,INT138FLG" "0,1"
|
|
bitfld.long 0x00 9. "INT137FLG,INT137FLG" "0,1"
|
|
bitfld.long 0x00 8. "INT136FLG,INT136FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "INT135FLG,INT135FLG" "0,1"
|
|
bitfld.long 0x00 6. "INT134FLG,INT134FLG" "0,1"
|
|
bitfld.long 0x00 5. "INT133FLG,INT133FLG" "0,1"
|
|
bitfld.long 0x00 4. "INT132FLG,INT132FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INT131FLG,INT131FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT130FLG,INT130FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT129FLG,INT129FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT128FLG,INT128FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "FLG5,Interrupt Monitor Flag 5 (160 - 191)"
|
|
bitfld.long 0x00 5. "INT165FLG,INT165FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "FLG5,Interrupt Monitor Flag 5 (160 - 191)"
|
|
bitfld.long 0x00 5. "INT165FLG,INT165FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT162FLG,INT162FLG" "0,1"
|
|
bitfld.long 0x00 1. "INT161FLG,INT161FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT160FLG,INT160FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KQ*")
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "FLG5,Interrupt Monitor Flag 5 (160 - 191)"
|
|
bitfld.long 0x00 5. "INT165FLG,INT165FLG" "0,1"
|
|
bitfld.long 0x00 4. "INT164FLG,INT164FLG" "0,1"
|
|
bitfld.long 0x00 3. "INT163FLG,INT163FLG" "0,1"
|
|
bitfld.long 0x00 2. "INT162FLG,INT162FLG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "INT161FLG,INT161FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT160FLG,INT160FLG" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "FLG5,Interrupt Monitor Flag 5 (160 - 191)"
|
|
bitfld.long 0x00 5. "INT165FLG,INT165FLG" "0,1"
|
|
bitfld.long 0x00 0. "INT160FLG,INT160FLG" "0,1"
|
|
endif
|
|
endif
|
|
tree.end
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "DNFA (DNF)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400A0200
|
|
elif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400A0200
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CKCR,DNF clock Control register"
|
|
bitfld.long 0x00 0.--2. "NFCKS,NFCKS" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ENCR,DNF Enable register"
|
|
bitfld.long 0x00 15. "NFEN15,NFEN15" "0,1"
|
|
bitfld.long 0x00 14. "NFEN14,NFEN14" "0,1"
|
|
bitfld.long 0x00 13. "NFEN13,NFEN13" "0,1"
|
|
bitfld.long 0x00 12. "NFEN12,NFEN12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "NFEN11,NFEN11" "0,1"
|
|
bitfld.long 0x00 10. "NFEN10,NFEN10" "0,1"
|
|
bitfld.long 0x00 9. "NFEN9,NFEN9" "0,1"
|
|
bitfld.long 0x00 8. "NFEN8,NFEN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "NFEN7,NFEN7" "0,1"
|
|
bitfld.long 0x00 6. "NFEN6,NFEN6" "0,1"
|
|
bitfld.long 0x00 5. "NFEN5,NFEN5" "0,1"
|
|
bitfld.long 0x00 4. "NFEN4,NFEN4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "NFEN3,NFEN3" "0,1"
|
|
bitfld.long 0x00 2. "NFEN2,NFEN2" "0,1"
|
|
bitfld.long 0x00 1. "NFEN1,NFEN1" "0,1"
|
|
bitfld.long 0x00 0. "NFEN0,NFEN0" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "DNFB (DNF)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400A0300
|
|
elif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400A0300
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CKCR,DNF clock Control register"
|
|
bitfld.long 0x00 0.--2. "NFCKS,NFCKS" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ENCR,DNF Enable register"
|
|
bitfld.long 0x00 15. "NFEN15,NFEN15" "0,1"
|
|
bitfld.long 0x00 14. "NFEN14,NFEN14" "0,1"
|
|
bitfld.long 0x00 13. "NFEN13,NFEN13" "0,1"
|
|
bitfld.long 0x00 12. "NFEN12,NFEN12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "NFEN11,NFEN11" "0,1"
|
|
bitfld.long 0x00 10. "NFEN10,NFEN10" "0,1"
|
|
bitfld.long 0x00 9. "NFEN9,NFEN9" "0,1"
|
|
bitfld.long 0x00 8. "NFEN8,NFEN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "NFEN7,NFEN7" "0,1"
|
|
bitfld.long 0x00 6. "NFEN6,NFEN6" "0,1"
|
|
bitfld.long 0x00 5. "NFEN5,NFEN5" "0,1"
|
|
bitfld.long 0x00 4. "NFEN4,NFEN4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "NFEN3,NFEN3" "0,1"
|
|
bitfld.long 0x00 2. "NFEN2,NFEN2" "0,1"
|
|
bitfld.long 0x00 1. "NFEN1,NFEN1" "0,1"
|
|
bitfld.long 0x00 0. "NFEN0,NFEN0" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "SIWD (Watchdog Timer (WD))"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400A0600
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40040600
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PRO,SIWD Protect Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PROTECT,PROTECT"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EN,SIWD Enable Register"
|
|
rbitfld.long 0x00 1. "WDTF,WDTF" "0,1"
|
|
bitfld.long 0x00 0. "WDTE,WDTE" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CR,SIWD Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WDCR,WDCR"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MOD,SIWD Mode Register"
|
|
bitfld.long 0x00 12.--13. "WDCLS,WDCLS" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "WDTP,WDTP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "WDCWD,WDCWD" "0,1,2,3"
|
|
bitfld.long 0x00 1. "INTF,INTF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESCR,RESCR" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "MONI,SIWD Monitor Register"
|
|
hexmask.long 0x00 0.--29. 1. "MONI,MONI"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "OSCCR,SIWD Oscillation control register"
|
|
bitfld.long 0x00 0. "OSCPRO,OSCPRO" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400BB400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PRO,SIWD Protect register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PROTECT,PROTECT"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EN,SIWD Enable register"
|
|
rbitfld.long 0x00 1. "WDTF,WDTF" "0,1"
|
|
bitfld.long 0x00 0. "WDTE,WDTE" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CR,SIWD Control register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WDCR,WDCR"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MOD,SIWD Mode register"
|
|
bitfld.long 0x00 12.--13. "WDCLS,WDCLS" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "WDTP,WDTP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "WDCWD,WDCWD" "0,1,2,3"
|
|
bitfld.long 0x00 1. "INTF,INTF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESCR,RESCR" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "MONI,SIWD Monitor register"
|
|
hexmask.long 0x00 0.--29. 1. "MONI,MONI"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "OSCCR,SIWD Oscillation control register"
|
|
bitfld.long 0x00 0. "OSCPRO,OSCPRO" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400A0600
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PRO,SIWD Protect Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PROTECT,PROTECT"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EN,SIWD Enable Register"
|
|
rbitfld.long 0x00 1. "WDTF,WDTF" "0,1"
|
|
bitfld.long 0x00 0. "WDTE,WDTE" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CR,SIWD Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WDCR,WDCR"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MOD,SIWD Mode Register"
|
|
bitfld.long 0x00 12.--13. "WDCLS,WDCLS" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "WDTP,WDTP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "WDCWD,WDCWD" "0,1,2,3"
|
|
bitfld.long 0x00 1. "INTF,INTF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESCR,RESCR" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "MONI,SIWD Count Monitor Register"
|
|
hexmask.long 0x00 0.--29. 1. "MONI,MONI"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "OSCCR,SIWD Oscillator Control Register"
|
|
bitfld.long 0x00 0. "OSCPRO,OSCPRO" "0,1"
|
|
endif
|
|
tree.end
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4K4A*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "NBD"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400A2000
|
|
elif cpuis("TMPM4K4A*")
|
|
base ad:0x400BBA00
|
|
elif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400A2000
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,NBD control register 0"
|
|
bitfld.long 0x00 0. "NBDEN,NBDEN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,NBD control register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "NBDCREN,NBDCREN"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
tree "MDMA (Malti Porpose Direct Memory Accsess(MDMA))"
|
|
base ad:0x400A4000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REV,MDMAC Revision Register"
|
|
hexmask.long 0x00 0.--31. 1. "REV,REV"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CEN,MDMAC Channel Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHENB,CHENB"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "REQ,MDMAC Transfer Request Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHREQ,CHREQ"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SUS,MDMAC Transfer Suspension Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHSUS,CHSUS"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ACT,MDMAC Transfer Active Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHACT,CHACT"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "END,MDMAC Transfer End Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHEND,CHEND"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PRI,MDMAC Priority Setting Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHPRI,CHPRI"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ENE,MDMAC End Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENDIE,ENDIE"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IAD,MDMAC Channel Information Address Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "CHIAD,CHIAD"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SAD,MDMAC Channel Save Address Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "CHSAD,CHSAD"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CHN,MDMAC Channel Number Register"
|
|
bitfld.long 0x00 0.--3. "CHNUM,CHNUM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "XFTYP,MDMAC Channel Number Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "XFSAD,MDMAC Transfer Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "XFDAD,MDMAC Transfer Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "XFSIZ,MDMAC Transfer Size Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "DSADS,MDMAC Descriptor Address Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "DSNUM,MDMAC Descriptor Number Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "LRQ,MDMAC Level Request Register"
|
|
hexmask.long 0x00 0.--31. 1. "LVREQ,LVREQ"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "C00XFTYP,MDMAC Channel 00 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "C00XFSAD,MDMAC Channel 00 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "C00XFDAD,MDMAC Channel 00 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "C00XFSIZ,MDMAC Channel 00 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "C00DSADS,MDMAC Channel 00 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "C00DSNUM,MDMAC Channel 00 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "C01XFTYP,MDMAC Channel 01 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "C01XFSAD,MDMAC Channel 01 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "C01XFDAD,MDMAC Channel 01 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "C01XFSIZ,MDMAC Channel 01 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "C01DSADS,MDMAC Channel 01 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "C01DSNUM,MDMAC Channel 01 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "C02XFTYP,MDMAC Channel 02 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "C02XFSAD,MDMAC Channel 02 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "C02XFDAD,MDMAC Channel 02 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "C02XFSIZ,MDMAC Channel 02 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "C02DSADS,MDMAC Channel 02 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "C02DSNUM,MDMAC Channel 02 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "C03XFTYP,MDMAC Channel 03 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "C03XFSAD,MDMAC Channel 03 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "C03XFDAD,MDMAC Channel 03 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "C03XFSIZ,MDMAC Channel 03 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "C03DSADS,MDMAC Channel 03 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "C03DSNUM,MDMAC Channel 03 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "C04XFTYP,MDMAC Channel 04 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "C04XFSAD,MDMAC Channel 04 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "C04XFDAD,MDMAC Channel 04 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "C04XFSIZ,MDMAC Channel 04 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "C04DSADS,MDMAC Channel 04 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "C04DSNUM,MDMAC Channel 04 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "C05XFTYP,MDMAC Channel 05 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "C05XFSAD,MDMAC Channel 05 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "C05XFDAD,MDMAC Channel 05 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "C05XFSIZ,MDMAC Channel 05 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "C05DSADS,MDMAC Channel 05 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "C05DSNUM,MDMAC Channel 05 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "C06XFTYP,MDMAC Channel 06 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "C06XFSAD,MDMAC Channel 06 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "C06XFDAD,MDMAC Channel 06 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "C06XFSIZ,MDMAC Channel 06 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "C06DSADS,MDMAC Channel 06 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "C06DSNUM,MDMAC Channel 06 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "C07XFTYP,MDMAC Channel 07 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "C07XFSAD,MDMAC Channel 07 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "C07XFDAD,MDMAC Channel 07 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "C07XFSIZ,MDMAC Channel 07 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "C07DSADS,MDMAC Channel 07 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "C07DSNUM,MDMAC Channel 07 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "C08XFTYP,MDMAC Channel 08 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "C08XFSAD,MDMAC Channel 08 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "C08XFDAD,MDMAC Channel 08 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "C08XFSIZ,MDMAC Channel 08 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "C08DSADS,MDMAC Channel 08 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "C08DSNUM,MDMAC Channel 08 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "C09XFTYP,MDMAC Channel 09 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "C09XFSAD,MDMAC Channel 09 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "C09XFDAD,MDMAC Channel 09 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "C09XFSIZ,MDMAC Channel 09 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "C09DSADS,MDMAC Channel 09 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "C09DSNUM,MDMAC Channel 09 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "C10XFTYP,MDMAC Channel 10 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "C10XFSAD,MDMAC Channel 10 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "C10XFDAD,MDMAC Channel 10 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "C10XFSIZ,MDMAC Channel 10 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "C10DSADS,MDMAC Channel 10 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "C10DSNUM,MDMAC Channel 10 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "C11XFTYP,MDMAC Channel 11 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "C11XFSAD,MDMAC Channel 11 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "C11XFDAD,MDMAC Channel 11 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "C11XFSIZ,MDMAC Channel 11 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "C11DSADS,MDMAC Channel 11 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "C11DSNUM,MDMAC Channel 11 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x1D0++0x03
|
|
line.long 0x00 "C12XFTYP,MDMAC Channel 12 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x1D4++0x03
|
|
line.long 0x00 "C12XFSAD,MDMAC Channel 12 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x1D8++0x03
|
|
line.long 0x00 "C12XFDAD,MDMAC Channel 12 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x1DC++0x03
|
|
line.long 0x00 "C12XFSIZ,MDMAC Channel 12 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "C12DSADS,MDMAC Channel 12 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x1E4++0x03
|
|
line.long 0x00 "C12DSNUM,MDMAC Channel 12 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x1F0++0x03
|
|
line.long 0x00 "C13XFTYP,MDMAC Channel 13 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x1F4++0x03
|
|
line.long 0x00 "C13XFSAD,MDMAC Channel 13 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x1F8++0x03
|
|
line.long 0x00 "C13XFDAD,MDMAC Channel 13 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x1FC++0x03
|
|
line.long 0x00 "C13XFSIZ,MDMAC Channel 13 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x200++0x03
|
|
line.long 0x00 "C13DSADS,MDMAC Channel 13 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "C13DSNUM,MDMAC Channel 13 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "C14XFTYP,MDMAC Channel 14 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "C14XFSAD,MDMAC Channel 14 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x218++0x03
|
|
line.long 0x00 "C14XFDAD,MDMAC Channel 14 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "C14XFSIZ,MDMAC Channel 14 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x220++0x03
|
|
line.long 0x00 "C14DSADS,MDMAC Channel 14 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x224++0x03
|
|
line.long 0x00 "C14DSNUM,MDMAC Channel 14 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x230++0x03
|
|
line.long 0x00 "C15XFTYP,MDMAC Channel 15 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x234++0x03
|
|
line.long 0x00 "C15XFSAD,MDMAC Channel 15 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x238++0x03
|
|
line.long 0x00 "C15XFDAD,MDMAC Channel 15 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x23C++0x03
|
|
line.long 0x00 "C15XFSIZ,MDMAC Channel 15 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "C15DSADS,MDMAC Channel 15 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x244++0x03
|
|
line.long 0x00 "C15DSNUM,MDMAC Channel 15 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x250++0x03
|
|
line.long 0x00 "C16XFTYP,MDMAC Channel 16 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x254++0x03
|
|
line.long 0x00 "C16XFSAD,MDMAC Channel 16 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x258++0x03
|
|
line.long 0x00 "C16XFDAD,MDMAC Channel 16 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "C16XFSIZ,MDMAC Channel 16 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x260++0x03
|
|
line.long 0x00 "C16DSADS,MDMAC Channel 16 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x264++0x03
|
|
line.long 0x00 "C16DSNUM,MDMAC Channel 16 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x270++0x03
|
|
line.long 0x00 "C17XFTYP,MDMAC Channel 17 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x274++0x03
|
|
line.long 0x00 "C17XFSAD,MDMAC Channel 17 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x278++0x03
|
|
line.long 0x00 "C17XFDAD,MDMAC Channel 17 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x27C++0x03
|
|
line.long 0x00 "C17XFSIZ,MDMAC Channel 17 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "C17DSADS,MDMAC Channel 17 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "C17DSNUM,MDMAC Channel 17 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x290++0x03
|
|
line.long 0x00 "C18XFTYP,MDMAC Channel 18 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "C18XFSAD,MDMAC Channel 18 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "C18XFDAD,MDMAC Channel 18 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x29C++0x03
|
|
line.long 0x00 "C18XFSIZ,MDMAC Channel 18 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x2A0++0x03
|
|
line.long 0x00 "C18DSADS,MDMAC Channel 18 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x2A4++0x03
|
|
line.long 0x00 "C18DSNUM,MDMAC Channel 18 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x2B0++0x03
|
|
line.long 0x00 "C19XFTYP,MDMAC Channel 19 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x2B4++0x03
|
|
line.long 0x00 "C19XFSAD,MDMAC Channel 19 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x2B8++0x03
|
|
line.long 0x00 "C19XFDAD,MDMAC Channel 19 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x2BC++0x03
|
|
line.long 0x00 "C19XFSIZ,MDMAC Channel 19 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x2C0++0x03
|
|
line.long 0x00 "C19DSADS,MDMAC Channel 19 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x2C4++0x03
|
|
line.long 0x00 "C19DSNUM,MDMAC Channel 19 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x2D0++0x03
|
|
line.long 0x00 "C20XFTYP,MDMAC Channel 20 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x2D4++0x03
|
|
line.long 0x00 "C20XFSAD,MDMAC Channel 20 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x2D8++0x03
|
|
line.long 0x00 "C20XFDAD,MDMAC Channel 20 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x2DC++0x03
|
|
line.long 0x00 "C20XFSIZ,MDMAC Channel 20 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x2E0++0x03
|
|
line.long 0x00 "C20DSADS,MDMAC Channel 20 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x2E4++0x03
|
|
line.long 0x00 "C20DSNUM,MDMAC Channel 20 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x2F0++0x03
|
|
line.long 0x00 "C21XFTYP,MDMAC Channel 21 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x2F4++0x03
|
|
line.long 0x00 "C21XFSAD,MDMAC Channel 21 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x2F8++0x03
|
|
line.long 0x00 "C21XFDAD,MDMAC Channel 21 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x2FC++0x03
|
|
line.long 0x00 "C21XFSIZ,MDMAC Channel 21 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "C21DSADS,MDMAC Channel 21 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "C21DSNUM,MDMAC Channel 21 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "C22XFTYP,MDMAC Channel 22 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "C22XFSAD,MDMAC Channel 22 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "C22XFDAD,MDMAC Channel 22 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "C22XFSIZ,MDMAC Channel 22 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x320++0x03
|
|
line.long 0x00 "C22DSADS,MDMAC Channel 22 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x324++0x03
|
|
line.long 0x00 "C22DSNUM,MDMAC Channel 22 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x330++0x03
|
|
line.long 0x00 "C23XFTYP,MDMAC Channel 23 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x334++0x03
|
|
line.long 0x00 "C23XFSAD,MDMAC Channel 23 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x338++0x03
|
|
line.long 0x00 "C23XFDAD,MDMAC Channel 23 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x33C++0x03
|
|
line.long 0x00 "C23XFSIZ,MDMAC Channel 23 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "C23DSADS,MDMAC Channel 23 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "C23DSNUM,MDMAC Channel 23 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "C24XFTYP,MDMAC Channel 24 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "C24XFSAD,MDMAC Channel 24 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "C24XFDAD,MDMAC Channel 24 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "C24XFSIZ,MDMAC Channel 24 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "C24DSADS,MDMAC Channel 24 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "C24DSNUM,MDMAC Channel 24 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "C25XFTYP,MDMAC Channel 25 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "C25XFSAD,MDMAC Channel 25 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "C25XFDAD,MDMAC Channel 25 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "C25XFSIZ,MDMAC Channel 25 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x380++0x03
|
|
line.long 0x00 "C25DSADS,MDMAC Channel 25 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x384++0x03
|
|
line.long 0x00 "C25DSNUM,MDMAC Channel 25 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x390++0x03
|
|
line.long 0x00 "C26XFTYP,MDMAC Channel 26 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x394++0x03
|
|
line.long 0x00 "C26XFSAD,MDMAC Channel 26 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x398++0x03
|
|
line.long 0x00 "C26XFDAD,MDMAC Channel 26 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x39C++0x03
|
|
line.long 0x00 "C26XFSIZ,MDMAC Channel 26 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x3A0++0x03
|
|
line.long 0x00 "C26DSADS,MDMAC Channel 26 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x3A4++0x03
|
|
line.long 0x00 "C26DSNUM,MDMAC Channel 26 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x3B0++0x03
|
|
line.long 0x00 "C27XFTYP,MDMAC Channel 27 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x3B4++0x03
|
|
line.long 0x00 "C27XFSAD,MDMAC Channel 27 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x3B8++0x03
|
|
line.long 0x00 "C27XFDAD,MDMAC Channel 27 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x3BC++0x03
|
|
line.long 0x00 "C27XFSIZ,MDMAC Channel 27 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x3C0++0x03
|
|
line.long 0x00 "C27DSADS,MDMAC Channel 27 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x3C4++0x03
|
|
line.long 0x00 "C27DSNUM,MDMAC Channel 27 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x3D0++0x03
|
|
line.long 0x00 "C28XFTYP,MDMAC Channel 28 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x3D4++0x03
|
|
line.long 0x00 "C28XFSAD,MDMAC Channel 28 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x3D8++0x03
|
|
line.long 0x00 "C28XFDAD,MDMAC Channel 28 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x3DC++0x03
|
|
line.long 0x00 "C28XFSIZ,MDMAC Channel 28 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x3E0++0x03
|
|
line.long 0x00 "C28DSADS,MDMAC Channel 28 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x3E4++0x03
|
|
line.long 0x00 "C28DSNUM,MDMAC Channel 28 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x3F0++0x03
|
|
line.long 0x00 "C29XFTYP,MDMAC Channel 29 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x3F4++0x03
|
|
line.long 0x00 "C29XFSAD,MDMAC Channel 29 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x3F8++0x03
|
|
line.long 0x00 "C29XFDAD,MDMAC Channel 29 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x3FC++0x03
|
|
line.long 0x00 "C29XFSIZ,MDMAC Channel 29 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "C29DSADS,MDMAC Channel 29 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x404++0x03
|
|
line.long 0x00 "C29DSNUM,MDMAC Channel 29 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "C30XFTYP,MDMAC Channel 30 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "C30XFSAD,MDMAC Channel 30 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x418++0x03
|
|
line.long 0x00 "C30XFDAD,MDMAC Channel 30 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x41C++0x03
|
|
line.long 0x00 "C30XFSIZ,MDMAC Channel 30 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x420++0x03
|
|
line.long 0x00 "C30DSADS,MDMAC Channel 30 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x424++0x03
|
|
line.long 0x00 "C30DSNUM,MDMAC Channel 30 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "C31XFTYP,MDMAC Channel 31 Number Avoidance Register"
|
|
bitfld.long 0x00 24. "DMODE,DMODE" "0,1"
|
|
bitfld.long 0x00 16. "UMODE,UMODE" "0,1"
|
|
bitfld.long 0x00 8.--10. "USIZE,USIZE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TTYPE,TTYPE" "0,1,2,3"
|
|
rgroup.long 0x434++0x03
|
|
line.long 0x00 "C31XFSAD,MDMAC Channel 31 Transfer Source Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "SRCAD,SRCAD"
|
|
rgroup.long 0x438++0x03
|
|
line.long 0x00 "C31XFDAD,MDMAC Channel 31 Transfer Destination Address Avoidance Register"
|
|
hexmask.long 0x00 0.--31. 1. "DSTAD,DSTAD"
|
|
rgroup.long 0x43C++0x03
|
|
line.long 0x00 "C31XFSIZ,MDMAC Channel 31 Transfer Size Avoidance Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "XFSIZ,XFSIZ"
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "C31DSADS,MDMAC Channel 31 Descriptor Address Avoidance Register"
|
|
hexmask.long 0x00 2.--31. 1. "DSADS,DSADS"
|
|
rgroup.long 0x444++0x03
|
|
line.long 0x00 "C31DSNUM,MDMAC Channel 31 Descriptor Number Avoidance Register"
|
|
bitfld.long 0x00 8. "DSINF,DSINF" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DSNUM,DSNUM"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "MSK,MDMAC Mask Register"
|
|
bitfld.long 0x00 31. "MSK31,MSK31" "0,1"
|
|
bitfld.long 0x00 30. "MSK30,MSK30" "0,1"
|
|
bitfld.long 0x00 29. "MSK29,MSK29" "0,1"
|
|
bitfld.long 0x00 28. "MSK28,MSK28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "MSK27,MSK27" "0,1"
|
|
bitfld.long 0x00 26. "MSK26,MSK26" "0,1"
|
|
bitfld.long 0x00 25. "MSK25,MSK25" "0,1"
|
|
bitfld.long 0x00 24. "MSK24,MSK24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "MSK23,MSK23" "0,1"
|
|
bitfld.long 0x00 22. "MSK22,MSK22" "0,1"
|
|
bitfld.long 0x00 21. "MSK21,MSK21" "0,1"
|
|
bitfld.long 0x00 20. "MSK20,MSK20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "MSK19,MSK19" "0,1"
|
|
bitfld.long 0x00 18. "MSK18,MSK18" "0,1"
|
|
bitfld.long 0x00 17. "MSK17,MSK17" "0,1"
|
|
bitfld.long 0x00 16. "MSK16,MSK16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "MSK15,MSK15" "0,1"
|
|
bitfld.long 0x00 14. "MSK14,MSK14" "0,1"
|
|
bitfld.long 0x00 13. "MSK13,MSK13" "0,1"
|
|
bitfld.long 0x00 12. "MSK12,MSK12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "MSK11,MSK11" "0,1"
|
|
bitfld.long 0x00 10. "MSK10,MSK10" "0,1"
|
|
bitfld.long 0x00 9. "MSK9,MSK9" "0,1"
|
|
bitfld.long 0x00 8. "MSK8,MSK8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "MSK7,MSK7" "0,1"
|
|
bitfld.long 0x00 6. "MSK6,MSK6" "0,1"
|
|
bitfld.long 0x00 5. "MSK5,MSK5" "0,1"
|
|
bitfld.long 0x00 4. "MSK4,MSK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MSK3,MSK3" "0,1"
|
|
bitfld.long 0x00 2. "MSK2,MSK2" "0,1"
|
|
bitfld.long 0x00 1. "MSK1,MSK1" "0,1"
|
|
bitfld.long 0x00 0. "MSK0,MSK0" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G8*")
|
|
tree "FURT (ARM Prime Cell PL011)"
|
|
repeat 2. (list 0. 1.) (list ad:0x400A8000 ad:0x400A9000)
|
|
tree "FURT$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Data Register"
|
|
rbitfld.long 0x00 11. "OE,OE" "0,1"
|
|
rbitfld.long 0x00 10. "BE,BE" "0,1"
|
|
rbitfld.long 0x00 9. "PE,PE" "0,1"
|
|
rbitfld.long 0x00 8. "FE,FE" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,DATA"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 3. "OE,OE" "0,1"
|
|
bitfld.long 0x00 2. "BE,BE" "0,1"
|
|
bitfld.long 0x00 1. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0. "FE,FE" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "ECR,Error Clear Register"
|
|
bitfld.long 0x00 3. "OE,OE" "0,1"
|
|
bitfld.long 0x00 2. "BE,BE" "0,1"
|
|
bitfld.long 0x00 1. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0. "FE,FE" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR,Flag Register"
|
|
bitfld.long 0x00 8. "RI,RI" "0,1"
|
|
bitfld.long 0x00 7. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x00 6. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x00 5. "TXFF,TXFF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RXFE,RXFE" "0,1"
|
|
bitfld.long 0x00 3. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x00 2. "DCD,DCD" "0,1"
|
|
bitfld.long 0x00 1. "DSR,DSR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CTS,CTS" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ILPR,IrDA Low-power Counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IPLDVSR,IPLDVSR"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IBDR,Integer Baud Rate Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "BAUDDIVINT,BAUDDIVINT"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FBDR,Fractional Baud Rate Register"
|
|
bitfld.long 0x00 0.--5. "BAUDDIVFRAC,BAUDDIVFRAC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "LCR_H,Line Control Register"
|
|
bitfld.long 0x00 7. "SPS,SPS" "0,1"
|
|
bitfld.long 0x00 5.--6. "WLEN,WLEN" "0,1,2,3"
|
|
bitfld.long 0x00 4. "FEN,FEN" "0,1"
|
|
bitfld.long 0x00 3. "STP2,STP2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EPS,EPS" "0,1"
|
|
bitfld.long 0x00 1. "PEN,PEN" "0,1"
|
|
bitfld.long 0x00 0. "BRK,BRK" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CR,Cntrol Register"
|
|
bitfld.long 0x00 15. "CTSEN,CTSEN" "0,1"
|
|
bitfld.long 0x00 14. "RTSEN,RTSEN" "0,1"
|
|
bitfld.long 0x00 13. "OUT2,OUT2" "0,1"
|
|
bitfld.long 0x00 12. "OUT1,OUT1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RTS,RTS" "0,1"
|
|
bitfld.long 0x00 10. "DTR,DTR" "0,1"
|
|
bitfld.long 0x00 9. "RXE,RXE" "0,1"
|
|
bitfld.long 0x00 8. "TXE,TXE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "LBE,LBE" "0,1"
|
|
bitfld.long 0x00 2. "SIRLP,SIRLP" "0,1"
|
|
bitfld.long 0x00 1. "SIREN,SIREN" "0,1"
|
|
bitfld.long 0x00 0. "UARTEN,UARTEN" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IFLS,Interrupt FIFO Level Select Register"
|
|
bitfld.long 0x00 3.--5. "RXIFLSEL,RXIFLSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TXIFLSEL,TXIFLSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IMSC,Interrupt Mask set_Clear Register"
|
|
bitfld.long 0x00 10. "OEIM,OEIM" "0,1"
|
|
bitfld.long 0x00 9. "BEIM,BEIM" "0,1"
|
|
bitfld.long 0x00 8. "PEIM,PEIM" "0,1"
|
|
bitfld.long 0x00 7. "FEIM,FEIM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTIM,RTIM" "0,1"
|
|
bitfld.long 0x00 5. "TXIM,TXIM" "0,1"
|
|
bitfld.long 0x00 4. "RXIM,RXIM" "0,1"
|
|
bitfld.long 0x00 3. "DSRMIM,DSRMIM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDMIM,DCDMIM" "0,1"
|
|
bitfld.long 0x00 1. "CTSMIM,CTSMIM" "0,1"
|
|
bitfld.long 0x00 0. "RIMIM,RIMIM" "0,1"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 10. "OERIS,OERIS" "0,1"
|
|
bitfld.long 0x00 9. "BERIS,BERIS" "0,1"
|
|
bitfld.long 0x00 8. "PERIS,PERIS" "0,1"
|
|
bitfld.long 0x00 7. "FERIS,FERIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTRIS,RTRIS" "0,1"
|
|
bitfld.long 0x00 5. "TXRIS,TXRIS" "0,1"
|
|
bitfld.long 0x00 4. "RXRIS,RXRIS" "0,1"
|
|
bitfld.long 0x00 3. "DSRRMIS,DSRRMIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDRMIS,DCDRMIS" "0,1"
|
|
bitfld.long 0x00 1. "CTSRMIS,CTSRMIS" "0,1"
|
|
bitfld.long 0x00 0. "RIRMIS,RIRMIS" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x00 10. "OEMIS,OEMIS" "0,1"
|
|
bitfld.long 0x00 9. "BEMIS,BEMIS" "0,1"
|
|
bitfld.long 0x00 8. "PEMIS,PEMIS" "0,1"
|
|
bitfld.long 0x00 7. "FEMIS,FEMIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTMIS,RTMIS" "0,1"
|
|
bitfld.long 0x00 5. "TXMIS,TXMIS" "0,1"
|
|
bitfld.long 0x00 4. "RXMIS,RXMIS" "0,1"
|
|
bitfld.long 0x00 3. "DSRMMIS,DSRMMIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDMMIS,DCDMMIS" "0,1"
|
|
bitfld.long 0x00 1. "CTSMMIS,CTSMMIS" "0,1"
|
|
bitfld.long 0x00 0. "RIMMIS,RIMMIS" "0,1"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 10. "OEIC,OEIC" "0,1"
|
|
bitfld.long 0x00 9. "BEIC,BEIC" "0,1"
|
|
bitfld.long 0x00 8. "PEIC,PEIC" "0,1"
|
|
bitfld.long 0x00 7. "FEIC,FEIC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTIC,RTIC" "0,1"
|
|
bitfld.long 0x00 5. "TXIC,TXIC" "0,1"
|
|
bitfld.long 0x00 4. "RXIC,RXIC" "0,1"
|
|
bitfld.long 0x00 3. "DSRMIC,DSRMIC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDMIC,DCDMIC" "0,1"
|
|
bitfld.long 0x00 1. "CTSMIC,CTSMIC" "0,1"
|
|
bitfld.long 0x00 0. "RIMIC,RIMIC" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMACR,DMA Control Register"
|
|
bitfld.long 0x00 2. "DMAONERR,DMAONERR" "0,1"
|
|
bitfld.long 0x00 1. "TXDMAE,TXDMAE" "0,1"
|
|
bitfld.long 0x00 0. "RXDMAE,RXDMAE" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "AD (ADC)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400BA000
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x4005A000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,AD Control Register 0"
|
|
bitfld.long 0x00 7. "ADEN,ADEN" "0,1"
|
|
bitfld.long 0x00 1. "SGL,SGL" "0,1"
|
|
bitfld.long 0x00 0. "CNT,CNT" "0,1"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,AD Control Register 1"
|
|
bitfld.long 0x00 6. "CNTDMEN,CNTDMEN" "0,1"
|
|
bitfld.long 0x00 5. "SGLDMEN,SGLDMEN" "0,1"
|
|
bitfld.long 0x00 4. "TRGDMEN,TRGDMEN" "0,1"
|
|
bitfld.long 0x00 0. "TRGEN,TRGEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,AD Control Register 1"
|
|
bitfld.long 0x00 0. "TRGEN,TRGEN" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ST,AD Status Register"
|
|
bitfld.long 0x00 7. "ADBF,ADBF" "0,1"
|
|
bitfld.long 0x00 3. "CNTF,CNTF" "0,1"
|
|
bitfld.long 0x00 2. "SNGF,SNGF" "0,1"
|
|
bitfld.long 0x00 1. "TRGF,TRGF" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ST,AD Status Register"
|
|
bitfld.long 0x00 7. "ADBF,ADBF" "0,1"
|
|
bitfld.long 0x00 3. "CNTF,CNTF" "0,1"
|
|
bitfld.long 0x00 2. "SNGF,SNGF" "0,1"
|
|
bitfld.long 0x00 1. "TRGF,TRGF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMDF,PMDF" "0,1"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,AD Conversion Clock Setting Register"
|
|
bitfld.long 0x00 3.--6. "EXAZ,EXAZ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "VADCLK,VADCLK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MOD0,AD Mode Control Register 0"
|
|
bitfld.long 0x00 1. "RCUT,RCUT" "0,1"
|
|
bitfld.long 0x00 0. "DACON,DACON" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MOD1,AD Mode Control Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MOD1,MOD1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MOD2,AD Mode Control Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "MOD2,MOD2"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPEN,AD Monitor function interrupt permission register"
|
|
bitfld.long 0x00 1. "CMP1EN,CMP1EN" "0,1"
|
|
bitfld.long 0x00 0. "CMP0EN,CMP0EN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPEN,AD Monitoring interrupt permission register"
|
|
bitfld.long 0x00 1. "CMP1EN,CMP1EN" "0,1"
|
|
bitfld.long 0x00 0. "CMP0EN,CMP0EN" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CMPCR0,AD Monitoring Setting Register 0"
|
|
bitfld.long 0x00 8.--11. "CMPCNT0,CMPCNT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "COMPCND0,COMPCND0" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG0,ADBIG0" "0,1"
|
|
bitfld.long 0x00 0.--2. "REGS0,REGS0" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CMPCR0,AD Monitor function Setting Register 0"
|
|
bitfld.long 0x00 8.--11. "CMPCNT0,CMPCNT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "CMPCND0,CMPCND0" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG0,ADBIG0" "0,1"
|
|
bitfld.long 0x00 0.--4. "REGS0,REGS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CMPCR1,AD Monitor function Setting Register 1"
|
|
bitfld.long 0x00 8.--11. "CMPCNT1,CMPCNT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "CMPCND1,CMPCND1" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG1,ADBIG1" "0,1"
|
|
bitfld.long 0x00 0.--4. "REGS1,REGS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CMPCR1,AD Monitoring Setting Register 1"
|
|
bitfld.long 0x00 8.--11. "CMPCNT1,CMPCNT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "COMPCND1,COMPCND1" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG1,ADBIG1" "0,1"
|
|
bitfld.long 0x00 0.--2. "REGS1,REGS1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CMP0,AD Conversion Result Comparison Register 0"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADCMP0,ADCMP0"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CMP0,AD Conversion Result Comparison Register 0"
|
|
hexmask.long.word 0x00 4.--15. 1. "AD0CMP0,AD0CMP0"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CMP1,AD Conversion Result Comparison Register 1"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADCMP1,ADCMP1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CMP1,AD Conversion Result Comparison Register 1"
|
|
hexmask.long.word 0x00 4.--15. 1. "AD0CMP1,AD0CMP1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CMPCR2,AD Conversion Monitor Function setting Register 2"
|
|
bitfld.long 0x00 8.--11. "CMPCNT2,CMPCNT2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "CMPCND2,CMPCND2" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG2,ADBIG2" "0,1"
|
|
rbitfld.long 0x00 0.--4. "REGS2,REGS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CMPCR3,AD Conversion Monitor Function setting Register 3"
|
|
bitfld.long 0x00 8.--11. "CMPCNT3,CMPCNT3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "CMPCND3,CMPCND3" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG3,ADBIG3" "0,1"
|
|
rbitfld.long 0x00 0.--4. "REGS3,REGS3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CMP2,AD Conversion Result Comparison Register 2"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADCMP2,ADCMP2"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CMP3,AD Conversion Result Comparison Register 3"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADCMP3,ADCMP3"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PSEL0,AD PMD Trigger Program Number Select Register 0"
|
|
bitfld.long 0x00 7. "PENS0,PENS0" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS0,PMDS0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PSEL1,AD PMD Trigger Program Number Select Register 1"
|
|
bitfld.long 0x00 7. "PENS1,PENS1" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS1,PMDS1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PSEL2,AD PMD Trigger Program Number Select Register 2"
|
|
bitfld.long 0x00 7. "PENS2,PENS2" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS2,PMDS2" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PSEL3,AD PMD Trigger Program Number Select Register 3"
|
|
bitfld.long 0x00 7. "PENS3,PENS3" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS3,PMDS3" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PSEL4,AD PMD Trigger Program Number Select Register 4"
|
|
bitfld.long 0x00 7. "PENS4,PENS4" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS4,PMDS4" "0,1,2,3,4,5,6,7"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PSEL5,AD PMD Trigger Program Number Select Register 5"
|
|
bitfld.long 0x00 7. "PENS5,PENS5" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS5,PMDS5" "0,1,2,3,4,5,6,7"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PSEL6,AD PMD Trigger Program Number Select Register 6"
|
|
bitfld.long 0x00 7. "PENS6,PENS6" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS6,PMDS6" "0,1,2,3,4,5,6,7"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PSEL7,AD PMD Trigger Program Number Select Register 7"
|
|
bitfld.long 0x00 7. "PENS7,PENS7" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS7,PMDS7" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PSEL8,AD PMD Trigger Program Number Select Register 8"
|
|
bitfld.long 0x00 7. "PENS8,PENS8" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS8,PMDS8" "0,1,2,3,4,5,6,7"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PSEL9,AD PMD Trigger Program Number Select Register 9"
|
|
bitfld.long 0x00 7. "PENS9,PENS9" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS9,PMDS9" "0,1,2,3,4,5,6,7"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PSEL10,AD PMD Trigger Program Number Select Register 10"
|
|
bitfld.long 0x00 7. "PENS10,PENS10" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS10,PMDS10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PSEL11,AD PMD Trigger Program Number Select Register 11"
|
|
bitfld.long 0x00 7. "PENS11,PENS11" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS11,PMDS11" "0,1,2,3,4,5,6,7"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PINTS0,AD PMD Trigger Interrupt Select Register 0"
|
|
bitfld.long 0x00 0.--1. "INTSEL0,INTSEL0" "0,1,2,3"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PINTS1,AD PMD Trigger Interrupt Select Register 1"
|
|
bitfld.long 0x00 0.--1. "INTSEL1,INTSEL1" "0,1,2,3"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PINTS2,AD PMD Trigger Interrupt Select Register 2"
|
|
bitfld.long 0x00 0.--1. "INTSEL2,INTSEL2" "0,1,2,3"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PINTS3,AD PMD Trigger Interrupt Select Register 3"
|
|
bitfld.long 0x00 0.--1. "INTSEL3,INTSEL3" "0,1,2,3"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PINTS4,AD PMD Trigger Interrupt Select Register 4"
|
|
bitfld.long 0x00 0.--1. "INTSEL4,INTSEL4" "0,1,2,3"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PINTS5,AD PMD Trigger Interrupt Select Register 5"
|
|
bitfld.long 0x00 0.--1. "INTSEL5,INTSEL5" "0,1,2,3"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PINTS6,AD PMD Trigger Interrupt Select Register 6"
|
|
bitfld.long 0x00 0.--1. "INTSEL6,INTSEL6" "0,1,2,3"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PINTS7,AD PMD Trigger Interrupt Select Register 7"
|
|
bitfld.long 0x00 0.--1. "INTSEL7,INTSEL7" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PREGS,AD PMD Trigger Conversion Result Storage Select Register 1"
|
|
bitfld.long 0x00 28.--30. "REGSEL7,REGSEL7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "REGSEL6,REGSEL6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. "REGSEL5,REGSEL5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "REGSEL4,REGSEL4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "REGSEL3,REGSEL3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "REGSEL2,REGSEL2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "REGSEL1,REGSEL1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "REGSEL0,REGSEL0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PSET0,AD PMD Trigger Program Register 0"
|
|
bitfld.long 0x00 31. "ENSP03,ENSP03" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS03,UVWIS03" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP03,AINSP03" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP02,ENSP02" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS02,UVWIS02" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP02,AINSP02" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP01,ENSP01" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS01,UVWIS01" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP01,AINSP01" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP00,ENSP00" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS00,UVWIS00" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP00,AINSP00" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "PSET1,AD PMD Trigger Program Register 1"
|
|
bitfld.long 0x00 31. "ENSP13,ENSP13" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS13,UVWIS13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP13,AINSP13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP12,ENSP12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS12,UVWIS12" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP12,AINSP12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP11,ENSP11" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS11,UVWIS11" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP11,AINSP11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP10,ENSP10" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS10,UVWIS10" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP10,AINSP10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PSET2,AD PMD Trigger Program Register 2"
|
|
bitfld.long 0x00 31. "ENSP23,ENSP23" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS23,UVWIS23" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP23,AINSP23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP22,ENSP22" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS22,UVWIS22" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP22,AINSP22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP21,ENSP21" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS21,UVWIS21" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP21,AINSP21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP20,ENSP20" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS20,UVWIS20" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP20,AINSP20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "PSET3,AD PMD Trigger Program Register 3"
|
|
bitfld.long 0x00 31. "ENSP33,ENSP33" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS33,UVWIS33" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP33,AINSP33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP32,ENSP32" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS32,UVWIS32" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP32,AINSP32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP31,ENSP31" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS31,UVWIS31" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP31,AINSP31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP30,ENSP30" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS30,UVWIS30" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP30,AINSP30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PSET4,AD PMD Trigger Program Register 4"
|
|
bitfld.long 0x00 31. "ENSP43,ENSP43" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS43,UVWIS43" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP43,AINSP43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP42,ENSP42" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS42,UVWIS42" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP42,AINSP42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP41,ENSP41" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS41,UVWIS41" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP41,AINSP41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP40,ENSP40" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS40,UVWIS40" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP40,AINSP40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "PSET5,AD PMD Trigger Program Register 5"
|
|
bitfld.long 0x00 31. "ENSP53,ENSP53" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS53,UVWIS53" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP53,AINSP53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP52,ENSP52" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS52,UVWIS52" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP52,AINSP52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP51,ENSP51" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS51,UVWIS51" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP51,AINSP51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP50,ENSP50" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS50,UVWIS50" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP50,AINSP50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PSET6,AD PMD Trigger Program Register 6"
|
|
bitfld.long 0x00 31. "ENSP63,ENSP63" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS63,UVWIS63" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP63,AINSP63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP62,ENSP62" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS62,UVWIS62" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP62,AINSP62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP61,ENSP61" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS61,UVWIS61" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP61,AINSP61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP60,ENSP60" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS60,UVWIS60" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP60,AINSP60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "PSET7,AD PMD Trigger Program Register 7"
|
|
bitfld.long 0x00 31. "ENSP73,ENSP73" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS73,UVWIS73" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP73,AINSP73" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP72,ENSP72" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS72,UVWIS72" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP72,AINSP72" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP71,ENSP71" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS71,UVWIS71" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP71,AINSP71" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP70,ENSP70" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS70,UVWIS70" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP70,AINSP70" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "EXAZSEL,AIN sampling period selection register"
|
|
hexmask.long 0x00 0.--31. 1. "EXAZSEL,EXAZSEL"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TSET0,AD General purpose Trigger Program Register 0"
|
|
bitfld.long 0x00 8.--10. "TRGS0,TRGS0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT0,ENINT0" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST0,AINST0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TSET0,AD General purpose Trigger Program Register 0"
|
|
bitfld.long 0x00 7. "ENINT0,ENINT0" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS0,TRGS0" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST0,AINST0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TSET1,AD General purpose Trigger Program Register 1"
|
|
bitfld.long 0x00 8.--10. "TRGS1,TRGS1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT1,ENINT1" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST1,AINST1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TSET1,AD General purpose Trigger Program Register 1"
|
|
bitfld.long 0x00 7. "ENINT1,ENINT1" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS1,TRGS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST1,AINST1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TSET2,AD General purpose Trigger Program Register 2"
|
|
bitfld.long 0x00 7. "ENINT2,ENINT2" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS2,TRGS2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST2,AINST2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TSET2,AD General purpose Trigger Program Register 2"
|
|
bitfld.long 0x00 8.--10. "TRGS2,TRGS2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT2,ENINT2" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST2,AINST2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TSET3,AD General purpose Trigger Program Register 3"
|
|
bitfld.long 0x00 7. "ENINT3,ENINT3" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS3,TRGS3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST3,AINST3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TSET3,AD General purpose Trigger Program Register 3"
|
|
bitfld.long 0x00 8.--10. "TRGS3,TRGS3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT3,ENINT3" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST3,AINST3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TSET4,AD General purpose Trigger Program Register 4"
|
|
bitfld.long 0x00 7. "ENINT4,ENINT4" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS4,TRGS4" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST4,AINST4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TSET4,AD General purpose Trigger Program Register 4"
|
|
bitfld.long 0x00 8.--10. "TRGS4,TRGS4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT4,ENINT4" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST4,AINST4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TSET5,AD General purpose Trigger Program Register 5"
|
|
bitfld.long 0x00 7. "ENINT5,ENINT5" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS5,TRGS5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST5,AINST5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TSET5,AD General purpose Trigger Program Register 5"
|
|
bitfld.long 0x00 8.--10. "TRGS5,TRGS5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT5,ENINT5" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST5,AINST5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TSET6,AD General purpose Trigger Program Register 6"
|
|
bitfld.long 0x00 7. "ENINT6,ENINT6" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS6,TRGS6" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST6,AINST6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TSET6,AD General purpose Trigger Program Register 6"
|
|
bitfld.long 0x00 8.--10. "TRGS6,TRGS6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT6,ENINT6" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST6,AINST6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TSET7,AD General purpose Trigger Program Register 7"
|
|
bitfld.long 0x00 7. "ENINT7,ENINT7" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS7,TRGS7" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST7,AINST7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TSET7,AD General purpose Trigger Program Register 7"
|
|
bitfld.long 0x00 8.--10. "TRGS7,TRGS7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT7,ENINT7" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST7,AINST7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TSET8,AD General purpose Trigger Program Register 8"
|
|
bitfld.long 0x00 7. "ENINT8,ENINT8" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS8,TRGS8" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST8,AINST8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TSET8,AD General purpose Trigger Program Register 8"
|
|
bitfld.long 0x00 8.--10. "TRGS8,TRGS8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT8,ENINT8" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST8,AINST8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TSET9,AD General purpose Trigger Program Register 9"
|
|
bitfld.long 0x00 7. "ENINT9,ENINT9" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS9,TRGS9" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST9,AINST9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TSET9,AD General purpose Trigger Program Register 9"
|
|
bitfld.long 0x00 8.--10. "TRGS9,TRGS9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT9,ENINT9" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST9,AINST9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TSET10,AD General purpose Trigger Program Register 10"
|
|
bitfld.long 0x00 7. "ENINT10,ENINT10" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS10,TRGS10" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST10,AINST10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TSET10,AD General purpose Trigger Program Register 10"
|
|
bitfld.long 0x00 8.--10. "TRGS10,TRGS10" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT10,ENINT10" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST10,AINST10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TSET11,AD General purpose Trigger Program Register 11"
|
|
bitfld.long 0x00 7. "ENINT11,ENINT11" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS11,TRGS11" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST11,AINST11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TSET11,AD General purpose Trigger Program Register 11"
|
|
bitfld.long 0x00 8.--10. "TRGS11,TRGS11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT11,ENINT11" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST11,AINST11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TSET12,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 7. "ENINT12,ENINT12" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS12,TRGS12" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST12,AINST12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TSET12,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 8.--10. "TRGS12,TRGS12" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT12,ENINT12" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST12,AINST12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TSET13,AD General purpose Trigger Program Register 13"
|
|
bitfld.long 0x00 7. "ENINT13,ENINT13" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS13,TRGS13" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST13,AINST13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TSET13,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 8.--10. "TRGS13,TRGS13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT13,ENINT13" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST13,AINST13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TSET14,AD General purpose Trigger Program Register 14"
|
|
bitfld.long 0x00 7. "ENINT14,ENINT14" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS14,TRGS14" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST14,AINST14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TSET14,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 8.--10. "TRGS14,TRGS14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT14,ENINT14" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST14,AINST14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TSET15,AD General purpose Trigger Program Register 15"
|
|
bitfld.long 0x00 7. "ENINT15,ENINT15" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS15,TRGS15" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST15,AINST15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TSET15,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 8.--10. "TRGS15,TRGS15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT15,ENINT15" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST15,AINST15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TSET16,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 8.--10. "TRGS16,TRGS16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT16,ENINT16" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST16,AINST16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TSET17,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 8.--10. "TRGS17,TRGS17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT17,ENINT17" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST17,AINST17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TSET18,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 8.--10. "TRGS18,TRGS18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT18,ENINT18" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST18,AINST18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TSET19,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 8.--10. "TRGS19,TRGS19" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT19,ENINT19" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST19,AINST19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TSET20,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 8.--10. "TRGS20,TRGS20" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT20,ENINT20" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST20,AINST20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TSET21,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 8.--10. "TRGS21,TRGS21" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT21,ENINT21" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST21,AINST21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TSET22,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 8.--10. "TRGS22,TRGS22" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT22,ENINT22" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST22,AINST22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TSET23,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 8.--10. "TRGS23,TRGS23" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "ENINT23,ENINT23" "0,1"
|
|
bitfld.long 0x00 0.--4. "AINST23,AINST23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "REG0,AD Conversion Result Register 0"
|
|
bitfld.long 0x00 29. "ADOVRF_M0,ADOVRF_M0" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M0,ADRF_M0" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M0,ADR_M0"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR0,ADR0"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF0,ADOVRF0" "0,1"
|
|
bitfld.long 0x00 0. "ADRF0,ADRF0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "REG0,AD AD Conversion Result Register 0"
|
|
bitfld.long 0x00 29. "ADOVR_M0,ADOVR_M0" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M0,ADRF_M0" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M0,ADR_M0"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR0,ADR0"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF0,ADOVRF0" "0,1"
|
|
bitfld.long 0x00 0. "ADRF0,ADRF0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "REG1,AD Conversion Result Register 1"
|
|
bitfld.long 0x00 29. "ADOVRF_M1,ADOVRF_M1" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M1,ADRF_M1" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M1,ADR_M1"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR1,ADR1"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF1,ADOVRF1" "0,1"
|
|
bitfld.long 0x00 0. "ADRF1,ADRF1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "REG1,AD Conversion Result Register 1"
|
|
bitfld.long 0x00 29. "ADOVR_M1,ADOVR_M1" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M1,ADRF_M1" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M1,ADR_M1"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR1,ADR1"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF1,ADOVRF1" "0,1"
|
|
bitfld.long 0x00 0. "ADRF1,ADRF1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "REG2,AD Conversion Result Register 2"
|
|
bitfld.long 0x00 29. "ADOVRF_M2,ADOVRF_M2" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M2,ADRF_M2" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M2,ADR_M2"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR2,ADR2"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF2,ADOVRF2" "0,1"
|
|
bitfld.long 0x00 0. "ADRF2,ADRF2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "REG2,AD Conversion Result Register 2"
|
|
bitfld.long 0x00 29. "ADOVR_M2,ADOVR_M2" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M2,ADRF_M2" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M2,ADR_M2"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR2,ADR2"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF2,ADOVRF2" "0,1"
|
|
bitfld.long 0x00 0. "ADRF2,ADRF2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "REG3,AD Conversion Result Register 3"
|
|
bitfld.long 0x00 29. "ADOVRF_M3,ADOVRF_M3" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M3,ADRF_M3" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M3,ADR_M3"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR3,ADR3"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF3,ADOVRF3" "0,1"
|
|
bitfld.long 0x00 0. "ADRF3,ADRF3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "REG3,AD Conversion Result Register 3"
|
|
bitfld.long 0x00 29. "ADOVR_M3,ADOVR_M3" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M3,ADRF_M3" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M3,ADR_M3"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR3,ADR3"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF3,ADOVRF3" "0,1"
|
|
bitfld.long 0x00 0. "ADRF3,ADRF3" "0,1"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "REG4,AD Conversion Result Register 4"
|
|
bitfld.long 0x00 29. "ADOVR_M4,ADOVR_M4" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M4,ADRF_M4" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M4,ADR_M4"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR4,ADR4"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF4,ADOVRF4" "0,1"
|
|
bitfld.long 0x00 0. "ADRF4,ADRF4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "REG4,AD Conversion Result Register 4"
|
|
bitfld.long 0x00 29. "ADOVRF_M4,ADOVRF_M4" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M4,ADRF_M4" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M4,ADR_M4"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR4,ADR4"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF4,ADOVRF4" "0,1"
|
|
bitfld.long 0x00 0. "ADRF4,ADRF4" "0,1"
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "REG5,AD Conversion Result Register 5"
|
|
bitfld.long 0x00 29. "ADOVRF_M5,ADOVRF_M5" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M5,ADRF_M5" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M5,ADR_M5"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR5,ADR5"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF5,ADOVRF5" "0,1"
|
|
bitfld.long 0x00 0. "ADRF5,ADRF5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "REG5,AD Conversion Result Register 5"
|
|
bitfld.long 0x00 29. "ADOVR_M5,ADOVR_M5" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M5,ADRF_M5" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M5,ADR_M5"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR5,ADR5"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF5,ADOVRF5" "0,1"
|
|
bitfld.long 0x00 0. "ADRF5,ADRF5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "REG6,AD Conversion Result Register 6"
|
|
bitfld.long 0x00 29. "ADOVRF_M6,ADOVRF_M6" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M6,ADRF_M6" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M6,ADR_M6"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR6,ADR6"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF6,ADOVRF6" "0,1"
|
|
bitfld.long 0x00 0. "ADRF6,ADRF6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "REG6,AD Conversion Result Register 6"
|
|
bitfld.long 0x00 29. "ADOVR_M6,ADOVR_M6" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M6,ADRF_M6" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M6,ADR_M6"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR6,ADR6"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF6,ADOVRF6" "0,1"
|
|
bitfld.long 0x00 0. "ADRF6,ADRF6" "0,1"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "REG7,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M7,ADOVR_M7" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M7,ADRF_M7" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M7,ADR_M7"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR7,ADR7"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF7,ADOVRF7" "0,1"
|
|
bitfld.long 0x00 0. "ADRF7,ADRF7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "REG7,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVRF_M7,ADOVRF_M7" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M7,ADRF_M7" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M7,ADR_M7"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR7,ADR7"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF7,ADOVRF7" "0,1"
|
|
bitfld.long 0x00 0. "ADRF7,ADRF7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "REG8,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M8,ADOVR_M8" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M8,ADRF_M8" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M8,ADR_M8"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR8,ADR8"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF8,ADOVRF8" "0,1"
|
|
bitfld.long 0x00 0. "ADRF8,ADRF8" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "REG8,AD Conversion Result Register 8"
|
|
bitfld.long 0x00 29. "ADOVRF_M8,ADOVRF_M8" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M8,ADRF_M8" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M8,ADR_M8"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR8,ADR8"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF8,ADOVRF8" "0,1"
|
|
bitfld.long 0x00 0. "ADRF8,ADRF8" "0,1"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "REG9,AD Conversion Result Register 9"
|
|
bitfld.long 0x00 29. "ADOVRF_M9,ADOVRF_M9" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M9,ADRF_M9" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M9,ADR_M9"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR9,ADR9"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF9,ADOVRF9" "0,1"
|
|
bitfld.long 0x00 0. "ADRF9,ADRF9" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "REG9,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M9,ADOVR_M9" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M9,ADRF_M9" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M9,ADR_M9"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR9,ADR9"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF9,ADOVRF9" "0,1"
|
|
bitfld.long 0x00 0. "ADRF9,ADRF9" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "REG10,AD Conversion Result Register 10"
|
|
bitfld.long 0x00 29. "ADOVRF_M10,ADOVRF_M10" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M10,ADRF_M10" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M10,ADR_M10"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR10,ADR10"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF10,ADOVRF10" "0,1"
|
|
bitfld.long 0x00 0. "ADRF10,ADRF10" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "REG10,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M10,ADOVR_M10" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M10,ADRF_M10" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M10,ADR_M10"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR10,ADR10"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF10,ADOVRF10" "0,1"
|
|
bitfld.long 0x00 0. "ADRF10,ADRF10" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "REG11,AD Conversion Result Register 11"
|
|
bitfld.long 0x00 29. "ADOVRF_M11,ADOVRF_M11" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M11,ADRF_M11" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M11,ADR_M11"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR11,ADR11"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF11,ADOVRF11" "0,1"
|
|
bitfld.long 0x00 0. "ADRF11,ADRF11" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "REG11,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M11,ADOVR_M11" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M11,ADRF_M11" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M11,ADR_M11"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR11,ADR11"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF11,ADOVRF11" "0,1"
|
|
bitfld.long 0x00 0. "ADRF11,ADRF11" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "REG12,AD Conversion Result Register 12"
|
|
bitfld.long 0x00 29. "ADOVRF_M12,ADOVRF_M12" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M12,ADRF_M12" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M12,ADR_M12"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR12,ADR12"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF12,ADOVRF12" "0,1"
|
|
bitfld.long 0x00 0. "ADRF12,ADRF12" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "REG12,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M12,ADOVR_M12" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M12,ADRF_M12" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M12,ADR_M12"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR12,ADR12"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF12,ADOVRF12" "0,1"
|
|
bitfld.long 0x00 0. "ADRF12,ADRF12" "0,1"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "REG13,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M13,ADOVR_M13" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M13,ADRF_M13" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M13,ADR_M13"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR13,ADR13"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF13,ADOVRF13" "0,1"
|
|
bitfld.long 0x00 0. "ADRF13,ADRF13" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "REG13,AD Conversion Result Register 13"
|
|
bitfld.long 0x00 29. "ADOVRF_M13,ADOVRF_M13" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M13,ADRF_M13" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M13,ADR_M13"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR13,ADR13"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF13,ADOVRF13" "0,1"
|
|
bitfld.long 0x00 0. "ADRF13,ADRF13" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "REG14,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M14,ADOVR_M14" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M14,ADRF_M14" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M14,ADR_M14"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR14,ADR14"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF14,ADOVRF14" "0,1"
|
|
bitfld.long 0x00 0. "ADRF14,ADRF14" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "REG14,AD Conversion Result Register 14"
|
|
bitfld.long 0x00 29. "ADOVRF_M14,ADOVRF_M14" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M14,ADRF_M14" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M14,ADR_M14"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR14,ADR14"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF14,ADOVRF14" "0,1"
|
|
bitfld.long 0x00 0. "ADRF14,ADRF14" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "REG15,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M15,ADOVR_M15" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M15,ADRF_M15" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M15,ADR_M15"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR15,ADR15"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF15,ADOVRF15" "0,1"
|
|
bitfld.long 0x00 0. "ADRF15,ADRF15" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "REG15,AD Conversion Result Register 15"
|
|
bitfld.long 0x00 29. "ADOVRF_M15,ADOVRF_M15" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M15,ADRF_M15" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M15,ADR_M15"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR15,ADR15"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF15,ADOVRF15" "0,1"
|
|
bitfld.long 0x00 0. "ADRF15,ADRF15" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "REG16,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M16,ADOVR_M16" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M16,ADRF_M16" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M16,ADR_M16"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR16,ADR16"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF16,ADOVRF16" "0,1"
|
|
bitfld.long 0x00 0. "ADRF16,ADRF16" "0,1"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "REG17,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M17,ADOVR_M17" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M17,ADRF_M17" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M17,ADR_M17"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR17,ADR17"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF17,ADOVRF17" "0,1"
|
|
bitfld.long 0x00 0. "ADRF17,ADRF17" "0,1"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "REG18,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M18,ADOVR_M18" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M18,ADRF_M18" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M18,ADR_M18"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR18,ADR18"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF18,ADOVRF18" "0,1"
|
|
bitfld.long 0x00 0. "ADRF18,ADRF18" "0,1"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "REG19,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M19,ADOVR_M19" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M19,ADRF_M19" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M19,ADR_M19"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR19,ADR19"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF19,ADOVRF19" "0,1"
|
|
bitfld.long 0x00 0. "ADRF19,ADRF19" "0,1"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "REG20,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M20,ADOVR_M20" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M20,ADRF_M20" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M20,ADR_M20"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR20,ADR20"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF20,ADOVRF20" "0,1"
|
|
bitfld.long 0x00 0. "ADRF20,ADRF20" "0,1"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "REG21,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M21,ADOVR_M21" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M21,ADRF_M21" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M21,ADR_M21"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR21,ADR21"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF21,ADOVRF21" "0,1"
|
|
bitfld.long 0x00 0. "ADRF21,ADRF21" "0,1"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "REG22,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M22,ADOVR_M22" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M22,ADRF_M22" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M22,ADR_M22"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR22,ADR22"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF22,ADOVRF22" "0,1"
|
|
bitfld.long 0x00 0. "ADRF22,ADRF22" "0,1"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "REG23,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVR_M23,ADOVR_M23" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M23,ADRF_M23" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M23,ADR_M23"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR23,ADR23"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF23,ADOVRF23" "0,1"
|
|
bitfld.long 0x00 0. "ADRF23,ADRF23" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400B8800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,AD Control Register 0"
|
|
bitfld.long 0x00 7. "ADEN,ADEN" "0,1"
|
|
bitfld.long 0x00 1. "SGL,SGL" "0,1"
|
|
bitfld.long 0x00 0. "CNT,CNT" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,AD Control Register 1"
|
|
bitfld.long 0x00 6. "CNTDMEN,CNTDMEN" "0,1"
|
|
bitfld.long 0x00 5. "SGLDMEN,SGLDMEN" "0,1"
|
|
bitfld.long 0x00 4. "TRGDMEN,TRGDMEN" "0,1"
|
|
bitfld.long 0x00 0. "TRGEN,TRGEN" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ST,AD Status Register"
|
|
bitfld.long 0x00 7. "ADBF,ADBF" "0,1"
|
|
bitfld.long 0x00 3. "CNTF,CNTF" "0,1"
|
|
bitfld.long 0x00 2. "SNGF,SNGF" "0,1"
|
|
bitfld.long 0x00 1. "TRGF,TRGF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMDF,PMDF" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,AD Conversion Clock Setting Register"
|
|
bitfld.long 0x00 3.--6. "EXAZ,EXAZ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "VADCLK,VADCLK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MOD0,AD Mode Control Register 0"
|
|
bitfld.long 0x00 3. "AZFSH,AZFSH" "0,1"
|
|
bitfld.long 0x00 2. "REFBSEL,REFBSEL" "0,1"
|
|
bitfld.long 0x00 1. "RCUT,RCUT" "0,1"
|
|
bitfld.long 0x00 0. "DACON,DACON" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MOD1,AD Mode Control Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MOD1,MOD1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MOD2,AD Mode Control Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "MOD2,MOD2"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPEN,AD Monitoring interrupt permission register"
|
|
bitfld.long 0x00 1. "CMP1EN,CMP1EN" "0,1"
|
|
bitfld.long 0x00 0. "CMP0EN,CMP0EN" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CMPCR0,AD Monitoring Setting Register 0"
|
|
bitfld.long 0x00 8.--11. "CMPCNT0,CMPCNT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "CMPCND0,CMPCND0" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG0,ADBIG0" "0,1"
|
|
bitfld.long 0x00 0.--4. "REGS0,REGS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CMPCR1,AD Monitoring Setting Register 1"
|
|
bitfld.long 0x00 8.--11. "CMPCNT1,CMPCNT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "CMPCND1,CMPCND1" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG1,ADBIG1" "0,1"
|
|
bitfld.long 0x00 0.--4. "REGS1,REGS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CMP0,AD Conversion Result Comparison Register 0"
|
|
hexmask.long.word 0x00 4.--15. 1. "AD0CMP0,AD0CMP0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CMP1,AD Conversion Result Comparison Register 1"
|
|
hexmask.long.word 0x00 4.--15. 1. "AD0CMP1,AD0CMP1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PSEL0,AD PMD Trigger Program Number Select Register 0"
|
|
bitfld.long 0x00 7. "PENS0,PENS0" "0,1"
|
|
bitfld.long 0x00 0.--3. "PMDS0,PMDS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PSEL1,AD PMD Trigger Program Number Select Register 1"
|
|
bitfld.long 0x00 7. "PENS1,PENS1" "0,1"
|
|
bitfld.long 0x00 0.--3. "PMDS1,PMDS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PSEL2,AD PMD Trigger Program Number Select Register 2"
|
|
bitfld.long 0x00 7. "PENS2,PENS2" "0,1"
|
|
bitfld.long 0x00 0.--3. "PMDS2,PMDS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PSEL3,AD PMD Trigger Program Number Select Register 3"
|
|
bitfld.long 0x00 7. "PENS3,PENS3" "0,1"
|
|
bitfld.long 0x00 0.--3. "PMDS3,PMDS3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PSEL4,AD PMD Trigger Program Number Select Register 4"
|
|
bitfld.long 0x00 7. "PENS4,PENS4" "0,1"
|
|
bitfld.long 0x00 0.--3. "PMDS4,PMDS4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PSEL5,AD PMD Trigger Program Number Select Register 5"
|
|
bitfld.long 0x00 7. "PENS5,PENS5" "0,1"
|
|
bitfld.long 0x00 0.--3. "PMDS5,PMDS5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PSEL6,AD PMD Trigger Program Number Select Register 6"
|
|
bitfld.long 0x00 7. "PENS6,PENS6" "0,1"
|
|
bitfld.long 0x00 0.--3. "PMDS6,PMDS6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PSEL7,AD PMD Trigger Program Number Select Register 7"
|
|
bitfld.long 0x00 7. "PENS7,PENS7" "0,1"
|
|
bitfld.long 0x00 0.--3. "PMDS7,PMDS7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PSEL8,AD PMD Trigger Program Number Select Register 8"
|
|
bitfld.long 0x00 7. "PENS8,PENS8" "0,1"
|
|
bitfld.long 0x00 0.--3. "PMDS8,PMDS8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PSEL9,AD PMD Trigger Program Number Select Register 9"
|
|
bitfld.long 0x00 7. "PENS9,PENS9" "0,1"
|
|
bitfld.long 0x00 0.--3. "PMDS9,PMDS9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PSEL10,AD PMD Trigger Program Number Select Register 10"
|
|
bitfld.long 0x00 7. "PENS10,PENS10" "0,1"
|
|
bitfld.long 0x00 0.--3. "PMDS10,PMDS10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PSEL11,AD PMD Trigger Program Number Select Register 11"
|
|
bitfld.long 0x00 7. "PENS11,PENS11" "0,1"
|
|
bitfld.long 0x00 0.--3. "PMDS11,PMDS11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PINTS0,AD PMD Trigger Interrupt Select Register 0"
|
|
bitfld.long 0x00 0.--2. "INTSEL0,INTSEL0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PINTS1,AD PMD Trigger Interrupt Select Register 1"
|
|
bitfld.long 0x00 0.--2. "INTSEL1,INTSEL1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PINTS2,AD PMD Trigger Interrupt Select Register 2"
|
|
bitfld.long 0x00 0.--2. "INTSEL2,INTSEL2" "0,1,2,3,4,5,6,7"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PINTS3,AD PMD Trigger Interrupt Select Register 3"
|
|
bitfld.long 0x00 0.--2. "INTSEL3,INTSEL3" "0,1,2,3,4,5,6,7"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PINTS4,AD PMD Trigger Interrupt Select Register 4"
|
|
bitfld.long 0x00 0.--2. "INTSEL4,INTSEL4" "0,1,2,3,4,5,6,7"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PINTS5,AD PMD Trigger Interrupt Select Register 5"
|
|
bitfld.long 0x00 0.--2. "INTSEL5,INTSEL5" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PINTS6,AD PMD Trigger Interrupt Select Register 6"
|
|
bitfld.long 0x00 0.--2. "INTSEL6,INTSEL6" "0,1,2,3,4,5,6,7"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PINTS7,AD PMD Trigger Interrupt Select Register 7"
|
|
bitfld.long 0x00 0.--2. "INTSEL7,INTSEL7" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PINTS8,AD PMD Trigger Interrupt Select Register 8"
|
|
bitfld.long 0x00 0.--2. "INTSEL8,INTSEL8" "0,1,2,3,4,5,6,7"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PREGS0,AD PMD Trigger Conversion Result Storage Select Register 1"
|
|
bitfld.long 0x00 28.--30. "REGSEL7,REGSEL7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "REGSEL6,REGSEL6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. "REGSEL5,REGSEL5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "REGSEL4,REGSEL4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "REGSEL3,REGSEL3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "REGSEL2,REGSEL2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "REGSEL1,REGSEL1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "REGSEL0,REGSEL0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PREGS1,AD PMD Trigger Conversion Result Storage Select Register 2"
|
|
bitfld.long 0x00 0.--2. "REGSEL8,REGSEL8" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PSET0,AD PMD Trigger Program Register 0"
|
|
bitfld.long 0x00 31. "ENSP03,ENSP03" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS03,UVWIS03" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP03,AINSP03" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP02,ENSP02" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS02,UVWIS02" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP02,AINSP02" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP01,ENSP01" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS01,UVWIS01" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP01,AINSP01" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP00,ENSP00" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS00,UVWIS00" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP00,AINSP00" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "PSET1,AD PMD Trigger Program Register 1"
|
|
bitfld.long 0x00 31. "ENSP13,ENSP13" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS13,UVWIS13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP13,AINSP13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP12,ENSP12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS12,UVWIS12" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP12,AINSP12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP11,ENSP11" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS11,UVWIS11" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP11,AINSP11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP10,ENSP10" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS10,UVWIS10" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP10,AINSP10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PSET2,AD PMD Trigger Program Register 2"
|
|
bitfld.long 0x00 31. "ENSP23,ENSP23" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS23,UVWIS23" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP23,AINSP23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP22,ENSP22" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS22,UVWIS22" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP22,AINSP22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP21,ENSP21" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS21,UVWIS21" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP21,AINSP21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP20,ENSP20" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS20,UVWIS20" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP20,AINSP20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "PSET3,AD PMD Trigger Program Register 3"
|
|
bitfld.long 0x00 31. "ENSP33,ENSP33" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS33,UVWIS33" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP33,AINSP33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP32,ENSP32" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS32,UVWIS32" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP32,AINSP32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP31,ENSP31" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS31,UVWIS31" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP31,AINSP31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP30,ENSP30" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS30,UVWIS30" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP30,AINSP30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xB0++0x03
|
|
line.long 0x00 "PSET4,AD PMD Trigger Program Register 4"
|
|
bitfld.long 0x00 31. "ENSP43,ENSP43" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS43,UVWIS43" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP43,AINSP43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 23. "ENSP42,ENSP42" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS42,UVWIS42" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP42,AINSP42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 15. "ENSP41,ENSP41" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS41,UVWIS41" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP41,AINSP41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 7. "ENSP40,ENSP40" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS40,UVWIS40" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP40,AINSP40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xB4++0x03
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|
line.long 0x00 "PSET5,AD PMD Trigger Program Register 5"
|
|
bitfld.long 0x00 31. "ENSP53,ENSP53" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS53,UVWIS53" "0,1,2,3"
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|
bitfld.long 0x00 24.--28. "AINSP53,AINSP53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 23. "ENSP52,ENSP52" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS52,UVWIS52" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP52,AINSP52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 15. "ENSP51,ENSP51" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS51,UVWIS51" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP51,AINSP51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 7. "ENSP50,ENSP50" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS50,UVWIS50" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP50,AINSP50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xB8++0x03
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|
line.long 0x00 "PSET6,AD PMD Trigger Program Register 6"
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|
bitfld.long 0x00 31. "ENSP63,ENSP63" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS63,UVWIS63" "0,1,2,3"
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|
bitfld.long 0x00 24.--28. "AINSP63,AINSP63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 23. "ENSP62,ENSP62" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS62,UVWIS62" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP62,AINSP62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 15. "ENSP61,ENSP61" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS61,UVWIS61" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP61,AINSP61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 7. "ENSP60,ENSP60" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS60,UVWIS60" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP60,AINSP60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xBC++0x03
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|
line.long 0x00 "PSET7,AD PMD Trigger Program Register 7"
|
|
bitfld.long 0x00 31. "ENSP73,ENSP73" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS73,UVWIS73" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP73,AINSP73" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 23. "ENSP72,ENSP72" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS72,UVWIS72" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP72,AINSP72" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 15. "ENSP71,ENSP71" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS71,UVWIS71" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP71,AINSP71" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 7. "ENSP70,ENSP70" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS70,UVWIS70" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP70,AINSP70" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xC0++0x03
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|
line.long 0x00 "PSET8,AD PMD Trigger Program Register 8"
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|
bitfld.long 0x00 31. "ENSP83,ENSP83" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS83,UVWIS83" "0,1,2,3"
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|
bitfld.long 0x00 24.--28. "AINSP83,AINSP83" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 23. "ENSP82,ENSP82" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS82,UVWIS82" "0,1,2,3"
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|
bitfld.long 0x00 16.--20. "AINSP82,AINSP82" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 15. "ENSP81,ENSP81" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS81,UVWIS81" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP81,AINSP81" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "ENSP80,ENSP80" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS80,UVWIS80" "0,1,2,3"
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|
bitfld.long 0x00 0.--4. "AINSP80,AINSP80" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xC4++0x03
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|
line.long 0x00 "TSET0,AD General purpose Trigger Program Register 0"
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|
bitfld.long 0x00 7. "ENINT0,ENINT0" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS0,TRGS0" "0,1,2,3"
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|
bitfld.long 0x00 0.--4. "AINST0,AINST0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xC8++0x03
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line.long 0x00 "TSET1,AD General purpose Trigger Program Register 1"
|
|
bitfld.long 0x00 7. "ENINT1,ENINT1" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS1,TRGS1" "0,1,2,3"
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bitfld.long 0x00 0.--4. "AINST1,AINST1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xCC++0x03
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line.long 0x00 "TSET2,AD General purpose Trigger Program Register 2"
|
|
bitfld.long 0x00 7. "ENINT2,ENINT2" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS2,TRGS2" "0,1,2,3"
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|
bitfld.long 0x00 0.--4. "AINST2,AINST2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xD0++0x03
|
|
line.long 0x00 "TSET3,AD General purpose Trigger Program Register 3"
|
|
bitfld.long 0x00 7. "ENINT3,ENINT3" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS3,TRGS3" "0,1,2,3"
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bitfld.long 0x00 0.--4. "AINST3,AINST3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xD4++0x03
|
|
line.long 0x00 "TSET4,AD General purpose Trigger Program Register 4"
|
|
bitfld.long 0x00 7. "ENINT4,ENINT4" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS4,TRGS4" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST4,AINST4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TSET5,AD General purpose Trigger Program Register 5"
|
|
bitfld.long 0x00 7. "ENINT5,ENINT5" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS5,TRGS5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST5,AINST5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TSET6,AD General purpose Trigger Program Register 6"
|
|
bitfld.long 0x00 7. "ENINT6,ENINT6" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS6,TRGS6" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST6,AINST6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TSET7,AD General purpose Trigger Program Register 7"
|
|
bitfld.long 0x00 7. "ENINT7,ENINT7" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS7,TRGS7" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST7,AINST7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TSET8,AD General purpose Trigger Program Register 8"
|
|
bitfld.long 0x00 7. "ENINT8,ENINT8" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS8,TRGS8" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST8,AINST8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TSET9,AD General purpose Trigger Program Register 9"
|
|
bitfld.long 0x00 7. "ENINT9,ENINT9" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS9,TRGS9" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST9,AINST9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TSET10,AD General purpose Trigger Program Register 10"
|
|
bitfld.long 0x00 7. "ENINT10,ENINT10" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS10,TRGS10" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST10,AINST10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TSET11,AD General purpose Trigger Program Register 11"
|
|
bitfld.long 0x00 7. "ENINT11,ENINT11" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS11,TRGS11" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST11,AINST11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TSET12,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 7. "ENINT12,ENINT12" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS12,TRGS12" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST12,AINST12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TSET13,AD General purpose Trigger Program Register 13"
|
|
bitfld.long 0x00 7. "ENINT13,ENINT13" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS13,TRGS13" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST13,AINST13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TSET14,AD General purpose Trigger Program Register 14"
|
|
bitfld.long 0x00 7. "ENINT14,ENINT14" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS14,TRGS14" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST14,AINST14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TSET15,AD General purpose Trigger Program Register 15"
|
|
bitfld.long 0x00 7. "ENINT15,ENINT15" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS15,TRGS15" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST15,AINST15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TSET16,AD General purpose Trigger Program Register 16"
|
|
bitfld.long 0x00 7. "ENINT16,ENINT16" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS16,TRGS16" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST16,AINST16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TSET17,AD General purpose Trigger Program Register 17"
|
|
bitfld.long 0x00 7. "ENINT17,ENINT17" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS17,TRGS17" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST17,AINST17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TSET18,AD General purpose Trigger Program Register 18"
|
|
bitfld.long 0x00 7. "ENINT18,ENINT18" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS18,TRGS18" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST18,AINST18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TSET19,AD General purpose Trigger Program Register 19"
|
|
bitfld.long 0x00 7. "ENINT19,ENINT19" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS19,TRGS19" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST19,AINST19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TSET20,AD General purpose Trigger Program Register 20"
|
|
bitfld.long 0x00 7. "ENINT20,ENINT20" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS20,TRGS20" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST20,AINST20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TSET21,AD General purpose Trigger Program Register 21"
|
|
bitfld.long 0x00 7. "ENINT21,ENINT21" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS21,TRGS21" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST21,AINST21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TSET22,AD General purpose Trigger Program Register 22"
|
|
bitfld.long 0x00 7. "ENINT22,ENINT22" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS22,TRGS22" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST22,AINST22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TSET23,AD General purpose Trigger Program Register 23"
|
|
bitfld.long 0x00 7. "ENINT23,ENINT23" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS23,TRGS23" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST23,AINST23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TSET24,AD General purpose Trigger Program Register 24"
|
|
bitfld.long 0x00 7. "ENINT24,ENINT24" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS24,TRGS24" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST24,AINST24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TSET25,AD General purpose Trigger Program Register 25"
|
|
bitfld.long 0x00 7. "ENINT25,ENINT25" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS25,TRGS25" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST25,AINST25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TSET26,AD General purpose Trigger Program Register 26"
|
|
bitfld.long 0x00 7. "ENINT26,ENINT26" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS26,TRGS26" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST26,AINST26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TSET27,AD General purpose Trigger Program Register 27"
|
|
bitfld.long 0x00 7. "ENINT27,ENINT27" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS27,TRGS27" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST27,AINST27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TSET28,AD General purpose Trigger Program Register 28"
|
|
bitfld.long 0x00 7. "ENINT28,ENINT28" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS28,TRGS28" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST28,AINST28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TSET29,AD General purpose Trigger Program Register 29"
|
|
bitfld.long 0x00 7. "ENINT29,ENINT29" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS29,TRGS29" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST29,AINST29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TSET30,AD General purpose Trigger Program Register 30"
|
|
bitfld.long 0x00 7. "ENINT30,ENINT30" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS30,TRGS30" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST30,AINST30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TSET31,AD General purpose Trigger Program Register 31"
|
|
bitfld.long 0x00 7. "ENINT31,ENINT31" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS31,TRGS31" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST31,AINST31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "REG0,AD AD Conversion Result Register 0"
|
|
bitfld.long 0x00 29. "ADOVRF_M0,ADOVRF_M0" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M0,ADRF_M0" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M0,ADR_M0"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR0,ADR0"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF0,ADOVRF0" "0,1"
|
|
bitfld.long 0x00 0. "ADRF0,ADRF0" "0,1"
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "REG1,AD Conversion Result Register 1"
|
|
bitfld.long 0x00 29. "ADOVRF_M1,ADOVRF_M1" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M1,ADRF_M1" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M1,ADR_M1"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR1,ADR1"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF1,ADOVRF1" "0,1"
|
|
bitfld.long 0x00 0. "ADRF1,ADRF1" "0,1"
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "REG2,AD Conversion Result Register 2"
|
|
bitfld.long 0x00 29. "ADOVRF_M2,ADOVRF_M2" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M2,ADRF_M2" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M2,ADR_M2"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR2,ADR2"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF2,ADOVRF2" "0,1"
|
|
bitfld.long 0x00 0. "ADRF2,ADRF2" "0,1"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "REG3,AD Conversion Result Register 3"
|
|
bitfld.long 0x00 29. "ADOVRF_M3,ADOVRF_M3" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M3,ADRF_M3" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M3,ADR_M3"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR3,ADR3"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF3,ADOVRF3" "0,1"
|
|
bitfld.long 0x00 0. "ADRF3,ADRF3" "0,1"
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "REG4,AD Conversion Result Register 4"
|
|
bitfld.long 0x00 29. "ADOVRF_M4,ADOVRF_M4" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M4,ADRF_M4" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M4,ADR_M4"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR4,ADR4"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF4,ADOVRF4" "0,1"
|
|
bitfld.long 0x00 0. "ADRF4,ADRF4" "0,1"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "REG5,AD Conversion Result Register 5"
|
|
bitfld.long 0x00 29. "ADOVRF_M5,ADOVRF_M5" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M5,ADRF_M5" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M5,ADR_M5"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR5,ADR5"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF5,ADOVRF5" "0,1"
|
|
bitfld.long 0x00 0. "ADRF5,ADRF5" "0,1"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "REG6,AD Conversion Result Register 6"
|
|
bitfld.long 0x00 29. "ADOVRF_M6,ADOVRF_M6" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M6,ADRF_M6" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M6,ADR_M6"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR6,ADR6"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF6,ADOVRF6" "0,1"
|
|
bitfld.long 0x00 0. "ADRF6,ADRF6" "0,1"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "REG7,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVRF_M7,ADOVRF_M7" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M7,ADRF_M7" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M7,ADR_M7"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR7,ADR7"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF7,ADOVRF7" "0,1"
|
|
bitfld.long 0x00 0. "ADRF7,ADRF7" "0,1"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "REG8,AD Conversion Result Register 8"
|
|
bitfld.long 0x00 29. "ADOVRF_M8,ADOVRF_M8" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M8,ADRF_M8" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M8,ADR_M8"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR8,ADR8"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF8,ADOVRF8" "0,1"
|
|
bitfld.long 0x00 0. "ADRF8,ADRF8" "0,1"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "REG9,AD Conversion Result Register 9"
|
|
bitfld.long 0x00 29. "ADOVRF_M9,ADOVRF_M9" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M9,ADRF_M9" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M9,ADR_M9"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR9,ADR9"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF9,ADOVRF9" "0,1"
|
|
bitfld.long 0x00 0. "ADRF9,ADRF9" "0,1"
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "REG10,AD Conversion Result Register 10"
|
|
bitfld.long 0x00 29. "ADOVRF_M10,ADOVRF_M10" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M10,ADRF_M10" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M10,ADR_M10"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR10,ADR10"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF10,ADOVRF10" "0,1"
|
|
bitfld.long 0x00 0. "ADRF10,ADRF10" "0,1"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "REG11,AD Conversion Result Register 11"
|
|
bitfld.long 0x00 29. "ADOVRF_M11,ADOVRF_M11" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M11,ADRF_M11" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M11,ADR_M11"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR11,ADR11"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF11,ADOVRF11" "0,1"
|
|
bitfld.long 0x00 0. "ADRF11,ADRF11" "0,1"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "REG12,AD Conversion Result Register 12"
|
|
bitfld.long 0x00 29. "ADOVRF_M12,ADOVRF_M12" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M12,ADRF_M12" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M12,ADR_M12"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR12,ADR12"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF12,ADOVRF12" "0,1"
|
|
bitfld.long 0x00 0. "ADRF12,ADRF12" "0,1"
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "REG13,AD Conversion Result Register 13"
|
|
bitfld.long 0x00 29. "ADOVRF_M13,ADOVRF_M13" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M13,ADRF_M13" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M13,ADR_M13"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR13,ADR13"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF13,ADOVRF13" "0,1"
|
|
bitfld.long 0x00 0. "ADRF13,ADRF13" "0,1"
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "REG14,AD Conversion Result Register 14"
|
|
bitfld.long 0x00 29. "ADOVRF_M14,ADOVRF_M14" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M14,ADRF_M14" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M14,ADR_M14"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR14,ADR14"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF14,ADOVRF14" "0,1"
|
|
bitfld.long 0x00 0. "ADRF14,ADRF14" "0,1"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "REG15,AD Conversion Result Register 15"
|
|
bitfld.long 0x00 29. "ADOVRF_M15,ADOVRF_M15" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M15,ADRF_M15" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M15,ADR_M15"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR15,ADR15"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF15,ADOVRF15" "0,1"
|
|
bitfld.long 0x00 0. "ADRF15,ADRF15" "0,1"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "REG16,AD Conversion Result Register 16"
|
|
bitfld.long 0x00 29. "ADOVRF_M16,ADOVRF_M16" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M16,ADRF_M16" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M16,ADR_M16"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR16,ADR16"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF16,ADOVRF16" "0,1"
|
|
bitfld.long 0x00 0. "ADRF16,ADRF16" "0,1"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "REG17,AD Conversion Result Register 17"
|
|
bitfld.long 0x00 29. "ADOVRF_M17,ADOVRF_M17" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M17,ADRF_M17" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M17,ADR_M17"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR17,ADR17"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF17,ADOVRF17" "0,1"
|
|
bitfld.long 0x00 0. "ADRF17,ADRF17" "0,1"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "REG18,AD Conversion Result Register 18"
|
|
bitfld.long 0x00 29. "ADOVRF_M18,ADOVRF_M18" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M18,ADRF_M18" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M18,ADR_M18"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR18,ADR18"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF18,ADOVRF18" "0,1"
|
|
bitfld.long 0x00 0. "ADRF18,ADRF18" "0,1"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "REG19,AD Conversion Result Register 19"
|
|
bitfld.long 0x00 29. "ADOVRF_M19,ADOVRF_M19" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M19,ADRF_M19" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M19,ADR_M19"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR19,ADR19"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF19,ADOVRF19" "0,1"
|
|
bitfld.long 0x00 0. "ADRF19,ADRF19" "0,1"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "REG20,AD Conversion Result Register 20"
|
|
bitfld.long 0x00 29. "ADOVRF_M20,ADOVRF_M20" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M20,ADRF_M20" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M20,ADR_M20"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR20,ADR20"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF20,ADOVRF20" "0,1"
|
|
bitfld.long 0x00 0. "ADRF20,ADRF20" "0,1"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "REG21,AD Conversion Result Register 21"
|
|
bitfld.long 0x00 29. "ADOVRF_M21,ADOVRF_M21" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M21,ADRF_M21" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M21,ADR_M21"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR21,ADR21"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF21,ADOVRF21" "0,1"
|
|
bitfld.long 0x00 0. "ADRF21,ADRF21" "0,1"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "REG22,AD Conversion Result Register 22"
|
|
bitfld.long 0x00 29. "ADOVRF_M22,ADOVRF_M22" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M22,ADRF_M22" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M22,ADR_M22"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR22,ADR22"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF22,ADOVRF22" "0,1"
|
|
bitfld.long 0x00 0. "ADRF22,ADRF22" "0,1"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "REG23,AD Conversion Result Register 23"
|
|
bitfld.long 0x00 29. "ADOVRF_M23,ADOVRF_M23" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M23,ADRF_M23" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M23,ADR_M23"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR23,ADR23"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF23,ADOVRF23" "0,1"
|
|
bitfld.long 0x00 0. "ADRF23,ADRF23" "0,1"
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "REG24,AD Conversion Result Register 24"
|
|
bitfld.long 0x00 29. "ADOVRF_M24,ADOVRF_M24" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M24,ADRF_M24" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M24,ADR_M24"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR24,ADR24"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF24,ADOVRF24" "0,1"
|
|
bitfld.long 0x00 0. "ADRF24,ADRF24" "0,1"
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "REG25,AD Conversion Result Register 25"
|
|
bitfld.long 0x00 29. "ADOVRF_M25,ADOVRF_M25" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M25,ADRF_M25" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M25,ADR_M25"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR25,ADR25"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF25,ADOVRF25" "0,1"
|
|
bitfld.long 0x00 0. "ADRF25,ADRF25" "0,1"
|
|
rgroup.long 0x1AC++0x03
|
|
line.long 0x00 "REG26,AD Conversion Result Register 26"
|
|
bitfld.long 0x00 29. "ADOVRF_M26,ADOVRF_M26" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M26,ADRF_M26" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M26,ADR_M26"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR26,ADR26"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF26,ADOVRF26" "0,1"
|
|
bitfld.long 0x00 0. "ADRF26,ADRF26" "0,1"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "REG27,AD Conversion Result Register 27"
|
|
bitfld.long 0x00 29. "ADOVRF_M27,ADOVRF_M27" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M27,ADRF_M27" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M27,ADR_M27"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR27,ADR27"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF27,ADOVRF27" "0,1"
|
|
bitfld.long 0x00 0. "ADRF27,ADRF27" "0,1"
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "REG28,AD Conversion Result Register 28"
|
|
bitfld.long 0x00 29. "ADOVRF_M28,ADOVRF_M28" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M28,ADRF_M28" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M28,ADR_M28"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR28,ADR28"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF28,ADOVRF28" "0,1"
|
|
bitfld.long 0x00 0. "ADRF28,ADRF28" "0,1"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "REG29,AD Conversion Result Register 29"
|
|
bitfld.long 0x00 29. "ADOVRF_M29,ADOVRF_M29" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M29,ADRF_M29" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M29,ADR_M29"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR29,ADR29"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF29,ADOVRF29" "0,1"
|
|
bitfld.long 0x00 0. "ADRF29,ADRF29" "0,1"
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "REG30,AD Conversion Result Register 30"
|
|
bitfld.long 0x00 29. "ADOVRF_M30,ADOVRF_M30" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M30,ADRF_M30" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M30,ADR_M30"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR30,ADR30"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF30,ADOVRF30" "0,1"
|
|
bitfld.long 0x00 0. "ADRF30,ADRF30" "0,1"
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "REG31,AD Conversion Result Register 31"
|
|
bitfld.long 0x00 29. "ADOVRF_M31,ADOVRF_M31" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M31,ADRF_M31" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M31,ADR_M31"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR31,ADR31"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF31,ADOVRF31" "0,1"
|
|
bitfld.long 0x00 0. "ADRF31,ADRF31" "0,1"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "PROSEL,Conversion program resumed select register"
|
|
bitfld.long 0x00 14. "PROSEL14,PROSEL14" "0,1"
|
|
bitfld.long 0x00 13. "PROSEL13,PROSEL13" "0,1"
|
|
bitfld.long 0x00 12. "PROSEL12,PROSEL12" "0,1"
|
|
bitfld.long 0x00 11. "PROSEL11,PROSEL11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "PROSEL10,PROSEL10" "0,1"
|
|
bitfld.long 0x00 9. "PROSEL9,PROSEL9" "0,1"
|
|
bitfld.long 0x00 8. "PROSEL8,PROSEL8" "0,1"
|
|
bitfld.long 0x00 7. "PROSEL7,PROSEL7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PROSEL6,PROSEL6" "0,1"
|
|
bitfld.long 0x00 5. "PROSEL5,PROSEL5" "0,1"
|
|
bitfld.long 0x00 4. "PROSEL4,PROSEL4" "0,1"
|
|
bitfld.long 0x00 3. "PROSEL3,PROSEL3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PROSEL2,PROSEL2" "0,1"
|
|
bitfld.long 0x00 1. "PROSEL1,PROSEL1" "0,1"
|
|
bitfld.long 0x00 0. "PROSEL0,PROSEL0" "0,1"
|
|
rgroup.long 0x1C8++0x03
|
|
line.long 0x00 "PFLG,Priority determination state flag register"
|
|
bitfld.long 0x00 14. "PFLG14,PFLG14" "0,1"
|
|
bitfld.long 0x00 13. "PFLG13,PFLG13" "0,1"
|
|
bitfld.long 0x00 12. "PFLG12,PFLG12" "0,1"
|
|
bitfld.long 0x00 11. "PFLG11,PFLG11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "PFLG10,PFLG10" "0,1"
|
|
bitfld.long 0x00 9. "PFLG9,PFLG9" "0,1"
|
|
bitfld.long 0x00 8. "PFLG8,PFLG8" "0,1"
|
|
bitfld.long 0x00 7. "PFLG7,PFLG7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PFLG6,PFLG6" "0,1"
|
|
bitfld.long 0x00 5. "PFLG5,PFLG5" "0,1"
|
|
bitfld.long 0x00 4. "PFLG4,PFLG4" "0,1"
|
|
bitfld.long 0x00 3. "PFLG3,PFLG3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PFLG2,PFLG2" "0,1"
|
|
bitfld.long 0x00 1. "PFLG1,PFLG1" "0,1"
|
|
bitfld.long 0x00 0. "PFLG0,PFLG0" "0,1"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "PINT,Priority interrupt control register"
|
|
bitfld.long 0x00 14. "PINT14,PINT14" "0,1"
|
|
bitfld.long 0x00 13. "PINT13,PINT13" "0,1"
|
|
bitfld.long 0x00 12. "PINT12,PINT12" "0,1"
|
|
bitfld.long 0x00 11. "PINT11,PINT11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "PINT10,PINT10" "0,1"
|
|
bitfld.long 0x00 9. "PINT9,PINT9" "0,1"
|
|
bitfld.long 0x00 8. "PINT8,PINT8" "0,1"
|
|
bitfld.long 0x00 7. "PINT7,PINT7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINT6,PINT6" "0,1"
|
|
bitfld.long 0x00 5. "PINT5,PINT5" "0,1"
|
|
bitfld.long 0x00 4. "PINT4,PINT4" "0,1"
|
|
bitfld.long 0x00 3. "PINT3,PINT3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PINT2,PINT2" "0,1"
|
|
bitfld.long 0x00 1. "PINT1,PINT1" "0,1"
|
|
bitfld.long 0x00 0. "PINT0,PINT0" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
tree "DA (Digital analog converter (DAC))"
|
|
repeat 2. (list 0. 1.) (list ad:0x400BC800 ad:0x400BC900)
|
|
tree "DA$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,DAC Control Register"
|
|
bitfld.long 0x00 0. "EN,EN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "REG,DAC output Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAC,DAC"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "T32A (32-bit Timer Event Counter (T32A))"
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "T32A0"
|
|
base ad:0x400C1000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture Control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output Control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output Control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt Mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter Capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Capture Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Capture Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enable Register A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture Control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output Control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output Control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt Mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter Capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Capture Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Capture Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output Control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output Control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt Mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter Capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Capture Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Capture Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enable Register C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse Count Control Register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
tree "T32A0"
|
|
base ad:0x400BA000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Counter control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Counter Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Timer capturer A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Timer capturer A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enabl eRegister A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Counter control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Counter Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Timer capturer B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Timer capturer B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Counter control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Counter Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Timer capturer C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Timer capturer C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enabl eRegister C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse count control register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
repeat 2. (list 0. 1.) (list ad:0x400C1000 ad:0x400C1400) (list ad:0x40061000 ad:0x40061400)
|
|
tree "T32A$1"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base $2
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base $3
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Counter Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture Control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output Control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output Control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt Mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter Capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Counter Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
endif
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Timer Capture A0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Capture Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Timer Cupture A1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Capture Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enable Register A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Counter Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture Control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output Control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output Control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt Mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter Capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Counter Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
endif
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Capture Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Timer Capture B0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Capture Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Timer Capture B1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
endif
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Counter Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output Control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output Control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt Mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter Capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Counter Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Capture Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Timer Capture C0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
endif
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Capture Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enable Register C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse Count Control Register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "T32A1"
|
|
base ad:0x400C1400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture Control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output Control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output Control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt Mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter Capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Capture Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Capture Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enable Register A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture Control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output Control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output Control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt Mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter Capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Capture Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Capture Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output Control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output Control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt Mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter Capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Capture Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Capture Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enable Register C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse Count Control Register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
tree "T32A1"
|
|
base ad:0x400BA100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Counter control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Counter Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Timer capturer A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Timer capturer A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enabl eRegister A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Counter control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Counter Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Timer capturer B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Timer capturer B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Counter control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Counter Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Timer capturer C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Timer capturer C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enabl eRegister C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse count control register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "T32A2"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400C1800
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40061800
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Counter Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture Control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output Control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output Control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt Mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter Capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Counter Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
endif
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Timer Capture A0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Capture Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Timer Cupture A1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Capture Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enable Register A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Counter Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture Control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output Control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output Control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt Mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter Capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Counter Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
endif
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Capture Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Timer Capture B0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Capture Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Timer Capture B1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
endif
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Counter Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output Control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output Control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt Mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter Capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Counter Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Capture Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Timer Capture C0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
endif
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Capture Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enable Register C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse Count Control Register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
tree "T32A2"
|
|
base ad:0x400BA200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Counter control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Counter Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Timer capturer A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Timer capturer A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enabl eRegister A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Counter control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Counter Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Timer capturer B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Timer capturer B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Counter control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Counter Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Timer capturer C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Timer capturer C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enabl eRegister C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse count control register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "T32A2"
|
|
base ad:0x400C1800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture Control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output Control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output Control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt Mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter Capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Capture Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Capture Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enable Register A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture Control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output Control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output Control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt Mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter Capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Capture Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Capture Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output Control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output Control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt Mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter Capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Capture Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Capture Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enable Register C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse Count Control Register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "T32A3"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400C1C00
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40061C00
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Counter Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture Control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output Control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output Control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt Mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter Capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Counter Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
endif
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Timer Capture A0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Capture Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Timer Cupture A1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Capture Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enable Register A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Counter Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture Control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output Control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output Control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt Mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter Capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Counter Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
endif
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Capture Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Timer Capture B0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Capture Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Timer Capture B1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
endif
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Counter Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output Control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output Control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt Mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter Capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Counter Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Capture Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Timer Capture C0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
endif
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Capture Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enable Register C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse Count Control Register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "T32A3"
|
|
base ad:0x400C1C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture Control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output Control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output Control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt Mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter Capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Capture Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Capture Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enable Register A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture Control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output Control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output Control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt Mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter Capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Capture Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Capture Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output Control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output Control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt Mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter Capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Capture Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Capture Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enable Register C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse Count Control Register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
repeat 2. (list 3. 4.) (list ad:0x400BA300 ad:0x400BA400)
|
|
tree "T32A$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Counter control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Counter Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Timer capturer A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Timer capturer A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enabl eRegister A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Counter control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Counter Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Timer capturer B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Timer capturer B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Counter control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Counter Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Timer capturer C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Timer capturer C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enabl eRegister C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse count control register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "T32A4"
|
|
base ad:0x400C2000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture Control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output Control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output Control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt Mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter Capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Capture Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Capture Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enable Register A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture Control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output Control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output Control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt Mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter Capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Capture Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Capture Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output Control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output Control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt Mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter Capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Capture Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Capture Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enable Register C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse Count Control Register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
endif
|
|
repeat 2. (list 4. 5.) (list ad:0x400C2000 ad:0x400C2400)
|
|
tree "T32A$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture Control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output Control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output Control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt Mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter Capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Capture Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Capture Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enable Register A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture Control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output Control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output Control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt Mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter Capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Capture Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Capture Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output Control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output Control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt Mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter Capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Capture Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Capture Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enable Register C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse Count Control Register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
tree "T32A5"
|
|
base ad:0x400BA500
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Counter control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Counter Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Timer capturer A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Timer capturer A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enabl eRegister A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Counter control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Counter Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Timer capturer B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Timer capturer B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Counter control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Counter Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Timer capturer C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Timer capturer C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enabl eRegister C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse count control register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "T32A5"
|
|
base ad:0x400C2400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture Control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output Control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output Control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt Mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter Capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Capture Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Capture Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enable Register A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture Control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output Control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output Control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt Mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter Capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Capture Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Capture Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMC1,CAPMC1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMC0,CAPMC0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output Control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output Control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt Mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter Capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Capture Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Capture Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enable Register C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse Count Control Register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
endif
|
|
repeat 8. (list 6. 7. 8. 9. 10. 11. 12. 13.) (list ad:0x400C2800 ad:0x400C2C00 ad:0x400C3000 ad:0x400C3400 ad:0x400C3800 ad:0x400C3C00 ad:0x400C4000 ad:0x400C4400)
|
|
tree "T32A$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MOD,T32A Mode Register"
|
|
bitfld.long 0x00 1. "HALT,HALT" "0,1"
|
|
bitfld.long 0x00 0. "MODE32,MODE32" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RUNA,T32A Run Register A"
|
|
rbitfld.long 0x00 4. "RUNFLGA,RUNFLGA" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPA,SFTSTPA" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAA,SFTSTAA" "0,1"
|
|
bitfld.long 0x00 0. "RUNA,RUNA" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRA,T32A Control Register A"
|
|
bitfld.long 0x00 28.--30. "PRSCLA,PRSCLA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKA,CLKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFA,WBFA" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNA,UPDNA" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDA,RELDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPA,STOPA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTA,STARTA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAPCRA,T32A Capture Control Register A"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "OUTCRA0,T32A Output Control Register A0"
|
|
bitfld.long 0x00 0.--1. "OCRA,OCRA" "0,1,2,3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTCRA1,T32A Output Control Register A1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPA1,OCRCAPA1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPA0,OCRCAPA0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPA1,OCRCMPA1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPA0,OCRCMPA0" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "STA,T32A Status Register A"
|
|
bitfld.long 0x00 3. "INTUFA,INTUFA" "0,1"
|
|
bitfld.long 0x00 2. "INTOFA,INTOFA" "0,1"
|
|
bitfld.long 0x00 1. "INTA1,INTA1" "0,1"
|
|
bitfld.long 0x00 0. "INTA0,INTA0" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IMA,T32A Interrupt Mask Register A"
|
|
bitfld.long 0x00 3. "IMUFA,IMUFA" "0,1"
|
|
bitfld.long 0x00 2. "IMOFA,IMOFA" "0,1"
|
|
bitfld.long 0x00 1. "IMA1,IMA1" "0,1"
|
|
bitfld.long 0x00 0. "IMA0,IMA0" "0,1"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TMRA,T32A Counter Capture Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRA,TMRA"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RELDA,T32A Reload Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDA,RELDA"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RGA0,T32A Timer Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA0,RGA0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "RGA1,T32A Timer Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGA1,RGA1"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CAPA0,T32A Capture Register A0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA0,CAPA0"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CAPA1,T32A Capture Register A1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPA1,CAPA1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DMAA,T32A DMA Request Enable Register A"
|
|
bitfld.long 0x00 2. "DMAENA2,DMAENA2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENA1,DMAENA1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENA0,DMAENA0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RUNB,T32A Run Register B"
|
|
rbitfld.long 0x00 4. "RUNFLGB,RUNFLGB" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPB,SFTSTPB" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAB,SFTSTAB" "0,1"
|
|
bitfld.long 0x00 0. "RUNB,RUNB" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRB,T32A Control Register B"
|
|
bitfld.long 0x00 28.--30. "PRSCLB,PRSCLB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKB,CLKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFB,WBFB" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNB,UPDNB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDB,RELDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPB,STOPB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTB,STARTB" "0,1,2,3,4,5,6,7"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CAPCRB,T32A Capture Control Register B"
|
|
bitfld.long 0x00 4.--6. "CAPMB1,CAPMB1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMB0,CAPMB0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "OUTCRB0,T32A Output Control Register B0"
|
|
bitfld.long 0x00 0.--1. "OCRB,OCRB" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "OUTCRB1,T32A Output Control Register B1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPB1,OCRCAPB1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPB0,OCRCAPB0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPB1,OCRCMPB1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPB0,OCRCMPB0" "0,1,2,3"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "STB,T32A Status Register B"
|
|
bitfld.long 0x00 3. "INTUFB,INTUFB" "0,1"
|
|
bitfld.long 0x00 2. "INTOFB,INTOFB" "0,1"
|
|
bitfld.long 0x00 1. "INTB1,INTB1" "0,1"
|
|
bitfld.long 0x00 0. "INTB0,INTB0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "IMB,T32A Interrupt Mask Register B"
|
|
bitfld.long 0x00 3. "IMUFB,IMUFB" "0,1"
|
|
bitfld.long 0x00 2. "IMOFB,IMOFB" "0,1"
|
|
bitfld.long 0x00 1. "IMB1,IMB1" "0,1"
|
|
bitfld.long 0x00 0. "IMB0,IMB0" "0,1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "TMRB,T32A Counter Capture Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "TMRB,TMRB"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RELDB,T32A Reload Register B"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELDB,RELDB"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "RGB0,T32A Timer Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB0,RGB0"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "RGB1,T32A Timer Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RGB1,RGB1"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CAPB0,T32A Capture Register B0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB0,CAPB0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CAPB1,T32A Capture Register B1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPB1,CAPB1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DMAB,T32A DMA Request Enable Register B"
|
|
bitfld.long 0x00 2. "DMAENB2,DMAENB2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENB1,DMAENB1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENB0,DMAENB0" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RUNC,T32A Run Register C"
|
|
rbitfld.long 0x00 4. "RUNFLGC,RUNFLGC" "0,1"
|
|
bitfld.long 0x00 2. "SFTSTPC,SFTSTPC" "0,1"
|
|
bitfld.long 0x00 1. "SFTSTAC,SFTSTAC" "0,1"
|
|
bitfld.long 0x00 0. "RUNC,RUNC" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRC,T32A Control Register C"
|
|
bitfld.long 0x00 28.--30. "PRSCLC,PRSCLC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "CLKC,CLKC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. "WBFC,WBFC" "0,1"
|
|
bitfld.long 0x00 16.--17. "UPDNC,UPDNC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RELDC,RELDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "STOPC,STOPC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "STARTC,STARTC" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CAPCRC,T32A Capture Control Register C"
|
|
bitfld.long 0x00 4.--6. "CAPMA1,CAPMA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CAPMA0,CAPMA0" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "OUTCRC0,T32A Output Control Register C0"
|
|
bitfld.long 0x00 0.--1. "OCRC,OCRC" "0,1,2,3"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "OUTCRC1,T32A Output Control Register C1"
|
|
bitfld.long 0x00 6.--7. "OCRCAPC1,OCRCAPC1" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OCRCAPC0,OCRCAPC0" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OCRCMPC1,OCRCMPC1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OCRCMPC0,OCRCMPC0" "0,1,2,3"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "STC,T32A Status Register C"
|
|
bitfld.long 0x00 4. "INTSTERR,INTSTERR" "0,1"
|
|
bitfld.long 0x00 3. "INTUFC,INTUFC" "0,1"
|
|
bitfld.long 0x00 2. "INTOFC,INTOFC" "0,1"
|
|
bitfld.long 0x00 1. "INTC1,INTC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTC0,INTC0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IMC,T32A Interrupt Mask Register C"
|
|
bitfld.long 0x00 4. "IMSTERR,IMSTERR" "0,1"
|
|
bitfld.long 0x00 3. "IMUFC,IMUFC" "0,1"
|
|
bitfld.long 0x00 2. "IMOFC,IMOFC" "0,1"
|
|
bitfld.long 0x00 1. "IMC1,IMC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IMC0,IMC0" "0,1"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "TMRC,T32A Counter Capture Register C"
|
|
hexmask.long 0x00 0.--31. 1. "TMRC,TMRC"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RELDC,T32A Reload Register C"
|
|
hexmask.long 0x00 0.--31. 1. "RELDC,RELDC"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "RGC0,T32A Timer Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "RGC0,RGC0"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "RGC1,T32A Timer Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "RGC1,RGC1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CAPC0,T32A Capture Register C0"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC0,CAPC0"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CAPC1,T32A Capture Register C1"
|
|
hexmask.long 0x00 0.--31. 1. "CAPC1,CAPC1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "DMAC,T32A DMA Request Enable Register C"
|
|
bitfld.long 0x00 2. "DMAENC2,DMAENC2" "0,1"
|
|
bitfld.long 0x00 1. "DMAENC1,DMAENC1" "0,1"
|
|
bitfld.long 0x00 0. "DMAENC0,DMAENC0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PLSCR,T32A Pulse Count Control Register"
|
|
bitfld.long 0x00 12.--14. "PDN,PDN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PUP,PUP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "NF,NF" "0,1,2,3"
|
|
bitfld.long 0x00 1. "PDIR,PDIR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMODE,PMODE" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G8*")
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "UART0"
|
|
base ad:0x400CE000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software Reset Register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control Register 0"
|
|
bitfld.long 0x00 18. "HBSST,HBSST" "0,1"
|
|
bitfld.long 0x00 17. "HBSMD,HBSMD" "0,1"
|
|
bitfld.long 0x00 16. "HBSEN,HBSEN" "0,1"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control Register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control Register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud Rate Register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer Enable Register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data Register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear Register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error Register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "UART0"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400CE000
|
|
elif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400BB000
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x4006E000
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software Reset Register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software reset register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control register 0"
|
|
bitfld.long 0x00 18. "HBSST,HBSST" "0,1"
|
|
bitfld.long 0x00 17. "HBSMD,HBSMD" "0,1"
|
|
bitfld.long 0x00 16. "HBSEN,HBSEN" "0,1"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control Register 0"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control Register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control Register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "CKSEL,CKSEL" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud rate register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud Rate Register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer enable register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer Enable Register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data Register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear Register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error Register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "UART1"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400CE400
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x4006E400
|
|
elif cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400BB100
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software Reset Register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software reset register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control register 0"
|
|
bitfld.long 0x00 18. "HBSST,HBSST" "0,1"
|
|
bitfld.long 0x00 17. "HBSMD,HBSMD" "0,1"
|
|
bitfld.long 0x00 16. "HBSEN,HBSEN" "0,1"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control Register 0"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control Register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control Register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "CKSEL,CKSEL" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud rate register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud Rate Register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer enable register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer Enable Register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data Register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear Register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error Register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "UART1"
|
|
base ad:0x400CE400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software Reset Register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control Register 0"
|
|
bitfld.long 0x00 18. "HBSST,HBSST" "0,1"
|
|
bitfld.long 0x00 17. "HBSMD,HBSMD" "0,1"
|
|
bitfld.long 0x00 16. "HBSEN,HBSEN" "0,1"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control Register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control Register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud Rate Register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer Enable Register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data Register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear Register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error Register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "UART2"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400CE800
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x4006E800
|
|
elif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400BB200
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software Reset Register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software reset register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control register 0"
|
|
bitfld.long 0x00 18. "HBSST,HBSST" "0,1"
|
|
bitfld.long 0x00 17. "HBSMD,HBSMD" "0,1"
|
|
bitfld.long 0x00 16. "HBSEN,HBSEN" "0,1"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control Register 0"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control Register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control Register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "CKSEL,CKSEL" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud rate register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud Rate Register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer enable register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer Enable Register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data Register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear Register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error Register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "UART2"
|
|
base ad:0x400CE800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software Reset Register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control Register 0"
|
|
bitfld.long 0x00 18. "HBSST,HBSST" "0,1"
|
|
bitfld.long 0x00 17. "HBSMD,HBSMD" "0,1"
|
|
bitfld.long 0x00 16. "HBSEN,HBSEN" "0,1"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control Register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control Register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud Rate Register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer Enable Register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data Register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear Register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error Register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K4A*")
|
|
tree "UART3"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400CEC00
|
|
elif cpuis("TMPM4K4A*")
|
|
base ad:0x400BB300
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software Reset Register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software reset register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control register 0"
|
|
bitfld.long 0x00 18. "HBSST,HBSST" "0,1"
|
|
bitfld.long 0x00 17. "HBSMD,HBSMD" "0,1"
|
|
bitfld.long 0x00 16. "HBSEN,HBSEN" "0,1"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control Register 0"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control Register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control Register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "CKSEL,CKSEL" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud rate register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud Rate Register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer enable register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer Enable Register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data Register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear Register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error Register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "UART3"
|
|
base ad:0x400CEC00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software Reset Register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control Register 0"
|
|
bitfld.long 0x00 18. "HBSST,HBSST" "0,1"
|
|
bitfld.long 0x00 17. "HBSMD,HBSMD" "0,1"
|
|
bitfld.long 0x00 16. "HBSEN,HBSEN" "0,1"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control Register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control Register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud Rate Register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer Enable Register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data Register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear Register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error Register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
tree.end
|
|
endif
|
|
repeat 2. (list 4. 5.) (list ad:0x400CF000 ad:0x400CF400)
|
|
tree "UART$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWRST,UART Software Reset Register"
|
|
rbitfld.long 0x00 7. "SWRSTF,SWRSTF" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRST,SWRST" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR0,UART Control Register 0"
|
|
bitfld.long 0x00 15. "LPB,LPB" "0,1"
|
|
bitfld.long 0x00 12.--14. "NF,NF" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10. "CTSE,CTSE" "0,1"
|
|
bitfld.long 0x00 9. "RTSE,RTSE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "WU,WU" "0,1"
|
|
bitfld.long 0x00 6. "IV,IV" "0,1"
|
|
bitfld.long 0x00 5. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 4. "SBLEN,SBLEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EVEN,EVEN" "0,1"
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0.--1. "SM,SM" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR1,UART Control Register 1"
|
|
bitfld.long 0x00 12.--14. "TIL,TIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "RIL,RIL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,UART Clock Control Register"
|
|
bitfld.long 0x00 4.--7. "PRSEL,PRSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "CKSEL,CKSEL" "0,1,2,3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BRD,UART Baud Rate Register"
|
|
bitfld.long 0x00 23. "KEN,KEN" "0,1"
|
|
bitfld.long 0x00 16.--21. "BRK,BRK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRN,BRN"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRANS,UART Transfer Enable Register"
|
|
bitfld.long 0x00 3. "BK,BK" "0,1"
|
|
bitfld.long 0x00 2. "TXTRG,TXTRG" "0,1"
|
|
bitfld.long 0x00 1. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 0. "RXE,RXE" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DR,UART Data Register"
|
|
rbitfld.long 0x00 18. "PERR,PERR" "0,1"
|
|
rbitfld.long 0x00 17. "FERR,FERR" "0,1"
|
|
rbitfld.long 0x00 16. "BERR,BERR" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "DR,DR"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
rbitfld.long 0x00 31. "SUE,SUE" "0,1"
|
|
rbitfld.long 0x00 15. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 14. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 13. "TXFF,TXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
bitfld.long 0x00 5. "RXFF,RXFF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FIFOCLR,UART FIFO Clear Register"
|
|
bitfld.long 0x00 1. "TFCLR,TFCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFCLR,RFCLR" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ERR,UART Error Register"
|
|
bitfld.long 0x00 4. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 3. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 2. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 1. "FERR,FERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BERR,BERR" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
tree "I2C0"
|
|
base ad:0x400D1000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,I2C Control Register 1"
|
|
bitfld.long 0x00 5.--7. "BC,BC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "ACK,ACK" "0,1"
|
|
bitfld.long 0x00 3. "NOACK,NOACK" "0,1"
|
|
bitfld.long 0x00 0.--2. "SCK,SCK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DBR,Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DB,DB"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "AR,Bus address Register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA,SA"
|
|
bitfld.long 0x00 0. "ALS,ALS" "0,1"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "I2CM,I2CM" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRES,SWRES" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AL,AL" "0,1"
|
|
bitfld.long 0x00 2. "AAS,AAS" "0,1"
|
|
bitfld.long 0x00 1. "ADO,ADO" "0,1"
|
|
bitfld.long 0x00 0. "LRB,LRB" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRS,Prescaler clcok setting Register"
|
|
bitfld.long 0x00 0.--4. "PRSCK,PRSCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x00 6. "SELPINCD,SELPINCD" "0,1"
|
|
bitfld.long 0x00 5. "DMARI2CTX,DMARI2CTX" "0,1"
|
|
bitfld.long 0x00 4. "DMARI2CRX,DMARI2CRX" "0,1"
|
|
bitfld.long 0x00 3. "INTNACK,INTNACK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTI2CBF,INTI2CBF" "0,1"
|
|
bitfld.long 0x00 1. "INTI2CAL,INTI2CAL" "0,1"
|
|
bitfld.long 0x00 0. "INTI2C,INTI2C" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ST,Interrupt Register"
|
|
bitfld.long 0x00 3. "NACK,NACK" "0,1"
|
|
bitfld.long 0x00 2. "I2CBF,I2CBF" "0,1"
|
|
bitfld.long 0x00 1. "I2CAL,I2CAL" "0,1"
|
|
bitfld.long 0x00 0. "I2C,I2C" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "OP,Optiononal Function register"
|
|
bitfld.long 0x00 7. "DISAL,DISAL" "0,1"
|
|
bitfld.long 0x00 6. "SA2ST,SA2ST" "0,1"
|
|
bitfld.long 0x00 5. "SAST,SAST" "0,1"
|
|
bitfld.long 0x00 4. "NFSEL,NFSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RSTA,RSTA" "0,1"
|
|
bitfld.long 0x00 2. "GCDI,GCDI" "0,1"
|
|
bitfld.long 0x00 1. "SREN,SREN" "0,1"
|
|
bitfld.long 0x00 0. "MFACK,MFACK" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PM,Bus Monitor register"
|
|
bitfld.long 0x00 1. "SDA,SDA" "0,1"
|
|
bitfld.long 0x00 0. "SCL,SCL" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AR2,Second Slave address register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA2,SA2"
|
|
bitfld.long 0x00 0. "SA2EN,SA2EN" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
repeat 2. (list 0. 1.) (list ad:0x400D1000 ad:0x400D2000)
|
|
tree "I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,I2C Control Register 1"
|
|
bitfld.long 0x00 5.--7. "BC,BC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "ACK,ACK" "0,1"
|
|
bitfld.long 0x00 3. "NOACK,NOACK" "0,1"
|
|
bitfld.long 0x00 0.--2. "SCK,SCK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DBR,Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DB,DB"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "AR,Bus address Register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA,SA"
|
|
bitfld.long 0x00 0. "ALS,ALS" "0,1"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "I2CM,I2CM" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRES,SWRES" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AL,AL" "0,1"
|
|
bitfld.long 0x00 2. "AAS,AAS" "0,1"
|
|
bitfld.long 0x00 1. "AD0,AD0" "0,1"
|
|
bitfld.long 0x00 0. "LRB,LRB" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRS,Prescaler clcok setting Register"
|
|
bitfld.long 0x00 0.--4. "PRSCK,PRSCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x00 6. "SELPINCD,SELPINCD" "0,1"
|
|
bitfld.long 0x00 5. "DMARI2CTX,DMARI2CTX" "0,1"
|
|
bitfld.long 0x00 4. "DMARI2CRX,DMARI2CRX" "0,1"
|
|
bitfld.long 0x00 3. "INTNACK,INTNACK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTI2CBF,INTI2CBF" "0,1"
|
|
bitfld.long 0x00 1. "INTI2CAL,INTI2CAL" "0,1"
|
|
bitfld.long 0x00 0. "INTI2C,INTI2C" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ST,Interrupt Register"
|
|
bitfld.long 0x00 3. "NACK,NACK" "0,1"
|
|
bitfld.long 0x00 2. "I2CBF,I2CBF" "0,1"
|
|
bitfld.long 0x00 1. "I2CAL,I2CAL" "0,1"
|
|
bitfld.long 0x00 0. "I2C,I2C" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "OP,Optiononal Function register"
|
|
bitfld.long 0x00 7. "DISAL,DISAL" "0,1"
|
|
rbitfld.long 0x00 6. "SA2ST,SA2ST" "0,1"
|
|
rbitfld.long 0x00 5. "SAST,SAST" "0,1"
|
|
bitfld.long 0x00 4. "NFSEL,NFSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RSTA,RSTA" "0,1"
|
|
bitfld.long 0x00 2. "GCDI,GCDI" "0,1"
|
|
bitfld.long 0x00 1. "SREN,SREN" "0,1"
|
|
bitfld.long 0x00 0. "MFACK,MFACK" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PM,Bus Monitor register"
|
|
bitfld.long 0x00 1. "SDA,SDA" "0,1"
|
|
bitfld.long 0x00 0. "SCL,SCL" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AR2,Second Slave address register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA2,SA2"
|
|
bitfld.long 0x00 0. "SA2EN,SA2EN" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
repeat 2. (list 1. 2.) (list ad:0x400D2000 ad:0x400D3000)
|
|
tree "I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,I2C Control Register 1"
|
|
bitfld.long 0x00 5.--7. "BC,BC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "ACK,ACK" "0,1"
|
|
bitfld.long 0x00 3. "NOACK,NOACK" "0,1"
|
|
bitfld.long 0x00 0.--2. "SCK,SCK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DBR,Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DB,DB"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "AR,Bus address Register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA,SA"
|
|
bitfld.long 0x00 0. "ALS,ALS" "0,1"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "I2CM,I2CM" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRES,SWRES" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AL,AL" "0,1"
|
|
bitfld.long 0x00 2. "AAS,AAS" "0,1"
|
|
bitfld.long 0x00 1. "ADO,ADO" "0,1"
|
|
bitfld.long 0x00 0. "LRB,LRB" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRS,Prescaler clcok setting Register"
|
|
bitfld.long 0x00 0.--4. "PRSCK,PRSCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x00 6. "SELPINCD,SELPINCD" "0,1"
|
|
bitfld.long 0x00 5. "DMARI2CTX,DMARI2CTX" "0,1"
|
|
bitfld.long 0x00 4. "DMARI2CRX,DMARI2CRX" "0,1"
|
|
bitfld.long 0x00 3. "INTNACK,INTNACK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTI2CBF,INTI2CBF" "0,1"
|
|
bitfld.long 0x00 1. "INTI2CAL,INTI2CAL" "0,1"
|
|
bitfld.long 0x00 0. "INTI2C,INTI2C" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ST,Interrupt Register"
|
|
bitfld.long 0x00 3. "NACK,NACK" "0,1"
|
|
bitfld.long 0x00 2. "I2CBF,I2CBF" "0,1"
|
|
bitfld.long 0x00 1. "I2CAL,I2CAL" "0,1"
|
|
bitfld.long 0x00 0. "I2C,I2C" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "OP,Optiononal Function register"
|
|
bitfld.long 0x00 7. "DISAL,DISAL" "0,1"
|
|
bitfld.long 0x00 6. "SA2ST,SA2ST" "0,1"
|
|
bitfld.long 0x00 5. "SAST,SAST" "0,1"
|
|
bitfld.long 0x00 4. "NFSEL,NFSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RSTA,RSTA" "0,1"
|
|
bitfld.long 0x00 2. "GCDI,GCDI" "0,1"
|
|
bitfld.long 0x00 1. "SREN,SREN" "0,1"
|
|
bitfld.long 0x00 0. "MFACK,MFACK" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PM,Bus Monitor register"
|
|
bitfld.long 0x00 1. "SDA,SDA" "0,1"
|
|
bitfld.long 0x00 0. "SCL,SCL" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AR2,Second Slave address register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA2,SA2"
|
|
bitfld.long 0x00 0. "SA2EN,SA2EN" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
tree "I2C3"
|
|
base ad:0x400D4000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,I2C Control Register 1"
|
|
bitfld.long 0x00 5.--7. "BC,BC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "ACK,ACK" "0,1"
|
|
bitfld.long 0x00 3. "NOACK,NOACK" "0,1"
|
|
bitfld.long 0x00 0.--2. "SCK,SCK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DBR,Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DB,DB"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "AR,Bus address Register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA,SA"
|
|
bitfld.long 0x00 0. "ALS,ALS" "0,1"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "I2CM,I2CM" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRES,SWRES" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AL,AL" "0,1"
|
|
bitfld.long 0x00 2. "AAS,AAS" "0,1"
|
|
bitfld.long 0x00 1. "ADO,ADO" "0,1"
|
|
bitfld.long 0x00 0. "LRB,LRB" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRS,Prescaler clcok setting Register"
|
|
bitfld.long 0x00 0.--4. "PRSCK,PRSCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x00 6. "SELPINCD,SELPINCD" "0,1"
|
|
bitfld.long 0x00 5. "DMARI2CTX,DMARI2CTX" "0,1"
|
|
bitfld.long 0x00 4. "DMARI2CRX,DMARI2CRX" "0,1"
|
|
bitfld.long 0x00 3. "INTNACK,INTNACK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTI2CBF,INTI2CBF" "0,1"
|
|
bitfld.long 0x00 1. "INTI2CAL,INTI2CAL" "0,1"
|
|
bitfld.long 0x00 0. "INTI2C,INTI2C" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ST,Interrupt Register"
|
|
bitfld.long 0x00 3. "NACK,NACK" "0,1"
|
|
bitfld.long 0x00 2. "I2CBF,I2CBF" "0,1"
|
|
bitfld.long 0x00 1. "I2CAL,I2CAL" "0,1"
|
|
bitfld.long 0x00 0. "I2C,I2C" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "OP,Optiononal Function register"
|
|
bitfld.long 0x00 7. "DISAL,DISAL" "0,1"
|
|
bitfld.long 0x00 6. "SA2ST,SA2ST" "0,1"
|
|
bitfld.long 0x00 5. "SAST,SAST" "0,1"
|
|
bitfld.long 0x00 4. "NFSEL,NFSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RSTA,RSTA" "0,1"
|
|
bitfld.long 0x00 2. "GCDI,GCDI" "0,1"
|
|
bitfld.long 0x00 1. "SREN,SREN" "0,1"
|
|
bitfld.long 0x00 0. "MFACK,MFACK" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PM,Bus Monitor register"
|
|
bitfld.long 0x00 1. "SDA,SDA" "0,1"
|
|
bitfld.long 0x00 0. "SCL,SCL" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AR2,Second Slave address register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA2,SA2"
|
|
bitfld.long 0x00 0. "SA2EN,SA2EN" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "I2C4"
|
|
base ad:0x400D5000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,I2C Control Register 1"
|
|
bitfld.long 0x00 5.--7. "BC,BC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "ACK,ACK" "0,1"
|
|
bitfld.long 0x00 3. "NOACK,NOACK" "0,1"
|
|
bitfld.long 0x00 0.--2. "SCK,SCK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DBR,Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DB,DB"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "AR,Bus address Register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA,SA"
|
|
bitfld.long 0x00 0. "ALS,ALS" "0,1"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "I2CM,I2CM" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRES,SWRES" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AL,AL" "0,1"
|
|
bitfld.long 0x00 2. "AAS,AAS" "0,1"
|
|
bitfld.long 0x00 1. "ADO,ADO" "0,1"
|
|
bitfld.long 0x00 0. "LRB,LRB" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRS,Prescaler clcok setting Register"
|
|
bitfld.long 0x00 0.--4. "PRSCK,PRSCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x00 6. "SELPINCD,SELPINCD" "0,1"
|
|
bitfld.long 0x00 5. "DMARI2CTX,DMARI2CTX" "0,1"
|
|
bitfld.long 0x00 4. "DMARI2CRX,DMARI2CRX" "0,1"
|
|
bitfld.long 0x00 3. "INTNACK,INTNACK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTI2CBF,INTI2CBF" "0,1"
|
|
bitfld.long 0x00 1. "INTI2CAL,INTI2CAL" "0,1"
|
|
bitfld.long 0x00 0. "INTI2C,INTI2C" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ST,Interrupt Register"
|
|
bitfld.long 0x00 3. "NACK,NACK" "0,1"
|
|
bitfld.long 0x00 2. "I2CBF,I2CBF" "0,1"
|
|
bitfld.long 0x00 1. "I2CAL,I2CAL" "0,1"
|
|
bitfld.long 0x00 0. "I2C,I2C" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "OP,Optiononal Function register"
|
|
bitfld.long 0x00 7. "DISAL,DISAL" "0,1"
|
|
bitfld.long 0x00 6. "SA2ST,SA2ST" "0,1"
|
|
bitfld.long 0x00 5. "SAST,SAST" "0,1"
|
|
bitfld.long 0x00 4. "NFSEL,NFSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RSTA,RSTA" "0,1"
|
|
bitfld.long 0x00 2. "GCDI,GCDI" "0,1"
|
|
bitfld.long 0x00 1. "SREN,SREN" "0,1"
|
|
bitfld.long 0x00 0. "MFACK,MFACK" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PM,Bus Monitor register"
|
|
bitfld.long 0x00 1. "SDA,SDA" "0,1"
|
|
bitfld.long 0x00 0. "SCL,SCL" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AR2,Second Slave address register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA2,SA2"
|
|
bitfld.long 0x00 0. "SA2EN,SA2EN" "0,1"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "PA (Port A)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E0000
|
|
elif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400C0000
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40080000
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PA Data Register"
|
|
bitfld.long 0x00 2. "PA2,PA2" "0,1"
|
|
bitfld.long 0x00 1. "PA1,PA1" "0,1"
|
|
bitfld.long 0x00 0. "PA0,PA0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port A Data Register"
|
|
bitfld.long 0x00 4. "PA4,PA4" "0,1"
|
|
bitfld.long 0x00 3. "PA3,PA3" "0,1"
|
|
bitfld.long 0x00 2. "PA2,PA2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PA Data Register"
|
|
bitfld.long 0x00 1. "PA1,PA1" "0,1"
|
|
bitfld.long 0x00 0. "PA0,PA0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PA Data Register"
|
|
bitfld.long 0x00 0. "PA0,PA0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port A Data Register"
|
|
bitfld.long 0x00 7. "PA7,PA7" "0,1"
|
|
bitfld.long 0x00 6. "PA6,PA6" "0,1"
|
|
bitfld.long 0x00 5. "PA5,PA5" "0,1"
|
|
bitfld.long 0x00 4. "PA4,PA4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PA3,PA3" "0,1"
|
|
bitfld.long 0x00 2. "PA2,PA2" "0,1"
|
|
bitfld.long 0x00 1. "PA1,PA1" "0,1"
|
|
bitfld.long 0x00 0. "PA0,PA0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port A Data Register"
|
|
bitfld.long 0x00 4. "PA4,PA4" "0,1"
|
|
bitfld.long 0x00 3. "PA3,PA3" "0,1"
|
|
bitfld.long 0x00 2. "PA2,PA2" "0,1"
|
|
bitfld.long 0x00 1. "PA1,PA1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PA0,PA0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port A Data Register"
|
|
bitfld.long 0x00 2. "PA2,PA2" "0,1"
|
|
bitfld.long 0x00 1. "PA1,PA1" "0,1"
|
|
bitfld.long 0x00 0. "PA0,PA0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port A Data Register"
|
|
bitfld.long 0x00 3. "PA3,PA3" "0,1"
|
|
bitfld.long 0x00 2. "PA2,PA2" "0,1"
|
|
bitfld.long 0x00 1. "PA1,PA1" "0,1"
|
|
bitfld.long 0x00 0. "PA0,PA0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PA Control Register"
|
|
bitfld.long 0x00 2. "PA2C,PA2C" "0,1"
|
|
bitfld.long 0x00 1. "PA1C,PA1C" "0,1"
|
|
bitfld.long 0x00 0. "PA0C,PA0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port A Output Control Register"
|
|
bitfld.long 0x00 7. "PA7C,PA7C" "0,1"
|
|
bitfld.long 0x00 6. "PA6C,PA6C" "0,1"
|
|
bitfld.long 0x00 5. "PA5C,PA5C" "0,1"
|
|
bitfld.long 0x00 4. "PA4C,PA4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PA3C,PA3C" "0,1"
|
|
bitfld.long 0x00 2. "PA2C,PA2C" "0,1"
|
|
bitfld.long 0x00 1. "PA1C,PA1C" "0,1"
|
|
bitfld.long 0x00 0. "PA0C,PA0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port A Output Control Register"
|
|
bitfld.long 0x00 4. "PA4C,PA4C" "0,1"
|
|
bitfld.long 0x00 3. "PA3C,PA3C" "0,1"
|
|
bitfld.long 0x00 2. "PA2C,PA2C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port A Output Control Register"
|
|
bitfld.long 0x00 3. "PA3C,PA3C" "0,1"
|
|
bitfld.long 0x00 2. "PA2C,PA2C" "0,1"
|
|
bitfld.long 0x00 1. "PA1C,PA1C" "0,1"
|
|
bitfld.long 0x00 0. "PA0C,PA0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PA Control Register"
|
|
bitfld.long 0x00 0. "PA0C,PA0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port A Output Control Register"
|
|
bitfld.long 0x00 4. "PA4C,PA4C" "0,1"
|
|
bitfld.long 0x00 3. "PA3C,PA3C" "0,1"
|
|
bitfld.long 0x00 2. "PA2C,PA2C" "0,1"
|
|
bitfld.long 0x00 1. "PA1C,PA1C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PA0C,PA0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PA Control Register"
|
|
bitfld.long 0x00 1. "PA1C,PA1C" "0,1"
|
|
bitfld.long 0x00 0. "PA0C,PA0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PA Function Register 1"
|
|
bitfld.long 0x00 0. "PA0F1,PA0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PA Function Register 1"
|
|
bitfld.long 0x00 1. "PA1F1,PA1F1" "0,1"
|
|
bitfld.long 0x00 0. "PA0F1,PA0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port A Function Register 1"
|
|
bitfld.long 0x00 4. "PA4F1,PA4F1" "0,1"
|
|
bitfld.long 0x00 3. "PA3F1,PA3F1" "0,1"
|
|
bitfld.long 0x00 2. "PA2F1,PA2F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port A Function Register 1"
|
|
bitfld.long 0x00 2. "PA2F1,PA2F1" "0,1"
|
|
bitfld.long 0x00 1. "PA1F1,PA1F1" "0,1"
|
|
bitfld.long 0x00 0. "PA0F1,PA0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port A Function Register 1"
|
|
bitfld.long 0x00 4. "PA4F1,PA4F1" "0,1"
|
|
bitfld.long 0x00 3. "PA3F1,PA3F1" "0,1"
|
|
bitfld.long 0x00 2. "PA2F1,PA2F1" "0,1"
|
|
bitfld.long 0x00 1. "PA1F1,PA1F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PA0F1,PA0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port A Function Register 1"
|
|
bitfld.long 0x00 3. "PA3F1,PA3F1" "0,1"
|
|
bitfld.long 0x00 2. "PA2F1,PA2F1" "0,1"
|
|
bitfld.long 0x00 1. "PA1F1,PA1F1" "0,1"
|
|
bitfld.long 0x00 0. "PA0F1,PA0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port A Function Register 1"
|
|
bitfld.long 0x00 7. "PA7F1,PA7F1" "0,1"
|
|
bitfld.long 0x00 6. "PA6F1,PA6F1" "0,1"
|
|
bitfld.long 0x00 5. "PA5F1,PA5F1" "0,1"
|
|
bitfld.long 0x00 4. "PA4F1,PA4F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PA3F1,PA3F1" "0,1"
|
|
bitfld.long 0x00 2. "PA2F1,PA2F1" "0,1"
|
|
bitfld.long 0x00 1. "PA1F1,PA1F1" "0,1"
|
|
bitfld.long 0x00 0. "PA0F1,PA0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,PA Function Register 2"
|
|
bitfld.long 0x00 1. "PA1F2,PA1F2" "0,1"
|
|
bitfld.long 0x00 0. "PA0F2,PA0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port A Function Register 2"
|
|
bitfld.long 0x00 7. "PA7F2,PA7F2" "0,1"
|
|
bitfld.long 0x00 4. "PA4F2,PA4F2" "0,1"
|
|
bitfld.long 0x00 3. "PA3F2,PA3F2" "0,1"
|
|
bitfld.long 0x00 0. "PA0F2,PA0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,PA Function Register 2"
|
|
bitfld.long 0x00 0. "PA0F2,PA0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port A Function Register 2"
|
|
bitfld.long 0x00 2. "PA2F2,PA2F2" "0,1"
|
|
bitfld.long 0x00 1. "PA1F2,PA1F2" "0,1"
|
|
bitfld.long 0x00 0. "PA0F2,PA0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port A Function Register 2"
|
|
bitfld.long 0x00 3. "PA3F2,PA3F2" "0,1"
|
|
bitfld.long 0x00 2. "PA2F2,PA2F2" "0,1"
|
|
bitfld.long 0x00 1. "PA1F2,PA1F2" "0,1"
|
|
bitfld.long 0x00 0. "PA0F2,PA0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,PA Function Register 3"
|
|
bitfld.long 0x00 2. "PA2F3,PA2F3" "0,1"
|
|
bitfld.long 0x00 1. "PA1F3,PA1F3" "0,1"
|
|
bitfld.long 0x00 0. "PA0F3,PA0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,PA Function Register 3"
|
|
bitfld.long 0x00 1. "PA1F3,PA1F3" "0,1"
|
|
bitfld.long 0x00 0. "PA0F3,PA0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port A Function Register 3"
|
|
bitfld.long 0x00 7. "PA7F3,PA7F3" "0,1"
|
|
bitfld.long 0x00 6. "PA6F3,PA6F3" "0,1"
|
|
bitfld.long 0x00 5. "PA5F3,PA5F3" "0,1"
|
|
bitfld.long 0x00 4. "PA4F3,PA4F3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PA3F3,PA3F3" "0,1"
|
|
bitfld.long 0x00 2. "PA2F3,PA2F3" "0,1"
|
|
bitfld.long 0x00 1. "PA1F3,PA1F3" "0,1"
|
|
bitfld.long 0x00 0. "PA0F3,PA0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,PA Function Register 3"
|
|
bitfld.long 0x00 0. "PA0F3,PA0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port A Function Register 3"
|
|
bitfld.long 0x00 2. "PA2F3,PA2F3" "0,1"
|
|
bitfld.long 0x00 1. "PA1F3,PA1F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,PA Function Register 4"
|
|
bitfld.long 0x00 0. "PA0F4,PA0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,PA Function Register 4"
|
|
bitfld.long 0x00 2. "PA2F4,PA2F4" "0,1"
|
|
bitfld.long 0x00 1. "PA1F4,PA1F4" "0,1"
|
|
bitfld.long 0x00 0. "PA0F4,PA0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port A Function Register 4"
|
|
bitfld.long 0x00 4. "PA4F4,PA4F4" "0,1"
|
|
bitfld.long 0x00 3. "PA3F4,PA3F4" "0,1"
|
|
bitfld.long 0x00 2. "PA2F4,PA2F4" "0,1"
|
|
bitfld.long 0x00 1. "PA1F4,PA1F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PA0F4,PA0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port A Function Register 4"
|
|
bitfld.long 0x00 4. "PA4F4,PA4F4" "0,1"
|
|
bitfld.long 0x00 3. "PA3F4,PA3F4" "0,1"
|
|
bitfld.long 0x00 2. "PA2F4,PA2F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port A Function Register 3"
|
|
bitfld.long 0x00 2. "PA2F4,PA2F4" "0,1"
|
|
bitfld.long 0x00 1. "PA1F4,PA1F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,PA Function Register 4"
|
|
bitfld.long 0x00 1. "PA1F4,PA1F4" "0,1"
|
|
bitfld.long 0x00 0. "PA0F4,PA0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PA Function Register 5"
|
|
bitfld.long 0x00 0. "PA0F5,PA0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port A Function Register 5"
|
|
bitfld.long 0x00 3. "PA3F5,PA3F5" "0,1"
|
|
bitfld.long 0x00 2. "PA2F5,PA2F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port A Function Register 5"
|
|
bitfld.long 0x00 7. "PA7F2,PA7F2" "0,1"
|
|
bitfld.long 0x00 5. "PA5F5,PA5F5" "0,1"
|
|
bitfld.long 0x00 4. "PA4F5,PA4F5" "0,1"
|
|
bitfld.long 0x00 3. "PA3F5,PA3F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PA1F5,PA1F5" "0,1"
|
|
bitfld.long 0x00 0. "PA0F5,PA0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port A Function Register 5"
|
|
bitfld.long 0x00 2. "PA2F5,PA2F5" "0,1"
|
|
bitfld.long 0x00 1. "PA1F5,PA1F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PA Function Register 5"
|
|
bitfld.long 0x00 2. "PA2F5,PA2F5" "0,1"
|
|
bitfld.long 0x00 1. "PA1F5,PA1F5" "0,1"
|
|
bitfld.long 0x00 0. "PA0F5,PA0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PA Function Register 5"
|
|
bitfld.long 0x00 1. "PA1F5,PA1F5" "0,1"
|
|
bitfld.long 0x00 0. "PA0F5,PA0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port A Function Register 6"
|
|
bitfld.long 0x00 7. "PA7F6,PA7F6" "0,1"
|
|
bitfld.long 0x00 6. "PA6F6,PA6F6" "0,1"
|
|
bitfld.long 0x00 5. "PA5F6,PA5F6" "0,1"
|
|
bitfld.long 0x00 4. "PA4F6,PA4F6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PA3F6,PA3F6" "0,1"
|
|
bitfld.long 0x00 0. "PA0F6,PA0F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port A Function Register 6"
|
|
bitfld.long 0x00 2. "PA2F6,PA2F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,PA Function Register 6"
|
|
bitfld.long 0x00 2. "PA2F6,PA2F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port A Function Register 6"
|
|
bitfld.long 0x00 2. "PA2F6,PA2F6" "0,1"
|
|
bitfld.long 0x00 1. "PA1F6,PA1F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port A Function Register 7"
|
|
bitfld.long 0x00 4. "PA4F7,PA4F7" "0,1"
|
|
bitfld.long 0x00 3. "PA3F7,PA3F7" "0,1"
|
|
bitfld.long 0x00 2. "PA2F7,PA2F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port A Function Register 7"
|
|
bitfld.long 0x00 7. "PA7F7,PA7F7" "0,1"
|
|
bitfld.long 0x00 6. "PA6F7,PA6F7" "0,1"
|
|
bitfld.long 0x00 5. "PA5F7,PA5F7" "0,1"
|
|
bitfld.long 0x00 4. "PA4F7,PA4F7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PA3F7,PA3F7" "0,1"
|
|
bitfld.long 0x00 2. "PA2F7,PA2F7" "0,1"
|
|
bitfld.long 0x00 1. "PA1F7,PA1F7" "0,1"
|
|
bitfld.long 0x00 0. "PA0F7,PA0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,PA Function Register 7"
|
|
bitfld.long 0x00 2. "PA2F7,PA2F7" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PA Open Drain Control Register"
|
|
bitfld.long 0x00 2. "PA2OD,PA2OD" "0,1"
|
|
bitfld.long 0x00 1. "PA1OD,PA1OD" "0,1"
|
|
bitfld.long 0x00 0. "PA0OD,PA0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port A Open Drain Control Register"
|
|
bitfld.long 0x00 4. "PA4OD,PA4OD" "0,1"
|
|
bitfld.long 0x00 3. "PA3OD,PA3OD" "0,1"
|
|
bitfld.long 0x00 2. "PA2OD,PA2OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port A Open Drain Control Register"
|
|
bitfld.long 0x00 2. "PA2OD,PA2OD" "0,1"
|
|
bitfld.long 0x00 1. "PA1OD,PA1OD" "0,1"
|
|
bitfld.long 0x00 0. "PA0OD,PA0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port A Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PA7OD,PA7OD" "0,1"
|
|
bitfld.long 0x00 6. "PA6OD,PA6OD" "0,1"
|
|
bitfld.long 0x00 5. "PA5OD,PA5OD" "0,1"
|
|
bitfld.long 0x00 4. "PA4OD,PA4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PA3OD,PA3OD" "0,1"
|
|
bitfld.long 0x00 2. "PA2OD,PA2OD" "0,1"
|
|
bitfld.long 0x00 1. "PA1OD,PA1OD" "0,1"
|
|
bitfld.long 0x00 0. "PA0OD,PA0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PA Open Drain Control Register"
|
|
bitfld.long 0x00 1. "PA1OD,PA1OD" "0,1"
|
|
bitfld.long 0x00 0. "PA0OD,PA0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PA Open Drain Control Register"
|
|
bitfld.long 0x00 0. "PA0OD,PA0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port A Open Drain Control Register"
|
|
bitfld.long 0x00 3. "PA3OD,PA3OD" "0,1"
|
|
bitfld.long 0x00 2. "PA2OD,PA2OD" "0,1"
|
|
bitfld.long 0x00 1. "PA1OD,PA1OD" "0,1"
|
|
bitfld.long 0x00 0. "PA0OD,PA0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port A Open Drain Control Register"
|
|
bitfld.long 0x00 4. "PA4OD,PA4OD" "0,1"
|
|
bitfld.long 0x00 3. "PA3OD,PA3OD" "0,1"
|
|
bitfld.long 0x00 2. "PA2OD,PA2OD" "0,1"
|
|
bitfld.long 0x00 1. "PA1OD,PA1OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PA0OD,PA0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PA Pull-up Control Register"
|
|
bitfld.long 0x00 2. "PA2PUP,PA2PUP" "0,1"
|
|
bitfld.long 0x00 1. "PA1PUP,PA1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PA0PUP,PA0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port A Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PA7UP,PA7UP" "0,1"
|
|
bitfld.long 0x00 6. "PA6UP,PA6UP" "0,1"
|
|
bitfld.long 0x00 5. "PA5UP,PA5UP" "0,1"
|
|
bitfld.long 0x00 4. "PA4UP,PA4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PA3UP,PA3UP" "0,1"
|
|
bitfld.long 0x00 2. "PA2UP,PA2UP" "0,1"
|
|
bitfld.long 0x00 1. "PA1UP,PA1UP" "0,1"
|
|
bitfld.long 0x00 0. "PA0UP,PA0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port A Pull-up Control Register"
|
|
bitfld.long 0x00 2. "PA2UP,PA2UP" "0,1"
|
|
bitfld.long 0x00 1. "PA1UP,PA1UP" "0,1"
|
|
bitfld.long 0x00 0. "PA0UP,PA0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PA Pull-up Control Register"
|
|
bitfld.long 0x00 0. "PA0PUP,PA0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port A Pull-up Control Register"
|
|
bitfld.long 0x00 4. "PA4UP,PA4UP" "0,1"
|
|
bitfld.long 0x00 3. "PA3UP,PA3UP" "0,1"
|
|
bitfld.long 0x00 2. "PA2UP,PA2UP" "0,1"
|
|
bitfld.long 0x00 1. "PA1UP,PA1UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PA0UP,PA0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port A Pull-up Control Register"
|
|
bitfld.long 0x00 3. "PA3UP,PA3UP" "0,1"
|
|
bitfld.long 0x00 2. "PA2UP,PA2UP" "0,1"
|
|
bitfld.long 0x00 1. "PA1UP,PA1UP" "0,1"
|
|
bitfld.long 0x00 0. "PA0UP,PA0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PA Pull-up Control Register"
|
|
bitfld.long 0x00 1. "PA1PUP,PA1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PA0PUP,PA0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port A Pull-up Control Register"
|
|
bitfld.long 0x00 4. "PA4UP,PA4UP" "0,1"
|
|
bitfld.long 0x00 3. "PA3UP,PA3UP" "0,1"
|
|
bitfld.long 0x00 2. "PA2UP,PA2UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port A Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PA7DN,PA7DN" "0,1"
|
|
bitfld.long 0x00 6. "PA6DN,PA6DN" "0,1"
|
|
bitfld.long 0x00 5. "PA5DN,PA5DN" "0,1"
|
|
bitfld.long 0x00 4. "PA4DN,PA4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PA3DN,PA3DN" "0,1"
|
|
bitfld.long 0x00 2. "PA2DN,PA2DN" "0,1"
|
|
bitfld.long 0x00 1. "PA1DN,PA1DN" "0,1"
|
|
bitfld.long 0x00 0. "PA0DN,PA0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port A Pull-down Control Register"
|
|
bitfld.long 0x00 4. "PA4DN,PA4DN" "0,1"
|
|
bitfld.long 0x00 3. "PA3DN,PA3DN" "0,1"
|
|
bitfld.long 0x00 2. "PA2DN,PA2DN" "0,1"
|
|
bitfld.long 0x00 1. "PA1DN,PA1DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PA0DN,PA0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PA Pull-Down Control Register"
|
|
bitfld.long 0x00 2. "PA2PDN,PA2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PA1PDN,PA1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PA0PDN,PA0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port A Pull-down Control Register"
|
|
bitfld.long 0x00 2. "PA2DN,PA2DN" "0,1"
|
|
bitfld.long 0x00 1. "PA1DN,PA1DN" "0,1"
|
|
bitfld.long 0x00 0. "PA0DN,PA0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port A Pull-down Control Register"
|
|
bitfld.long 0x00 3. "PA3DN,PA3DN" "0,1"
|
|
bitfld.long 0x00 2. "PA2DN,PA2DN" "0,1"
|
|
bitfld.long 0x00 1. "PA1DN,PA1DN" "0,1"
|
|
bitfld.long 0x00 0. "PA0DN,PA0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PA Pull-Down Control Register"
|
|
bitfld.long 0x00 0. "PA0PDN,PA0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PA Pull-Down Control Register"
|
|
bitfld.long 0x00 1. "PA1PDN,PA1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PA0PDN,PA0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port A Input Control Register"
|
|
bitfld.long 0x00 2. "PA2IE,PA2IE" "0,1"
|
|
bitfld.long 0x00 1. "PA1IE,PA1IE" "0,1"
|
|
bitfld.long 0x00 0. "PA0IE,PA0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port A Input Control Register"
|
|
bitfld.long 0x00 4. "PA4IE,PA4IE" "0,1"
|
|
bitfld.long 0x00 3. "PA3IE,PA3IE" "0,1"
|
|
bitfld.long 0x00 2. "PA2IE,PA2IE" "0,1"
|
|
bitfld.long 0x00 1. "PA1IE,PA1IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PA0IE,PA0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port A Input Control Register"
|
|
bitfld.long 0x00 7. "PA7IE,PA7IE" "0,1"
|
|
bitfld.long 0x00 6. "PA6IE,PA6IE" "0,1"
|
|
bitfld.long 0x00 5. "PA5IE,PA5IE" "0,1"
|
|
bitfld.long 0x00 4. "PA4IE,PA4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PA3IE,PA3IE" "0,1"
|
|
bitfld.long 0x00 2. "PA2IE,PA2IE" "0,1"
|
|
bitfld.long 0x00 1. "PA1IE,PA1IE" "0,1"
|
|
bitfld.long 0x00 0. "PA0IE,PA0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PA Input Enable Control Register"
|
|
bitfld.long 0x00 0. "PA0IE,PA0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port A Input Control Register"
|
|
bitfld.long 0x00 3. "PA3IE,PA3IE" "0,1"
|
|
bitfld.long 0x00 2. "PA2IE,PA2IE" "0,1"
|
|
bitfld.long 0x00 1. "PA1IE,PA1IE" "0,1"
|
|
bitfld.long 0x00 0. "PA0IE,PA0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PA Input Enable Control Register"
|
|
bitfld.long 0x00 1. "PA1IE,PA1IE" "0,1"
|
|
bitfld.long 0x00 0. "PA0IE,PA0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PA Input Enable Control Register"
|
|
bitfld.long 0x00 2. "PA2IE,PA2IE" "0,1"
|
|
bitfld.long 0x00 1. "PA1IE,PA1IE" "0,1"
|
|
bitfld.long 0x00 0. "PA0IE,PA0IE" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "PB (Port B)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E0100
|
|
elif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400C0100
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40080100
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port B Data Register"
|
|
bitfld.long 0x00 6. "PB6,PB6" "0,1"
|
|
bitfld.long 0x00 5. "PB5,PB5" "0,1"
|
|
bitfld.long 0x00 4. "PB4,PB4" "0,1"
|
|
bitfld.long 0x00 3. "PB3,PB3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PB2,PB2" "0,1"
|
|
bitfld.long 0x00 1. "PB1,PB1" "0,1"
|
|
bitfld.long 0x00 0. "PB0,PB0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PB Data Register"
|
|
bitfld.long 0x00 1. "PB1,PB1" "0,1"
|
|
bitfld.long 0x00 0. "PB0,PB0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port B Data Register"
|
|
bitfld.long 0x00 7. "PB7,PB7" "0,1"
|
|
bitfld.long 0x00 6. "PB6,PB6" "0,1"
|
|
bitfld.long 0x00 5. "PB5,PB5" "0,1"
|
|
bitfld.long 0x00 4. "PB4,PB4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PB3,PB3" "0,1"
|
|
bitfld.long 0x00 2. "PB2,PB2" "0,1"
|
|
bitfld.long 0x00 1. "PB1,PB1" "0,1"
|
|
bitfld.long 0x00 0. "PB0,PB0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port B Data Register"
|
|
bitfld.long 0x00 3. "PB3,PB3" "0,1"
|
|
bitfld.long 0x00 2. "PB2,PB2" "0,1"
|
|
bitfld.long 0x00 1. "PB1,PB1" "0,1"
|
|
bitfld.long 0x00 0. "PB0,PB0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port B Output Control Register"
|
|
bitfld.long 0x00 3. "PB3C,PB3C" "0,1"
|
|
bitfld.long 0x00 2. "PB2C,PB2C" "0,1"
|
|
bitfld.long 0x00 1. "PB1C,PB1C" "0,1"
|
|
bitfld.long 0x00 0. "PB0C,PB0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port B Output Control Register"
|
|
bitfld.long 0x00 6. "PB6C,PB6C" "0,1"
|
|
bitfld.long 0x00 5. "PB5C,PB5C" "0,1"
|
|
bitfld.long 0x00 4. "PB4C,PB4C" "0,1"
|
|
bitfld.long 0x00 3. "PB3C,PB3C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PB2C,PB2C" "0,1"
|
|
bitfld.long 0x00 1. "PB1C,PB1C" "0,1"
|
|
bitfld.long 0x00 0. "PB0C,PB0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PB Control Register"
|
|
bitfld.long 0x00 1. "PB1C,PB1C" "0,1"
|
|
bitfld.long 0x00 0. "PB0C,PB0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port B Output Control Register"
|
|
bitfld.long 0x00 7. "PB7C,PB7C" "0,1"
|
|
bitfld.long 0x00 6. "PB6C,PB6C" "0,1"
|
|
bitfld.long 0x00 5. "PB5C,PB5C" "0,1"
|
|
bitfld.long 0x00 4. "PB4C,PB4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PB3C,PB3C" "0,1"
|
|
bitfld.long 0x00 2. "PB2C,PB2C" "0,1"
|
|
bitfld.long 0x00 1. "PB1C,PB1C" "0,1"
|
|
bitfld.long 0x00 0. "PB0C,PB0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port A Function Register 1"
|
|
bitfld.long 0x00 3. "PB3F1,PB3F1" "0,1"
|
|
bitfld.long 0x00 2. "PB2F1,PB2F1" "0,1"
|
|
bitfld.long 0x00 1. "PB1F1,PB1F1" "0,1"
|
|
bitfld.long 0x00 0. "PB0F1,PB0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PB Function Register 1"
|
|
bitfld.long 0x00 1. "PB1F1,PB1F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port B Function Register 1"
|
|
bitfld.long 0x00 7. "PB7F1,PB7F1" "0,1"
|
|
bitfld.long 0x00 6. "PB6F1,PB6F1" "0,1"
|
|
bitfld.long 0x00 5. "PB5F1,PB5F1" "0,1"
|
|
bitfld.long 0x00 4. "PB4F1,PB4F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PB3F1,PB3F1" "0,1"
|
|
bitfld.long 0x00 2. "PB2F1,PB2F1" "0,1"
|
|
bitfld.long 0x00 1. "PB1F1,PB1F1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port B Function Register 2"
|
|
bitfld.long 0x00 7. "PB7F2,PB7F2" "0,1"
|
|
bitfld.long 0x00 6. "PB6F2,PB6F2" "0,1"
|
|
bitfld.long 0x00 1. "PB1F2,PB1F2" "0,1"
|
|
bitfld.long 0x00 0. "PB0F2,PB0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,PB Function Register 3"
|
|
bitfld.long 0x00 1. "PB1F3,PB1F3" "0,1"
|
|
bitfld.long 0x00 0. "PB0F3,PB0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port B Function Register 3"
|
|
bitfld.long 0x00 7. "PB7F3,PB7F3" "0,1"
|
|
bitfld.long 0x00 6. "PB6F3,PB6F3" "0,1"
|
|
bitfld.long 0x00 5. "PB5F3,PB5F3" "0,1"
|
|
bitfld.long 0x00 4. "PB4F3,PB4F3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PB3F3,PB3F3" "0,1"
|
|
bitfld.long 0x00 2. "PB2F3,PB2F3" "0,1"
|
|
bitfld.long 0x00 1. "PB1F3,PB1F3" "0,1"
|
|
bitfld.long 0x00 0. "PB0F3,PB0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port B Function Register 4"
|
|
bitfld.long 0x00 7. "PB7F4,PB7F4" "0,1"
|
|
bitfld.long 0x00 6. "PB6F4,PB6F4" "0,1"
|
|
bitfld.long 0x00 5. "PB5F4,PB5F4" "0,1"
|
|
bitfld.long 0x00 4. "PB4F4,PB4F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PB3F4,PB3F4" "0,1"
|
|
bitfld.long 0x00 2. "PB2F4,PB2F4" "0,1"
|
|
bitfld.long 0x00 1. "PB1F4,PB1F4" "0,1"
|
|
bitfld.long 0x00 0. "PB0F4,PB0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port B Function Register 4"
|
|
bitfld.long 0x00 6. "PB6F4,PB6F4" "0,1"
|
|
bitfld.long 0x00 5. "PB5F4,PB5F4" "0,1"
|
|
bitfld.long 0x00 4. "PB4F4,PB4F4" "0,1"
|
|
bitfld.long 0x00 3. "PB3F4,PB3F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PB2F4,PB2F4" "0,1"
|
|
bitfld.long 0x00 1. "PB1F4,PB1F4" "0,1"
|
|
bitfld.long 0x00 0. "PB0F4,PB0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,PB Function Register 4"
|
|
bitfld.long 0x00 1. "PB1F4,PB1F4" "0,1"
|
|
bitfld.long 0x00 0. "PB0F4,PB0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port B Function Register 5"
|
|
bitfld.long 0x00 7. "PB7F5,PB7F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PB Function Register 5"
|
|
bitfld.long 0x00 1. "PB1F5,PB1F5" "0,1"
|
|
bitfld.long 0x00 0. "PB0F5,PB0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port B Function Register 5"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port B Function Register 5"
|
|
bitfld.long 0x00 7. "PB7F5,PB7F5" "0,1"
|
|
bitfld.long 0x00 6. "PB6F5,PB6F5" "0,1"
|
|
bitfld.long 0x00 4. "PB4F5,PB4F5" "0,1"
|
|
bitfld.long 0x00 2. "PB2F5,PB2F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PB1F5,PB1F5" "0,1"
|
|
bitfld.long 0x00 0. "PB0F5,PB0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,PB Function Register 6"
|
|
bitfld.long 0x00 1. "PB1F6,PB1F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port B Function Register 6"
|
|
bitfld.long 0x00 1. "PB1F6,PB1F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,PB Function Register 7"
|
|
bitfld.long 0x00 1. "PB1F7,PB1F7" "0,1"
|
|
bitfld.long 0x00 0. "PB0F7,PB0F7" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PB Open Drain Control Register"
|
|
bitfld.long 0x00 1. "PB1OD,PB1OD" "0,1"
|
|
bitfld.long 0x00 0. "PB0OD,PB0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port B Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PB7OD,PB7OD" "0,1"
|
|
bitfld.long 0x00 6. "PB6OD,PB6OD" "0,1"
|
|
bitfld.long 0x00 5. "PB5OD,PB5OD" "0,1"
|
|
bitfld.long 0x00 4. "PB4OD,PB4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PB3OD,PB3OD" "0,1"
|
|
bitfld.long 0x00 2. "PB2OD,PB2OD" "0,1"
|
|
bitfld.long 0x00 1. "PB1OD,PB1OD" "0,1"
|
|
bitfld.long 0x00 0. "PB0OD,PB0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port B Open Drain Control Register"
|
|
bitfld.long 0x00 6. "PB6OD,PB6OD" "0,1"
|
|
bitfld.long 0x00 5. "PB5OD,PB5OD" "0,1"
|
|
bitfld.long 0x00 4. "PB4OD,PB4OD" "0,1"
|
|
bitfld.long 0x00 3. "PB3OD,PB3OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PB2OD,PB2OD" "0,1"
|
|
bitfld.long 0x00 1. "PB1OD,PB1OD" "0,1"
|
|
bitfld.long 0x00 0. "PB0OD,PB0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port B Open Drain Control Register"
|
|
bitfld.long 0x00 3. "PB3OD,PB3OD" "0,1"
|
|
bitfld.long 0x00 2. "PB2OD,PB2OD" "0,1"
|
|
bitfld.long 0x00 1. "PB1OD,PB1OD" "0,1"
|
|
bitfld.long 0x00 0. "PB0OD,PB0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port B Pull-up Control Register"
|
|
bitfld.long 0x00 6. "PB6UP,PB6UP" "0,1"
|
|
bitfld.long 0x00 5. "PB5UP,PB5UP" "0,1"
|
|
bitfld.long 0x00 4. "PB4UP,PB4UP" "0,1"
|
|
bitfld.long 0x00 3. "PB3UP,PB3UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PB2UP,PB2UP" "0,1"
|
|
bitfld.long 0x00 1. "PB1UP,PB1UP" "0,1"
|
|
bitfld.long 0x00 0. "PB0UP,PB0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port B Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PB7UP,PB7UP" "0,1"
|
|
bitfld.long 0x00 6. "PB6UP,PB6UP" "0,1"
|
|
bitfld.long 0x00 5. "PB5UP,PB5UP" "0,1"
|
|
bitfld.long 0x00 4. "PB4UP,PB4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PB3UP,PB3UP" "0,1"
|
|
bitfld.long 0x00 2. "PB2UP,PB2UP" "0,1"
|
|
bitfld.long 0x00 1. "PB1UP,PB1UP" "0,1"
|
|
bitfld.long 0x00 0. "PB0UP,PB0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PB Pull-up Control Register"
|
|
bitfld.long 0x00 1. "PB1PUP,PB1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PB0PUP,PB0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port B Pull-up Control Register"
|
|
bitfld.long 0x00 3. "PB3UP,PB3UP" "0,1"
|
|
bitfld.long 0x00 2. "PB2UP,PB2UP" "0,1"
|
|
bitfld.long 0x00 1. "PB1UP,PB1UP" "0,1"
|
|
bitfld.long 0x00 0. "PB0UP,PB0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port B Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PB7DN,PB7DN" "0,1"
|
|
bitfld.long 0x00 6. "PB6DN,PB6DN" "0,1"
|
|
bitfld.long 0x00 5. "PB5DN,PB5DN" "0,1"
|
|
bitfld.long 0x00 4. "PB4DN,PB4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PB3DN,PB3DN" "0,1"
|
|
bitfld.long 0x00 2. "PB2DN,PB2DN" "0,1"
|
|
bitfld.long 0x00 1. "PB1DN,PB1DN" "0,1"
|
|
bitfld.long 0x00 0. "PB0DN,PB0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PB Pull-Down Control Register"
|
|
bitfld.long 0x00 1. "PB1PDN,PB1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PB0PDN,PB0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port B Pull-down Control Register"
|
|
bitfld.long 0x00 6. "PB6DN,PB6DN" "0,1"
|
|
bitfld.long 0x00 5. "PB5DN,PB5DN" "0,1"
|
|
bitfld.long 0x00 4. "PB4DN,PB4DN" "0,1"
|
|
bitfld.long 0x00 3. "PB3DN,PB3DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PB2DN,PB2DN" "0,1"
|
|
bitfld.long 0x00 1. "PB1DN,PB1DN" "0,1"
|
|
bitfld.long 0x00 0. "PB0DN,PB0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port B Pull-down Control Register"
|
|
bitfld.long 0x00 3. "PB3DN,PB3DN" "0,1"
|
|
bitfld.long 0x00 2. "PB2DN,PB2DN" "0,1"
|
|
bitfld.long 0x00 1. "PB1DN,PB1DN" "0,1"
|
|
bitfld.long 0x00 0. "PB0DN,PB0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port B Input Control Register"
|
|
bitfld.long 0x00 7. "PB7IE,PB7IE" "0,1"
|
|
bitfld.long 0x00 6. "PB6IE,PB6IE" "0,1"
|
|
bitfld.long 0x00 5. "PB5IE,PB5IE" "0,1"
|
|
bitfld.long 0x00 4. "PB4IE,PB4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PB3IE,PB3IE" "0,1"
|
|
bitfld.long 0x00 2. "PB2IE,PB2IE" "0,1"
|
|
bitfld.long 0x00 1. "PB1IE,PB1IE" "0,1"
|
|
bitfld.long 0x00 0. "PB0IE,PB0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PB Input Enable Control Register"
|
|
bitfld.long 0x00 1. "PB1IE,PB1IE" "0,1"
|
|
bitfld.long 0x00 0. "PB0IE,PB0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port B Input Control Register"
|
|
bitfld.long 0x00 3. "PB3IE,PB3IE" "0,1"
|
|
bitfld.long 0x00 2. "PB2IE,PB2IE" "0,1"
|
|
bitfld.long 0x00 1. "PB1IE,PB1IE" "0,1"
|
|
bitfld.long 0x00 0. "PB0IE,PB0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port B Input Control Register"
|
|
bitfld.long 0x00 6. "PB6IE,PB6IE" "0,1"
|
|
bitfld.long 0x00 5. "PB5IE,PB5IE" "0,1"
|
|
bitfld.long 0x00 4. "PB4IE,PB4IE" "0,1"
|
|
bitfld.long 0x00 3. "PB3IE,PB3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PB2IE,PB2IE" "0,1"
|
|
bitfld.long 0x00 1. "PB1IE,PB1IE" "0,1"
|
|
bitfld.long 0x00 0. "PB0IE,PB0IE" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "PC (Port C)"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E0200
|
|
elif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400C0200
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40080200
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4L*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port C Data Register"
|
|
bitfld.long 0x00 3. "PC3,PC3" "0,1"
|
|
bitfld.long 0x00 2. "PC2,PC2" "0,1"
|
|
bitfld.long 0x00 1. "PC1,PC1" "0,1"
|
|
bitfld.long 0x00 0. "PC0,PC0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PC Data Register"
|
|
bitfld.long 0x00 0. "PC0,PC0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PC Data Register"
|
|
bitfld.long 0x00 2. "PC2,PC2" "0,1"
|
|
bitfld.long 0x00 1. "PC1,PC1" "0,1"
|
|
bitfld.long 0x00 0. "PC0,PC0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port C Data Register"
|
|
bitfld.long 0x00 5. "PC5,PC5" "0,1"
|
|
bitfld.long 0x00 4. "PC4,PC4" "0,1"
|
|
bitfld.long 0x00 3. "PC3,PC3" "0,1"
|
|
bitfld.long 0x00 2. "PC2,PC2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC1,PC1" "0,1"
|
|
bitfld.long 0x00 0. "PC0,PC0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port C Data Register"
|
|
bitfld.long 0x00 7. "PC7,PC7" "0,1"
|
|
bitfld.long 0x00 6. "PC6,PC6" "0,1"
|
|
bitfld.long 0x00 5. "PC5,PC5" "0,1"
|
|
bitfld.long 0x00 4. "PC4,PC4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PC3,PC3" "0,1"
|
|
bitfld.long 0x00 2. "PC2,PC2" "0,1"
|
|
bitfld.long 0x00 1. "PC1,PC1" "0,1"
|
|
bitfld.long 0x00 0. "PC0,PC0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port C Output Control Register"
|
|
bitfld.long 0x00 7. "PC7C,PC7C" "0,1"
|
|
bitfld.long 0x00 6. "PC6C,PC6C" "0,1"
|
|
bitfld.long 0x00 5. "PC5C,PC5C" "0,1"
|
|
bitfld.long 0x00 4. "PC4C,PC4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PC3C,PC3C" "0,1"
|
|
bitfld.long 0x00 2. "PC2C,PC2C" "0,1"
|
|
bitfld.long 0x00 1. "PC1C,PC1C" "0,1"
|
|
bitfld.long 0x00 0. "PC0C,PC0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4L*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port C Output Control Register"
|
|
bitfld.long 0x00 3. "PC3C,PC3C" "0,1"
|
|
bitfld.long 0x00 2. "PC2C,PC2C" "0,1"
|
|
bitfld.long 0x00 1. "PC1C,PC1C" "0,1"
|
|
bitfld.long 0x00 0. "PC0C,PC0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PC Control Register"
|
|
bitfld.long 0x00 2. "PC2C,PC2C" "0,1"
|
|
bitfld.long 0x00 1. "PC1C,PC1C" "0,1"
|
|
bitfld.long 0x00 0. "PC0C,PC0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port C Output Control Register"
|
|
bitfld.long 0x00 5. "PC5C,PC5C" "0,1"
|
|
bitfld.long 0x00 4. "PC4C,PC4C" "0,1"
|
|
bitfld.long 0x00 3. "PC3C,PC3C" "0,1"
|
|
bitfld.long 0x00 2. "PC2C,PC2C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC1C,PC1C" "0,1"
|
|
bitfld.long 0x00 0. "PC0C,PC0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PC Control Register"
|
|
bitfld.long 0x00 0. "PC0C,PC0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port C Function Register 1"
|
|
bitfld.long 0x00 1. "PC1F1,PC1F1" "0,1"
|
|
bitfld.long 0x00 0. "PC0F1,PC0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PC Function Register 1"
|
|
bitfld.long 0x00 0. "PC0F1,PC0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port C Function Register 1"
|
|
bitfld.long 0x00 5. "PC5F1,PC5F1" "0,1"
|
|
bitfld.long 0x00 4. "PC4F1,PC4F1" "0,1"
|
|
bitfld.long 0x00 1. "PC1F1,PC1F1" "0,1"
|
|
bitfld.long 0x00 0. "PC0F1,PC0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port C Function Register 1"
|
|
bitfld.long 0x00 4. "PC4F1,PC4F1" "0,1"
|
|
bitfld.long 0x00 3. "PC3F1,PC3F1" "0,1"
|
|
bitfld.long 0x00 2. "PC2F1,PC2F1" "0,1"
|
|
bitfld.long 0x00 1. "PC1F1,PC1F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PC Function Register 1"
|
|
bitfld.long 0x00 1. "PC1F1,PC1F1" "0,1"
|
|
bitfld.long 0x00 0. "PC0F1,PC0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port C Function Register 1"
|
|
bitfld.long 0x00 5. "PC5F1,PC5F1" "0,1"
|
|
bitfld.long 0x00 4. "PC4F1,PC4F1" "0,1"
|
|
bitfld.long 0x00 3. "PC3F1,PC3F1" "0,1"
|
|
bitfld.long 0x00 2. "PC2F1,PC2F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC1F1,PC1F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port C Function Register 1"
|
|
bitfld.long 0x00 7. "PC7F1,PC7F1" "0,1"
|
|
bitfld.long 0x00 6. "PC6F1,PC6F1" "0,1"
|
|
bitfld.long 0x00 5. "PC5F1,PC5F1" "0,1"
|
|
bitfld.long 0x00 4. "PC4F1,PC4F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PC3F1,PC3F1" "0,1"
|
|
bitfld.long 0x00 2. "PC2F1,PC2F1" "0,1"
|
|
bitfld.long 0x00 1. "PC1F1,PC1F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port C Function Register 2"
|
|
bitfld.long 0x00 1. "PC1F2,PC1F2" "0,1"
|
|
bitfld.long 0x00 0. "PC0F2,PC0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port C Function Register 2"
|
|
bitfld.long 0x00 5. "PC5F2,PC5F2" "0,1"
|
|
bitfld.long 0x00 4. "PC4F2,PC4F2" "0,1"
|
|
bitfld.long 0x00 1. "PC1F2,PC1F2" "0,1"
|
|
bitfld.long 0x00 0. "PC0F2,PC0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,PC Function Register 2"
|
|
bitfld.long 0x00 1. "PC1F2,PC1F2" "0,1"
|
|
bitfld.long 0x00 0. "PC0F2,PC0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,PC Function Register 2"
|
|
bitfld.long 0x00 0. "PC0F2,PC0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port C Function Register 1"
|
|
bitfld.long 0x00 5. "PC5F2,PC5F2" "0,1"
|
|
bitfld.long 0x00 4. "PC4F2,PC4F2" "0,1"
|
|
bitfld.long 0x00 3. "PC3F2,PC3F2" "0,1"
|
|
bitfld.long 0x00 2. "PC2F2,PC2F2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC1F2,PC1F2" "0,1"
|
|
bitfld.long 0x00 0. "PC0F2,PC0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,PC Function Register 3"
|
|
bitfld.long 0x00 2. "PC2F3,PC2F3" "0,1"
|
|
bitfld.long 0x00 1. "PC1F3,PC1F3" "0,1"
|
|
bitfld.long 0x00 0. "PC0F3,PC0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port C Function Register 3"
|
|
bitfld.long 0x00 5. "PC5F3,PC5F3" "0,1"
|
|
bitfld.long 0x00 4. "PC4F3,PC4F3" "0,1"
|
|
bitfld.long 0x00 3. "PC3F3,PC3F3" "0,1"
|
|
bitfld.long 0x00 2. "PC2F3,PC2F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port C Function Register 3"
|
|
bitfld.long 0x00 4. "PC4F3,PC4F3" "0,1"
|
|
bitfld.long 0x00 3. "PC3F3,PC3F3" "0,1"
|
|
bitfld.long 0x00 2. "PC2F3,PC2F3" "0,1"
|
|
bitfld.long 0x00 1. "PC1F3,PC1F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port C Function Register 3"
|
|
bitfld.long 0x00 7. "PC7F3,PC7F3" "0,1"
|
|
bitfld.long 0x00 6. "PC6F3,PC6F3" "0,1"
|
|
bitfld.long 0x00 5. "PC5F3,PC5F3" "0,1"
|
|
bitfld.long 0x00 4. "PC4F3,PC4F3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PC3F3,PC3F3" "0,1"
|
|
bitfld.long 0x00 2. "PC2F3,PC2F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port C Function Register 3"
|
|
bitfld.long 0x00 5. "PC5F3,PC5F3" "0,1"
|
|
bitfld.long 0x00 4. "PC4F3,PC4F3" "0,1"
|
|
bitfld.long 0x00 3. "PC3F3,PC3F3" "0,1"
|
|
bitfld.long 0x00 1. "PC1F3,PC1F3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PC0F3,PC0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port C Function Register 3"
|
|
bitfld.long 0x00 3. "PC3F3,PC3F3" "0,1"
|
|
bitfld.long 0x00 2. "PC2F3,PC2F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port C Function Register 3"
|
|
bitfld.long 0x00 5. "PC5F3,PC5F3" "0,1"
|
|
bitfld.long 0x00 4. "PC4F3,PC4F3" "0,1"
|
|
bitfld.long 0x00 3. "PC3F3,PC3F3" "0,1"
|
|
bitfld.long 0x00 2. "PC2F3,PC2F3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC1F3,PC1F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,PC Function Register 4"
|
|
bitfld.long 0x00 0. "PC0F4,PC0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port C Function Register 4"
|
|
bitfld.long 0x00 1. "PC1F4,PC1F4" "0,1"
|
|
bitfld.long 0x00 0. "PC0F4,PC0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port C Function Register 3"
|
|
bitfld.long 0x00 3. "PC3F4,PC3F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,PC Function Register 4"
|
|
bitfld.long 0x00 2. "PC2F4,PC2F4" "0,1"
|
|
bitfld.long 0x00 1. "PC1F4,PC1F4" "0,1"
|
|
bitfld.long 0x00 0. "PC0F4,PC0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PC Function Register 5"
|
|
bitfld.long 0x00 0. "PC0F5,PC0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port C Function Register 5"
|
|
bitfld.long 0x00 7. "PC7F5,PC7F5" "0,1"
|
|
bitfld.long 0x00 6. "PC6F5,PC6F5" "0,1"
|
|
bitfld.long 0x00 3. "PC3F5,PC3F5" "0,1"
|
|
bitfld.long 0x00 2. "PC2F5,PC2F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC1F5,PC1F5" "0,1"
|
|
bitfld.long 0x00 0. "PC0F5,PC0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port C Function Register 5"
|
|
bitfld.long 0x00 4. "PC4F5,PC4F5" "0,1"
|
|
bitfld.long 0x00 2. "PC2F5,PC2F5" "0,1"
|
|
bitfld.long 0x00 1. "PC1F5,PC1F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PC Function Register 5"
|
|
bitfld.long 0x00 2. "PC2F5,PC2F5" "0,1"
|
|
bitfld.long 0x00 1. "PC1F5,PC1F5" "0,1"
|
|
bitfld.long 0x00 0. "PC0F5,PC0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port C Function Register 5"
|
|
bitfld.long 0x00 3. "PC3F5,PC3F5" "0,1"
|
|
bitfld.long 0x00 2. "PC2F5,PC2F5" "0,1"
|
|
bitfld.long 0x00 1. "PC1F5,PC1F5" "0,1"
|
|
bitfld.long 0x00 0. "PC0F5,PC0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port C Function Register 6"
|
|
bitfld.long 0x00 6. "PC6F6,PC6F6" "0,1"
|
|
bitfld.long 0x00 2. "PC2F6,PC2F6" "0,1"
|
|
bitfld.long 0x00 1. "PC1F6,PC1F6" "0,1"
|
|
bitfld.long 0x00 0. "PC0F6,PC0F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port C Function Register 6"
|
|
bitfld.long 0x00 2. "PC2F6,PC2F6" "0,1"
|
|
bitfld.long 0x00 1. "PC1F6,PC1F6" "0,1"
|
|
bitfld.long 0x00 0. "PC0F6,PC0F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port C Function Register 7"
|
|
bitfld.long 0x00 3. "PC3F7,PC3F7" "0,1"
|
|
bitfld.long 0x00 2. "PC2F7,PC2F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PC Open Drain Control Register"
|
|
bitfld.long 0x00 0. "PC0OD,PC0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port C Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PC7OD,PC7OD" "0,1"
|
|
bitfld.long 0x00 6. "PC6OD,PC6OD" "0,1"
|
|
bitfld.long 0x00 5. "PC5OD,PC5OD" "0,1"
|
|
bitfld.long 0x00 4. "PC4OD,PC4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PC3OD,PC3OD" "0,1"
|
|
bitfld.long 0x00 2. "PC2OD,PC2OD" "0,1"
|
|
bitfld.long 0x00 1. "PC1OD,PC1OD" "0,1"
|
|
bitfld.long 0x00 0. "PC0OD,PC0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PC Open Drain Control Register"
|
|
bitfld.long 0x00 2. "PC2OD,PC2OD" "0,1"
|
|
bitfld.long 0x00 1. "PC1OD,PC1OD" "0,1"
|
|
bitfld.long 0x00 0. "PC0OD,PC0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4L*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port C Open Drain Control Register"
|
|
bitfld.long 0x00 3. "PC3OD,PC3OD" "0,1"
|
|
bitfld.long 0x00 2. "PC2OD,PC2OD" "0,1"
|
|
bitfld.long 0x00 1. "PC1OD,PC1OD" "0,1"
|
|
bitfld.long 0x00 0. "PC0OD,PC0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port C Open Drain Control Register"
|
|
bitfld.long 0x00 5. "PC5OD,PC5OD" "0,1"
|
|
bitfld.long 0x00 4. "PC4OD,PC4OD" "0,1"
|
|
bitfld.long 0x00 3. "PC3OD,PC3OD" "0,1"
|
|
bitfld.long 0x00 2. "PC2OD,PC2OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC1OD,PC1OD" "0,1"
|
|
bitfld.long 0x00 0. "PC0OD,PC0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port C Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PC7UP,PC7UP" "0,1"
|
|
bitfld.long 0x00 6. "PC6UP,PC6UP" "0,1"
|
|
bitfld.long 0x00 5. "PC5UP,PC5UP" "0,1"
|
|
bitfld.long 0x00 4. "PC4UP,PC4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PC3UP,PC3UP" "0,1"
|
|
bitfld.long 0x00 2. "PC2UP,PC2UP" "0,1"
|
|
bitfld.long 0x00 1. "PC1UP,PC1UP" "0,1"
|
|
bitfld.long 0x00 0. "PC0UP,PC0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PC Pull-up Control Register"
|
|
bitfld.long 0x00 2. "PC2PUP,PC2PUP" "0,1"
|
|
bitfld.long 0x00 1. "PC1PUP,PC1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PC0PUP,PC0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PC Pull-up Control Register"
|
|
bitfld.long 0x00 0. "PC0PUP,PC0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port C Pull-up Control Register"
|
|
bitfld.long 0x00 5. "PC5UP,PC5UP" "0,1"
|
|
bitfld.long 0x00 4. "PC4UP,PC4UP" "0,1"
|
|
bitfld.long 0x00 3. "PC3UP,PC3UP" "0,1"
|
|
bitfld.long 0x00 2. "PC2UP,PC2UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC1UP,PC1UP" "0,1"
|
|
bitfld.long 0x00 0. "PC0UP,PC0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4L*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port C Pull-up Control Register"
|
|
bitfld.long 0x00 3. "PC3UP,PC3UP" "0,1"
|
|
bitfld.long 0x00 2. "PC2UP,PC2UP" "0,1"
|
|
bitfld.long 0x00 1. "PC1UP,PC1UP" "0,1"
|
|
bitfld.long 0x00 0. "PC0UP,PC0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PC Pull-Down Control Register"
|
|
bitfld.long 0x00 2. "PC2PDN,PC2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PC1PDN,PC1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PC0PDN,PC0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4L*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port C Pull-down Control Register"
|
|
bitfld.long 0x00 3. "PC3DN,PC3DN" "0,1"
|
|
bitfld.long 0x00 2. "PC2DN,PC2DN" "0,1"
|
|
bitfld.long 0x00 1. "PC1DN,PC1DN" "0,1"
|
|
bitfld.long 0x00 0. "PC0DN,PC0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PC Pull-Down Control Register"
|
|
bitfld.long 0x00 0. "PC0PDN,PC0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port C Pull-down Control Register"
|
|
bitfld.long 0x00 5. "PC5DN,PC5DN" "0,1"
|
|
bitfld.long 0x00 4. "PC4DN,PC4DN" "0,1"
|
|
bitfld.long 0x00 3. "PC3DN,PC3DN" "0,1"
|
|
bitfld.long 0x00 2. "PC2DN,PC2DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC1DN,PC1DN" "0,1"
|
|
bitfld.long 0x00 0. "PC0DN,PC0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port C Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PC7DN,PC7DN" "0,1"
|
|
bitfld.long 0x00 6. "PC6DN,PC6DN" "0,1"
|
|
bitfld.long 0x00 5. "PC5DN,PC5DN" "0,1"
|
|
bitfld.long 0x00 4. "PC4DN,PC4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PC3DN,PC3DN" "0,1"
|
|
bitfld.long 0x00 2. "PC2DN,PC2DN" "0,1"
|
|
bitfld.long 0x00 1. "PC1DN,PC1DN" "0,1"
|
|
bitfld.long 0x00 0. "PC0DN,PC0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port C Input Control Register"
|
|
bitfld.long 0x00 7. "PC7IE,PC7IE" "0,1"
|
|
bitfld.long 0x00 6. "PC6IE,PC6IE" "0,1"
|
|
bitfld.long 0x00 5. "PC5IE,PC5IE" "0,1"
|
|
bitfld.long 0x00 4. "PC4IE,PC4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PC3IE,PC3IE" "0,1"
|
|
bitfld.long 0x00 2. "PC2IE,PC2IE" "0,1"
|
|
bitfld.long 0x00 1. "PC1IE,PC1IE" "0,1"
|
|
bitfld.long 0x00 0. "PC0IE,PC0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PC Input Enable Control Register"
|
|
bitfld.long 0x00 0. "PC0IE,PC0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4L*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port C Input Control Register"
|
|
bitfld.long 0x00 3. "PC3IE,PC3IE" "0,1"
|
|
bitfld.long 0x00 2. "PC2IE,PC2IE" "0,1"
|
|
bitfld.long 0x00 1. "PC1IE,PC1IE" "0,1"
|
|
bitfld.long 0x00 0. "PC0IE,PC0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port C Input Control Register"
|
|
bitfld.long 0x00 5. "PC5IE,PC5IE" "0,1"
|
|
bitfld.long 0x00 4. "PC4IE,PC4IE" "0,1"
|
|
bitfld.long 0x00 3. "PC3IE,PC3IE" "0,1"
|
|
bitfld.long 0x00 2. "PC2IE,PC2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PC1IE,PC1IE" "0,1"
|
|
bitfld.long 0x00 0. "PC0IE,PC0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PC Input Enable Control Register"
|
|
bitfld.long 0x00 2. "PC2IE,PC2IE" "0,1"
|
|
bitfld.long 0x00 1. "PC1IE,PC1IE" "0,1"
|
|
bitfld.long 0x00 0. "PC0IE,PC0IE" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "PD (Port D)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E0300
|
|
elif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400C0300
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40080300
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port D Data Register"
|
|
bitfld.long 0x00 7. "PD7,PD7" "0,1"
|
|
bitfld.long 0x00 6. "PD6,PD6" "0,1"
|
|
bitfld.long 0x00 5. "PD5,PD5" "0,1"
|
|
bitfld.long 0x00 4. "PD4,PD4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PD3,PD3" "0,1"
|
|
bitfld.long 0x00 2. "PD2,PD2" "0,1"
|
|
bitfld.long 0x00 1. "PD1,PD1" "0,1"
|
|
bitfld.long 0x00 0. "PD0,PD0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port D Data Register"
|
|
bitfld.long 0x00 5. "PD5,PD5" "0,1"
|
|
bitfld.long 0x00 4. "PD4,PD4" "0,1"
|
|
bitfld.long 0x00 3. "PD3,PD3" "0,1"
|
|
bitfld.long 0x00 2. "PD2,PD2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PD1,PD1" "0,1"
|
|
bitfld.long 0x00 0. "PD0,PD0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PD Data Register"
|
|
bitfld.long 0x00 6. "PD6,PD6" "0,1"
|
|
bitfld.long 0x00 5. "PD5,PD5" "0,1"
|
|
bitfld.long 0x00 4. "PD4,PD4" "0,1"
|
|
bitfld.long 0x00 3. "PD3,PD3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PD2,PD2" "0,1"
|
|
bitfld.long 0x00 1. "PD1,PD1" "0,1"
|
|
bitfld.long 0x00 0. "PD0,PD0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port D Data Register"
|
|
bitfld.long 0x00 3. "PD3,PD3" "0,1"
|
|
bitfld.long 0x00 2. "PD2,PD2" "0,1"
|
|
bitfld.long 0x00 1. "PD1,PD1" "0,1"
|
|
bitfld.long 0x00 0. "PD0,PD0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PD Data Register"
|
|
bitfld.long 0x00 6. "PD6,PD6" "0,1"
|
|
bitfld.long 0x00 4. "PD4,PD4" "0,1"
|
|
bitfld.long 0x00 2. "PD2,PD2" "0,1"
|
|
bitfld.long 0x00 1. "PD1,PD1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0,PD0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port D Data Register"
|
|
bitfld.long 0x00 4. "PD4,PD4" "0,1"
|
|
bitfld.long 0x00 3. "PD3,PD3" "0,1"
|
|
bitfld.long 0x00 2. "PD2,PD2" "0,1"
|
|
bitfld.long 0x00 1. "PD1,PD1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0,PD0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port D Output Control Register"
|
|
bitfld.long 0x00 5. "PD5C,PD5C" "0,1"
|
|
bitfld.long 0x00 4. "PD4C,PD4C" "0,1"
|
|
bitfld.long 0x00 3. "PD3C,PD3C" "0,1"
|
|
bitfld.long 0x00 2. "PD2C,PD2C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PD1C,PD1C" "0,1"
|
|
bitfld.long 0x00 0. "PD0C,PD0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port D Output Control Register"
|
|
bitfld.long 0x00 3. "PD3C,PD3C" "0,1"
|
|
bitfld.long 0x00 2. "PD2C,PD2C" "0,1"
|
|
bitfld.long 0x00 1. "PD1C,PD1C" "0,1"
|
|
bitfld.long 0x00 0. "PD0C,PD0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PD Control Register"
|
|
bitfld.long 0x00 6. "PD6C,PD6C" "0,1"
|
|
bitfld.long 0x00 5. "PD5C,PD5C" "0,1"
|
|
bitfld.long 0x00 4. "PD4C,PD4C" "0,1"
|
|
bitfld.long 0x00 3. "PD3C,PD3C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PD2C,PD2C" "0,1"
|
|
bitfld.long 0x00 1. "PD1C,PD1C" "0,1"
|
|
bitfld.long 0x00 0. "PD0C,PD0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PD Control Register"
|
|
bitfld.long 0x00 6. "PD6C,PD6C" "0,1"
|
|
bitfld.long 0x00 4. "PD4C,PD4C" "0,1"
|
|
bitfld.long 0x00 2. "PD2C,PD2C" "0,1"
|
|
bitfld.long 0x00 1. "PD1C,PD1C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0C,PD0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port D Output Control Register"
|
|
bitfld.long 0x00 7. "PD7C,PD7C" "0,1"
|
|
bitfld.long 0x00 6. "PD6C,PD6C" "0,1"
|
|
bitfld.long 0x00 5. "PD5C,PD5C" "0,1"
|
|
bitfld.long 0x00 4. "PD4C,PD4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PD3C,PD3C" "0,1"
|
|
bitfld.long 0x00 2. "PD2C,PD2C" "0,1"
|
|
bitfld.long 0x00 1. "PD1C,PD1C" "0,1"
|
|
bitfld.long 0x00 0. "PD0C,PD0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port D Output Control Register"
|
|
bitfld.long 0x00 4. "PD4C,PD4C" "0,1"
|
|
bitfld.long 0x00 3. "PD3C,PD3C" "0,1"
|
|
bitfld.long 0x00 2. "PD2C,PD2C" "0,1"
|
|
bitfld.long 0x00 1. "PD1C,PD1C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0C,PD0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port D Function Register 1"
|
|
bitfld.long 0x00 3. "PD3F1,PD3F1" "0,1"
|
|
bitfld.long 0x00 2. "PD2F1,PD2F1" "0,1"
|
|
bitfld.long 0x00 1. "PD1F1,PD1F1" "0,1"
|
|
bitfld.long 0x00 0. "PD0F1,PD0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port D Function Register 1"
|
|
bitfld.long 0x00 7. "PD7F1,PD7F1" "0,1"
|
|
bitfld.long 0x00 6. "PD6F1,PD6F1" "0,1"
|
|
bitfld.long 0x00 5. "PD5F1,PD5F1" "0,1"
|
|
bitfld.long 0x00 4. "PD4F1,PD4F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PD3F1,PD3F1" "0,1"
|
|
bitfld.long 0x00 2. "PD2F1,PD2F1" "0,1"
|
|
bitfld.long 0x00 1. "PD1F1,PD1F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port D Function Register 1"
|
|
bitfld.long 0x00 3. "PD3F1,PD3F1" "0,1"
|
|
bitfld.long 0x00 2. "PD2F1,PD2F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port D Function Register 1"
|
|
bitfld.long 0x00 4. "PD4F1,PD4F1" "0,1"
|
|
bitfld.long 0x00 3. "PD3F1,PD3F1" "0,1"
|
|
bitfld.long 0x00 2. "PD2F1,PD2F1" "0,1"
|
|
bitfld.long 0x00 1. "PD1F1,PD1F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0F1,PD0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port D Function Register 2"
|
|
bitfld.long 0x00 7. "PD7F2,PD7F2" "0,1"
|
|
bitfld.long 0x00 6. "PD6F2,PD6F2" "0,1"
|
|
bitfld.long 0x00 1. "PD1F2,PD1F2" "0,1"
|
|
bitfld.long 0x00 0. "PD0F2,PD0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port D Function Register 2"
|
|
bitfld.long 0x00 4. "PD4F2,PD4F2" "0,1"
|
|
bitfld.long 0x00 3. "PD3F2,PD3F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port D Function Register 2"
|
|
bitfld.long 0x00 4. "PD4F2,PD4F2" "0,1"
|
|
bitfld.long 0x00 3. "PD3F2,PD3F2" "0,1"
|
|
bitfld.long 0x00 2. "PD2F2,PD2F2" "0,1"
|
|
bitfld.long 0x00 1. "PD1F2,PD1F2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0F2,PD0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port D Function Register 2"
|
|
bitfld.long 0x00 3. "PD3F2,PD3F2" "0,1"
|
|
bitfld.long 0x00 2. "PD2F2,PD2F2" "0,1"
|
|
bitfld.long 0x00 1. "PD1F2,PD1F2" "0,1"
|
|
bitfld.long 0x00 0. "PD0F2,PD0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port D Function Register 3"
|
|
bitfld.long 0x00 3. "PD3F3,PD3F3" "0,1"
|
|
bitfld.long 0x00 2. "PD2F2,PD2F2" "0,1"
|
|
bitfld.long 0x00 1. "PD1F3,PD1F3" "0,1"
|
|
bitfld.long 0x00 0. "PD0F3,PD0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port D Function Register 3"
|
|
bitfld.long 0x00 7. "PD7F3,PD7F3" "0,1"
|
|
bitfld.long 0x00 6. "PD6F3,PD6F3" "0,1"
|
|
bitfld.long 0x00 5. "PD5F3,PD5F3" "0,1"
|
|
bitfld.long 0x00 4. "PD4F3,PD4F3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PD3F3,PD3F3" "0,1"
|
|
bitfld.long 0x00 2. "PD2F2,PD2F2" "0,1"
|
|
bitfld.long 0x00 1. "PD1F3,PD1F3" "0,1"
|
|
bitfld.long 0x00 0. "PD0F3,PD0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port D Function Register 4"
|
|
bitfld.long 0x00 5. "PD5F4,PD5F4" "0,1"
|
|
bitfld.long 0x00 4. "PD4F4,PD4F4" "0,1"
|
|
bitfld.long 0x00 3. "PD3F4,PD3F4" "0,1"
|
|
bitfld.long 0x00 2. "PD2F4,PD2F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PD1F4,PD1F4" "0,1"
|
|
bitfld.long 0x00 0. "PD0F4,PD0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port D Function Register 4"
|
|
bitfld.long 0x00 3. "PD3F4,PD3F4" "0,1"
|
|
bitfld.long 0x00 2. "PD2F4,PD2F4" "0,1"
|
|
bitfld.long 0x00 1. "PD1F4,PD1F4" "0,1"
|
|
bitfld.long 0x00 0. "PD0F4,PD0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port D Function Register 4"
|
|
bitfld.long 0x00 3. "PD3F4,PD3F4" "0,1"
|
|
bitfld.long 0x00 2. "PD2F4,PD2F4" "0,1"
|
|
bitfld.long 0x00 0. "PD0F4,PD0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PD Function Register 5"
|
|
bitfld.long 0x00 6. "PD6F5,PD6F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port D Function Register 5"
|
|
bitfld.long 0x00 7. "PD7F5,PD7F5" "0,1"
|
|
bitfld.long 0x00 6. "PD6F5,PD6F5" "0,1"
|
|
bitfld.long 0x00 4. "PD4F5,PD4F5" "0,1"
|
|
bitfld.long 0x00 2. "PD2F5,PD2F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PD1F5,PD1F5" "0,1"
|
|
bitfld.long 0x00 0. "PD0F5,PD0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port D Function Register 5"
|
|
bitfld.long 0x00 3. "PD3F5,PD3F5" "0,1"
|
|
bitfld.long 0x00 2. "PD2F5,PD2F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port D Function Register 6"
|
|
bitfld.long 0x00 0. "PD0F6,PD0F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port D Function Register 6"
|
|
bitfld.long 0x00 5. "PD5F6,PD5F6" "0,1"
|
|
bitfld.long 0x00 4. "PD4F6,PD4F6" "0,1"
|
|
bitfld.long 0x00 3. "PD3F6,PD3F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port D Function Register 7"
|
|
bitfld.long 0x00 7. "PD7F7,PD7F7" "0,1"
|
|
bitfld.long 0x00 6. "PD6F7,PD6F7" "0,1"
|
|
bitfld.long 0x00 5. "PD5F7,PD5F7" "0,1"
|
|
bitfld.long 0x00 4. "PD4F7,PD4F7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PD3F7,PD3F7" "0,1"
|
|
bitfld.long 0x00 2. "PD2F7,PD2F7" "0,1"
|
|
bitfld.long 0x00 1. "PD1F7,PD1F7" "0,1"
|
|
bitfld.long 0x00 0. "PD0F7,PD0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PD Open Drain Control Register"
|
|
bitfld.long 0x00 6. "PD6OD,PD6OD" "0,1"
|
|
bitfld.long 0x00 4. "PD4OD,PD4OD" "0,1"
|
|
bitfld.long 0x00 2. "PD2OD,PD2OD" "0,1"
|
|
bitfld.long 0x00 1. "PD1OD,PD1OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0OD,PD0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PD Open Drain Control Register"
|
|
bitfld.long 0x00 6. "PD6OD,PD6OD" "0,1"
|
|
bitfld.long 0x00 5. "PD5OD,PD5OD" "0,1"
|
|
bitfld.long 0x00 4. "PD4OD,PD4OD" "0,1"
|
|
bitfld.long 0x00 3. "PD3OD,PD3OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PD2OD,PD2OD" "0,1"
|
|
bitfld.long 0x00 1. "PD1OD,PD1OD" "0,1"
|
|
bitfld.long 0x00 0. "PD0OD,PD0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port D Open Drain Control Register"
|
|
bitfld.long 0x00 5. "PD5OD,PD5OD" "0,1"
|
|
bitfld.long 0x00 4. "PD4OD,PD4OD" "0,1"
|
|
bitfld.long 0x00 3. "PD3OD,PD3OD" "0,1"
|
|
bitfld.long 0x00 2. "PD2OD,PD2OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PD1OD,PD1OD" "0,1"
|
|
bitfld.long 0x00 0. "PD0OD,PD0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port D Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PD7OD,PD7OD" "0,1"
|
|
bitfld.long 0x00 6. "PD6OD,PD6OD" "0,1"
|
|
bitfld.long 0x00 5. "PD5OD,PD5OD" "0,1"
|
|
bitfld.long 0x00 4. "PD4OD,PD4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PD3OD,PD3OD" "0,1"
|
|
bitfld.long 0x00 2. "PD2OD,PD2OD" "0,1"
|
|
bitfld.long 0x00 1. "PD1OD,PD1OD" "0,1"
|
|
bitfld.long 0x00 0. "PD0OD,PD0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port D Open Drain Control Register"
|
|
bitfld.long 0x00 3. "PD3OD,PD3OD" "0,1"
|
|
bitfld.long 0x00 2. "PD2OD,PD2OD" "0,1"
|
|
bitfld.long 0x00 1. "PD1OD,PD1OD" "0,1"
|
|
bitfld.long 0x00 0. "PD0OD,PD0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port D Open Drain Control Register"
|
|
bitfld.long 0x00 4. "PD4OD,PD4OD" "0,1"
|
|
bitfld.long 0x00 3. "PD3OD,PD3OD" "0,1"
|
|
bitfld.long 0x00 2. "PD2OD,PD2OD" "0,1"
|
|
bitfld.long 0x00 1. "PD1OD,PD1OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0OD,PD0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port D Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PD7UP,PD7UP" "0,1"
|
|
bitfld.long 0x00 6. "PD6UP,PD6UP" "0,1"
|
|
bitfld.long 0x00 5. "PD5UP,PD5UP" "0,1"
|
|
bitfld.long 0x00 4. "PD4UP,PD4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PD3UP,PD3UP" "0,1"
|
|
bitfld.long 0x00 2. "PD2UP,PD2UP" "0,1"
|
|
bitfld.long 0x00 1. "PD1UP,PD1UP" "0,1"
|
|
bitfld.long 0x00 0. "PD0UP,PD0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port D Pull-up Control Register"
|
|
bitfld.long 0x00 5. "PD5UP,PD5UP" "0,1"
|
|
bitfld.long 0x00 4. "PD4UP,PD4UP" "0,1"
|
|
bitfld.long 0x00 3. "PD3UP,PD3UP" "0,1"
|
|
bitfld.long 0x00 2. "PD2UP,PD2UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PD1UP,PD1UP" "0,1"
|
|
bitfld.long 0x00 0. "PD0UP,PD0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port D Pull-up Control Register"
|
|
bitfld.long 0x00 3. "PD3UP,PD3UP" "0,1"
|
|
bitfld.long 0x00 2. "PD2UP,PD2UP" "0,1"
|
|
bitfld.long 0x00 1. "PD1UP,PD1UP" "0,1"
|
|
bitfld.long 0x00 0. "PD0UP,PD0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PD Pull-up Control Register"
|
|
bitfld.long 0x00 6. "PD6PUP,PD6PUP" "0,1"
|
|
bitfld.long 0x00 5. "PD5PUP,PD5PUP" "0,1"
|
|
bitfld.long 0x00 4. "PD4PUP,PD4PUP" "0,1"
|
|
bitfld.long 0x00 3. "PD3PUP,PD3PUP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PD2PUP,PD2PUP" "0,1"
|
|
bitfld.long 0x00 1. "PD1PUP,PD1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PD0PUP,PD0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port D Pull-up Control Register"
|
|
bitfld.long 0x00 4. "PD4UP,PD4UP" "0,1"
|
|
bitfld.long 0x00 3. "PD3UP,PD3UP" "0,1"
|
|
bitfld.long 0x00 2. "PD2UP,PD2UP" "0,1"
|
|
bitfld.long 0x00 1. "PD1UP,PD1UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0UP,PD0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PD Pull-up Control Register"
|
|
bitfld.long 0x00 6. "PD6PUP,PD6PUP" "0,1"
|
|
bitfld.long 0x00 4. "PD4PUP,PD4PUP" "0,1"
|
|
bitfld.long 0x00 2. "PD2PUP,PD2PUP" "0,1"
|
|
bitfld.long 0x00 1. "PD1PUP,PD1PUP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0PUP,PD0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port D Pull-down Control Register"
|
|
bitfld.long 0x00 5. "PD5DN,PD5DN" "0,1"
|
|
bitfld.long 0x00 4. "PD4DN,PD4DN" "0,1"
|
|
bitfld.long 0x00 3. "PD3DN,PD3DN" "0,1"
|
|
bitfld.long 0x00 2. "PD2DN,PD2DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PD1DN,PD1DN" "0,1"
|
|
bitfld.long 0x00 0. "PD0DN,PD0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port D Pull-down Control Register"
|
|
bitfld.long 0x00 3. "PD3DN,PD3DN" "0,1"
|
|
bitfld.long 0x00 2. "PD2DN,PD2DN" "0,1"
|
|
bitfld.long 0x00 1. "PD1DN,PD1DN" "0,1"
|
|
bitfld.long 0x00 0. "PD0DN,PD0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port D Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PD7DN,PD7DN" "0,1"
|
|
bitfld.long 0x00 6. "PD6DN,PD6DN" "0,1"
|
|
bitfld.long 0x00 5. "PD5DN,PD5DN" "0,1"
|
|
bitfld.long 0x00 4. "PD4DN,PD4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PD3DN,PD3DN" "0,1"
|
|
bitfld.long 0x00 2. "PD2DN,PD2DN" "0,1"
|
|
bitfld.long 0x00 1. "PD1DN,PD1DN" "0,1"
|
|
bitfld.long 0x00 0. "PD0DN,PD0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PD Pull-Down Control Register"
|
|
bitfld.long 0x00 6. "PD6PDN,PD6PDN" "0,1"
|
|
bitfld.long 0x00 5. "PD5PDN,PD5PDN" "0,1"
|
|
bitfld.long 0x00 4. "PD4PDN,PD4PDN" "0,1"
|
|
bitfld.long 0x00 3. "PD3PDN,PD3PDN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PD2PDN,PD2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PD1PDN,PD1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PD0PDN,PD0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port D Pull-down Control Register"
|
|
bitfld.long 0x00 4. "PD4DN,PD4DN" "0,1"
|
|
bitfld.long 0x00 3. "PD3DN,PD3DN" "0,1"
|
|
bitfld.long 0x00 2. "PD2DN,PD2DN" "0,1"
|
|
bitfld.long 0x00 1. "PD1DN,PD1DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0DN,PD0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PD Pull-Down Control Register"
|
|
bitfld.long 0x00 6. "PD6PDN,PD6PDN" "0,1"
|
|
bitfld.long 0x00 4. "PD4PDN,PD4PDN" "0,1"
|
|
bitfld.long 0x00 2. "PD2PDN,PD2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PD1PDN,PD1PDN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0PDN,PD0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PD Input Enable Control Register"
|
|
bitfld.long 0x00 6. "PD6IE,PD6IE" "0,1"
|
|
bitfld.long 0x00 5. "PD5IE,PD5IE" "0,1"
|
|
bitfld.long 0x00 4. "PD4IE,PD4IE" "0,1"
|
|
bitfld.long 0x00 3. "PD3IE,PD3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PD2IE,PD2IE" "0,1"
|
|
bitfld.long 0x00 1. "PD1IE,PD1IE" "0,1"
|
|
bitfld.long 0x00 0. "PD0IE,PD0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port D Input Control Register"
|
|
bitfld.long 0x00 3. "PD3IE,PD3IE" "0,1"
|
|
bitfld.long 0x00 2. "PD2IE,PD2IE" "0,1"
|
|
bitfld.long 0x00 1. "PD1IE,PD1IE" "0,1"
|
|
bitfld.long 0x00 0. "PD0IE,PD0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port D Input Control Register"
|
|
bitfld.long 0x00 7. "PD7IE,PD7IE" "0,1"
|
|
bitfld.long 0x00 6. "PD6IE,PD6IE" "0,1"
|
|
bitfld.long 0x00 5. "PD5IE,PD5IE" "0,1"
|
|
bitfld.long 0x00 4. "PD4IE,PD4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PD3IE,PD3IE" "0,1"
|
|
bitfld.long 0x00 2. "PD2IE,PD2IE" "0,1"
|
|
bitfld.long 0x00 1. "PD1IE,PD1IE" "0,1"
|
|
bitfld.long 0x00 0. "PD0IE,PD0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port D Input Control Register"
|
|
bitfld.long 0x00 4. "PD4IE,PD4IE" "0,1"
|
|
bitfld.long 0x00 3. "PD3IE,PD3IE" "0,1"
|
|
bitfld.long 0x00 2. "PD2IE,PD2IE" "0,1"
|
|
bitfld.long 0x00 1. "PD1IE,PD1IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0IE,PD0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port D Input Control Register"
|
|
bitfld.long 0x00 5. "PD5IE,PD5IE" "0,1"
|
|
bitfld.long 0x00 4. "PD4IE,PD4IE" "0,1"
|
|
bitfld.long 0x00 3. "PD3IE,PD3IE" "0,1"
|
|
bitfld.long 0x00 2. "PD2IE,PD2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PD1IE,PD1IE" "0,1"
|
|
bitfld.long 0x00 0. "PD0IE,PD0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PD Input Enable Control Register"
|
|
bitfld.long 0x00 6. "PD6IE,PD6IE" "0,1"
|
|
bitfld.long 0x00 4. "PD4IE,PD4IE" "0,1"
|
|
bitfld.long 0x00 2. "PD2IE,PD2IE" "0,1"
|
|
bitfld.long 0x00 1. "PD1IE,PD1IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PD0IE,PD0IE" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "PE (Port E)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E0400
|
|
elif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400C0400
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40080400
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port E Data Register"
|
|
bitfld.long 0x00 6. "PE6,PE6" "0,1"
|
|
bitfld.long 0x00 5. "PE5,PE5" "0,1"
|
|
bitfld.long 0x00 4. "PE4,PE4" "0,1"
|
|
bitfld.long 0x00 3. "PE3,PE3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE2,PE2" "0,1"
|
|
bitfld.long 0x00 1. "PE1,PE1" "0,1"
|
|
bitfld.long 0x00 0. "PE0,PE0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PE Data Register"
|
|
bitfld.long 0x00 5. "PE5,PE5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PE Data Register"
|
|
bitfld.long 0x00 5. "PE5,PE5" "0,1"
|
|
bitfld.long 0x00 2. "PE2,PE2" "0,1"
|
|
bitfld.long 0x00 1. "PE1,PE1" "0,1"
|
|
bitfld.long 0x00 0. "PE0,PE0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PE Data Register"
|
|
bitfld.long 0x00 5. "PE5,PE5" "0,1"
|
|
bitfld.long 0x00 4. "PE4,PE4" "0,1"
|
|
bitfld.long 0x00 3. "PE3,PE3" "0,1"
|
|
bitfld.long 0x00 2. "PE2,PE2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PE1,PE1" "0,1"
|
|
bitfld.long 0x00 0. "PE0,PE0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PE Data Register"
|
|
bitfld.long 0x00 5. "PE5,PE5" "0,1"
|
|
bitfld.long 0x00 1. "PE1,PE1" "0,1"
|
|
bitfld.long 0x00 0. "PE0,PE0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port E Data Register"
|
|
bitfld.long 0x00 7. "PE7,PE7" "0,1"
|
|
bitfld.long 0x00 6. "PE6,PE6" "0,1"
|
|
bitfld.long 0x00 5. "PE5,PE5" "0,1"
|
|
bitfld.long 0x00 4. "PE4,PE4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE3,PE3" "0,1"
|
|
bitfld.long 0x00 2. "PE2,PE2" "0,1"
|
|
bitfld.long 0x00 1. "PE1,PE1" "0,1"
|
|
bitfld.long 0x00 0. "PE0,PE0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port E Output Control Register"
|
|
bitfld.long 0x00 6. "PE6C,PE6C" "0,1"
|
|
bitfld.long 0x00 5. "PE5C,PE5C" "0,1"
|
|
bitfld.long 0x00 4. "PE4C,PE4C" "0,1"
|
|
bitfld.long 0x00 3. "PE3C,PE3C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE2C,PE2C" "0,1"
|
|
bitfld.long 0x00 1. "PE1C,PE1C" "0,1"
|
|
bitfld.long 0x00 0. "PE0C,PE0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PE Control Register"
|
|
bitfld.long 0x00 5. "PE5C,PE5C" "0,1"
|
|
bitfld.long 0x00 4. "PE4C,PE4C" "0,1"
|
|
bitfld.long 0x00 3. "PE3C,PE3C" "0,1"
|
|
bitfld.long 0x00 2. "PE2C,PE2C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PE1C,PE1C" "0,1"
|
|
bitfld.long 0x00 0. "PE0C,PE0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PE Control Register"
|
|
bitfld.long 0x00 5. "PE5C,PE5C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PE Control Register"
|
|
bitfld.long 0x00 5. "PE5C,PE5C" "0,1"
|
|
bitfld.long 0x00 1. "PE1C,PE1C" "0,1"
|
|
bitfld.long 0x00 0. "PE0C,PE0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PE Control Register"
|
|
bitfld.long 0x00 5. "PE5C,PE5C" "0,1"
|
|
bitfld.long 0x00 2. "PE2C,PE2C" "0,1"
|
|
bitfld.long 0x00 1. "PE1C,PE1C" "0,1"
|
|
bitfld.long 0x00 0. "PE0C,PE0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port E Output Control Register"
|
|
bitfld.long 0x00 7. "PE7C,PE7C" "0,1"
|
|
bitfld.long 0x00 6. "PE6C,PE6C" "0,1"
|
|
bitfld.long 0x00 5. "PE5C,PE5C" "0,1"
|
|
bitfld.long 0x00 4. "PE4C,PE4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE3C,PE3C" "0,1"
|
|
bitfld.long 0x00 2. "PE2C,PE2C" "0,1"
|
|
bitfld.long 0x00 1. "PE1C,PE1C" "0,1"
|
|
bitfld.long 0x00 0. "PE0C,PE0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port E Function Register 1"
|
|
bitfld.long 0x00 1. "PE1F1,PE1F1" "0,1"
|
|
bitfld.long 0x00 0. "PE0F1,PE0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port E Function Register 1"
|
|
bitfld.long 0x00 7. "PE7F1,PE7F1" "0,1"
|
|
bitfld.long 0x00 6. "PE6F1,PE6F1" "0,1"
|
|
bitfld.long 0x00 5. "PE5F1,PE5F1" "0,1"
|
|
bitfld.long 0x00 4. "PE4F1,PE4F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE3F1,PE3F1" "0,1"
|
|
bitfld.long 0x00 2. "PE2F1,PE2F1" "0,1"
|
|
bitfld.long 0x00 1. "PE1F1,PE1F1" "0,1"
|
|
bitfld.long 0x00 0. "PE0F1,PE0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port E Function Register 2"
|
|
bitfld.long 0x00 7. "PE7F2,PE7F2" "0,1"
|
|
bitfld.long 0x00 0. "PE0F2,PE0F2" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port E Function Register 3"
|
|
bitfld.long 0x00 7. "PE7F3,PE7F3" "0,1"
|
|
bitfld.long 0x00 6. "PE6F3,PE6F3" "0,1"
|
|
bitfld.long 0x00 5. "PE5F3,PE5F3" "0,1"
|
|
bitfld.long 0x00 4. "PE4F3,PE4F3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE3F3,PE3F3" "0,1"
|
|
bitfld.long 0x00 2. "PE2F3,PE2F3" "0,1"
|
|
bitfld.long 0x00 0. "PE0F3,PE0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port E Function Register 4"
|
|
bitfld.long 0x00 6. "PE6F4,PE6F4" "0,1"
|
|
bitfld.long 0x00 5. "PE5F4,PE5F4" "0,1"
|
|
bitfld.long 0x00 4. "PE4F4,PE4F4" "0,1"
|
|
bitfld.long 0x00 3. "PE3F4,PE3F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE2F4,PE2F4" "0,1"
|
|
bitfld.long 0x00 1. "PE1F4,PE1F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port E Function Register 4"
|
|
bitfld.long 0x00 7. "PE7F4,PE7F4" "0,1"
|
|
bitfld.long 0x00 6. "PE6F4,PE6F4" "0,1"
|
|
bitfld.long 0x00 5. "PE5F4,PE5F4" "0,1"
|
|
bitfld.long 0x00 4. "PE4F4,PE4F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE3F4,PE3F4" "0,1"
|
|
bitfld.long 0x00 2. "PE2F4,PE2F4" "0,1"
|
|
bitfld.long 0x00 0. "PE0F4,PE0F4" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port E Function Register 5"
|
|
bitfld.long 0x00 7. "PE7F5,PE7F5" "0,1"
|
|
bitfld.long 0x00 6. "PE6F5,PE6F5" "0,1"
|
|
bitfld.long 0x00 5. "PE5F5,PE5F5" "0,1"
|
|
bitfld.long 0x00 4. "PE4F5,PE4F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE3F5,PE3F5" "0,1"
|
|
bitfld.long 0x00 2. "PE2F5,PE2F5" "0,1"
|
|
bitfld.long 0x00 0. "PE0F5,PE0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port E Function Register 5"
|
|
bitfld.long 0x00 3. "PE3F5,PE3F5" "0,1"
|
|
bitfld.long 0x00 2. "PE2F5,PE2F5" "0,1"
|
|
bitfld.long 0x00 1. "PE1F5,PE1F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port E Function Register 6"
|
|
bitfld.long 0x00 6. "PE6F6,PE6F6" "0,1"
|
|
bitfld.long 0x00 5. "PE5F6,PE5F6" "0,1"
|
|
bitfld.long 0x00 4. "PE4F6,PE4F6" "0,1"
|
|
bitfld.long 0x00 3. "PE3F6,PE3F6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE2F6,PE2F6" "0,1"
|
|
bitfld.long 0x00 1. "PE1F6,PE1F6" "0,1"
|
|
bitfld.long 0x00 0. "PE0F6,PE0F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port E Function Register 6"
|
|
bitfld.long 0x00 7. "PE7F6,PE7F6" "0,1"
|
|
bitfld.long 0x00 6. "PE6F6,PE6F6" "0,1"
|
|
bitfld.long 0x00 5. "PE5F6,PE5F6" "0,1"
|
|
bitfld.long 0x00 4. "PE4F6,PE4F6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE3F6,PE3F6" "0,1"
|
|
bitfld.long 0x00 2. "PE2F6,PE2F6" "0,1"
|
|
bitfld.long 0x00 1. "PE1F6,PE1F6" "0,1"
|
|
bitfld.long 0x00 0. "PE0F6,PE0F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port E Function Register 7"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port E Function Register 7"
|
|
bitfld.long 0x00 7. "PE7F7,PE7F7" "0,1"
|
|
bitfld.long 0x00 6. "PE6F7,PE6F7" "0,1"
|
|
bitfld.long 0x00 5. "PE5F7,PE5F7" "0,1"
|
|
bitfld.long 0x00 4. "PE4F7,PE4F7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE3F7,PE3F7" "0,1"
|
|
bitfld.long 0x00 2. "PE2F7,PE2F7" "0,1"
|
|
bitfld.long 0x00 0. "PE0F7,PE0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port E Function Register 7"
|
|
bitfld.long 0x00 7. "PE7F7,PE7F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port E Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PE7OD,PE7OD" "0,1"
|
|
bitfld.long 0x00 6. "PE6OD,PE6OD" "0,1"
|
|
bitfld.long 0x00 5. "PE5OD,PE5OD" "0,1"
|
|
bitfld.long 0x00 4. "PE4OD,PE4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE3OD,PE3OD" "0,1"
|
|
bitfld.long 0x00 2. "PE2OD,PE2OD" "0,1"
|
|
bitfld.long 0x00 1. "PE1OD,PE1OD" "0,1"
|
|
bitfld.long 0x00 0. "PE0OD,PE0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PE Open Drain Control Register"
|
|
bitfld.long 0x00 5. "PE5OD,PE5OD" "0,1"
|
|
bitfld.long 0x00 2. "PE2OD,PE2OD" "0,1"
|
|
bitfld.long 0x00 1. "PE1OD,PE1OD" "0,1"
|
|
bitfld.long 0x00 0. "PE0OD,PE0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port E Open Drain Control Register"
|
|
bitfld.long 0x00 6. "PE6OD,PE6OD" "0,1"
|
|
bitfld.long 0x00 5. "PE5OD,PE5OD" "0,1"
|
|
bitfld.long 0x00 4. "PE4OD,PE4OD" "0,1"
|
|
bitfld.long 0x00 3. "PE3OD,PE3OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE2OD,PE2OD" "0,1"
|
|
bitfld.long 0x00 1. "PE1OD,PE1OD" "0,1"
|
|
bitfld.long 0x00 0. "PE0OD,PE0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PE Open Drain Control Register"
|
|
bitfld.long 0x00 5. "PE5OD,PE5OD" "0,1"
|
|
bitfld.long 0x00 1. "PE1OD,PE1OD" "0,1"
|
|
bitfld.long 0x00 0. "PE0OD,PE0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PE Open Drain Control Register"
|
|
bitfld.long 0x00 5. "PE5OD,PE5OD" "0,1"
|
|
bitfld.long 0x00 4. "PE4OD,PE4OD" "0,1"
|
|
bitfld.long 0x00 3. "PE3OD,PE3OD" "0,1"
|
|
bitfld.long 0x00 2. "PE2OD,PE2OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PE1OD,PE1OD" "0,1"
|
|
bitfld.long 0x00 0. "PE0OD,PE0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PE Open Drain Control Register"
|
|
bitfld.long 0x00 5. "PE5OD,PE5OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port E Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PE7UP,PE7UP" "0,1"
|
|
bitfld.long 0x00 6. "PE6UP,PE6UP" "0,1"
|
|
bitfld.long 0x00 5. "PE5UP,PE5UP" "0,1"
|
|
bitfld.long 0x00 4. "PE4UP,PE4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE3UP,PE3UP" "0,1"
|
|
bitfld.long 0x00 2. "PE2UP,PE2UP" "0,1"
|
|
bitfld.long 0x00 1. "PE1UP,PE1UP" "0,1"
|
|
bitfld.long 0x00 0. "PE0UP,PE0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port E Pull-up Control Register"
|
|
bitfld.long 0x00 6. "PE6UP,PE6UP" "0,1"
|
|
bitfld.long 0x00 5. "PE5UP,PE5UP" "0,1"
|
|
bitfld.long 0x00 4. "PE4UP,PE4UP" "0,1"
|
|
bitfld.long 0x00 3. "PE3UP,PE3UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE2UP,PE2UP" "0,1"
|
|
bitfld.long 0x00 1. "PE1UP,PE1UP" "0,1"
|
|
bitfld.long 0x00 0. "PE0UP,PE0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PE Pull-up Control Register"
|
|
bitfld.long 0x00 5. "PE5PUP,PE5PUP" "0,1"
|
|
bitfld.long 0x00 1. "PE1PUP,PE1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PE0PUP,PE0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PE Pull-up Control Register"
|
|
bitfld.long 0x00 5. "PE5PUP,PE5PUP" "0,1"
|
|
bitfld.long 0x00 2. "PE2PUP,PE2PUP" "0,1"
|
|
bitfld.long 0x00 1. "PE1PUP,PE1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PE0PUP,PE0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PE Pull-up Control Register"
|
|
bitfld.long 0x00 5. "PE5PUP,PE5PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PE Pull-up Control Register"
|
|
bitfld.long 0x00 5. "PE5PUP,PE5PUP" "0,1"
|
|
bitfld.long 0x00 4. "PE4PUP,PE4PUP" "0,1"
|
|
bitfld.long 0x00 3. "PE3PUP,PE3PUP" "0,1"
|
|
bitfld.long 0x00 2. "PE2PUP,PE2PUP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PE1PUP,PE1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PE0PUP,PE0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PE Pull-Down Control Register"
|
|
bitfld.long 0x00 5. "PE5PDN,PE5PDN" "0,1"
|
|
bitfld.long 0x00 2. "PE2PDN,PE2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PE1PDN,PE1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PE0PDN,PE0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port E Pull-down Control Register"
|
|
bitfld.long 0x00 6. "PE6DN,PE6DN" "0,1"
|
|
bitfld.long 0x00 5. "PE5DN,PE5DN" "0,1"
|
|
bitfld.long 0x00 4. "PE4DN,PE4DN" "0,1"
|
|
bitfld.long 0x00 3. "PE3DN,PE3DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE2DN,PE2DN" "0,1"
|
|
bitfld.long 0x00 1. "PE1DN,PE1DN" "0,1"
|
|
bitfld.long 0x00 0. "PE0DN,PE0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PE Pull-Down Control Register"
|
|
bitfld.long 0x00 5. "PE5PDN,PE5PDN" "0,1"
|
|
bitfld.long 0x00 1. "PE1PDN,PE1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PE0PDN,PE0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PE Pull-Down Control Register"
|
|
bitfld.long 0x00 5. "PE5PDN,PE5PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PE Pull-Down Control Register"
|
|
bitfld.long 0x00 5. "PE5PDN,PE5PDN" "0,1"
|
|
bitfld.long 0x00 4. "PE4PDN,PE4PDN" "0,1"
|
|
bitfld.long 0x00 3. "PE3PDN,PE3PDN" "0,1"
|
|
bitfld.long 0x00 2. "PE2PDN,PE2PDN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PE1PDN,PE1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PE0PDN,PE0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port E Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PE7DN,PE7DN" "0,1"
|
|
bitfld.long 0x00 6. "PE6DN,PE6DN" "0,1"
|
|
bitfld.long 0x00 5. "PE5DN,PE5DN" "0,1"
|
|
bitfld.long 0x00 4. "PE4DN,PE4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE3DN,PE3DN" "0,1"
|
|
bitfld.long 0x00 2. "PE2DN,PE2DN" "0,1"
|
|
bitfld.long 0x00 1. "PE1DN,PE1DN" "0,1"
|
|
bitfld.long 0x00 0. "PE0DN,PE0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port E Input Control Register"
|
|
bitfld.long 0x00 6. "PE6IE,PE6IE" "0,1"
|
|
bitfld.long 0x00 5. "PE5IE,PE5IE" "0,1"
|
|
bitfld.long 0x00 4. "PE4IE,PE4IE" "0,1"
|
|
bitfld.long 0x00 3. "PE3IE,PE3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE2IE,PE2IE" "0,1"
|
|
bitfld.long 0x00 1. "PE1IE,PE1IE" "0,1"
|
|
bitfld.long 0x00 0. "PE0IE,PE0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PE Input Enable Control Register"
|
|
bitfld.long 0x00 5. "PE5IE,PE5IE" "0,1"
|
|
bitfld.long 0x00 2. "PE2IE,PE2IE" "0,1"
|
|
bitfld.long 0x00 1. "PE1IE,PE1IE" "0,1"
|
|
bitfld.long 0x00 0. "PE0IE,PE0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PE Input Enable Control Register"
|
|
bitfld.long 0x00 5. "PE5IE,PE5IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PE Input Enable Control Register"
|
|
bitfld.long 0x00 5. "PE5IE,PE5IE" "0,1"
|
|
bitfld.long 0x00 1. "PE1IE,PE1IE" "0,1"
|
|
bitfld.long 0x00 0. "PE0IE,PE0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PE Input Enable Control Register"
|
|
bitfld.long 0x00 5. "PE5IE,PE5IE" "0,1"
|
|
bitfld.long 0x00 4. "PE4IE,PE4IE" "0,1"
|
|
bitfld.long 0x00 3. "PE3IE,PE3IE" "0,1"
|
|
bitfld.long 0x00 2. "PE2IE,PE2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PE1IE,PE1IE" "0,1"
|
|
bitfld.long 0x00 0. "PE0IE,PE0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port E Input Control Register"
|
|
bitfld.long 0x00 7. "PE7IE,PE7IE" "0,1"
|
|
bitfld.long 0x00 6. "PE6IE,PE6IE" "0,1"
|
|
bitfld.long 0x00 5. "PE5IE,PE5IE" "0,1"
|
|
bitfld.long 0x00 4. "PE4IE,PE4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE3IE,PE3IE" "0,1"
|
|
bitfld.long 0x00 2. "PE2IE,PE2IE" "0,1"
|
|
bitfld.long 0x00 1. "PE1IE,PE1IE" "0,1"
|
|
bitfld.long 0x00 0. "PE0IE,PE0IE" "0,1"
|
|
endif
|
|
tree.end
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "PF (Port F)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E0500
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40080500
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port F Data Register"
|
|
bitfld.long 0x00 1. "PF1,PF1" "0,1"
|
|
bitfld.long 0x00 0. "PF0,PF0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port F Data Register"
|
|
bitfld.long 0x00 7. "PF7,PF7" "0,1"
|
|
bitfld.long 0x00 6. "PF6,PF6" "0,1"
|
|
bitfld.long 0x00 5. "PF5,PF5" "0,1"
|
|
bitfld.long 0x00 4. "PF4,PF4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PF3,PF3" "0,1"
|
|
bitfld.long 0x00 2. "PF2,PF2" "0,1"
|
|
bitfld.long 0x00 1. "PF1,PF1" "0,1"
|
|
bitfld.long 0x00 0. "PF0,PF0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port F Data Register"
|
|
bitfld.long 0x00 7. "PF7,PF7" "0,1"
|
|
bitfld.long 0x00 6. "PF6,PF6" "0,1"
|
|
bitfld.long 0x00 4. "PF4,PF4" "0,1"
|
|
bitfld.long 0x00 3. "PF3,PF3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1,PF1" "0,1"
|
|
bitfld.long 0x00 0. "PF0,PF0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port F Data Register"
|
|
bitfld.long 0x00 7. "PF7,PF7" "0,1"
|
|
bitfld.long 0x00 6. "PF6,PF6" "0,1"
|
|
bitfld.long 0x00 3. "PF3,PF3" "0,1"
|
|
bitfld.long 0x00 2. "PF2,PF2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1,PF1" "0,1"
|
|
bitfld.long 0x00 0. "PF0,PF0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port F Data Register"
|
|
bitfld.long 0x00 0. "PF0,PF0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port F Output Control Register"
|
|
bitfld.long 0x00 7. "PF7C,PF7C" "0,1"
|
|
bitfld.long 0x00 6. "PF6C,PF6C" "0,1"
|
|
bitfld.long 0x00 4. "PF4C,PF4C" "0,1"
|
|
bitfld.long 0x00 3. "PF3C,PF3C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1C,PF1C" "0,1"
|
|
bitfld.long 0x00 0. "PF0C,PF0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port F Output Control Register"
|
|
bitfld.long 0x00 7. "PF7C,PF7C" "0,1"
|
|
bitfld.long 0x00 6. "PF6C,PF6C" "0,1"
|
|
bitfld.long 0x00 3. "PF3C,PF3C" "0,1"
|
|
bitfld.long 0x00 2. "PF2C,PF2C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1C,PF1C" "0,1"
|
|
bitfld.long 0x00 0. "PF0C,PF0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port F Output Control Register"
|
|
bitfld.long 0x00 7. "PF7C,PF7C" "0,1"
|
|
bitfld.long 0x00 6. "PF6C,PF6C" "0,1"
|
|
bitfld.long 0x00 5. "PF5C,PF5C" "0,1"
|
|
bitfld.long 0x00 4. "PF4C,PF4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PF3C,PF3C" "0,1"
|
|
bitfld.long 0x00 2. "PF2C,PF2C" "0,1"
|
|
bitfld.long 0x00 1. "PF1C,PF1C" "0,1"
|
|
bitfld.long 0x00 0. "PF0C,PF0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port F Output Control Register"
|
|
bitfld.long 0x00 1. "PF1C,PF1C" "0,1"
|
|
bitfld.long 0x00 0. "PF0C,PF0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port F Output Control Register"
|
|
bitfld.long 0x00 0. "PF0C,PF0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port F Function Register 1"
|
|
bitfld.long 0x00 7. "PF7F1,PF7F1" "0,1"
|
|
bitfld.long 0x00 6. "PF6F1,PF6F1" "0,1"
|
|
bitfld.long 0x00 5. "PF5F1,PF5F1" "0,1"
|
|
bitfld.long 0x00 4. "PF4F1,PF4F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1F1,PF1F1" "0,1"
|
|
bitfld.long 0x00 0. "PF0F1,PF0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port F Function Register 1"
|
|
bitfld.long 0x00 7. "PF7F1,PF7F1" "0,1"
|
|
bitfld.long 0x00 6. "PF6F1,PF6F1" "0,1"
|
|
bitfld.long 0x00 1. "PF1F1,PF1F1" "0,1"
|
|
bitfld.long 0x00 0. "PF0F1,PF0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port F Function Register 1"
|
|
bitfld.long 0x00 1. "PF1F1,PF1F1" "0,1"
|
|
bitfld.long 0x00 0. "PF0F1,PF0F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port F Function Register 1"
|
|
bitfld.long 0x00 7. "PF7F1,PF7F1" "0,1"
|
|
bitfld.long 0x00 6. "PF6F1,PF6F1" "0,1"
|
|
bitfld.long 0x00 4. "PF4F1,PF4F1" "0,1"
|
|
bitfld.long 0x00 3. "PF3F1,PF3F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1F1,PF1F1" "0,1"
|
|
bitfld.long 0x00 0. "PF0F1,PF0F1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port F Function Register 2"
|
|
bitfld.long 0x00 7. "PF7F2,PF7F2" "0,1"
|
|
bitfld.long 0x00 6. "PF6F2,PF6F2" "0,1"
|
|
bitfld.long 0x00 4. "PF4F2,PF4F2" "0,1"
|
|
bitfld.long 0x00 3. "PF3F2,PF3F2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1F2,PF1F2" "0,1"
|
|
bitfld.long 0x00 0. "PF0F2,PF0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port F Function Register 2"
|
|
bitfld.long 0x00 1. "PF1F2,PF1F2" "0,1"
|
|
bitfld.long 0x00 0. "PF0F2,PF0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port F Function Register 3"
|
|
bitfld.long 0x00 7. "PF7F3,PF7F3" "0,1"
|
|
bitfld.long 0x00 6. "PF6F3,PF6F3" "0,1"
|
|
bitfld.long 0x00 4. "PF4F3,PF4F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port F Function Register 3"
|
|
bitfld.long 0x00 7. "PF7F3,PF7F3" "0,1"
|
|
bitfld.long 0x00 6. "PF6F3,PF6F3" "0,1"
|
|
bitfld.long 0x00 5. "PF5F3,PF5F3" "0,1"
|
|
bitfld.long 0x00 4. "PF4F3,PF4F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port F Function Register 3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port F Function Register 4"
|
|
bitfld.long 0x00 1. "PF1F4,PF1F4" "0,1"
|
|
bitfld.long 0x00 0. "PF0F4,PF0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port F Function Register 4"
|
|
bitfld.long 0x00 7. "PF7F4,PF7F4" "0,1"
|
|
bitfld.long 0x00 6. "PF6F4,PF6F4" "0,1"
|
|
bitfld.long 0x00 4. "PF4F4,PF4F4" "0,1"
|
|
bitfld.long 0x00 3. "PF3F4,PF3F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1F4,PF1F4" "0,1"
|
|
bitfld.long 0x00 0. "PF0F4,PF0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port F Function Register 4"
|
|
bitfld.long 0x00 7. "PF7F4,PF7F4" "0,1"
|
|
bitfld.long 0x00 6. "PF6F4,PF6F4" "0,1"
|
|
bitfld.long 0x00 5. "PF5F4,PF5F4" "0,1"
|
|
bitfld.long 0x00 4. "PF4F4,PF4F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PF3F4,PF3F4" "0,1"
|
|
bitfld.long 0x00 2. "PF2F4,PF2F4" "0,1"
|
|
bitfld.long 0x00 1. "PF1F4,PF1F4" "0,1"
|
|
bitfld.long 0x00 0. "PF0F4,PF0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port F Function Register 5"
|
|
bitfld.long 0x00 4. "PF4F5,PF4F5" "0,1"
|
|
bitfld.long 0x00 3. "PF3F5,PF3F5" "0,1"
|
|
bitfld.long 0x00 1. "PF1F5,PF1F5" "0,1"
|
|
bitfld.long 0x00 0. "PF0F5,PF0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port F Function Register 5"
|
|
bitfld.long 0x00 5. "PF5F5,PF5F5" "0,1"
|
|
bitfld.long 0x00 4. "PF4F5,PF4F5" "0,1"
|
|
bitfld.long 0x00 3. "PF3F5,PF3F5" "0,1"
|
|
bitfld.long 0x00 2. "PF2F5,PF2F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1F5,PF1F5" "0,1"
|
|
bitfld.long 0x00 0. "PF0F5,PF0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port F Function Register 5"
|
|
bitfld.long 0x00 1. "PF1F5,PF1F5" "0,1"
|
|
bitfld.long 0x00 0. "PF0F5,PF0F5" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port F Function Register 6"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port F Function Register 6"
|
|
bitfld.long 0x00 4. "PF4F6,PF4F6" "0,1"
|
|
bitfld.long 0x00 3. "PF3F6,PF3F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port F Function Register 6"
|
|
bitfld.long 0x00 5. "PF5F6,PF5F6" "0,1"
|
|
bitfld.long 0x00 4. "PF4F6,PF4F6" "0,1"
|
|
bitfld.long 0x00 3. "PF3F6,PF3F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port F Function Register 7"
|
|
bitfld.long 0x00 7. "PF7F7,PF7F7" "0,1"
|
|
bitfld.long 0x00 6. "PF6F7,PF6F7" "0,1"
|
|
bitfld.long 0x00 4. "PF4F7,PF4F7" "0,1"
|
|
bitfld.long 0x00 3. "PF3F7,PF3F7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1F7,PF1F7" "0,1"
|
|
bitfld.long 0x00 0. "PF0F7,PF0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port F Function Register 7"
|
|
bitfld.long 0x00 1. "PF1F7,PF1F7" "0,1"
|
|
bitfld.long 0x00 0. "PF0F7,PF0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port F Function Register 7"
|
|
bitfld.long 0x00 7. "PF7F7,PF7F7" "0,1"
|
|
bitfld.long 0x00 6. "PF6F7,PF6F7" "0,1"
|
|
bitfld.long 0x00 5. "PF5F7,PF5F7" "0,1"
|
|
bitfld.long 0x00 4. "PF4F7,PF4F7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PF3F7,PF3F7" "0,1"
|
|
bitfld.long 0x00 2. "PF2F7,PF2F7" "0,1"
|
|
bitfld.long 0x00 1. "PF1F7,PF1F7" "0,1"
|
|
bitfld.long 0x00 0. "PF0F7,PF0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port F Function Register 7"
|
|
bitfld.long 0x00 3. "PF3F7,PF3F7" "0,1"
|
|
bitfld.long 0x00 2. "PF2F7,PF2F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port F Open Drain Control Register"
|
|
bitfld.long 0x00 1. "PF1OD,PF1OD" "0,1"
|
|
bitfld.long 0x00 0. "PF0OD,PF0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port F Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PF7OD,PF7OD" "0,1"
|
|
bitfld.long 0x00 6. "PF6OD,PF6OD" "0,1"
|
|
bitfld.long 0x00 3. "PF3OD,PF3OD" "0,1"
|
|
bitfld.long 0x00 2. "PF2OD,PF2OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1OD,PF1OD" "0,1"
|
|
bitfld.long 0x00 0. "PF0OD,PF0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port F Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PF7OD,PF7OD" "0,1"
|
|
bitfld.long 0x00 6. "PF6OD,PF6OD" "0,1"
|
|
bitfld.long 0x00 5. "PF5OD,PF5OD" "0,1"
|
|
bitfld.long 0x00 4. "PF4OD,PF4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PF3OD,PF3OD" "0,1"
|
|
bitfld.long 0x00 2. "PF2OD,PF2OD" "0,1"
|
|
bitfld.long 0x00 1. "PF1OD,PF1OD" "0,1"
|
|
bitfld.long 0x00 0. "PF0OD,PF0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port F Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PF7OD,PF7OD" "0,1"
|
|
bitfld.long 0x00 6. "PF6OD,PF6OD" "0,1"
|
|
bitfld.long 0x00 4. "PF4OD,PF4OD" "0,1"
|
|
bitfld.long 0x00 3. "PF3OD,PF3OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1OD,PF1OD" "0,1"
|
|
bitfld.long 0x00 0. "PF0OD,PF0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port F Open Drain Control Register"
|
|
bitfld.long 0x00 0. "PF0OD,PF0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port F Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PF7UP,PF7UP" "0,1"
|
|
bitfld.long 0x00 6. "PF6UP,PF6UP" "0,1"
|
|
bitfld.long 0x00 4. "PF4UP,PF4UP" "0,1"
|
|
bitfld.long 0x00 3. "PF3UP,PF3UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1UP,PF1UP" "0,1"
|
|
bitfld.long 0x00 0. "PF0UP,PF0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port F Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PF7UP,PF7UP" "0,1"
|
|
bitfld.long 0x00 6. "PF6UP,PF6UP" "0,1"
|
|
bitfld.long 0x00 3. "PF3UP,PF3UP" "0,1"
|
|
bitfld.long 0x00 2. "PF2UP,PF2UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1UP,PF1UP" "0,1"
|
|
bitfld.long 0x00 0. "PF0UP,PF0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port F Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PF7UP,PF7UP" "0,1"
|
|
bitfld.long 0x00 6. "PF6UP,PF6UP" "0,1"
|
|
bitfld.long 0x00 5. "PF5UP,PF5UP" "0,1"
|
|
bitfld.long 0x00 4. "PF4UP,PF4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PF3UP,PF3UP" "0,1"
|
|
bitfld.long 0x00 2. "PF2UP,PF2UP" "0,1"
|
|
bitfld.long 0x00 1. "PF1UP,PF1UP" "0,1"
|
|
bitfld.long 0x00 0. "PF0UP,PF0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port F Pull-up Control Register"
|
|
bitfld.long 0x00 0. "PF0UP,PF0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port F Pull-up Control Register"
|
|
bitfld.long 0x00 1. "PF1UP,PF1UP" "0,1"
|
|
bitfld.long 0x00 0. "PF0UP,PF0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port F Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PF7DN,PF7DN" "0,1"
|
|
bitfld.long 0x00 6. "PF6DN,PF6DN" "0,1"
|
|
bitfld.long 0x00 4. "PF4DN,PF4DN" "0,1"
|
|
bitfld.long 0x00 3. "PF3DN,PF3DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1DN,PF1DN" "0,1"
|
|
bitfld.long 0x00 0. "PF0DN,PF0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port F Pull-down Control Register"
|
|
bitfld.long 0x00 1. "PF1DN,PF1DN" "0,1"
|
|
bitfld.long 0x00 0. "PF0DN,PF0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port F Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PF7DN,PF7DN" "0,1"
|
|
bitfld.long 0x00 6. "PF6DN,PF6DN" "0,1"
|
|
bitfld.long 0x00 3. "PF3DN,PF3DN" "0,1"
|
|
bitfld.long 0x00 2. "PF2DN,PF2DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1DN,PF1DN" "0,1"
|
|
bitfld.long 0x00 0. "PF0DN,PF0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port F Pull-down Control Register"
|
|
bitfld.long 0x00 0. "PF0DN,PF0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port F Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PF7DN,PF7DN" "0,1"
|
|
bitfld.long 0x00 6. "PF6DN,PF6DN" "0,1"
|
|
bitfld.long 0x00 5. "PF5DN,PF5DN" "0,1"
|
|
bitfld.long 0x00 4. "PF4DN,PF4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PF3DN,PF3DN" "0,1"
|
|
bitfld.long 0x00 2. "PF2DN,PF2DN" "0,1"
|
|
bitfld.long 0x00 1. "PF1DN,PF1DN" "0,1"
|
|
bitfld.long 0x00 0. "PF0DN,PF0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port F Input Control Register"
|
|
bitfld.long 0x00 7. "PF7IE,PF7IE" "0,1"
|
|
bitfld.long 0x00 6. "PF6IE,PF6IE" "0,1"
|
|
bitfld.long 0x00 5. "PF5IE,PF5IE" "0,1"
|
|
bitfld.long 0x00 4. "PF4IE,PF4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PF3IE,PF3IE" "0,1"
|
|
bitfld.long 0x00 2. "PF2IE,PF2IE" "0,1"
|
|
bitfld.long 0x00 1. "PF1IE,PF1IE" "0,1"
|
|
bitfld.long 0x00 0. "PF0IE,PF0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port F Input Control Register"
|
|
bitfld.long 0x00 1. "PF1IE,PF1IE" "0,1"
|
|
bitfld.long 0x00 0. "PF0IE,PF0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port F Input Control Register"
|
|
bitfld.long 0x00 7. "PF7IE,PF7IE" "0,1"
|
|
bitfld.long 0x00 6. "PF6IE,PF6IE" "0,1"
|
|
bitfld.long 0x00 3. "PF3IE,PF3IE" "0,1"
|
|
bitfld.long 0x00 2. "PF2IE,PF2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1IE,PF1IE" "0,1"
|
|
bitfld.long 0x00 0. "PF0IE,PF0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port F Input Control Register"
|
|
bitfld.long 0x00 0. "PF0IE,PF0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port F Input Control Register"
|
|
bitfld.long 0x00 7. "PF7IE,PF7IE" "0,1"
|
|
bitfld.long 0x00 6. "PF6IE,PF6IE" "0,1"
|
|
bitfld.long 0x00 4. "PF4IE,PF4IE" "0,1"
|
|
bitfld.long 0x00 3. "PF3IE,PF3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PF1IE,PF1IE" "0,1"
|
|
bitfld.long 0x00 0. "PF0IE,PF0IE" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400C0500
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PF Data Register"
|
|
bitfld.long 0x00 0. "PF0,PF0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PF Data Register"
|
|
bitfld.long 0x00 2. "PF2,PF2" "0,1"
|
|
bitfld.long 0x00 1. "PF1,PF1" "0,1"
|
|
bitfld.long 0x00 0. "PF0,PF0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PF Control Register"
|
|
bitfld.long 0x00 2. "PF2C,PF2C" "0,1"
|
|
bitfld.long 0x00 1. "PF1C,PF1C" "0,1"
|
|
bitfld.long 0x00 0. "PF0C,PF0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PF Control Register"
|
|
bitfld.long 0x00 0. "PF0C,PF0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,PF Function Register 4"
|
|
bitfld.long 0x00 2. "PF2F4,PF2F4" "0,1"
|
|
bitfld.long 0x00 1. "PF1F4,PF1F4" "0,1"
|
|
bitfld.long 0x00 0. "PF0F4,PF0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,PF Function Register 4"
|
|
bitfld.long 0x00 0. "PF0F4,PF0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PF Function Register 5"
|
|
bitfld.long 0x00 2. "PF2F5,PF2F5" "0,1"
|
|
bitfld.long 0x00 1. "PF1F5,PF1F5" "0,1"
|
|
bitfld.long 0x00 0. "PF0F5,PF0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PF Function Register 5"
|
|
bitfld.long 0x00 0. "PF0F5,PF0F5" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,PF Function Register 6"
|
|
bitfld.long 0x00 0. "PF0F6,PF0F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,PF Function Register 6"
|
|
bitfld.long 0x00 2. "PF2F6,PF2F6" "0,1"
|
|
bitfld.long 0x00 0. "PF0F6,PF0F6" "0,1"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,PF Function Register 7"
|
|
bitfld.long 0x00 0. "PF0F7,PF0F7" "0,1"
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PF Open Drain Control Register"
|
|
bitfld.long 0x00 2. "PF2OD,PF2OD" "0,1"
|
|
bitfld.long 0x00 1. "PF1OD,PF1OD" "0,1"
|
|
bitfld.long 0x00 0. "PF0OD,PF0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PF Open Drain Control Register"
|
|
bitfld.long 0x00 0. "PF0OD,PF0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PF Pull-up Control Register"
|
|
bitfld.long 0x00 0. "PF0PUP,PF0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PF Pull-up Control Register"
|
|
bitfld.long 0x00 2. "PF2PUP,PF2PUP" "0,1"
|
|
bitfld.long 0x00 1. "PF1PUP,PF1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PF0PUP,PF0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PF Pull-Down Control Register"
|
|
bitfld.long 0x00 0. "PF0PDN,PF0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PF Pull-Down Control Register"
|
|
bitfld.long 0x00 2. "PF2PDN,PF2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PF1PDN,PF1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PF0PDN,PF0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PF Input Enable Control Register"
|
|
bitfld.long 0x00 0. "PF0IE,PF0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PF Input Enable Control Register"
|
|
bitfld.long 0x00 2. "PF2IE,PF2IE" "0,1"
|
|
bitfld.long 0x00 1. "PF1IE,PF1IE" "0,1"
|
|
bitfld.long 0x00 0. "PF0IE,PF0IE" "0,1"
|
|
endif
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "PG (Port G)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E0600
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40080600
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port G Data Register"
|
|
bitfld.long 0x00 6. "PG6,PG6" "0,1"
|
|
bitfld.long 0x00 5. "PG5,PG5" "0,1"
|
|
bitfld.long 0x00 4. "PG4,PG4" "0,1"
|
|
bitfld.long 0x00 3. "PG3,PG3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2,PG2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port G Data Register"
|
|
bitfld.long 0x00 7. "PG7,PG7" "0,1"
|
|
bitfld.long 0x00 6. "PG6,PG6" "0,1"
|
|
bitfld.long 0x00 5. "PG5,PG5" "0,1"
|
|
bitfld.long 0x00 4. "PG4,PG4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PG3,PG3" "0,1"
|
|
bitfld.long 0x00 2. "PG2,PG2" "0,1"
|
|
bitfld.long 0x00 1. "PG1,PG1" "0,1"
|
|
bitfld.long 0x00 0. "PG0,PG0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port G Data Register"
|
|
bitfld.long 0x00 2. "PG2,PG2" "0,1"
|
|
bitfld.long 0x00 1. "PG1,PG1" "0,1"
|
|
bitfld.long 0x00 0. "PG0,PG0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port G Data Register"
|
|
bitfld.long 0x00 6. "PG6,PG6" "0,1"
|
|
bitfld.long 0x00 5. "PG5,PG5" "0,1"
|
|
bitfld.long 0x00 4. "PG4,PG4" "0,1"
|
|
bitfld.long 0x00 3. "PG3,PG3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2,PG2" "0,1"
|
|
bitfld.long 0x00 1. "PG1,PG1" "0,1"
|
|
bitfld.long 0x00 0. "PG0,PG0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port G Data Register"
|
|
bitfld.long 0x00 3. "PG3,PG3" "0,1"
|
|
bitfld.long 0x00 2. "PG2,PG2" "0,1"
|
|
bitfld.long 0x00 1. "PG1,PG1" "0,1"
|
|
bitfld.long 0x00 0. "PG0,PG0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port G Output Control Register"
|
|
bitfld.long 0x00 6. "PG6C,PG6C" "0,1"
|
|
bitfld.long 0x00 5. "PG5C,PG5C" "0,1"
|
|
bitfld.long 0x00 4. "PG4C,PG4C" "0,1"
|
|
bitfld.long 0x00 3. "PG3C,PG3C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2C,PG2C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port G Output Control Register"
|
|
bitfld.long 0x00 7. "PG7C,PG7C" "0,1"
|
|
bitfld.long 0x00 6. "PG6C,PG6C" "0,1"
|
|
bitfld.long 0x00 5. "PG5C,PG5C" "0,1"
|
|
bitfld.long 0x00 4. "PG4C,PG4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PG3C,PG3C" "0,1"
|
|
bitfld.long 0x00 2. "PG2C,PG2C" "0,1"
|
|
bitfld.long 0x00 1. "PG1C,PG1C" "0,1"
|
|
bitfld.long 0x00 0. "PG0C,PG0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port G Output Control Register"
|
|
bitfld.long 0x00 6. "PG6C,PG6C" "0,1"
|
|
bitfld.long 0x00 5. "PG5C,PG5C" "0,1"
|
|
bitfld.long 0x00 4. "PG4C,PG4C" "0,1"
|
|
bitfld.long 0x00 3. "PG3C,PG3C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2C,PG2C" "0,1"
|
|
bitfld.long 0x00 1. "PG1C,PG1C" "0,1"
|
|
bitfld.long 0x00 0. "PG0C,PG0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port G Output Control Register"
|
|
bitfld.long 0x00 3. "PG3C,PG3C" "0,1"
|
|
bitfld.long 0x00 2. "PG2C,PG2C" "0,1"
|
|
bitfld.long 0x00 1. "PG1C,PG1C" "0,1"
|
|
bitfld.long 0x00 0. "PG0C,PG0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port G Output Control Register"
|
|
bitfld.long 0x00 2. "PG2C,PG2C" "0,1"
|
|
bitfld.long 0x00 1. "PG1C,PG1C" "0,1"
|
|
bitfld.long 0x00 0. "PG0C,PG0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port G Function Register 1"
|
|
bitfld.long 0x00 6. "PG6F1,PG6F1" "0,1"
|
|
bitfld.long 0x00 5. "PG5F1,PG5F1" "0,1"
|
|
bitfld.long 0x00 4. "PG4F1,PG4F1" "0,1"
|
|
bitfld.long 0x00 3. "PG3F1,PG3F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2F1,PG2F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port G Function Register 1"
|
|
bitfld.long 0x00 6. "PG6F1,PG6F1" "0,1"
|
|
bitfld.long 0x00 5. "PG5F1,PG5F1" "0,1"
|
|
bitfld.long 0x00 4. "PG4F1,PG4F1" "0,1"
|
|
bitfld.long 0x00 3. "PG3F1,PG3F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2F1,PG2F1" "0,1"
|
|
bitfld.long 0x00 1. "PG1F1,PG1F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port G Function Register 1"
|
|
bitfld.long 0x00 7. "PG7F1,PG7F1" "0,1"
|
|
bitfld.long 0x00 6. "PG6F1,PG6F1" "0,1"
|
|
bitfld.long 0x00 1. "PG1F1,PG1F1" "0,1"
|
|
bitfld.long 0x00 0. "PG0F1,PG0F1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port G Function Register 2"
|
|
bitfld.long 0x00 5. "PG5F2,PG5F2" "0,1"
|
|
bitfld.long 0x00 4. "PG4F2,PG4F2" "0,1"
|
|
bitfld.long 0x00 3. "PG3F2,PG3F2" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port G Function Register 3"
|
|
bitfld.long 0x00 5. "PG5F3,PG5F3" "0,1"
|
|
rbitfld.long 0x00 3. "PG3F3,PG3F3" "0,1"
|
|
rbitfld.long 0x00 1. "PG1F3,PG1F3" "0,1"
|
|
rbitfld.long 0x00 0. "PG0F3,PG0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port G Function Register 4"
|
|
bitfld.long 0x00 5. "PG5F4,PG5F4" "0,1"
|
|
bitfld.long 0x00 4. "PG4F4,PG4F4" "0,1"
|
|
bitfld.long 0x00 3. "PG3F4,PG3F4" "0,1"
|
|
bitfld.long 0x00 2. "PG2F4,PG2F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port G Function Register 4"
|
|
bitfld.long 0x00 7. "PG7F4,PG7F4" "0,1"
|
|
bitfld.long 0x00 6. "PG6F4,PG6F4" "0,1"
|
|
bitfld.long 0x00 5. "PG5F4,PG5F4" "0,1"
|
|
bitfld.long 0x00 4. "PG4F4,PG4F4" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "PG3F4,PG3F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port G Function Register 4"
|
|
bitfld.long 0x00 5. "PG5F4,PG5F4" "0,1"
|
|
bitfld.long 0x00 4. "PG4F4,PG4F4" "0,1"
|
|
bitfld.long 0x00 3. "PG3F4,PG3F4" "0,1"
|
|
bitfld.long 0x00 2. "PG2F4,PG2F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PG1F4,PG1F4" "0,1"
|
|
bitfld.long 0x00 0. "PG0F4,PG0F4" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port G Function Register 5"
|
|
bitfld.long 0x00 2. "PG2F5,PG2F5" "0,1"
|
|
bitfld.long 0x00 1. "PG1F5,PG1F5" "0,1"
|
|
bitfld.long 0x00 0. "PG0F5,PG0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port G Function Register 5"
|
|
bitfld.long 0x00 7. "PG7F5,PG7F5" "0,1"
|
|
bitfld.long 0x00 6. "PG6F5,PG6F5" "0,1"
|
|
bitfld.long 0x00 5. "PG5F5,PG5F5" "0,1"
|
|
bitfld.long 0x00 4. "PG4F5,PG4F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PG3F5,PG3F5" "0,1"
|
|
bitfld.long 0x00 1. "PG1F5,PG1F5" "0,1"
|
|
bitfld.long 0x00 0. "PG0F5,PG0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port G Function Register 5"
|
|
bitfld.long 0x00 2. "PG2F5,PG2F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port G Function Register 7"
|
|
bitfld.long 0x00 5. "PG5F7,PG5F7" "0,1"
|
|
bitfld.long 0x00 4. "PG4F7,PG4F7" "0,1"
|
|
bitfld.long 0x00 3. "PG3F7,PG3F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port G Open Drain Control Register"
|
|
bitfld.long 0x00 6. "PG6OD,PG6OD" "0,1"
|
|
bitfld.long 0x00 5. "PG5OD,PG5OD" "0,1"
|
|
bitfld.long 0x00 4. "PG4OD,PG4OD" "0,1"
|
|
bitfld.long 0x00 3. "PG3OD,PG3OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2OD,PG2OD" "0,1"
|
|
bitfld.long 0x00 1. "PG1OD,PG1OD" "0,1"
|
|
bitfld.long 0x00 0. "PG0OD,PG0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port G Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PG7OD,PG7OD" "0,1"
|
|
bitfld.long 0x00 6. "PG6OD,PG6OD" "0,1"
|
|
bitfld.long 0x00 5. "PG5OD,PG5OD" "0,1"
|
|
bitfld.long 0x00 4. "PG4OD,PG4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PG3OD,PG3OD" "0,1"
|
|
bitfld.long 0x00 2. "PG2OD,PG2OD" "0,1"
|
|
bitfld.long 0x00 1. "PG1OD,PG1OD" "0,1"
|
|
bitfld.long 0x00 0. "PG0OD,PG0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port G Open Drain Control Register"
|
|
bitfld.long 0x00 6. "PG6OD,PG6OD" "0,1"
|
|
bitfld.long 0x00 5. "PG5OD,PG5OD" "0,1"
|
|
bitfld.long 0x00 4. "PG4OD,PG4OD" "0,1"
|
|
bitfld.long 0x00 3. "PG3OD,PG3OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2OD,PG2OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port G Open Drain Control Register"
|
|
bitfld.long 0x00 2. "PG2OD,PG2OD" "0,1"
|
|
bitfld.long 0x00 1. "PG1OD,PG1OD" "0,1"
|
|
bitfld.long 0x00 0. "PG0OD,PG0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port G Open Drain Control Register"
|
|
bitfld.long 0x00 3. "PG3OD,PG3OD" "0,1"
|
|
bitfld.long 0x00 2. "PG2OD,PG2OD" "0,1"
|
|
bitfld.long 0x00 1. "PG1OD,PG1OD" "0,1"
|
|
bitfld.long 0x00 0. "PG0OD,PG0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port G Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PG7UP,PG7UP" "0,1"
|
|
bitfld.long 0x00 6. "PG6UP,PG6UP" "0,1"
|
|
bitfld.long 0x00 5. "PG5UP,PG5UP" "0,1"
|
|
bitfld.long 0x00 4. "PG4UP,PG4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PG3UP,PG3UP" "0,1"
|
|
bitfld.long 0x00 2. "PG2UP,PG2UP" "0,1"
|
|
bitfld.long 0x00 1. "PG1UP,PG1UP" "0,1"
|
|
bitfld.long 0x00 0. "PG0UP,PG0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port G Pull-up Control Register"
|
|
bitfld.long 0x00 2. "PG2UP,PG2UP" "0,1"
|
|
bitfld.long 0x00 1. "PG1UP,PG1UP" "0,1"
|
|
bitfld.long 0x00 0. "PG0UP,PG0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port G Pull-up Control Register"
|
|
bitfld.long 0x00 6. "PG6UP,PG6UP" "0,1"
|
|
bitfld.long 0x00 5. "PG5UP,PG5UP" "0,1"
|
|
bitfld.long 0x00 4. "PG4UP,PG4UP" "0,1"
|
|
bitfld.long 0x00 3. "PG3UP,PG3UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2UP,PG2UP" "0,1"
|
|
bitfld.long 0x00 1. "PG1UP,PG1UP" "0,1"
|
|
bitfld.long 0x00 0. "PG0UP,PG0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port G Pull-up Control Register"
|
|
bitfld.long 0x00 6. "PG6UP,PG6UP" "0,1"
|
|
bitfld.long 0x00 5. "PG5UP,PG5UP" "0,1"
|
|
bitfld.long 0x00 4. "PG4UP,PG4UP" "0,1"
|
|
bitfld.long 0x00 3. "PG3UP,PG3UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2UP,PG2UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port G Pull-up Control Register"
|
|
bitfld.long 0x00 3. "PG3UP,PG3UP" "0,1"
|
|
bitfld.long 0x00 2. "PG2UP,PG2UP" "0,1"
|
|
bitfld.long 0x00 1. "PG1UP,PG1UP" "0,1"
|
|
bitfld.long 0x00 0. "PG0UP,PG0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port G Pull-down Control Register"
|
|
bitfld.long 0x00 2. "PG2DN,PG2DN" "0,1"
|
|
bitfld.long 0x00 1. "PG1DN,PG1DN" "0,1"
|
|
bitfld.long 0x00 0. "PG0DN,PG0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port G Pull-down Control Register"
|
|
bitfld.long 0x00 6. "PG6DN,PG6DN" "0,1"
|
|
bitfld.long 0x00 5. "PG5DN,PG5DN" "0,1"
|
|
bitfld.long 0x00 4. "PG4DN,PG4DN" "0,1"
|
|
bitfld.long 0x00 3. "PG3DN,PG3DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2DN,PG2DN" "0,1"
|
|
bitfld.long 0x00 1. "PG1DN,PG1DN" "0,1"
|
|
bitfld.long 0x00 0. "PG0DN,PG0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port G Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PG7DN,PG7DN" "0,1"
|
|
bitfld.long 0x00 6. "PG6DN,PG6DN" "0,1"
|
|
bitfld.long 0x00 5. "PG5DN,PG5DN" "0,1"
|
|
bitfld.long 0x00 4. "PG4DN,PG4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PG3DN,PG3DN" "0,1"
|
|
bitfld.long 0x00 2. "PG2DN,PG2DN" "0,1"
|
|
bitfld.long 0x00 1. "PG1DN,PG1DN" "0,1"
|
|
bitfld.long 0x00 0. "PG0DN,PG0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port G Pull-down Control Register"
|
|
bitfld.long 0x00 6. "PG6DN,PG6DN" "0,1"
|
|
bitfld.long 0x00 5. "PG5DN,PG5DN" "0,1"
|
|
bitfld.long 0x00 4. "PG4DN,PG4DN" "0,1"
|
|
bitfld.long 0x00 3. "PG3DN,PG3DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2DN,PG2DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port G Pull-down Control Register"
|
|
bitfld.long 0x00 3. "PG3DN,PG3DN" "0,1"
|
|
bitfld.long 0x00 2. "PG2DN,PG2DN" "0,1"
|
|
bitfld.long 0x00 1. "PG1DN,PG1DN" "0,1"
|
|
bitfld.long 0x00 0. "PG0DN,PG0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port G Input Control Register"
|
|
bitfld.long 0x00 2. "PG2IE,PG2IE" "0,1"
|
|
bitfld.long 0x00 1. "PG1IE,PG1IE" "0,1"
|
|
bitfld.long 0x00 0. "PG0IE,PG0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port G Input Control Register"
|
|
bitfld.long 0x00 6. "PG6IE,PG6IE" "0,1"
|
|
bitfld.long 0x00 5. "PG5IE,PG5IE" "0,1"
|
|
bitfld.long 0x00 4. "PG4IE,PG4IE" "0,1"
|
|
bitfld.long 0x00 3. "PG3IE,PG3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2IE,PG2IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port G Input Control Register"
|
|
bitfld.long 0x00 6. "PG6IE,PG6IE" "0,1"
|
|
bitfld.long 0x00 5. "PG5IE,PG5IE" "0,1"
|
|
bitfld.long 0x00 4. "PG4IE,PG4IE" "0,1"
|
|
bitfld.long 0x00 3. "PG3IE,PG3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PG2IE,PG2IE" "0,1"
|
|
bitfld.long 0x00 1. "PG1IE,PG1IE" "0,1"
|
|
bitfld.long 0x00 0. "PG0IE,PG0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port G Input Control Register"
|
|
bitfld.long 0x00 3. "PG3IE,PG3IE" "0,1"
|
|
bitfld.long 0x00 2. "PG2IE,PG2IE" "0,1"
|
|
bitfld.long 0x00 1. "PG1IE,PG1IE" "0,1"
|
|
bitfld.long 0x00 0. "PG0IE,PG0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port G Input Control Register"
|
|
bitfld.long 0x00 7. "PG7IE,PG7IE" "0,1"
|
|
bitfld.long 0x00 6. "PG6IE,PG6IE" "0,1"
|
|
bitfld.long 0x00 5. "PG5IE,PG5IE" "0,1"
|
|
bitfld.long 0x00 4. "PG4IE,PG4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PG3IE,PG3IE" "0,1"
|
|
bitfld.long 0x00 2. "PG2IE,PG2IE" "0,1"
|
|
bitfld.long 0x00 1. "PG1IE,PG1IE" "0,1"
|
|
bitfld.long 0x00 0. "PG0IE,PG0IE" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400C0600
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PG Data Register"
|
|
bitfld.long 0x00 2. "PG2,PG2" "0,1"
|
|
bitfld.long 0x00 1. "PG1,PG1" "0,1"
|
|
bitfld.long 0x00 0. "PG0,PG0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PG Data Register"
|
|
bitfld.long 0x00 5. "PG5,PG5" "0,1"
|
|
bitfld.long 0x00 4. "PG4,PG4" "0,1"
|
|
bitfld.long 0x00 3. "PG3,PG3" "0,1"
|
|
bitfld.long 0x00 2. "PG2,PG2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PG1,PG1" "0,1"
|
|
bitfld.long 0x00 0. "PG0,PG0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PG Control Register"
|
|
bitfld.long 0x00 2. "PG2C,PG2C" "0,1"
|
|
bitfld.long 0x00 1. "PG1C,PG1C" "0,1"
|
|
bitfld.long 0x00 0. "PG0C,PG0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PG Control Register"
|
|
bitfld.long 0x00 5. "PG5C,PG5C" "0,1"
|
|
bitfld.long 0x00 4. "PG4C,PG4C" "0,1"
|
|
bitfld.long 0x00 3. "PG3C,PG3C" "0,1"
|
|
bitfld.long 0x00 2. "PG2C,PG2C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PG1C,PG1C" "0,1"
|
|
bitfld.long 0x00 0. "PG0C,PG0C" "0,1"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PG Function Register 1"
|
|
bitfld.long 0x00 1. "PG1F1,PG1F1" "0,1"
|
|
bitfld.long 0x00 0. "PG0F1,PG0F1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,PG Function Register 2"
|
|
bitfld.long 0x00 2. "PG2F2,PG2F2" "0,1"
|
|
bitfld.long 0x00 1. "PG1F2,PG1F2" "0,1"
|
|
bitfld.long 0x00 0. "PG0F2,PG0F2" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,PG Function Register 3"
|
|
bitfld.long 0x00 2. "PG2F3,PG2F3" "0,1"
|
|
bitfld.long 0x00 1. "PG1F3,PG1F3" "0,1"
|
|
bitfld.long 0x00 0. "PG0F3,PG0F3" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,PG Function Register 4"
|
|
bitfld.long 0x00 2. "PG2F4,PG2F4" "0,1"
|
|
bitfld.long 0x00 1. "PG1F4,PG1F4" "0,1"
|
|
bitfld.long 0x00 0. "PG0F4,PG0F4" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PG Function Register 5"
|
|
bitfld.long 0x00 2. "PG2F5,PG2F5" "0,1"
|
|
bitfld.long 0x00 1. "PG1F5,PG1F5" "0,1"
|
|
bitfld.long 0x00 0. "PG0F5,PG0F5" "0,1"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,PG Function Register 6"
|
|
bitfld.long 0x00 2. "PG2F6,PG2F6" "0,1"
|
|
bitfld.long 0x00 1. "PG1F6,PG1F6" "0,1"
|
|
bitfld.long 0x00 0. "PG0F6,PG0F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,PG Function Register 6"
|
|
bitfld.long 0x00 5. "PG5F6,PG5F6" "0,1"
|
|
bitfld.long 0x00 4. "PG4F6,PG4F6" "0,1"
|
|
bitfld.long 0x00 3. "PG3F6,PG3F6" "0,1"
|
|
bitfld.long 0x00 2. "PG2F6,PG2F6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PG1F6,PG1F6" "0,1"
|
|
bitfld.long 0x00 0. "PG0F6,PG0F6" "0,1"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,PG Function Register 7"
|
|
bitfld.long 0x00 1. "PG1F7,PG1F7" "0,1"
|
|
bitfld.long 0x00 0. "PG0F7,PG0F7" "0,1"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PG Open Drain Control Register"
|
|
bitfld.long 0x00 2. "PG2OD,PG2OD" "0,1"
|
|
bitfld.long 0x00 1. "PG1OD,PG1OD" "0,1"
|
|
bitfld.long 0x00 0. "PG0OD,PG0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PG Open Drain Control Register"
|
|
bitfld.long 0x00 5. "PG5OD,PG5OD" "0,1"
|
|
bitfld.long 0x00 4. "PG4OD,PG4OD" "0,1"
|
|
bitfld.long 0x00 3. "PG3OD,PG3OD" "0,1"
|
|
bitfld.long 0x00 2. "PG2OD,PG2OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PG1OD,PG1OD" "0,1"
|
|
bitfld.long 0x00 0. "PG0OD,PG0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PG Pull-up Control Register"
|
|
bitfld.long 0x00 2. "PG2PUP,PG2PUP" "0,1"
|
|
bitfld.long 0x00 1. "PG1PUP,PG1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PG0PUP,PG0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PG Pull-up Control Register"
|
|
bitfld.long 0x00 5. "PG5PUP,PG5PUP" "0,1"
|
|
bitfld.long 0x00 4. "PG4PUP,PG4PUP" "0,1"
|
|
bitfld.long 0x00 3. "PG3PUP,PG3PUP" "0,1"
|
|
bitfld.long 0x00 2. "PG2PUP,PG2PUP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PG1PUP,PG1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PG0PUP,PG0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PG Pull-Down Control Register"
|
|
bitfld.long 0x00 2. "PG2PDN,PG2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PG1PDN,PG1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PG0PDN,PG0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PG Pull-Down Control Register"
|
|
bitfld.long 0x00 5. "PG5PDN,PG5PDN" "0,1"
|
|
bitfld.long 0x00 4. "PG4PDN,PG4PDN" "0,1"
|
|
bitfld.long 0x00 3. "PG3PDN,PG3PDN" "0,1"
|
|
bitfld.long 0x00 2. "PG2PDN,PG2PDN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PG1PDN,PG1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PG0PDN,PG0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PG Input Enable Control Register"
|
|
bitfld.long 0x00 2. "PG2IE,PG2IE" "0,1"
|
|
bitfld.long 0x00 1. "PG1IE,PG1IE" "0,1"
|
|
bitfld.long 0x00 0. "PG0IE,PG0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PG Input Enable Control Register"
|
|
bitfld.long 0x00 5. "PG5IE,PG5IE" "0,1"
|
|
bitfld.long 0x00 4. "PG4IE,PG4IE" "0,1"
|
|
bitfld.long 0x00 3. "PG3IE,PG3IE" "0,1"
|
|
bitfld.long 0x00 2. "PG2IE,PG2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PG1IE,PG1IE" "0,1"
|
|
bitfld.long 0x00 0. "PG0IE,PG0IE" "0,1"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "PH (Port H)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E0700
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40080700
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port H Data Register"
|
|
bitfld.long 0x00 7. "PH7,PH7" "0,1"
|
|
bitfld.long 0x00 6. "PH6,PH6" "0,1"
|
|
bitfld.long 0x00 5. "PH5,PH5" "0,1"
|
|
bitfld.long 0x00 4. "PH4,PH4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PH3,PH3" "0,1"
|
|
bitfld.long 0x00 2. "PH2,PH2" "0,1"
|
|
bitfld.long 0x00 1. "PH1,PH1" "0,1"
|
|
bitfld.long 0x00 0. "PH0,PH0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port H Data Register"
|
|
bitfld.long 0x00 1. "PH1,PH1" "0,1"
|
|
bitfld.long 0x00 0. "PH0,PH0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port H Output Control Register"
|
|
bitfld.long 0x00 7. "PH7C,PH7C" "0,1"
|
|
bitfld.long 0x00 6. "PH6C,PH6C" "0,1"
|
|
bitfld.long 0x00 5. "PH5C,PH5C" "0,1"
|
|
bitfld.long 0x00 4. "PH4C,PH4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PH3C,PH3C" "0,1"
|
|
bitfld.long 0x00 2. "PH2C,PH2C" "0,1"
|
|
bitfld.long 0x00 1. "PH1C,PH1C" "0,1"
|
|
bitfld.long 0x00 0. "PH0C,PH0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port H Output Control Register"
|
|
bitfld.long 0x00 1. "PH1C,PH1C" "0,1"
|
|
bitfld.long 0x00 0. "PH0C,PH0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port H Function Register 1"
|
|
bitfld.long 0x00 7. "PH7F1,PH7F1" "0,1"
|
|
bitfld.long 0x00 6. "PH6F1,PH6F1" "0,1"
|
|
bitfld.long 0x00 5. "PH5F1,PH5F1" "0,1"
|
|
bitfld.long 0x00 4. "PH4F1,PH4F1" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "PH1F3,PH1F3" "0,1"
|
|
rbitfld.long 0x00 2. "PH1F2,PH1F2" "0,1"
|
|
bitfld.long 0x00 1. "PH1F1,PH1F1" "0,1"
|
|
bitfld.long 0x00 0. "PH0F1,PH0F1" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port H Function Register 3"
|
|
bitfld.long 0x00 4. "PH4F3,PH4F3" "0,1"
|
|
bitfld.long 0x00 3. "PH3F3,PH3F3" "0,1"
|
|
bitfld.long 0x00 2. "PH2F3,PH2F3" "0,1"
|
|
bitfld.long 0x00 1. "PH1F3,PH1F3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PH0F3,PH0F3" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port H Function Register 4"
|
|
bitfld.long 0x00 3. "PH3F4,PH3F4" "0,1"
|
|
bitfld.long 0x00 2. "PH2F4,PH2F4" "0,1"
|
|
bitfld.long 0x00 1. "PH1F4,PH1F4" "0,1"
|
|
bitfld.long 0x00 0. "PH0F4,PH0F4" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port H Function Register 5"
|
|
bitfld.long 0x00 7. "PH7F5,PH7F5" "0,1"
|
|
bitfld.long 0x00 6. "PH6F5,PH6F5" "0,1"
|
|
bitfld.long 0x00 5. "PH5F5,PH5F5" "0,1"
|
|
bitfld.long 0x00 4. "PH4F5,PH4F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PH3F5,PH3F5" "0,1"
|
|
bitfld.long 0x00 2. "PH2F5,PH2F5" "0,1"
|
|
bitfld.long 0x00 1. "PH1F5,PH1F5" "0,1"
|
|
bitfld.long 0x00 0. "PH0F5,PH0F5" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port H Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PH7OD,PH7OD" "0,1"
|
|
bitfld.long 0x00 6. "PH6OD,PH6OD" "0,1"
|
|
bitfld.long 0x00 5. "PH5OD,PH5OD" "0,1"
|
|
bitfld.long 0x00 4. "PH4OD,PH4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PH3OD,PH3OD" "0,1"
|
|
bitfld.long 0x00 2. "PH2OD,PH2OD" "0,1"
|
|
bitfld.long 0x00 1. "PH1OD,PH1OD" "0,1"
|
|
bitfld.long 0x00 0. "PH0OD,PH0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port H Open Drain Control Register"
|
|
bitfld.long 0x00 1. "PH1OD,PH1OD" "0,1"
|
|
bitfld.long 0x00 0. "PH0OD,PH0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port H Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PH7UP,PH7UP" "0,1"
|
|
bitfld.long 0x00 6. "PH6UP,PH6UP" "0,1"
|
|
bitfld.long 0x00 5. "PH5UP,PH5UP" "0,1"
|
|
bitfld.long 0x00 4. "PH4UP,PH4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PH3UP,PH3UP" "0,1"
|
|
bitfld.long 0x00 2. "PH2UP,PH2UP" "0,1"
|
|
bitfld.long 0x00 1. "PH1UP,PH1UP" "0,1"
|
|
bitfld.long 0x00 0. "PH0UP,PH0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port H Pull-up Control Register"
|
|
bitfld.long 0x00 1. "PH1UP,PH1UP" "0,1"
|
|
bitfld.long 0x00 0. "PH0UP,PH0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port H Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PH7DN,PH7DN" "0,1"
|
|
bitfld.long 0x00 6. "PH6DN,PH6DN" "0,1"
|
|
bitfld.long 0x00 5. "PH5DN,PH5DN" "0,1"
|
|
bitfld.long 0x00 4. "PH4DN,PH4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PH3DN,PH3DN" "0,1"
|
|
bitfld.long 0x00 2. "PH2DN,PH2DN" "0,1"
|
|
bitfld.long 0x00 1. "PH1DN,PH1DN" "0,1"
|
|
bitfld.long 0x00 0. "PH0DN,PH0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port H Pull-down Control Register"
|
|
bitfld.long 0x00 1. "PH1DN,PH1DN" "0,1"
|
|
bitfld.long 0x00 0. "PH0DN,PH0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port H Input Control Register"
|
|
bitfld.long 0x00 1. "PH1IE,PH1IE" "0,1"
|
|
bitfld.long 0x00 0. "PH0IE,PH0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port H Input Control Register"
|
|
bitfld.long 0x00 7. "PH7IE,PH7IE" "0,1"
|
|
bitfld.long 0x00 6. "PH6IE,PH6IE" "0,1"
|
|
bitfld.long 0x00 5. "PH5IE,PH5IE" "0,1"
|
|
bitfld.long 0x00 4. "PH4IE,PH4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PH3IE,PH3IE" "0,1"
|
|
bitfld.long 0x00 2. "PH2IE,PH2IE" "0,1"
|
|
bitfld.long 0x00 1. "PH1IE,PH1IE" "0,1"
|
|
bitfld.long 0x00 0. "PH0IE,PH0IE" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400C0700
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PH Data Register"
|
|
bitfld.long 0x00 1. "PH1,PH1" "0,1"
|
|
bitfld.long 0x00 0. "PH0,PH0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PH Data Register"
|
|
bitfld.long 0x00 3. "PH3,PH3" "0,1"
|
|
bitfld.long 0x00 2. "PH2,PH2" "0,1"
|
|
bitfld.long 0x00 1. "PH1,PH1" "0,1"
|
|
bitfld.long 0x00 0. "PH0,PH0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PH Data Register"
|
|
bitfld.long 0x00 2. "PH2,PH2" "0,1"
|
|
bitfld.long 0x00 1. "PH1,PH1" "0,1"
|
|
bitfld.long 0x00 0. "PH0,PH0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PH Control Register"
|
|
bitfld.long 0x00 2. "PH2C,PH2C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PH Control Register"
|
|
bitfld.long 0x00 3. "PH3C,PH3C" "0,1"
|
|
bitfld.long 0x00 2. "PH2C,PH2C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PH Function Register 5"
|
|
bitfld.long 0x00 2. "PH2F5,PH2F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PH Open Drain Control Register"
|
|
bitfld.long 0x00 2. "PH2OD,PH2OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PH Open Drain Control Register"
|
|
bitfld.long 0x00 3. "PH3OD,PH3OD" "0,1"
|
|
bitfld.long 0x00 2. "PH2OD,PH2OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PH Pull-up Control Register"
|
|
bitfld.long 0x00 2. "PH2PUP,PH2PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PH Pull-up Control Register"
|
|
bitfld.long 0x00 3. "PH3PUP,PH3PUP" "0,1"
|
|
bitfld.long 0x00 2. "PH2PUP,PH2PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PH Pull-Down Control Register"
|
|
bitfld.long 0x00 1. "PH1PDN,PH1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PH0PDN,PH0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PH Pull-Down Control Register"
|
|
bitfld.long 0x00 3. "PH3PDN,PH3PDN" "0,1"
|
|
bitfld.long 0x00 2. "PH2PDN,PH2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PH1PDN,PH1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PH0PDN,PH0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PH Pull-Down Control Register"
|
|
bitfld.long 0x00 2. "PH2PDN,PH2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PH1PDN,PH1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PH0PDN,PH0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PH Input Enable Control Register"
|
|
bitfld.long 0x00 3. "PH3IE,PH3IE" "0,1"
|
|
bitfld.long 0x00 2. "PH2IE,PH2IE" "0,1"
|
|
bitfld.long 0x00 1. "PH1IE,PH1IE" "0,1"
|
|
bitfld.long 0x00 0. "PH0IE,PH0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PH Input Enable Control Register"
|
|
bitfld.long 0x00 1. "PH1IE,PH1IE" "0,1"
|
|
bitfld.long 0x00 0. "PH0IE,PH0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PH Input Enable Control Register"
|
|
bitfld.long 0x00 2. "PH2IE,PH2IE" "0,1"
|
|
bitfld.long 0x00 1. "PH1IE,PH1IE" "0,1"
|
|
bitfld.long 0x00 0. "PH0IE,PH0IE" "0,1"
|
|
endif
|
|
endif
|
|
tree.end
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "PJ (Port J)"
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E0800
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40080800
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port J Data Register"
|
|
bitfld.long 0x00 7. "PJ7,PJ7" "0,1"
|
|
bitfld.long 0x00 6. "PJ6,PJ6" "0,1"
|
|
bitfld.long 0x00 5. "PJ5,PJ5" "0,1"
|
|
bitfld.long 0x00 4. "PJ4,PJ4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3,PJ3" "0,1"
|
|
bitfld.long 0x00 2. "PJ2,PJ2" "0,1"
|
|
bitfld.long 0x00 1. "PJ1,PJ1" "0,1"
|
|
bitfld.long 0x00 0. "PJ0,PJ0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port J Data Register"
|
|
bitfld.long 0x00 3. "PJ3,PJ3" "0,1"
|
|
bitfld.long 0x00 2. "PJ2,PJ2" "0,1"
|
|
bitfld.long 0x00 1. "PJ1,PJ1" "0,1"
|
|
bitfld.long 0x00 0. "PJ0,PJ0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port J Data Register"
|
|
bitfld.long 0x00 5. "PJ5,PJ5" "0,1"
|
|
bitfld.long 0x00 4. "PJ4,PJ4" "0,1"
|
|
bitfld.long 0x00 3. "PJ3,PJ3" "0,1"
|
|
bitfld.long 0x00 2. "PJ2,PJ2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PJ1,PJ1" "0,1"
|
|
bitfld.long 0x00 0. "PJ0,PJ0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port J Data Register"
|
|
bitfld.long 0x00 2. "PJ2,PJ2" "0,1"
|
|
bitfld.long 0x00 1. "PJ1,PJ1" "0,1"
|
|
bitfld.long 0x00 0. "PJ0,PJ0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port J Data Register"
|
|
bitfld.long 0x00 1. "PJ1,PJ1" "0,1"
|
|
bitfld.long 0x00 0. "PJ0,PJ0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port J Output Control Register"
|
|
bitfld.long 0x00 7. "PJ7C,PJ7C" "0,1"
|
|
bitfld.long 0x00 6. "PJ6C,PJ6C" "0,1"
|
|
bitfld.long 0x00 5. "PJ5C,PJ5C" "0,1"
|
|
bitfld.long 0x00 4. "PJ4C,PJ4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3C,PJ3C" "0,1"
|
|
bitfld.long 0x00 2. "PJ2C,PJ2C" "0,1"
|
|
bitfld.long 0x00 1. "PJ1C,PJ1C" "0,1"
|
|
bitfld.long 0x00 0. "PJ0C,PJ0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port J Output Control Register"
|
|
bitfld.long 0x00 5. "PJ5C,PJ5C" "0,1"
|
|
bitfld.long 0x00 4. "PJ4C,PJ4C" "0,1"
|
|
bitfld.long 0x00 3. "PJ3C,PJ3C" "0,1"
|
|
bitfld.long 0x00 2. "PJ2C,PJ2C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PJ1C,PJ1C" "0,1"
|
|
bitfld.long 0x00 0. "PJ0C,PJ0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port J Output Control Register"
|
|
bitfld.long 0x00 3. "PJ3C,PJ3C" "0,1"
|
|
bitfld.long 0x00 2. "PJ2C,PJ2C" "0,1"
|
|
bitfld.long 0x00 1. "PJ1C,PJ1C" "0,1"
|
|
bitfld.long 0x00 0. "PJ0C,PJ0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port J Output Control Register"
|
|
bitfld.long 0x00 2. "PJ2C,PJ2C" "0,1"
|
|
bitfld.long 0x00 1. "PJ1C,PJ1C" "0,1"
|
|
bitfld.long 0x00 0. "PJ0C,PJ0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port J Function Register 2"
|
|
bitfld.long 0x00 5. "PJ5F2,PJ5F2" "0,1"
|
|
bitfld.long 0x00 4. "PJ4F2,PJ4F2" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port J Function Register 3"
|
|
bitfld.long 0x00 5. "PJ5F3,PJ5F3" "0,1"
|
|
bitfld.long 0x00 4. "PJ4F3,PJ4F3" "0,1"
|
|
bitfld.long 0x00 3. "PJ3F3,PJ3F3" "0,1"
|
|
bitfld.long 0x00 2. "PJ2F3,PJ2F3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PJ1F3,PJ1F3" "0,1"
|
|
bitfld.long 0x00 0. "PJ0F3,PJ0F3" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port J Function Register 5"
|
|
bitfld.long 0x00 7. "PJ7F5,PJ7F5" "0,1"
|
|
bitfld.long 0x00 6. "PJ6F5,PJ6F5" "0,1"
|
|
bitfld.long 0x00 5. "PJ5F5,PJ5F5" "0,1"
|
|
bitfld.long 0x00 4. "PJ4F5,PJ4F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3F5,PJ3F5" "0,1"
|
|
bitfld.long 0x00 2. "PJ2F5,PJ2F5" "0,1"
|
|
bitfld.long 0x00 1. "PJ1F5,PJ1F5" "0,1"
|
|
bitfld.long 0x00 0. "PJ0F5,PJ0F5" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port J Function Register 7"
|
|
bitfld.long 0x00 7. "PJ7F7,PJ7F7" "0,1"
|
|
bitfld.long 0x00 6. "PJ6F7,PJ6F7" "0,1"
|
|
bitfld.long 0x00 3. "PJ3F7,PJ3F7" "0,1"
|
|
bitfld.long 0x00 2. "PJ2F7,PJ2F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port J Open Drain Control Register"
|
|
bitfld.long 0x00 2. "PJ2OD,PJ2OD" "0,1"
|
|
bitfld.long 0x00 1. "PJ1OD,PJ1OD" "0,1"
|
|
bitfld.long 0x00 0. "PJ0OD,PJ0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port J Open Drain Control Register"
|
|
bitfld.long 0x00 3. "PJ3OD,PJ3OD" "0,1"
|
|
bitfld.long 0x00 2. "PJ2OD,PJ2OD" "0,1"
|
|
bitfld.long 0x00 1. "PJ1OD,PJ1OD" "0,1"
|
|
bitfld.long 0x00 0. "PJ0OD,PJ0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port J Open Drain Control Register"
|
|
bitfld.long 0x00 5. "PJ5OD,PJ5OD" "0,1"
|
|
bitfld.long 0x00 4. "PJ4OD,PJ4OD" "0,1"
|
|
bitfld.long 0x00 3. "PJ3OD,PJ3OD" "0,1"
|
|
bitfld.long 0x00 2. "PJ2OD,PJ2OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PJ1OD,PJ1OD" "0,1"
|
|
bitfld.long 0x00 0. "PJ0OD,PJ0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port J Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PJ7OD,PJ7OD" "0,1"
|
|
bitfld.long 0x00 6. "PJ6OD,PJ6OD" "0,1"
|
|
bitfld.long 0x00 5. "PJ5OD,PJ5OD" "0,1"
|
|
bitfld.long 0x00 4. "PJ4OD,PJ4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3OD,PJ3OD" "0,1"
|
|
bitfld.long 0x00 2. "PJ2OD,PJ2OD" "0,1"
|
|
bitfld.long 0x00 1. "PJ1OD,PJ1OD" "0,1"
|
|
bitfld.long 0x00 0. "PJ0OD,PJ0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port J Pull-up Control Register"
|
|
bitfld.long 0x00 3. "PJ3UP,PJ3UP" "0,1"
|
|
bitfld.long 0x00 2. "PJ2UP,PJ2UP" "0,1"
|
|
bitfld.long 0x00 1. "PJ1UP,PJ1UP" "0,1"
|
|
bitfld.long 0x00 0. "PJ0UP,PJ0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port J Pull-up Control Register"
|
|
bitfld.long 0x00 2. "PJ2UP,PJ2UP" "0,1"
|
|
bitfld.long 0x00 1. "PJ1UP,PJ1UP" "0,1"
|
|
bitfld.long 0x00 0. "PJ0UP,PJ0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port J Pull-up Control Register"
|
|
bitfld.long 0x00 5. "PJ5UP,PJ5UP" "0,1"
|
|
bitfld.long 0x00 4. "PJ4UP,PJ4UP" "0,1"
|
|
bitfld.long 0x00 3. "PJ3UP,PJ3UP" "0,1"
|
|
bitfld.long 0x00 2. "PJ2UP,PJ2UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PJ1UP,PJ1UP" "0,1"
|
|
bitfld.long 0x00 0. "PJ0UP,PJ0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port J Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PJ7UP,PJ7UP" "0,1"
|
|
bitfld.long 0x00 6. "PJ6UP,PJ6UP" "0,1"
|
|
bitfld.long 0x00 5. "PJ5UP,PJ5UP" "0,1"
|
|
bitfld.long 0x00 4. "PJ4UP,PJ4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3UP,PJ3UP" "0,1"
|
|
bitfld.long 0x00 2. "PJ2UP,PJ2UP" "0,1"
|
|
bitfld.long 0x00 1. "PJ1UP,PJ1UP" "0,1"
|
|
bitfld.long 0x00 0. "PJ0UP,PJ0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port J Pull-down Control Register"
|
|
bitfld.long 0x00 3. "PJ3DN,PJ3DN" "0,1"
|
|
bitfld.long 0x00 2. "PJ2DN,PJ2DN" "0,1"
|
|
bitfld.long 0x00 1. "PJ1DN,PJ1DN" "0,1"
|
|
bitfld.long 0x00 0. "PJ0DN,PJ0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port J Pull-down Control Register"
|
|
bitfld.long 0x00 2. "PJ2DN,PJ2DN" "0,1"
|
|
bitfld.long 0x00 1. "PJ1DN,PJ1DN" "0,1"
|
|
bitfld.long 0x00 0. "PJ0DN,PJ0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port J Pull-down Control Register"
|
|
bitfld.long 0x00 5. "PJ5DN,PJ5DN" "0,1"
|
|
bitfld.long 0x00 4. "PJ4DN,PJ4DN" "0,1"
|
|
bitfld.long 0x00 3. "PJ3DN,PJ3DN" "0,1"
|
|
bitfld.long 0x00 2. "PJ2DN,PJ2DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PJ1DN,PJ1DN" "0,1"
|
|
bitfld.long 0x00 0. "PJ0DN,PJ0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port J Pull-down Control Register"
|
|
bitfld.long 0x00 1. "PJ1DN,PJ1DN" "0,1"
|
|
bitfld.long 0x00 0. "PJ0DN,PJ0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port J Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PJ7DN,PJ7DN" "0,1"
|
|
bitfld.long 0x00 6. "PJ6DN,PJ6DN" "0,1"
|
|
bitfld.long 0x00 5. "PJ5DN,PJ5DN" "0,1"
|
|
bitfld.long 0x00 4. "PJ4DN,PJ4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3DN,PJ3DN" "0,1"
|
|
bitfld.long 0x00 2. "PJ2DN,PJ2DN" "0,1"
|
|
bitfld.long 0x00 1. "PJ1DN,PJ1DN" "0,1"
|
|
bitfld.long 0x00 0. "PJ0DN,PJ0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port J Input Control Register"
|
|
bitfld.long 0x00 5. "PJ5IE,PJ5IE" "0,1"
|
|
bitfld.long 0x00 4. "PJ4IE,PJ4IE" "0,1"
|
|
bitfld.long 0x00 3. "PJ3IE,PJ3IE" "0,1"
|
|
bitfld.long 0x00 2. "PJ2IE,PJ2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PJ1IE,PJ1IE" "0,1"
|
|
bitfld.long 0x00 0. "PJ0IE,PJ0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port J Input Control Register"
|
|
bitfld.long 0x00 2. "PJ2IE,PJ2IE" "0,1"
|
|
bitfld.long 0x00 1. "PJ1IE,PJ1IE" "0,1"
|
|
bitfld.long 0x00 0. "PJ0IE,PJ0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port J Input Control Register"
|
|
bitfld.long 0x00 3. "PJ3IE,PJ3IE" "0,1"
|
|
bitfld.long 0x00 2. "PJ2IE,PJ2IE" "0,1"
|
|
bitfld.long 0x00 1. "PJ1IE,PJ1IE" "0,1"
|
|
bitfld.long 0x00 0. "PJ0IE,PJ0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port J Input Control Register"
|
|
bitfld.long 0x00 1. "PJ1IE,PJ1IE" "0,1"
|
|
bitfld.long 0x00 0. "PJ0IE,PJ0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port J Input Control Register"
|
|
bitfld.long 0x00 7. "PJ7IE,PJ7IE" "0,1"
|
|
bitfld.long 0x00 6. "PJ6IE,PJ6IE" "0,1"
|
|
bitfld.long 0x00 5. "PJ5IE,PJ5IE" "0,1"
|
|
bitfld.long 0x00 4. "PJ4IE,PJ4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3IE,PJ3IE" "0,1"
|
|
bitfld.long 0x00 2. "PJ2IE,PJ2IE" "0,1"
|
|
bitfld.long 0x00 1. "PJ1IE,PJ1IE" "0,1"
|
|
bitfld.long 0x00 0. "PJ0IE,PJ0IE" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400C0800
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PJ Data Register"
|
|
bitfld.long 0x00 6. "PJ6,PJ6" "0,1"
|
|
bitfld.long 0x00 5. "PJ5,PJ5" "0,1"
|
|
bitfld.long 0x00 4. "PJ4,PJ4" "0,1"
|
|
bitfld.long 0x00 3. "PJ3,PJ3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PJ2,PJ2" "0,1"
|
|
bitfld.long 0x00 1. "PJ1,PJ1" "0,1"
|
|
bitfld.long 0x00 0. "PJ0,PJ0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PJ Data Register"
|
|
bitfld.long 0x00 7. "PJ7,PJ7" "0,1"
|
|
bitfld.long 0x00 6. "PJ6,PJ6" "0,1"
|
|
bitfld.long 0x00 5. "PJ5,PJ5" "0,1"
|
|
bitfld.long 0x00 4. "PJ4,PJ4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3,PJ3" "0,1"
|
|
bitfld.long 0x00 2. "PJ2,PJ2" "0,1"
|
|
bitfld.long 0x00 1. "PJ1,PJ1" "0,1"
|
|
bitfld.long 0x00 0. "PJ0,PJ0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PJ Control Register"
|
|
bitfld.long 0x00 6. "PJ6C,PJ6C" "0,1"
|
|
bitfld.long 0x00 5. "PJ5C,PJ5C" "0,1"
|
|
bitfld.long 0x00 4. "PJ4C,PJ4C" "0,1"
|
|
bitfld.long 0x00 3. "PJ3C,PJ3C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PJ2C,PJ2C" "0,1"
|
|
bitfld.long 0x00 1. "PJ1C,PJ1C" "0,1"
|
|
bitfld.long 0x00 0. "PJ0C,PJ0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PJ Control Register"
|
|
bitfld.long 0x00 7. "PJ7C,PJ7C" "0,1"
|
|
bitfld.long 0x00 6. "PJ6C,PJ6C" "0,1"
|
|
bitfld.long 0x00 5. "PJ5C,PJ5C" "0,1"
|
|
bitfld.long 0x00 4. "PJ4C,PJ4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3C,PJ3C" "0,1"
|
|
bitfld.long 0x00 2. "PJ2C,PJ2C" "0,1"
|
|
bitfld.long 0x00 1. "PJ1C,PJ1C" "0,1"
|
|
bitfld.long 0x00 0. "PJ0C,PJ0C" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PJ Function Register 5"
|
|
bitfld.long 0x00 7. "PJ7F5,PJ7F5" "0,1"
|
|
bitfld.long 0x00 6. "PJ6F5,PJ6F5" "0,1"
|
|
bitfld.long 0x00 5. "PJ5F5,PJ5F5" "0,1"
|
|
bitfld.long 0x00 4. "PJ4F5,PJ4F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3F5,PJ3F5" "0,1"
|
|
bitfld.long 0x00 2. "PJ2F5,PJ2F5" "0,1"
|
|
bitfld.long 0x00 1. "PJ1F5,PJ1F5" "0,1"
|
|
bitfld.long 0x00 0. "PJ0F5,PJ0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PJ Function Register 5"
|
|
bitfld.long 0x00 6. "PJ6F5,PJ6F5" "0,1"
|
|
bitfld.long 0x00 5. "PJ5F5,PJ5F5" "0,1"
|
|
bitfld.long 0x00 4. "PJ4F5,PJ4F5" "0,1"
|
|
bitfld.long 0x00 3. "PJ3F5,PJ3F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PJ2F5,PJ2F5" "0,1"
|
|
bitfld.long 0x00 1. "PJ1F5,PJ1F5" "0,1"
|
|
bitfld.long 0x00 0. "PJ0F5,PJ0F5" "0,1"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,PJ Function Register 6"
|
|
bitfld.long 0x00 0. "PJ0F6,PJ0F6" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,PJ Function Register 7"
|
|
bitfld.long 0x00 1. "PJ1F7,PJ1F7" "0,1"
|
|
bitfld.long 0x00 0. "PJ0F7,PJ0F7" "0,1"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PJ Open Drain Control Register"
|
|
bitfld.long 0x00 6. "PJ6OD,PJ6OD" "0,1"
|
|
bitfld.long 0x00 5. "PJ5OD,PJ5OD" "0,1"
|
|
bitfld.long 0x00 4. "PJ4OD,PJ4OD" "0,1"
|
|
bitfld.long 0x00 3. "PJ3OD,PJ3OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PJ2OD,PJ2OD" "0,1"
|
|
bitfld.long 0x00 1. "PJ1OD,PJ1OD" "0,1"
|
|
bitfld.long 0x00 0. "PJ0OD,PJ0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PJ Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PJ7OD,PJ7OD" "0,1"
|
|
bitfld.long 0x00 6. "PJ6OD,PJ6OD" "0,1"
|
|
bitfld.long 0x00 5. "PJ5OD,PJ5OD" "0,1"
|
|
bitfld.long 0x00 4. "PJ4OD,PJ4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3OD,PJ3OD" "0,1"
|
|
bitfld.long 0x00 2. "PJ2OD,PJ2OD" "0,1"
|
|
bitfld.long 0x00 1. "PJ1OD,PJ1OD" "0,1"
|
|
bitfld.long 0x00 0. "PJ0OD,PJ0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PJ Pull-up Control Register"
|
|
bitfld.long 0x00 6. "PJ6PUP,PJ6PUP" "0,1"
|
|
bitfld.long 0x00 5. "PJ5PUP,PJ5PUP" "0,1"
|
|
bitfld.long 0x00 4. "PJ4PUP,PJ4PUP" "0,1"
|
|
bitfld.long 0x00 3. "PJ3PUP,PJ3PUP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PJ2PUP,PJ2PUP" "0,1"
|
|
bitfld.long 0x00 1. "PJ1PUP,PJ1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PJ0PUP,PJ0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PJ Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PJ7PUP,PJ7PUP" "0,1"
|
|
bitfld.long 0x00 6. "PJ6PUP,PJ6PUP" "0,1"
|
|
bitfld.long 0x00 5. "PJ5PUP,PJ5PUP" "0,1"
|
|
bitfld.long 0x00 4. "PJ4PUP,PJ4PUP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3PUP,PJ3PUP" "0,1"
|
|
bitfld.long 0x00 2. "PJ2PUP,PJ2PUP" "0,1"
|
|
bitfld.long 0x00 1. "PJ1PUP,PJ1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PJ0PUP,PJ0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PJ Pull-Down Control Register"
|
|
bitfld.long 0x00 6. "PJ6PDN,PJ6PDN" "0,1"
|
|
bitfld.long 0x00 5. "PJ5PDN,PJ5PDN" "0,1"
|
|
bitfld.long 0x00 4. "PJ4PDN,PJ4PDN" "0,1"
|
|
bitfld.long 0x00 3. "PJ3PDN,PJ3PDN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PJ2PDN,PJ2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PJ1PDN,PJ1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PJ0PDN,PJ0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PJ Pull-Down Control Register"
|
|
bitfld.long 0x00 7. "PJ7PDN,PJ7PDN" "0,1"
|
|
bitfld.long 0x00 6. "PJ6PDN,PJ6PDN" "0,1"
|
|
bitfld.long 0x00 5. "PJ5PDN,PJ5PDN" "0,1"
|
|
bitfld.long 0x00 4. "PJ4PDN,PJ4PDN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3PDN,PJ3PDN" "0,1"
|
|
bitfld.long 0x00 2. "PJ2PDN,PJ2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PJ1PDN,PJ1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PJ0PDN,PJ0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PJ Input Enable Control Register"
|
|
bitfld.long 0x00 6. "PJ6IE,PJ6IE" "0,1"
|
|
bitfld.long 0x00 5. "PJ5IE,PJ5IE" "0,1"
|
|
bitfld.long 0x00 4. "PJ4IE,PJ4IE" "0,1"
|
|
bitfld.long 0x00 3. "PJ3IE,PJ3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PJ2IE,PJ2IE" "0,1"
|
|
bitfld.long 0x00 1. "PJ1IE,PJ1IE" "0,1"
|
|
bitfld.long 0x00 0. "PJ0IE,PJ0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PJ Input Enable Control Register"
|
|
bitfld.long 0x00 7. "PJ7IE,PJ7IE" "0,1"
|
|
bitfld.long 0x00 6. "PJ6IE,PJ6IE" "0,1"
|
|
bitfld.long 0x00 5. "PJ5IE,PJ5IE" "0,1"
|
|
bitfld.long 0x00 4. "PJ4IE,PJ4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PJ3IE,PJ3IE" "0,1"
|
|
bitfld.long 0x00 2. "PJ2IE,PJ2IE" "0,1"
|
|
bitfld.long 0x00 1. "PJ1IE,PJ1IE" "0,1"
|
|
bitfld.long 0x00 0. "PJ0IE,PJ0IE" "0,1"
|
|
endif
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L2*")
|
|
tree "PK (Port K)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E0900
|
|
elif cpuis("TMPM4L2*")
|
|
base ad:0x40080900
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port K Data Register"
|
|
bitfld.long 0x00 4. "PK4,PK4" "0,1"
|
|
bitfld.long 0x00 3. "PK3,PK3" "0,1"
|
|
bitfld.long 0x00 2. "PK2,PK2" "0,1"
|
|
bitfld.long 0x00 1. "PK1,PK1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0,PK0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port K Data Register"
|
|
bitfld.long 0x00 7. "PK7,PK7" "0,1"
|
|
bitfld.long 0x00 6. "PK6,PK6" "0,1"
|
|
bitfld.long 0x00 5. "PK5,PK5" "0,1"
|
|
bitfld.long 0x00 4. "PK4,PK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PK3,PK3" "0,1"
|
|
bitfld.long 0x00 2. "PK2,PK2" "0,1"
|
|
bitfld.long 0x00 1. "PK1,PK1" "0,1"
|
|
bitfld.long 0x00 0. "PK0,PK0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port K Data Register"
|
|
bitfld.long 0x00 2. "PK2,PK2" "0,1"
|
|
bitfld.long 0x00 1. "PK1,PK1" "0,1"
|
|
bitfld.long 0x00 0. "PK0,PK0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port K Data Register"
|
|
bitfld.long 0x00 0. "PK0,PK0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port K Output Control Register"
|
|
bitfld.long 0x00 7. "PK7C,PK7C" "0,1"
|
|
bitfld.long 0x00 6. "PK6C,PK6C" "0,1"
|
|
bitfld.long 0x00 5. "PK5C,PK5C" "0,1"
|
|
bitfld.long 0x00 4. "PK4C,PK4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PK3C,PK3C" "0,1"
|
|
bitfld.long 0x00 2. "PK2C,PK2C" "0,1"
|
|
bitfld.long 0x00 1. "PK1C,PK1C" "0,1"
|
|
bitfld.long 0x00 0. "PK0C,PK0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port K Output Control Register"
|
|
bitfld.long 0x00 4. "PK4C,PK4C" "0,1"
|
|
bitfld.long 0x00 3. "PK3C,PK3C" "0,1"
|
|
bitfld.long 0x00 2. "PK2C,PK2C" "0,1"
|
|
bitfld.long 0x00 1. "PK1C,PK1C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0C,PK0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port K Output Control Register"
|
|
bitfld.long 0x00 0. "PK0C,PK0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port K Output Control Register"
|
|
bitfld.long 0x00 2. "PK2C,PK2C" "0,1"
|
|
bitfld.long 0x00 1. "PK1C,PK1C" "0,1"
|
|
bitfld.long 0x00 0. "PK0C,PK0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port K Function Register 1"
|
|
bitfld.long 0x00 5. "PK5F1,PK5F1" "0,1"
|
|
bitfld.long 0x00 4. "PK4F1,PK4F1" "0,1"
|
|
bitfld.long 0x00 3. "PK3F1,PK3F1" "0,1"
|
|
bitfld.long 0x00 2. "PK2F1,PK2F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PK1F1,PK1F1" "0,1"
|
|
bitfld.long 0x00 0. "PK0F1,PK0F1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port K Function Register 2"
|
|
bitfld.long 0x00 7. "PK7F2,PK7F2" "0,1"
|
|
bitfld.long 0x00 6. "PK6F2,PK6F2" "0,1"
|
|
bitfld.long 0x00 3. "PK3F2,PK3F2" "0,1"
|
|
bitfld.long 0x00 2. "PK2F2,PK2F2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PK1F2,PK1F2" "0,1"
|
|
bitfld.long 0x00 0. "PK0F2,PK0F2" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port K Function Register 3"
|
|
bitfld.long 0x00 7. "PK7F3,PK7F3" "0,1"
|
|
bitfld.long 0x00 6. "PK6F3,PK6F3" "0,1"
|
|
bitfld.long 0x00 1. "PK1F3,PK1F3" "0,1"
|
|
bitfld.long 0x00 0. "PK0F3,PK0F3" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port K Function Register 4"
|
|
bitfld.long 0x00 7. "PK7F4,PK7F4" "0,1"
|
|
bitfld.long 0x00 6. "PK6F4,PK6F4" "0,1"
|
|
bitfld.long 0x00 5. "PK5F4,PK5F4" "0,1"
|
|
bitfld.long 0x00 4. "PK4F4,PK4F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PK1F4,PK1F4" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port K Function Register 6"
|
|
bitfld.long 0x00 7. "PK7F6,PK7F6" "0,1"
|
|
bitfld.long 0x00 6. "PK6F6,PK6F6" "0,1"
|
|
bitfld.long 0x00 5. "PK5F6,PK5F6" "0,1"
|
|
bitfld.long 0x00 4. "PK4F6,PK4F6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PK3F6,PK3F6" "0,1"
|
|
bitfld.long 0x00 2. "PK2F6,PK2F6" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port K Function Register 7"
|
|
bitfld.long 0x00 7. "PK7F7,PK7F7" "0,1"
|
|
bitfld.long 0x00 0. "PK0F7,PK0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port K Open Drain Control Register"
|
|
bitfld.long 0x00 2. "PK2OD,PK2OD" "0,1"
|
|
bitfld.long 0x00 1. "PK1OD,PK1OD" "0,1"
|
|
bitfld.long 0x00 0. "PK0OD,PK0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port K Open Drain Control Register"
|
|
bitfld.long 0x00 6. "PK6OD,PK6OD" "0,1"
|
|
bitfld.long 0x00 5. "PK5OD,PK5OD" "0,1"
|
|
bitfld.long 0x00 4. "PK4OD,PK4OD" "0,1"
|
|
bitfld.long 0x00 3. "PK3OD,PK3OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PK2OD,PK2OD" "0,1"
|
|
bitfld.long 0x00 1. "PK1OD,PK1OD" "0,1"
|
|
bitfld.long 0x00 0. "PK0OD,PK0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port K Open Drain Control Register"
|
|
bitfld.long 0x00 4. "PK4OD,PK4OD" "0,1"
|
|
bitfld.long 0x00 3. "PK3OD,PK3OD" "0,1"
|
|
bitfld.long 0x00 2. "PK2OD,PK2OD" "0,1"
|
|
bitfld.long 0x00 1. "PK1OD,PK1OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0OD,PK0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port K Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PK7OD,PK7OD" "0,1"
|
|
bitfld.long 0x00 6. "PK6OD,PK6OD" "0,1"
|
|
bitfld.long 0x00 5. "PK5OD,PK5OD" "0,1"
|
|
bitfld.long 0x00 4. "PK4OD,PK4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PK3OD,PK3OD" "0,1"
|
|
bitfld.long 0x00 2. "PK2OD,PK2OD" "0,1"
|
|
bitfld.long 0x00 1. "PK1OD,PK1OD" "0,1"
|
|
bitfld.long 0x00 0. "PK0OD,PK0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port K Open Drain Control Register"
|
|
bitfld.long 0x00 0. "PK0OD,PK0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port K Pull-up Control Register"
|
|
bitfld.long 0x00 2. "PK2UP,PK2UP" "0,1"
|
|
bitfld.long 0x00 1. "PK1UP,PK1UP" "0,1"
|
|
bitfld.long 0x00 0. "PK0UP,PK0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port K Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PK7UP,PK7UP" "0,1"
|
|
bitfld.long 0x00 6. "PK6UP,PK6UP" "0,1"
|
|
bitfld.long 0x00 5. "PK5UP,PK5UP" "0,1"
|
|
bitfld.long 0x00 4. "PK4UP,PK4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PK3UP,PK3UP" "0,1"
|
|
bitfld.long 0x00 2. "PK2UP,PK2UP" "0,1"
|
|
bitfld.long 0x00 1. "PK1UP,PK1UP" "0,1"
|
|
bitfld.long 0x00 0. "PK0UP,PK0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port K Pull-up Control Register"
|
|
bitfld.long 0x00 4. "PK4UP,PK4UP" "0,1"
|
|
bitfld.long 0x00 3. "PK3UP,PK3UP" "0,1"
|
|
bitfld.long 0x00 2. "PK2UP,PK2UP" "0,1"
|
|
bitfld.long 0x00 1. "PK1UP,PK1UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0UP,PK0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port K Pull-up Control Register"
|
|
bitfld.long 0x00 0. "PK0UP,PK0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port K Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PK7DN,PK7DN" "0,1"
|
|
bitfld.long 0x00 6. "PK6DN,PK6DN" "0,1"
|
|
bitfld.long 0x00 5. "PK5DN,PK5DN" "0,1"
|
|
bitfld.long 0x00 4. "PK4DN,PK4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PK3DN,PK3DN" "0,1"
|
|
bitfld.long 0x00 2. "PK2DN,PK2DN" "0,1"
|
|
bitfld.long 0x00 1. "PK1DN,PK1DN" "0,1"
|
|
bitfld.long 0x00 0. "PK0DN,PK0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port K Pull-down Control Register"
|
|
bitfld.long 0x00 4. "PK4DN,PK4DN" "0,1"
|
|
bitfld.long 0x00 3. "PK3DN,PK3DN" "0,1"
|
|
bitfld.long 0x00 2. "PK2DN,PK2DN" "0,1"
|
|
bitfld.long 0x00 1. "PK1DN,PK1DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0DN,PK0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port K Pull-down Control Register"
|
|
bitfld.long 0x00 2. "PK2DN,PK2DN" "0,1"
|
|
bitfld.long 0x00 1. "PK1DN,PK1DN" "0,1"
|
|
bitfld.long 0x00 0. "PK0DN,PK0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port K Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PK7DN,PK7DN" "0,1"
|
|
bitfld.long 0x00 6. "PK6DN,PK6DN" "0,1"
|
|
bitfld.long 0x00 5. "PK5DN,PK5DN" "0,1"
|
|
bitfld.long 0x00 4. "PK4DN,PK4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PK3DN,PK3DN" "0,1"
|
|
bitfld.long 0x00 2. "PK2DN,PK2DN" "0,1"
|
|
bitfld.long 0x00 1. "PK1DN,PK1DN" "0,1"
|
|
bitfld.long 0x00 0. "PK0DN,PK0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port K Pull-up Control Register"
|
|
bitfld.long 0x00 0. "PK0DN,PK0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port K Input Control Register"
|
|
bitfld.long 0x00 7. "PK7IE,PK7IE" "0,1"
|
|
bitfld.long 0x00 6. "PK6IE,PK6IE" "0,1"
|
|
bitfld.long 0x00 5. "PK5IE,PK5IE" "0,1"
|
|
bitfld.long 0x00 4. "PK4IE,PK4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PK3IE,PK3IE" "0,1"
|
|
bitfld.long 0x00 2. "PK2IE,PK2IE" "0,1"
|
|
bitfld.long 0x00 1. "PK1IE,PK1IE" "0,1"
|
|
bitfld.long 0x00 0. "PK0IE,PK0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port K Input Control Register"
|
|
bitfld.long 0x00 2. "PK2IE,PK2IE" "0,1"
|
|
bitfld.long 0x00 1. "PK1IE,PK1IE" "0,1"
|
|
bitfld.long 0x00 0. "PK0IE,PK0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port K Input Control Register"
|
|
bitfld.long 0x00 0. "PK0IE,PK0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port K Input Control Register"
|
|
bitfld.long 0x00 4. "PK4IE,PK4IE" "0,1"
|
|
bitfld.long 0x00 3. "PK3IE,PK3IE" "0,1"
|
|
bitfld.long 0x00 2. "PK2IE,PK2IE" "0,1"
|
|
bitfld.long 0x00 1. "PK1IE,PK1IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0IE,PK0IE" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400C0900
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PK Data Register"
|
|
bitfld.long 0x00 3. "PK3,PK3" "0,1"
|
|
bitfld.long 0x00 2. "PK2,PK2" "0,1"
|
|
bitfld.long 0x00 1. "PK1,PK1" "0,1"
|
|
bitfld.long 0x00 0. "PK0,PK0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PK Data Register"
|
|
bitfld.long 0x00 4. "PK4,PK4" "0,1"
|
|
bitfld.long 0x00 3. "PK3,PK3" "0,1"
|
|
bitfld.long 0x00 2. "PK2,PK2" "0,1"
|
|
bitfld.long 0x00 1. "PK1,PK1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0,PK0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PK Control Register"
|
|
bitfld.long 0x00 3. "PK3C,PK3C" "0,1"
|
|
bitfld.long 0x00 2. "PK2C,PK2C" "0,1"
|
|
bitfld.long 0x00 1. "PK1C,PK1C" "0,1"
|
|
bitfld.long 0x00 0. "PK0C,PK0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PK Control Register"
|
|
bitfld.long 0x00 4. "PK4C,PK4C" "0,1"
|
|
bitfld.long 0x00 3. "PK3C,PK3C" "0,1"
|
|
bitfld.long 0x00 2. "PK2C,PK2C" "0,1"
|
|
bitfld.long 0x00 1. "PK1C,PK1C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0C,PK0C" "0,1"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,PK Function Register 1"
|
|
bitfld.long 0x00 3. "PK3F1,PK3F1" "0,1"
|
|
bitfld.long 0x00 2. "PK2F1,PK2F1" "0,1"
|
|
bitfld.long 0x00 1. "PK1F1,PK1F1" "0,1"
|
|
bitfld.long 0x00 0. "PK0F1,PK0F1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,PK Function Register 2"
|
|
bitfld.long 0x00 3. "PK3F2,PK3F2" "0,1"
|
|
bitfld.long 0x00 2. "PK2F2,PK2F2" "0,1"
|
|
bitfld.long 0x00 1. "PK1F2,PK1F2" "0,1"
|
|
bitfld.long 0x00 0. "PK0F2,PK0F2" "0,1"
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,PK Function Register 3"
|
|
bitfld.long 0x00 4. "PK4F3,PK4F3" "0,1"
|
|
bitfld.long 0x00 3. "PK3F3,PK3F3" "0,1"
|
|
bitfld.long 0x00 2. "PK2F3,PK2F3" "0,1"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,PK Function Register 4"
|
|
bitfld.long 0x00 1. "PK1F4,PK1F4" "0,1"
|
|
bitfld.long 0x00 0. "PK0F4,PK0F4" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,PK Function Register 5"
|
|
bitfld.long 0x00 1. "PK1F5,PK1F5" "0,1"
|
|
bitfld.long 0x00 0. "PK0F5,PK0F5" "0,1"
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,PK Function Register 6"
|
|
bitfld.long 0x00 4. "PK4F6,PK4F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,PK Function Register 7"
|
|
bitfld.long 0x00 3. "PK3F7,PK3F7" "0,1"
|
|
bitfld.long 0x00 2. "PK2F7,PK2F7" "0,1"
|
|
bitfld.long 0x00 1. "PK1F7,PK1F7" "0,1"
|
|
bitfld.long 0x00 0. "PK0F7,PK0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,PK Function Register 7"
|
|
bitfld.long 0x00 4. "PK4F7,PK4F7" "0,1"
|
|
bitfld.long 0x00 3. "PK3F7,PK3F7" "0,1"
|
|
bitfld.long 0x00 2. "PK2F7,PK2F7" "0,1"
|
|
bitfld.long 0x00 1. "PK1F7,PK1F7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0F7,PK0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PK Open Drain Control Register"
|
|
bitfld.long 0x00 3. "PK3OD,PK3OD" "0,1"
|
|
bitfld.long 0x00 2. "PK2OD,PK2OD" "0,1"
|
|
bitfld.long 0x00 1. "PK1OD,PK1OD" "0,1"
|
|
bitfld.long 0x00 0. "PK0OD,PK0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PK Open Drain Control Register"
|
|
bitfld.long 0x00 4. "PK4OD,PK4OD" "0,1"
|
|
bitfld.long 0x00 3. "PK3OD,PK3OD" "0,1"
|
|
bitfld.long 0x00 2. "PK2OD,PK2OD" "0,1"
|
|
bitfld.long 0x00 1. "PK1OD,PK1OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0OD,PK0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PK Pull-up Control Register"
|
|
bitfld.long 0x00 4. "PK4PUP,PK4PUP" "0,1"
|
|
bitfld.long 0x00 3. "PK3PUP,PK3PUP" "0,1"
|
|
bitfld.long 0x00 2. "PK2PUP,PK2PUP" "0,1"
|
|
bitfld.long 0x00 1. "PK1PUP,PK1PUP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0PUP,PK0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PK Pull-up Control Register"
|
|
bitfld.long 0x00 3. "PK3PUP,PK3PUP" "0,1"
|
|
bitfld.long 0x00 2. "PK2PUP,PK2PUP" "0,1"
|
|
bitfld.long 0x00 1. "PK1PUP,PK1PUP" "0,1"
|
|
bitfld.long 0x00 0. "PK0PUP,PK0PUP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PK Pull-Down Control Register"
|
|
bitfld.long 0x00 4. "PK4PDN,PK4PDN" "0,1"
|
|
bitfld.long 0x00 3. "PK3PDN,PK3PDN" "0,1"
|
|
bitfld.long 0x00 2. "PK2PDN,PK2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PK1PDN,PK1PDN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0PDN,PK0PDN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PK Pull-Down Control Register"
|
|
bitfld.long 0x00 3. "PK3PDN,PK3PDN" "0,1"
|
|
bitfld.long 0x00 2. "PK2PDN,PK2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PK1PDN,PK1PDN" "0,1"
|
|
bitfld.long 0x00 0. "PK0PDN,PK0PDN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PK Input Enable Control Register"
|
|
bitfld.long 0x00 3. "PK3IE,PK3IE" "0,1"
|
|
bitfld.long 0x00 2. "PK2IE,PK2IE" "0,1"
|
|
bitfld.long 0x00 1. "PK1IE,PK1IE" "0,1"
|
|
bitfld.long 0x00 0. "PK0IE,PK0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PK Input Enable Control Register"
|
|
bitfld.long 0x00 4. "PK4IE,PK4IE" "0,1"
|
|
bitfld.long 0x00 3. "PK3IE,PK3IE" "0,1"
|
|
bitfld.long 0x00 2. "PK2IE,PK2IE" "0,1"
|
|
bitfld.long 0x00 1. "PK1IE,PK1IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PK0IE,PK0IE" "0,1"
|
|
endif
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "PL (Port L)"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E0A00
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port L Data Register"
|
|
bitfld.long 0x00 7. "PL7,PL7" "0,1"
|
|
bitfld.long 0x00 6. "PL6,PL6" "0,1"
|
|
bitfld.long 0x00 5. "PL5,PL5" "0,1"
|
|
bitfld.long 0x00 4. "PL4,PL4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PL3,PL3" "0,1"
|
|
bitfld.long 0x00 2. "PL2,PL2" "0,1"
|
|
bitfld.long 0x00 1. "PL1,PL1" "0,1"
|
|
bitfld.long 0x00 0. "PL0,PL0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port L Data Register"
|
|
bitfld.long 0x00 3. "PL3,PL3" "0,1"
|
|
bitfld.long 0x00 2. "PL2,PL2" "0,1"
|
|
bitfld.long 0x00 1. "PL1,PL1" "0,1"
|
|
bitfld.long 0x00 0. "PL0,PL0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port L Output Control Register"
|
|
bitfld.long 0x00 7. "PL7C,PL7C" "0,1"
|
|
bitfld.long 0x00 6. "PL6C,PL6C" "0,1"
|
|
bitfld.long 0x00 5. "PL5C,PL5C" "0,1"
|
|
bitfld.long 0x00 4. "PL4C,PL4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PL3C,PL3C" "0,1"
|
|
bitfld.long 0x00 2. "PL2C,PL2C" "0,1"
|
|
bitfld.long 0x00 1. "PL1C,PL1C" "0,1"
|
|
bitfld.long 0x00 0. "PL0C,PL0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port L Output Control Register"
|
|
bitfld.long 0x00 3. "PL3C,PL3C" "0,1"
|
|
bitfld.long 0x00 2. "PL2C,PL2C" "0,1"
|
|
bitfld.long 0x00 1. "PL1C,PL1C" "0,1"
|
|
bitfld.long 0x00 0. "PL0C,PL0C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port L Function Register 1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port L Function Register 1"
|
|
bitfld.long 0x00 7. "PL7F1,PL7F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port L Function Register 2"
|
|
bitfld.long 0x00 3. "PL3F2,PL3F2" "0,1"
|
|
bitfld.long 0x00 0. "PL0F2,PL0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port L Function Register 2"
|
|
bitfld.long 0x00 7. "PL7F2,PL7F2" "0,1"
|
|
bitfld.long 0x00 6. "PL6F2,PL6F2" "0,1"
|
|
bitfld.long 0x00 5. "PL5F2,PL5F2" "0,1"
|
|
bitfld.long 0x00 4. "PL4F2,PL4F2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PL3F2,PL3F2" "0,1"
|
|
bitfld.long 0x00 0. "PL0F2,PL0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port L Function Register 3"
|
|
bitfld.long 0x00 3. "PL3F3,PL3F3" "0,1"
|
|
bitfld.long 0x00 0. "PL0F3,PL0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port L Function Register 3"
|
|
bitfld.long 0x00 6. "PL6F3,PL6F3" "0,1"
|
|
bitfld.long 0x00 4. "PL4F3,PL4F3" "0,1"
|
|
bitfld.long 0x00 3. "PL3F3,PL3F3" "0,1"
|
|
bitfld.long 0x00 0. "PL0F3,PL0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port L Function Register 6"
|
|
bitfld.long 0x00 3. "PL3F6,PL3F6" "0,1"
|
|
bitfld.long 0x00 0. "PL0F6,PL0F6" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port L Function Register 7"
|
|
bitfld.long 0x00 3. "PL3F7,PL3F7" "0,1"
|
|
bitfld.long 0x00 2. "PL2F7,PL2F7" "0,1"
|
|
bitfld.long 0x00 1. "PL1F7,PL1F7" "0,1"
|
|
bitfld.long 0x00 0. "PL0F7,PL0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port L Open Drain Control Register"
|
|
bitfld.long 0x00 3. "PL3OD,PL3OD" "0,1"
|
|
bitfld.long 0x00 2. "PL2OD,PL2OD" "0,1"
|
|
bitfld.long 0x00 1. "PL1OD,PL1OD" "0,1"
|
|
bitfld.long 0x00 0. "PL0OD,PL0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port L Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PL7OD,PL7OD" "0,1"
|
|
bitfld.long 0x00 6. "PL6OD,PL6OD" "0,1"
|
|
bitfld.long 0x00 5. "PL5OD,PL5OD" "0,1"
|
|
bitfld.long 0x00 4. "PL4OD,PL4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PL3OD,PL3OD" "0,1"
|
|
bitfld.long 0x00 2. "PL2OD,PL2OD" "0,1"
|
|
bitfld.long 0x00 1. "PL1OD,PL1OD" "0,1"
|
|
bitfld.long 0x00 0. "PL0OD,PL0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port L Pull-up Control Register"
|
|
bitfld.long 0x00 3. "PL3UP,PL3UP" "0,1"
|
|
bitfld.long 0x00 2. "PL2UP,PL2UP" "0,1"
|
|
bitfld.long 0x00 1. "PL1UP,PL1UP" "0,1"
|
|
bitfld.long 0x00 0. "PL0UP,PL0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port L Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PL7UP,PL7UP" "0,1"
|
|
bitfld.long 0x00 6. "PL6UP,PL6UP" "0,1"
|
|
bitfld.long 0x00 5. "PL5UP,PL5UP" "0,1"
|
|
bitfld.long 0x00 4. "PL4UP,PL4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PL3UP,PL3UP" "0,1"
|
|
bitfld.long 0x00 2. "PL2UP,PL2UP" "0,1"
|
|
bitfld.long 0x00 1. "PL1UP,PL1UP" "0,1"
|
|
bitfld.long 0x00 0. "PL0UP,PL0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port L Pull-down Control Register"
|
|
bitfld.long 0x00 3. "PL3DN,PL3DN" "0,1"
|
|
bitfld.long 0x00 2. "PL2DN,PL2DN" "0,1"
|
|
bitfld.long 0x00 1. "PL1DN,PL1DN" "0,1"
|
|
bitfld.long 0x00 0. "PL0DN,PL0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port L Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PL7DN,PL7DN" "0,1"
|
|
bitfld.long 0x00 6. "PL6DN,PL6DN" "0,1"
|
|
bitfld.long 0x00 5. "PL5DN,PL5DN" "0,1"
|
|
bitfld.long 0x00 4. "PL4DN,PL4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PL3DN,PL3DN" "0,1"
|
|
bitfld.long 0x00 2. "PL2DN,PL2DN" "0,1"
|
|
bitfld.long 0x00 1. "PL1DN,PL1DN" "0,1"
|
|
bitfld.long 0x00 0. "PL0DN,PL0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port L Input Control Register"
|
|
bitfld.long 0x00 7. "PL7IE,PL7IE" "0,1"
|
|
bitfld.long 0x00 6. "PL6IE,PL6IE" "0,1"
|
|
bitfld.long 0x00 5. "PL5IE,PL5IE" "0,1"
|
|
bitfld.long 0x00 4. "PL4IE,PL4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PL3IE,PL3IE" "0,1"
|
|
bitfld.long 0x00 2. "PL2IE,PL2IE" "0,1"
|
|
bitfld.long 0x00 1. "PL1IE,PL1IE" "0,1"
|
|
bitfld.long 0x00 0. "PL0IE,PL0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port L Input Control Register"
|
|
bitfld.long 0x00 3. "PL3IE,PL3IE" "0,1"
|
|
bitfld.long 0x00 2. "PL2IE,PL2IE" "0,1"
|
|
bitfld.long 0x00 1. "PL1IE,PL1IE" "0,1"
|
|
bitfld.long 0x00 0. "PL0IE,PL0IE" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("TMPM4K4A*")
|
|
base ad:0x400C0A00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,PL Data Register"
|
|
bitfld.long 0x00 4. "PL4,PL4" "0,1"
|
|
bitfld.long 0x00 3. "PL3,PL3" "0,1"
|
|
bitfld.long 0x00 2. "PL2,PL2" "0,1"
|
|
bitfld.long 0x00 1. "PL1,PL1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PL0,PL0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,PL Control Register"
|
|
bitfld.long 0x00 4. "PL4C,PL4C" "0,1"
|
|
bitfld.long 0x00 3. "PL3C,PL3C" "0,1"
|
|
bitfld.long 0x00 2. "PL2C,PL2C" "0,1"
|
|
bitfld.long 0x00 1. "PL1C,PL1C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PL0C,PL0C" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,PL Function Register 6"
|
|
bitfld.long 0x00 4. "PL4F6,PL4F6" "0,1"
|
|
bitfld.long 0x00 3. "PL3F6,PL3F6" "0,1"
|
|
bitfld.long 0x00 2. "PL2F6,PL2F6" "0,1"
|
|
bitfld.long 0x00 1. "PL1F6,PL1F6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PL0F6,PL0F6" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,PL Function Register 7"
|
|
bitfld.long 0x00 4. "PL4F7,PL4F7" "0,1"
|
|
bitfld.long 0x00 3. "PL3F7,PL3F7" "0,1"
|
|
bitfld.long 0x00 2. "PL2F7,PL2F7" "0,1"
|
|
bitfld.long 0x00 1. "PL1F7,PL1F7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PL0F7,PL0F7" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,PL Open Drain Control Register"
|
|
bitfld.long 0x00 4. "PL4OD,PL4OD" "0,1"
|
|
bitfld.long 0x00 3. "PL3OD,PL3OD" "0,1"
|
|
bitfld.long 0x00 2. "PL2OD,PL2OD" "0,1"
|
|
bitfld.long 0x00 1. "PL1OD,PL1OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PL0OD,PL0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,PL Pull-up Control Register"
|
|
bitfld.long 0x00 4. "PL4PUP,PL4PUP" "0,1"
|
|
bitfld.long 0x00 3. "PL3PUP,PL3PUP" "0,1"
|
|
bitfld.long 0x00 2. "PL2PUP,PL2PUP" "0,1"
|
|
bitfld.long 0x00 1. "PL1PUP,PL1PUP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PL0PUP,PL0PUP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,PL Pull-Down Control Register"
|
|
bitfld.long 0x00 4. "PL4PDN,PL4PDN" "0,1"
|
|
bitfld.long 0x00 3. "PL3PDN,PL3PDN" "0,1"
|
|
bitfld.long 0x00 2. "PL2PDN,PL2PDN" "0,1"
|
|
bitfld.long 0x00 1. "PL1PDN,PL1PDN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PL0PDN,PL0PDN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,PL Input Enable Control Register"
|
|
bitfld.long 0x00 4. "PL4IE,PL4IE" "0,1"
|
|
bitfld.long 0x00 3. "PL3IE,PL3IE" "0,1"
|
|
bitfld.long 0x00 2. "PL2IE,PL2IE" "0,1"
|
|
bitfld.long 0x00 1. "PL1IE,PL1IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PL0IE,PL0IE" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G8*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "PM (Port M)"
|
|
base ad:0x400E0B00
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port M Data Register"
|
|
bitfld.long 0x00 7. "PM7,PM7" "0,1"
|
|
bitfld.long 0x00 6. "PM6,PM6" "0,1"
|
|
bitfld.long 0x00 5. "PM5,PM5" "0,1"
|
|
bitfld.long 0x00 4. "PM4,PM4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PM3,PM3" "0,1"
|
|
bitfld.long 0x00 2. "PM2,PM2" "0,1"
|
|
bitfld.long 0x00 1. "PM1,PM1" "0,1"
|
|
bitfld.long 0x00 0. "PM0,PM0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port M Data Register"
|
|
bitfld.long 0x00 2. "PM2,PM2" "0,1"
|
|
bitfld.long 0x00 1. "PM1,PM1" "0,1"
|
|
bitfld.long 0x00 0. "PM0,PM0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port M Output Control Register"
|
|
bitfld.long 0x00 2. "PM2C,PM2C" "0,1"
|
|
bitfld.long 0x00 1. "PM1C,PM1C" "0,1"
|
|
bitfld.long 0x00 0. "PM0C,PM0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port M Output Control Register"
|
|
bitfld.long 0x00 7. "PM7C,PM7C" "0,1"
|
|
bitfld.long 0x00 6. "PM6C,PM6C" "0,1"
|
|
bitfld.long 0x00 5. "PM5C,PM5C" "0,1"
|
|
bitfld.long 0x00 4. "PM4C,PM4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PM3C,PM3C" "0,1"
|
|
bitfld.long 0x00 2. "PM2C,PM2C" "0,1"
|
|
bitfld.long 0x00 1. "PM1C,PM1C" "0,1"
|
|
bitfld.long 0x00 0. "PM0C,PM0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port M Function Register 2"
|
|
bitfld.long 0x00 7. "PM7F2,PM7F2" "0,1"
|
|
bitfld.long 0x00 6. "PM6F2,PM6F2" "0,1"
|
|
bitfld.long 0x00 5. "PM5F2,PM5F2" "0,1"
|
|
bitfld.long 0x00 4. "PM4F2,PM4F2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PM3F2,PM3F2" "0,1"
|
|
bitfld.long 0x00 2. "PM2F2,PM2F2" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port M Function Register 3"
|
|
bitfld.long 0x00 6. "PM6F3,PM6F3" "0,1"
|
|
bitfld.long 0x00 5. "PM5F3,PM5F3" "0,1"
|
|
bitfld.long 0x00 2. "PM2F3,PM2F3" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port M Function Register 4"
|
|
bitfld.long 0x00 7. "PM7F4,PM7F4" "0,1"
|
|
bitfld.long 0x00 6. "PM6F4,PM6F4" "0,1"
|
|
bitfld.long 0x00 4. "PM4F4,PM4F4" "0,1"
|
|
bitfld.long 0x00 3. "PM3F4,PM3F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PM1F4,PM1F4" "0,1"
|
|
bitfld.long 0x00 0. "PM0F4,PM0F4" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port M Function Register 5"
|
|
bitfld.long 0x00 7. "PM7F5,PM7F5" "0,1"
|
|
bitfld.long 0x00 6. "PM6F5,PM6F5" "0,1"
|
|
bitfld.long 0x00 3. "PM3F5,PM3F5" "0,1"
|
|
bitfld.long 0x00 2. "PM2F5,PM2F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PM1F5,PM1F5" "0,1"
|
|
bitfld.long 0x00 0. "PM0F5,PM0F5" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port M Function Register 6"
|
|
bitfld.long 0x00 7. "PM7F6,PM7F6" "0,1"
|
|
bitfld.long 0x00 6. "PM6F6,PM6F6" "0,1"
|
|
bitfld.long 0x00 5. "PM5F6,PM5F6" "0,1"
|
|
bitfld.long 0x00 4. "PM4F6,PM4F6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PM3F6,PM3F6" "0,1"
|
|
bitfld.long 0x00 2. "PM2F6,PM2F6" "0,1"
|
|
bitfld.long 0x00 1. "PM1F6,PM1F6" "0,1"
|
|
bitfld.long 0x00 0. "PM0F6,PM0F6" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port M Function Register 7"
|
|
bitfld.long 0x00 7. "PM7F7,PM7F7" "0,1"
|
|
bitfld.long 0x00 6. "PM6F7,PM6F7" "0,1"
|
|
bitfld.long 0x00 5. "PM5F7,PM5F7" "0,1"
|
|
bitfld.long 0x00 4. "PM4F7,PM4F7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PM3F7,PM3F7" "0,1"
|
|
bitfld.long 0x00 2. "PM2F7,PM2F7" "0,1"
|
|
bitfld.long 0x00 1. "PM1F7,PM1F7" "0,1"
|
|
bitfld.long 0x00 0. "PM0F7,PM0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port M Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PM7OD,PM7OD" "0,1"
|
|
bitfld.long 0x00 6. "PM6OD,PM6OD" "0,1"
|
|
bitfld.long 0x00 5. "PM5OD,PM5OD" "0,1"
|
|
bitfld.long 0x00 4. "PM4OD,PM4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PM3OD,PM3OD" "0,1"
|
|
bitfld.long 0x00 2. "PM2OD,PM2OD" "0,1"
|
|
bitfld.long 0x00 1. "PM1OD,PM1OD" "0,1"
|
|
bitfld.long 0x00 0. "PM0OD,PM0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port M Open Drain Control Register"
|
|
bitfld.long 0x00 2. "PM2OD,PM2OD" "0,1"
|
|
bitfld.long 0x00 1. "PM1OD,PM1OD" "0,1"
|
|
bitfld.long 0x00 0. "PM0OD,PM0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port M Pull-up Control Register"
|
|
bitfld.long 0x00 2. "PM2UP,PM2UP" "0,1"
|
|
bitfld.long 0x00 1. "PM1UP,PM1UP" "0,1"
|
|
bitfld.long 0x00 0. "PM0UP,PM0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port M Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PM7UP,PM7UP" "0,1"
|
|
bitfld.long 0x00 6. "PM6UP,PM6UP" "0,1"
|
|
bitfld.long 0x00 5. "PM5UP,PM5UP" "0,1"
|
|
bitfld.long 0x00 4. "PM4UP,PM4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PM3UP,PM3UP" "0,1"
|
|
bitfld.long 0x00 2. "PM2UP,PM2UP" "0,1"
|
|
bitfld.long 0x00 1. "PM1UP,PM1UP" "0,1"
|
|
bitfld.long 0x00 0. "PM0UP,PM0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port M Pull-down Control Register"
|
|
bitfld.long 0x00 2. "PM2DN,PM2DN" "0,1"
|
|
bitfld.long 0x00 1. "PM1DN,PM1DN" "0,1"
|
|
bitfld.long 0x00 0. "PM0DN,PM0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port M Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PM7DN,PM7DN" "0,1"
|
|
bitfld.long 0x00 6. "PM6DN,PM6DN" "0,1"
|
|
bitfld.long 0x00 5. "PM5DN,PM5DN" "0,1"
|
|
bitfld.long 0x00 4. "PM4DN,PM4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PM3DN,PM3DN" "0,1"
|
|
bitfld.long 0x00 2. "PM2DN,PM2DN" "0,1"
|
|
bitfld.long 0x00 1. "PM1DN,PM1DN" "0,1"
|
|
bitfld.long 0x00 0. "PM0DN,PM0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port M Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PM7DN,PM7DN" "0,1"
|
|
bitfld.long 0x00 6. "PM6DN,PM6DN" "0,1"
|
|
bitfld.long 0x00 5. "PM5DN,PM5DN" "0,1"
|
|
bitfld.long 0x00 4. "PM4DN,PM4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PM3DN,PM3DN" "0,1"
|
|
bitfld.long 0x00 2. "PM2DN,PM2DN" "0,1"
|
|
bitfld.long 0x00 1. "PM1DN,PM1DN" "0,1"
|
|
bitfld.long 0x00 0. "PM0DN,PM0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port M Input Control Register"
|
|
bitfld.long 0x00 2. "PM2IE,PM2IE" "0,1"
|
|
bitfld.long 0x00 1. "PM1IE,PM1IE" "0,1"
|
|
bitfld.long 0x00 0. "PM0IE,PM0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port M Input Control Register"
|
|
bitfld.long 0x00 7. "PM7IE,PM7IE" "0,1"
|
|
bitfld.long 0x00 6. "PM6IE,PM6IE" "0,1"
|
|
bitfld.long 0x00 5. "PM5IE,PM5IE" "0,1"
|
|
bitfld.long 0x00 4. "PM4IE,PM4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PM3IE,PM3IE" "0,1"
|
|
bitfld.long 0x00 2. "PM2IE,PM2IE" "0,1"
|
|
bitfld.long 0x00 1. "PM1IE,PM1IE" "0,1"
|
|
bitfld.long 0x00 0. "PM0IE,PM0IE" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "PN (Port N)"
|
|
base ad:0x400E0C00
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port N Data Register"
|
|
bitfld.long 0x00 7. "PN7,PN7" "0,1"
|
|
bitfld.long 0x00 6. "PN6,PN6" "0,1"
|
|
bitfld.long 0x00 5. "PN5,PN5" "0,1"
|
|
bitfld.long 0x00 4. "PN4,PN4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PN3,PN3" "0,1"
|
|
bitfld.long 0x00 2. "PN2,PN2" "0,1"
|
|
bitfld.long 0x00 1. "PN1,PN1" "0,1"
|
|
bitfld.long 0x00 0. "PN0,PN0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port N Data Register"
|
|
bitfld.long 0x00 2. "PN2,PN2" "0,1"
|
|
bitfld.long 0x00 1. "PN1,PN1" "0,1"
|
|
bitfld.long 0x00 0. "PN0,PN0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port N Output Control Register"
|
|
bitfld.long 0x00 7. "PN7C,PN7C" "0,1"
|
|
bitfld.long 0x00 6. "PN6C,PN6C" "0,1"
|
|
bitfld.long 0x00 5. "PN5C,PN5C" "0,1"
|
|
bitfld.long 0x00 4. "PN4C,PN4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PN3C,PN3C" "0,1"
|
|
bitfld.long 0x00 2. "PN2C,PN2C" "0,1"
|
|
bitfld.long 0x00 1. "PN1C,PN1C" "0,1"
|
|
bitfld.long 0x00 0. "PN0C,PN0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port N Output Control Register"
|
|
bitfld.long 0x00 2. "PN2C,PN2C" "0,1"
|
|
bitfld.long 0x00 1. "PN1C,PN1C" "0,1"
|
|
bitfld.long 0x00 0. "PN0C,PN0C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port N Function Register 1"
|
|
bitfld.long 0x00 2. "PN2F1,PN2F1" "0,1"
|
|
bitfld.long 0x00 1. "PN1F1,PN1F1" "0,1"
|
|
bitfld.long 0x00 0. "PN0F1,PN0F1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port N Function Register 2"
|
|
bitfld.long 0x00 1. "PN1F2,PN1F2" "0,1"
|
|
bitfld.long 0x00 0. "PN0F2,PN0F2" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port N Function Register 3"
|
|
bitfld.long 0x00 1. "PN1F3,PN1F3" "0,1"
|
|
bitfld.long 0x00 0. "PN0F3,PN0F3" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port N Function Register 4"
|
|
bitfld.long 0x00 2. "PN2F4,PN2F4" "0,1"
|
|
bitfld.long 0x00 1. "PN1F4,PN1F4" "0,1"
|
|
bitfld.long 0x00 0. "PN0F4,PN0F4" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port N Function Register 5"
|
|
bitfld.long 0x00 2. "PN2F5,PN2F5" "0,1"
|
|
bitfld.long 0x00 1. "PN1F5,PN1F5" "0,1"
|
|
bitfld.long 0x00 0. "PN0F5,PN0F5" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port N Function Register 6"
|
|
bitfld.long 0x00 2. "PN2F6,PN2F6" "0,1"
|
|
bitfld.long 0x00 1. "PN1F6,PN1F6" "0,1"
|
|
bitfld.long 0x00 0. "PN0F6,PN0F6" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port N Function Register 7"
|
|
bitfld.long 0x00 1. "PN1F7,PN1F7" "0,1"
|
|
bitfld.long 0x00 0. "PN0F7,PN0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port N Opend Drain Control Register"
|
|
bitfld.long 0x00 7. "PN7OD,PN7OD" "0,1"
|
|
bitfld.long 0x00 6. "PN6OD,PN6OD" "0,1"
|
|
bitfld.long 0x00 5. "PN5OD,PN5OD" "0,1"
|
|
bitfld.long 0x00 4. "PN4OD,PN4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PN3OD,PN3OD" "0,1"
|
|
bitfld.long 0x00 2. "PN2OD,PN2OD" "0,1"
|
|
bitfld.long 0x00 1. "PN1OD,PN1OD" "0,1"
|
|
bitfld.long 0x00 0. "PN0OD,PN0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port N Opend Drain Control Register"
|
|
bitfld.long 0x00 2. "PN2OD,PN2OD" "0,1"
|
|
bitfld.long 0x00 1. "PN1OD,PN1OD" "0,1"
|
|
bitfld.long 0x00 0. "PN0OD,PN0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port N Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PN7UP,PN7UP" "0,1"
|
|
bitfld.long 0x00 6. "PN6UP,PN6UP" "0,1"
|
|
bitfld.long 0x00 5. "PN5UP,PN5UP" "0,1"
|
|
bitfld.long 0x00 4. "PN4UP,PN4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PN3UP,PN3UP" "0,1"
|
|
bitfld.long 0x00 2. "PN2UP,PN2UP" "0,1"
|
|
bitfld.long 0x00 1. "PN1UP,PN1UP" "0,1"
|
|
bitfld.long 0x00 0. "PN0UP,PN0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port N Pull-up Control Register"
|
|
bitfld.long 0x00 2. "PN2UP,PN2UP" "0,1"
|
|
bitfld.long 0x00 1. "PN1UP,PN1UP" "0,1"
|
|
bitfld.long 0x00 0. "PN0UP,PN0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port N Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PN7DN,PN7DN" "0,1"
|
|
bitfld.long 0x00 6. "PN6DN,PN6DN" "0,1"
|
|
bitfld.long 0x00 5. "PN5DN,PN5DN" "0,1"
|
|
bitfld.long 0x00 4. "PN4DN,PN4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PN3DN,PN3DN" "0,1"
|
|
bitfld.long 0x00 2. "PN2DN,PN2DN" "0,1"
|
|
bitfld.long 0x00 1. "PN1DN,PN1DN" "0,1"
|
|
bitfld.long 0x00 0. "PN0DN,PN0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port N Pull-down Control Register"
|
|
bitfld.long 0x00 2. "PN2DN,PN2DN" "0,1"
|
|
bitfld.long 0x00 1. "PN1DN,PN1DN" "0,1"
|
|
bitfld.long 0x00 0. "PN0DN,PN0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port N Input Control Register"
|
|
bitfld.long 0x00 7. "PN7IE,PN7IE" "0,1"
|
|
bitfld.long 0x00 6. "PN6IE,PN6IE" "0,1"
|
|
bitfld.long 0x00 5. "PN5IE,PN5IE" "0,1"
|
|
bitfld.long 0x00 4. "PN4IE,PN4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PN3IE,PN3IE" "0,1"
|
|
bitfld.long 0x00 2. "PN2IE,PN2IE" "0,1"
|
|
bitfld.long 0x00 1. "PN1IE,PN1IE" "0,1"
|
|
bitfld.long 0x00 0. "PN0IE,PN0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port N Input Control Register"
|
|
bitfld.long 0x00 2. "PN2IE,PN2IE" "0,1"
|
|
bitfld.long 0x00 1. "PN1IE,PN1IE" "0,1"
|
|
bitfld.long 0x00 0. "PN0IE,PN0IE" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "PP (Port P)"
|
|
base ad:0x400E0D00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port P Data Register"
|
|
bitfld.long 0x00 7. "PP7,PP7" "0,1"
|
|
bitfld.long 0x00 6. "PP6,PP6" "0,1"
|
|
bitfld.long 0x00 5. "PP5,PP5" "0,1"
|
|
bitfld.long 0x00 4. "PP4,PP4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PP3,PP3" "0,1"
|
|
bitfld.long 0x00 2. "PP2,PP2" "0,1"
|
|
bitfld.long 0x00 1. "PP1,PP1" "0,1"
|
|
bitfld.long 0x00 0. "PP0,PP0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port P Output Control Register"
|
|
bitfld.long 0x00 7. "PP7C,PP7C" "0,1"
|
|
bitfld.long 0x00 6. "PP6C,PP6C" "0,1"
|
|
bitfld.long 0x00 5. "PP5C,PP5C" "0,1"
|
|
bitfld.long 0x00 4. "PP4C,PP4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PP3C,PP3C" "0,1"
|
|
bitfld.long 0x00 2. "PP2C,PP2C" "0,1"
|
|
bitfld.long 0x00 1. "PP1C,PP1C" "0,1"
|
|
bitfld.long 0x00 0. "PP0C,PP0C" "0,1"
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port P Function Register 1"
|
|
bitfld.long 0x00 7. "PP7F1,PP7F1" "0,1"
|
|
bitfld.long 0x00 6. "PP6F1,PP6F1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port P Function Register 2"
|
|
bitfld.long 0x00 7. "PP7F2,PP7F2" "0,1"
|
|
bitfld.long 0x00 6. "PP6F2,PP6F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port P Function Register 2"
|
|
bitfld.long 0x00 7. "PP7FR2,PP7FR2" "0,1"
|
|
bitfld.long 0x00 6. "PP6FR2,PP6FR2" "0,1"
|
|
bitfld.long 0x00 5. "PP5FR2,PP5FR2" "0,1"
|
|
bitfld.long 0x00 4. "PP4FR2,PP4FR2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PP3FR2,PP3FR2" "0,1"
|
|
bitfld.long 0x00 2. "PP2FR2,PP2FR2" "0,1"
|
|
bitfld.long 0x00 1. "PP1FR2,PP1FR2" "0,1"
|
|
bitfld.long 0x00 0. "PP0FR2,PP0FR2" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port P Function Register 3"
|
|
bitfld.long 0x00 7. "PP7FR3,PP7FR3" "0,1"
|
|
bitfld.long 0x00 6. "PP6FR3,PP6FR3" "0,1"
|
|
bitfld.long 0x00 5. "PP5FR3,PP5FR3" "0,1"
|
|
bitfld.long 0x00 4. "PP4FR3,PP4FR3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PP3FR3,PP3FR3" "0,1"
|
|
bitfld.long 0x00 2. "PP2FR3,PP2FR3" "0,1"
|
|
bitfld.long 0x00 1. "PP1FR3,PP1FR3" "0,1"
|
|
bitfld.long 0x00 0. "PP0FR3,PP0FR3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port P Function Register 4"
|
|
bitfld.long 0x00 5. "PP5F4,PP5F4" "0,1"
|
|
bitfld.long 0x00 4. "PP4F4,PP4F4" "0,1"
|
|
bitfld.long 0x00 3. "PP3F4,PP3F4" "0,1"
|
|
bitfld.long 0x00 2. "PP2F4,PP2F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PP1F4,PP1F4" "0,1"
|
|
bitfld.long 0x00 0. "PP0F4,PP0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port P Function Register 5"
|
|
bitfld.long 0x00 7. "PP7FR5,PP7FR5" "0,1"
|
|
bitfld.long 0x00 6. "PP6FR5,PP6FR5" "0,1"
|
|
bitfld.long 0x00 5. "PP5FR5,PP5FR5" "0,1"
|
|
bitfld.long 0x00 4. "PP4FR5,PP4FR5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PP3FR5,PP3FR5" "0,1"
|
|
bitfld.long 0x00 2. "PP2FR5,PP2FR5" "0,1"
|
|
bitfld.long 0x00 1. "PP1FR5,PP1FR5" "0,1"
|
|
bitfld.long 0x00 0. "PP0FR5,PP0FR5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port P Function Register 5"
|
|
bitfld.long 0x00 5. "PP5F5,PP5F5" "0,1"
|
|
bitfld.long 0x00 4. "PP4F5,PP4F5" "0,1"
|
|
bitfld.long 0x00 3. "PP3F5,PP3F5" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port P Function Register 6"
|
|
bitfld.long 0x00 5. "PP5F6,PP5F6" "0,1"
|
|
bitfld.long 0x00 4. "PP4F6,PP4F6" "0,1"
|
|
bitfld.long 0x00 3. "PP3F6,PP3F6" "0,1"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port P Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PP7OD,PP7OD" "0,1"
|
|
bitfld.long 0x00 6. "PP6OD,PP6OD" "0,1"
|
|
bitfld.long 0x00 5. "PP5OD,PP5OD" "0,1"
|
|
bitfld.long 0x00 4. "PP4OD,PP4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PP3OD,PP3OD" "0,1"
|
|
bitfld.long 0x00 2. "PP2OD,PP2OD" "0,1"
|
|
bitfld.long 0x00 1. "PP1OD,PP1OD" "0,1"
|
|
bitfld.long 0x00 0. "PP0OD,PP0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port P Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PP7UP,PP7UP" "0,1"
|
|
bitfld.long 0x00 6. "PP6UP,PP6UP" "0,1"
|
|
bitfld.long 0x00 5. "PP5UP,PP5UP" "0,1"
|
|
bitfld.long 0x00 4. "PP4UP,PP4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PP3UP,PP3UP" "0,1"
|
|
bitfld.long 0x00 2. "PP2UP,PP2UP" "0,1"
|
|
bitfld.long 0x00 1. "PP1UP,PP1UP" "0,1"
|
|
bitfld.long 0x00 0. "PP0UP,PP0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port P Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PP7DN,PP7DN" "0,1"
|
|
bitfld.long 0x00 6. "PP6DN,PP6DN" "0,1"
|
|
bitfld.long 0x00 5. "PP5DN,PP5DN" "0,1"
|
|
bitfld.long 0x00 4. "PP4DN,PP4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PP3DN,PP3DN" "0,1"
|
|
bitfld.long 0x00 2. "PP2DN,PP2DN" "0,1"
|
|
bitfld.long 0x00 1. "PP1DN,PP1DN" "0,1"
|
|
bitfld.long 0x00 0. "PP0DN,PP0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port P Input Control Register"
|
|
bitfld.long 0x00 7. "PP7IE,PP7IE" "0,1"
|
|
bitfld.long 0x00 6. "PP6IE,PP6IE" "0,1"
|
|
bitfld.long 0x00 5. "PP5IE,PP5IE" "0,1"
|
|
bitfld.long 0x00 4. "PP4IE,PP4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PP3IE,PP3IE" "0,1"
|
|
bitfld.long 0x00 2. "PP2IE,PP2IE" "0,1"
|
|
bitfld.long 0x00 1. "PP1IE,PP1IE" "0,1"
|
|
bitfld.long 0x00 0. "PP0IE,PP0IE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4KQ*")
|
|
tree "PR (Port R)"
|
|
base ad:0x400E0E00
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port R Data Register"
|
|
bitfld.long 0x00 7. "PR7,PR7" "0,1"
|
|
bitfld.long 0x00 6. "PR6,PR6" "0,1"
|
|
bitfld.long 0x00 5. "PR5,PR5" "0,1"
|
|
bitfld.long 0x00 4. "PR4,PR4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PR3,PR3" "0,1"
|
|
bitfld.long 0x00 2. "PR2,PR2" "0,1"
|
|
bitfld.long 0x00 1. "PR1,PR1" "0,1"
|
|
bitfld.long 0x00 0. "PR0,PR0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port R Data Register"
|
|
bitfld.long 0x00 3. "PR3,PR3" "0,1"
|
|
bitfld.long 0x00 2. "PR2,PR2" "0,1"
|
|
bitfld.long 0x00 1. "PR1,PR1" "0,1"
|
|
bitfld.long 0x00 0. "PR0,PR0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port R Output Control Register"
|
|
bitfld.long 0x00 3. "PR3C,PR3C" "0,1"
|
|
bitfld.long 0x00 2. "PR2C,PR2C" "0,1"
|
|
bitfld.long 0x00 1. "PR1C,PR1C" "0,1"
|
|
bitfld.long 0x00 0. "PR0C,PR0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port R Output Control Register"
|
|
bitfld.long 0x00 7. "PR7C,PR7C" "0,1"
|
|
bitfld.long 0x00 6. "PR6C,PR6C" "0,1"
|
|
bitfld.long 0x00 5. "PR5C,PR5C" "0,1"
|
|
bitfld.long 0x00 4. "PR4C,PR4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PR3C,PR3C" "0,1"
|
|
bitfld.long 0x00 2. "PR2C,PR2C" "0,1"
|
|
bitfld.long 0x00 1. "PR1C,PR1C" "0,1"
|
|
bitfld.long 0x00 0. "PR0C,PR0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KQ*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port R Function Register 1"
|
|
bitfld.long 0x00 4. "PR4F1,PR4F1" "0,1"
|
|
bitfld.long 0x00 3. "PR3F1,PR3F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port R Function Register 2"
|
|
bitfld.long 0x00 3. "PR3FR2,PR3FR2" "0,1"
|
|
bitfld.long 0x00 2. "PR2FR2,PR2FR2" "0,1"
|
|
bitfld.long 0x00 1. "PR1FR2,PR1FR2" "0,1"
|
|
bitfld.long 0x00 0. "PR0FR2,PR0FR2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port R Function Register 2"
|
|
bitfld.long 0x00 7. "PR7FR2,PR7FR2" "0,1"
|
|
bitfld.long 0x00 6. "PR6FR2,PR6FR2" "0,1"
|
|
bitfld.long 0x00 5. "PR5FR2,PR5FR2" "0,1"
|
|
bitfld.long 0x00 4. "PR4FR2,PR4FR2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PR3FR2,PR3FR2" "0,1"
|
|
bitfld.long 0x00 2. "PR2FR2,PR2FR2" "0,1"
|
|
bitfld.long 0x00 1. "PR1FR2,PR1FR2" "0,1"
|
|
bitfld.long 0x00 0. "PR0FR2,PR0FR2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port R Function Register 3"
|
|
bitfld.long 0x00 3. "PR3FR3,PR3FR3" "0,1"
|
|
bitfld.long 0x00 2. "PR2FR3,PR2FR3" "0,1"
|
|
bitfld.long 0x00 1. "PR1FR3,PR1FR3" "0,1"
|
|
bitfld.long 0x00 0. "PR0FR3,PR0FR3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port R Function Register 3"
|
|
bitfld.long 0x00 7. "PR7FR3,PR7FR3" "0,1"
|
|
bitfld.long 0x00 6. "PR6FR3,PR6FR3" "0,1"
|
|
bitfld.long 0x00 5. "PR5FR3,PR5FR3" "0,1"
|
|
bitfld.long 0x00 4. "PR4FR3,PR4FR3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PR3FR3,PR3FR3" "0,1"
|
|
bitfld.long 0x00 2. "PR2FR3,PR2FR3" "0,1"
|
|
bitfld.long 0x00 1. "PR1FR3,PR1FR3" "0,1"
|
|
bitfld.long 0x00 0. "PR0FR3,PR0FR3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port R Function Register 4"
|
|
bitfld.long 0x00 7. "PR7F4,PR7F4" "0,1"
|
|
bitfld.long 0x00 6. "PR6F4,PR6F4" "0,1"
|
|
bitfld.long 0x00 5. "PR5F4,PR5F4" "0,1"
|
|
bitfld.long 0x00 2. "PR2F4,PR2F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PR1F4,PR1F4" "0,1"
|
|
bitfld.long 0x00 0. "PR0F4,PR0F4" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port R Function Register 5"
|
|
bitfld.long 0x00 5. "PR5F5,PR5F5" "0,1"
|
|
bitfld.long 0x00 4. "PR4F5,PR4F5" "0,1"
|
|
bitfld.long 0x00 3. "PR3F5,PR3F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port R Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PR7OD,PR7OD" "0,1"
|
|
bitfld.long 0x00 6. "PR6OD,PR6OD" "0,1"
|
|
bitfld.long 0x00 5. "PR5OD,PR5OD" "0,1"
|
|
bitfld.long 0x00 4. "PR4OD,PR4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PR3OD,PR3OD" "0,1"
|
|
bitfld.long 0x00 2. "PR2OD,PR2OD" "0,1"
|
|
bitfld.long 0x00 1. "PR1OD,PR1OD" "0,1"
|
|
bitfld.long 0x00 0. "PR0OD,PR0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port R Open Drain Control Register"
|
|
bitfld.long 0x00 3. "PR3OD,PR3OD" "0,1"
|
|
bitfld.long 0x00 2. "PR2OD,PR2OD" "0,1"
|
|
bitfld.long 0x00 1. "PR1OD,PR1OD" "0,1"
|
|
bitfld.long 0x00 0. "PR0OD,PR0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port R Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PR7UP,PR7UP" "0,1"
|
|
bitfld.long 0x00 6. "PR6UP,PR6UP" "0,1"
|
|
bitfld.long 0x00 5. "PR5UP,PR5UP" "0,1"
|
|
bitfld.long 0x00 4. "PR4UP,PR4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PR3UP,PR3UP" "0,1"
|
|
bitfld.long 0x00 2. "PR2UP,PR2UP" "0,1"
|
|
bitfld.long 0x00 1. "PR1UP,PR1UP" "0,1"
|
|
bitfld.long 0x00 0. "PR0UP,PR0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port R Pull-up Control Register"
|
|
bitfld.long 0x00 3. "PR3UP,PR3UP" "0,1"
|
|
bitfld.long 0x00 2. "PR2UP,PR2UP" "0,1"
|
|
bitfld.long 0x00 1. "PR1UP,PR1UP" "0,1"
|
|
bitfld.long 0x00 0. "PR0UP,PR0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port R Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PR7DN,PR7DN" "0,1"
|
|
bitfld.long 0x00 6. "PR6DN,PR6DN" "0,1"
|
|
bitfld.long 0x00 5. "PR5DN,PR5DN" "0,1"
|
|
bitfld.long 0x00 4. "PR4DN,PR4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PR3DN,PR3DN" "0,1"
|
|
bitfld.long 0x00 2. "PR2DN,PR2DN" "0,1"
|
|
bitfld.long 0x00 1. "PR1DN,PR1DN" "0,1"
|
|
bitfld.long 0x00 0. "PR0DN,PR0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port R Pull-down Control Register"
|
|
bitfld.long 0x00 3. "PR3DN,PR3DN" "0,1"
|
|
bitfld.long 0x00 2. "PR2DN,PR2DN" "0,1"
|
|
bitfld.long 0x00 1. "PR1DN,PR1DN" "0,1"
|
|
bitfld.long 0x00 0. "PR0DN,PR0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port R Input Control Register"
|
|
bitfld.long 0x00 3. "PR3IE,PR3IE" "0,1"
|
|
bitfld.long 0x00 2. "PR2IE,PR2IE" "0,1"
|
|
bitfld.long 0x00 1. "PR1IE,PR1IE" "0,1"
|
|
bitfld.long 0x00 0. "PR0IE,PR0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4KQ*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port R Input Control Register"
|
|
bitfld.long 0x00 7. "PR7IE,PR7IE" "0,1"
|
|
bitfld.long 0x00 6. "PR6IE,PR6IE" "0,1"
|
|
bitfld.long 0x00 5. "PR5IE,PR5IE" "0,1"
|
|
bitfld.long 0x00 4. "PR4IE,PR4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PR3IE,PR3IE" "0,1"
|
|
bitfld.long 0x00 2. "PR2IE,PR2IE" "0,1"
|
|
bitfld.long 0x00 1. "PR1IE,PR1IE" "0,1"
|
|
bitfld.long 0x00 0. "PR0IE,PR0IE" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "PT (Port T)"
|
|
base ad:0x400E0F00
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port T Data Register"
|
|
bitfld.long 0x00 5. "PT5,PT5" "0,1"
|
|
bitfld.long 0x00 4. "PT4,PT4" "0,1"
|
|
bitfld.long 0x00 3. "PT3,PT3" "0,1"
|
|
bitfld.long 0x00 2. "PT2,PT2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PT1,PT1" "0,1"
|
|
bitfld.long 0x00 0. "PT0,PT0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port T Data Register"
|
|
bitfld.long 0x00 3. "PT3,PT3" "0,1"
|
|
bitfld.long 0x00 2. "PT2,PT2" "0,1"
|
|
bitfld.long 0x00 1. "PT1,PT1" "0,1"
|
|
bitfld.long 0x00 0. "PT0,PT0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port T Data Register"
|
|
bitfld.long 0x00 7. "PT7,PT7" "0,1"
|
|
bitfld.long 0x00 6. "PT6,PT6" "0,1"
|
|
bitfld.long 0x00 5. "PT5,PT5" "0,1"
|
|
bitfld.long 0x00 4. "PT4,PT4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PT3,PT3" "0,1"
|
|
bitfld.long 0x00 2. "PT2,PT2" "0,1"
|
|
bitfld.long 0x00 1. "PT1,PT1" "0,1"
|
|
bitfld.long 0x00 0. "PT0,PT0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port T Output Control Register"
|
|
bitfld.long 0x00 3. "PT3C,PT3C" "0,1"
|
|
bitfld.long 0x00 2. "PT2C,PT2C" "0,1"
|
|
bitfld.long 0x00 1. "PT1C,PT1C" "0,1"
|
|
bitfld.long 0x00 0. "PT0C,PT0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port T Output Control Register"
|
|
bitfld.long 0x00 5. "PT5C,PT5C" "0,1"
|
|
bitfld.long 0x00 4. "PT4C,PT4C" "0,1"
|
|
bitfld.long 0x00 3. "PT3C,PT3C" "0,1"
|
|
bitfld.long 0x00 2. "PT2C,PT2C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PT1C,PT1C" "0,1"
|
|
bitfld.long 0x00 0. "PT0C,PT0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port T Output Control Register"
|
|
bitfld.long 0x00 7. "PT7C,PT7C" "0,1"
|
|
bitfld.long 0x00 6. "PT6C,PT6C" "0,1"
|
|
bitfld.long 0x00 5. "PT5C,PT5C" "0,1"
|
|
bitfld.long 0x00 4. "PT4C,PT4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PT3C,PT3C" "0,1"
|
|
bitfld.long 0x00 2. "PT2C,PT2C" "0,1"
|
|
bitfld.long 0x00 1. "PT1C,PT1C" "0,1"
|
|
bitfld.long 0x00 0. "PT0C,PT0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port T Function Register 1"
|
|
bitfld.long 0x00 3. "PT3FR1,PT3FR1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port T Function Register 1"
|
|
bitfld.long 0x00 7. "PT7F1,PT7F1" "0,1"
|
|
bitfld.long 0x00 6. "PT6F1,PT6F1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port T Function Register 2"
|
|
bitfld.long 0x00 1. "PT1F2,PT1F2" "0,1"
|
|
bitfld.long 0x00 0. "PT0F2,PT0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port T Function Register 2"
|
|
bitfld.long 0x00 3. "PT3FR2,PT3FR2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port T Function Register 2"
|
|
bitfld.long 0x00 5. "PT5FR2,PT5FR2" "0,1"
|
|
bitfld.long 0x00 3. "PT3FR2,PT3FR2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port T Function Register 3"
|
|
bitfld.long 0x00 3. "PT3FR3,PT3FR3" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port T Function Register 4"
|
|
bitfld.long 0x00 4. "PT4FR4,PT4FR4" "0,1"
|
|
bitfld.long 0x00 3. "PT3FR4,PT3FR4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port T Function Register 4"
|
|
bitfld.long 0x00 5. "PT5F4,PT5F4" "0,1"
|
|
bitfld.long 0x00 4. "PT4F4,PT4F4" "0,1"
|
|
bitfld.long 0x00 3. "PT3F4,PT3F4" "0,1"
|
|
bitfld.long 0x00 2. "PT2F4,PT2F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PT1F4,PT1F4" "0,1"
|
|
bitfld.long 0x00 0. "PT0F4,PT0F4" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port T Function Register 5"
|
|
bitfld.long 0x00 2. "PT2F5,PT2F5" "0,1"
|
|
bitfld.long 0x00 1. "PT1F5,PT1F5" "0,1"
|
|
bitfld.long 0x00 0. "PT0F5,PT0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port T Function Register 6"
|
|
bitfld.long 0x00 3. "PT3FR6,PT3FR6" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port T Function Register 7"
|
|
bitfld.long 0x00 2. "PT2FR7,PT2FR7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port T Open Drain Control Register"
|
|
bitfld.long 0x00 3. "PT3OD,PT3OD" "0,1"
|
|
bitfld.long 0x00 2. "PT2OD,PT2OD" "0,1"
|
|
bitfld.long 0x00 1. "PT1OD,PT1OD" "0,1"
|
|
bitfld.long 0x00 0. "PT0OD,PT0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port T Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PT7OD,PT7OD" "0,1"
|
|
bitfld.long 0x00 6. "PT6OD,PT6OD" "0,1"
|
|
bitfld.long 0x00 5. "PT5OD,PT5OD" "0,1"
|
|
bitfld.long 0x00 4. "PT4OD,PT4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PT3OD,PT3OD" "0,1"
|
|
bitfld.long 0x00 2. "PT2OD,PT2OD" "0,1"
|
|
bitfld.long 0x00 1. "PT1OD,PT1OD" "0,1"
|
|
bitfld.long 0x00 0. "PT0OD,PT0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port T Open Drain Control Register"
|
|
bitfld.long 0x00 5. "PT5OD,PT5OD" "0,1"
|
|
bitfld.long 0x00 4. "PT4OD,PT4OD" "0,1"
|
|
bitfld.long 0x00 3. "PT3OD,PT3OD" "0,1"
|
|
bitfld.long 0x00 2. "PT2OD,PT2OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PT1OD,PT1OD" "0,1"
|
|
bitfld.long 0x00 0. "PT0OD,PT0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port T Pull-up Control Register"
|
|
bitfld.long 0x00 3. "PT3UP,PT3UP" "0,1"
|
|
bitfld.long 0x00 2. "PT2UP,PT2UP" "0,1"
|
|
bitfld.long 0x00 1. "PT1UP,PT1UP" "0,1"
|
|
bitfld.long 0x00 0. "PT0UP,PT0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port T Pull-up Control Register"
|
|
bitfld.long 0x00 5. "PT5UP,PT5UP" "0,1"
|
|
bitfld.long 0x00 4. "PT4UP,PT4UP" "0,1"
|
|
bitfld.long 0x00 3. "PT3UP,PT3UP" "0,1"
|
|
bitfld.long 0x00 2. "PT2UP,PT2UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PT1UP,PT1UP" "0,1"
|
|
bitfld.long 0x00 0. "PT0UP,PT0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port T Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PT7UP,PT7UP" "0,1"
|
|
bitfld.long 0x00 6. "PT6UP,PT6UP" "0,1"
|
|
bitfld.long 0x00 5. "PT5UP,PT5UP" "0,1"
|
|
bitfld.long 0x00 4. "PT4UP,PT4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PT3UP,PT3UP" "0,1"
|
|
bitfld.long 0x00 2. "PT2UP,PT2UP" "0,1"
|
|
bitfld.long 0x00 1. "PT1UP,PT1UP" "0,1"
|
|
bitfld.long 0x00 0. "PT0UP,PT0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port T Pull-down Control Register"
|
|
bitfld.long 0x00 5. "PT5DN,PT5DN" "0,1"
|
|
bitfld.long 0x00 4. "PT4DN,PT4DN" "0,1"
|
|
bitfld.long 0x00 3. "PT3DN,PT3DN" "0,1"
|
|
bitfld.long 0x00 2. "PT2DN,PT2DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PT1DN,PT1DN" "0,1"
|
|
bitfld.long 0x00 0. "PT0DN,PT0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port T Pull-down Control Register"
|
|
bitfld.long 0x00 3. "PT3DN,PT3DN" "0,1"
|
|
bitfld.long 0x00 2. "PT2DN,PT2DN" "0,1"
|
|
bitfld.long 0x00 1. "PT1DN,PT1DN" "0,1"
|
|
bitfld.long 0x00 0. "PT0DN,PT0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port T Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PT7DN,PT7DN" "0,1"
|
|
bitfld.long 0x00 6. "PT6DN,PT6DN" "0,1"
|
|
bitfld.long 0x00 5. "PT5DN,PT5DN" "0,1"
|
|
bitfld.long 0x00 4. "PT4DN,PT4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PT3DN,PT3DN" "0,1"
|
|
bitfld.long 0x00 2. "PT2DN,PT2DN" "0,1"
|
|
bitfld.long 0x00 1. "PT1DN,PT1DN" "0,1"
|
|
bitfld.long 0x00 0. "PT0DN,PT0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port T Input Control Register"
|
|
bitfld.long 0x00 3. "PT3IE,PT3IE" "0,1"
|
|
bitfld.long 0x00 2. "PT2IE,PT2IE" "0,1"
|
|
bitfld.long 0x00 1. "PT1IE,PT1IE" "0,1"
|
|
bitfld.long 0x00 0. "PT0IE,PT0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port T Input Control Register"
|
|
bitfld.long 0x00 5. "PT5IE,PT5IE" "0,1"
|
|
bitfld.long 0x00 4. "PT4IE,PT4IE" "0,1"
|
|
bitfld.long 0x00 3. "PT3IE,PT3IE" "0,1"
|
|
bitfld.long 0x00 2. "PT2IE,PT2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PT1IE,PT1IE" "0,1"
|
|
bitfld.long 0x00 0. "PT0IE,PT0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port T Input Control Register"
|
|
bitfld.long 0x00 7. "PT7IE,PT7IE" "0,1"
|
|
bitfld.long 0x00 6. "PT6IE,PT6IE" "0,1"
|
|
bitfld.long 0x00 5. "PT5IE,PT5IE" "0,1"
|
|
bitfld.long 0x00 4. "PT4IE,PT4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PT3IE,PT3IE" "0,1"
|
|
bitfld.long 0x00 2. "PT2IE,PT2IE" "0,1"
|
|
bitfld.long 0x00 1. "PT1IE,PT1IE" "0,1"
|
|
bitfld.long 0x00 0. "PT0IE,PT0IE" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "PU (Port U)"
|
|
base ad:0x400E1000
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port U Data Register"
|
|
bitfld.long 0x00 7. "PU7,PU7" "0,1"
|
|
bitfld.long 0x00 6. "PU6,PU6" "0,1"
|
|
bitfld.long 0x00 5. "PU5,PU5" "0,1"
|
|
bitfld.long 0x00 4. "PU4,PU4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PU3,PU3" "0,1"
|
|
bitfld.long 0x00 2. "PU2,PU2" "0,1"
|
|
bitfld.long 0x00 1. "PU1,PU1" "0,1"
|
|
bitfld.long 0x00 0. "PU0,PU0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port U Data Register"
|
|
bitfld.long 0x00 6. "PU6,PU6" "0,1"
|
|
bitfld.long 0x00 5. "PU5,PU5" "0,1"
|
|
bitfld.long 0x00 4. "PU4,PU4" "0,1"
|
|
bitfld.long 0x00 3. "PU3,PU3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PU2,PU2" "0,1"
|
|
bitfld.long 0x00 1. "PU1,PU1" "0,1"
|
|
bitfld.long 0x00 0. "PU0,PU0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port U Output Control Register"
|
|
bitfld.long 0x00 7. "PU7C,PU7C" "0,1"
|
|
bitfld.long 0x00 6. "PU6C,PU6C" "0,1"
|
|
bitfld.long 0x00 5. "PU5C,PU5C" "0,1"
|
|
bitfld.long 0x00 4. "PU4C,PU4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PU3C,PU3C" "0,1"
|
|
bitfld.long 0x00 2. "PU2C,PU2C" "0,1"
|
|
bitfld.long 0x00 1. "PU1C,PU1C" "0,1"
|
|
bitfld.long 0x00 0. "PU0C,PU0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port U Output Control Register"
|
|
bitfld.long 0x00 6. "PU6C,PU6C" "0,1"
|
|
bitfld.long 0x00 5. "PU5C,PU5C" "0,1"
|
|
bitfld.long 0x00 4. "PU4C,PU4C" "0,1"
|
|
bitfld.long 0x00 3. "PU3C,PU3C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PU2C,PU2C" "0,1"
|
|
bitfld.long 0x00 1. "PU1C,PU1C" "0,1"
|
|
bitfld.long 0x00 0. "PU0C,PU0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port U Function Register 1"
|
|
bitfld.long 0x00 6. "PU6F1,PU6F1" "0,1"
|
|
bitfld.long 0x00 5. "PU5F1,PU5F1" "0,1"
|
|
bitfld.long 0x00 4. "PU4F1,PU4F1" "0,1"
|
|
bitfld.long 0x00 3. "PU3F1,PU3F1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PU1F1,PU1F1" "0,1"
|
|
bitfld.long 0x00 0. "PU0F1,PU0F1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port U Function Register 2"
|
|
bitfld.long 0x00 6. "PU6F2,PU6F2" "0,1"
|
|
bitfld.long 0x00 5. "PU5F2,PU5F2" "0,1"
|
|
bitfld.long 0x00 1. "PU1F2,PU1F2" "0,1"
|
|
bitfld.long 0x00 0. "PU0F2,PU0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port U Function Register 2"
|
|
bitfld.long 0x00 7. "PU7F2,PU7F2" "0,1"
|
|
bitfld.long 0x00 6. "PU6F2,PU6F2" "0,1"
|
|
bitfld.long 0x00 5. "PU5F2,PU5F2" "0,1"
|
|
bitfld.long 0x00 4. "PU4F2,PU4F2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PU3F2,PU3F2" "0,1"
|
|
bitfld.long 0x00 2. "PU2F2,PU2F2" "0,1"
|
|
bitfld.long 0x00 1. "PU1F2,PU1F2" "0,1"
|
|
bitfld.long 0x00 0. "PU0F2,PU0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port U Function Register 3"
|
|
bitfld.long 0x00 1. "PU1F3,PU1F3" "0,1"
|
|
bitfld.long 0x00 0. "PU0F3,PU0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port U Function Register 3"
|
|
bitfld.long 0x00 6. "PU6F3,PU6F3" "0,1"
|
|
bitfld.long 0x00 5. "PU5F3,PU5F3" "0,1"
|
|
bitfld.long 0x00 4. "PU4F3,PU4F3" "0,1"
|
|
bitfld.long 0x00 3. "PU3F3,PU3F3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PU2F3,PU2F3" "0,1"
|
|
bitfld.long 0x00 0. "PU0F3,PU0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port U Function Register 4"
|
|
bitfld.long 0x00 5. "PU5F4,PU5F4" "0,1"
|
|
bitfld.long 0x00 4. "PU4F4,PU4F4" "0,1"
|
|
bitfld.long 0x00 3. "PU3F4,PU3F4" "0,1"
|
|
bitfld.long 0x00 2. "PU2F4,PU2F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PU1F4,PU1F4" "0,1"
|
|
bitfld.long 0x00 0. "PU0F4,PU0F4" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port U Function Register 5"
|
|
bitfld.long 0x00 6. "PU6F5,PU6F5" "0,1"
|
|
bitfld.long 0x00 5. "PU5F5,PU5F5" "0,1"
|
|
bitfld.long 0x00 4. "PU4F5,PU4F5" "0,1"
|
|
bitfld.long 0x00 3. "PU3F5,PU3F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PU2F5,PU2F5" "0,1"
|
|
bitfld.long 0x00 1. "PU1F5,PU1F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port U Function Register 6"
|
|
bitfld.long 0x00 6. "PU6F6,PU6F6" "0,1"
|
|
bitfld.long 0x00 5. "PU5F6,PU5F6" "0,1"
|
|
bitfld.long 0x00 4. "PU4F6,PU4F6" "0,1"
|
|
bitfld.long 0x00 3. "PU3F6,PU3F6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PU2F6,PU2F6" "0,1"
|
|
bitfld.long 0x00 1. "PU1F6,PU1F6" "0,1"
|
|
bitfld.long 0x00 0. "PU0F6,PU0F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port U Function Register 6"
|
|
bitfld.long 0x00 7. "PU7F6,PU7F6" "0,1"
|
|
bitfld.long 0x00 6. "PU6F6,PU6F6" "0,1"
|
|
bitfld.long 0x00 5. "PU5F6,PU5F6" "0,1"
|
|
bitfld.long 0x00 4. "PU4F6,PU4F6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PU3F6,PU3F6" "0,1"
|
|
bitfld.long 0x00 2. "PU2F6,PU2F6" "0,1"
|
|
bitfld.long 0x00 1. "PU1F6,PU1F6" "0,1"
|
|
bitfld.long 0x00 0. "PU0F6,PU0F6" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port U Function Register 7"
|
|
bitfld.long 0x00 7. "PU7F7,PU7F7" "0,1"
|
|
bitfld.long 0x00 6. "PU6F7,PU6F7" "0,1"
|
|
bitfld.long 0x00 5. "PU5F7,PU5F7" "0,1"
|
|
bitfld.long 0x00 4. "PU4F7,PU4F7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PU3F7,PU3F7" "0,1"
|
|
bitfld.long 0x00 2. "PU2F7,PU2F7" "0,1"
|
|
bitfld.long 0x00 1. "PU1F7,PU1F7" "0,1"
|
|
bitfld.long 0x00 0. "PU0F7,PU0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port U Function Register 7"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port U Function Register 7"
|
|
bitfld.long 0x00 7. "PU7F7,PU7F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port U Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PU7OD,PU7OD" "0,1"
|
|
bitfld.long 0x00 6. "PU6OD,PU6OD" "0,1"
|
|
bitfld.long 0x00 5. "PU5OD,PU5OD" "0,1"
|
|
bitfld.long 0x00 4. "PU4OD,PU4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PU3OD,PU3OD" "0,1"
|
|
bitfld.long 0x00 2. "PU2OD,PU2OD" "0,1"
|
|
bitfld.long 0x00 1. "PU1OD,PU1OD" "0,1"
|
|
bitfld.long 0x00 0. "PU0OD,PU0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port U Open Drain Control Register"
|
|
bitfld.long 0x00 6. "PU6OD,PU6OD" "0,1"
|
|
bitfld.long 0x00 5. "PU5OD,PU5OD" "0,1"
|
|
bitfld.long 0x00 4. "PU4OD,PU4OD" "0,1"
|
|
bitfld.long 0x00 3. "PU3OD,PU3OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PU2OD,PU2OD" "0,1"
|
|
bitfld.long 0x00 1. "PU1OD,PU1OD" "0,1"
|
|
bitfld.long 0x00 0. "PU0OD,PU0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port U Pull-up Control Register"
|
|
bitfld.long 0x00 6. "PU6UP,PU6UP" "0,1"
|
|
bitfld.long 0x00 5. "PU5UP,PU5UP" "0,1"
|
|
bitfld.long 0x00 4. "PU4UP,PU4UP" "0,1"
|
|
bitfld.long 0x00 3. "PU3UP,PU3UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PU2UP,PU2UP" "0,1"
|
|
bitfld.long 0x00 1. "PU1UP,PU1UP" "0,1"
|
|
bitfld.long 0x00 0. "PU0UP,PU0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port U Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PU7UP,PU7UP" "0,1"
|
|
bitfld.long 0x00 6. "PU6UP,PU6UP" "0,1"
|
|
bitfld.long 0x00 5. "PU5UP,PU5UP" "0,1"
|
|
bitfld.long 0x00 4. "PU4UP,PU4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PU3UP,PU3UP" "0,1"
|
|
bitfld.long 0x00 2. "PU2UP,PU2UP" "0,1"
|
|
bitfld.long 0x00 1. "PU1UP,PU1UP" "0,1"
|
|
bitfld.long 0x00 0. "PU0UP,PU0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port U Pull-down Control Register"
|
|
bitfld.long 0x00 6. "PU6DN,PU6DN" "0,1"
|
|
bitfld.long 0x00 5. "PU5DN,PU5DN" "0,1"
|
|
bitfld.long 0x00 4. "PU4DN,PU4DN" "0,1"
|
|
bitfld.long 0x00 3. "PU3DN,PU3DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PU2DN,PU2DN" "0,1"
|
|
bitfld.long 0x00 1. "PU1DN,PU1DN" "0,1"
|
|
bitfld.long 0x00 0. "PU0DN,PU0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port U Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PU7DN,PU7DN" "0,1"
|
|
bitfld.long 0x00 6. "PU6DN,PU6DN" "0,1"
|
|
bitfld.long 0x00 5. "PU5DN,PU5DN" "0,1"
|
|
bitfld.long 0x00 4. "PU4DN,PU4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PU3DN,PU3DN" "0,1"
|
|
bitfld.long 0x00 2. "PU2DN,PU2DN" "0,1"
|
|
bitfld.long 0x00 1. "PU1DN,PU1DN" "0,1"
|
|
bitfld.long 0x00 0. "PU0DN,PU0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port U Input Control Register"
|
|
bitfld.long 0x00 6. "PU6IE,PU6IE" "0,1"
|
|
bitfld.long 0x00 5. "PU5IE,PU5IE" "0,1"
|
|
bitfld.long 0x00 4. "PU4IE,PU4IE" "0,1"
|
|
bitfld.long 0x00 3. "PU3IE,PU3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PU2IE,PU2IE" "0,1"
|
|
bitfld.long 0x00 1. "PU1IE,PU1IE" "0,1"
|
|
bitfld.long 0x00 0. "PU0IE,PU0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port U Input Control Register"
|
|
bitfld.long 0x00 7. "PU7IE,PU7IE" "0,1"
|
|
bitfld.long 0x00 6. "PU6IE,PU6IE" "0,1"
|
|
bitfld.long 0x00 5. "PU5IE,PU5IE" "0,1"
|
|
bitfld.long 0x00 4. "PU4IE,PU4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PU3IE,PU3IE" "0,1"
|
|
bitfld.long 0x00 2. "PU2IE,PU2IE" "0,1"
|
|
bitfld.long 0x00 1. "PU1IE,PU1IE" "0,1"
|
|
bitfld.long 0x00 0. "PU0IE,PU0IE" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "PV (Port V)"
|
|
base ad:0x400E1100
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port V Data Register"
|
|
bitfld.long 0x00 1. "PV1,PV1" "0,1"
|
|
bitfld.long 0x00 0. "PV0,PV0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port V Data Register"
|
|
bitfld.long 0x00 7. "PV7,PV7" "0,1"
|
|
bitfld.long 0x00 6. "PV6,PV6" "0,1"
|
|
bitfld.long 0x00 5. "PV5,PV5" "0,1"
|
|
bitfld.long 0x00 4. "PV4,PV4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PV3,PV3" "0,1"
|
|
bitfld.long 0x00 2. "PV2,PV2" "0,1"
|
|
bitfld.long 0x00 1. "PV1,PV1" "0,1"
|
|
bitfld.long 0x00 0. "PV0,PV0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port V Data Register"
|
|
bitfld.long 0x00 3. "PV3,PV3" "0,1"
|
|
bitfld.long 0x00 2. "PV2,PV2" "0,1"
|
|
bitfld.long 0x00 1. "PV1,PV1" "0,1"
|
|
bitfld.long 0x00 0. "PV0,PV0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port V OutPut Control Register"
|
|
bitfld.long 0x00 1. "PV1C,PV1C" "0,1"
|
|
bitfld.long 0x00 0. "PV0C,PV0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port V OutPut Control Register"
|
|
bitfld.long 0x00 3. "PV3C,PV3C" "0,1"
|
|
bitfld.long 0x00 2. "PV2C,PV2C" "0,1"
|
|
bitfld.long 0x00 1. "PV1C,PV1C" "0,1"
|
|
bitfld.long 0x00 0. "PV0C,PV0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port V OutPut Control Register"
|
|
bitfld.long 0x00 7. "PV7C,PV7C" "0,1"
|
|
bitfld.long 0x00 6. "PV6C,PV6C" "0,1"
|
|
bitfld.long 0x00 5. "PV5C,PV5C" "0,1"
|
|
bitfld.long 0x00 4. "PV4C,PV4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PV3C,PV3C" "0,1"
|
|
bitfld.long 0x00 2. "PV2C,PV2C" "0,1"
|
|
bitfld.long 0x00 1. "PV1C,PV1C" "0,1"
|
|
bitfld.long 0x00 0. "PV0C,PV0C" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port V Function Register 1"
|
|
bitfld.long 0x00 3. "PV3F1,PV3F1" "0,1"
|
|
bitfld.long 0x00 2. "PV2F1,PV2F1" "0,1"
|
|
bitfld.long 0x00 1. "PV1F1,PV1F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port V Function Register 1"
|
|
bitfld.long 0x00 1. "PV1F1,PV1F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port V Function Register 2"
|
|
bitfld.long 0x00 7. "PV7F2,PV7F2" "0,1"
|
|
bitfld.long 0x00 6. "PV6F2,PV6F2" "0,1"
|
|
bitfld.long 0x00 5. "PV5F2,PV5F2" "0,1"
|
|
bitfld.long 0x00 4. "PV4F2,PV4F2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PV3F2,PV3F2" "0,1"
|
|
bitfld.long 0x00 2. "PV2F2,PV2F2" "0,1"
|
|
bitfld.long 0x00 1. "PV1F2,PV1F2" "0,1"
|
|
bitfld.long 0x00 0. "PV0F2,PV0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port V Function Register 2"
|
|
bitfld.long 0x00 1. "PV1F2,PV1F2" "0,1"
|
|
bitfld.long 0x00 0. "PV0F2,PV0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FR2,Port V Function Register 2"
|
|
bitfld.long 0x00 3. "PV3F2,PV3F2" "0,1"
|
|
bitfld.long 0x00 2. "PV2F2,PV2F2" "0,1"
|
|
bitfld.long 0x00 1. "PV1F2,PV1F2" "0,1"
|
|
bitfld.long 0x00 0. "PV0F2,PV0F2" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port V Function Register 3"
|
|
bitfld.long 0x00 6. "PV6F3,PV6F3" "0,1"
|
|
bitfld.long 0x00 5. "PV5F3,PV5F3" "0,1"
|
|
bitfld.long 0x00 2. "PV2F3,PV2F3" "0,1"
|
|
bitfld.long 0x00 1. "PV1F3,PV1F3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PV0F3,PV0F3" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port V Function Register 4"
|
|
bitfld.long 0x00 0. "PV0F4,PV0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port V Function Register 4"
|
|
bitfld.long 0x00 7. "PV7F4,PV7F4" "0,1"
|
|
bitfld.long 0x00 6. "PV6F4,PV6F4" "0,1"
|
|
bitfld.long 0x00 5. "PV5F4,PV5F4" "0,1"
|
|
bitfld.long 0x00 4. "PV4F4,PV4F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PV3F4,PV3F4" "0,1"
|
|
bitfld.long 0x00 2. "PV2F4,PV2F4" "0,1"
|
|
bitfld.long 0x00 1. "PV1F4,PV1F4" "0,1"
|
|
bitfld.long 0x00 0. "PV0F4,PV0F4" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port V Function Register 5"
|
|
bitfld.long 0x00 7. "PV7F5,PV7F5" "0,1"
|
|
bitfld.long 0x00 6. "PV6F5,PV6F5" "0,1"
|
|
bitfld.long 0x00 5. "PV5F5,PV5F5" "0,1"
|
|
bitfld.long 0x00 4. "PV4F5,PV4F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PV3F5,PV3F5" "0,1"
|
|
bitfld.long 0x00 2. "PV2F5,PV2F5" "0,1"
|
|
bitfld.long 0x00 1. "PV1F5,PV1F5" "0,1"
|
|
bitfld.long 0x00 0. "PV0F5,PV0F5" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port V Function Register 6"
|
|
bitfld.long 0x00 7. "PV7F6,PV7F6" "0,1"
|
|
bitfld.long 0x00 5. "PV5F6,PV5F6" "0,1"
|
|
bitfld.long 0x00 4. "PV4F6,PV4F6" "0,1"
|
|
bitfld.long 0x00 3. "PV3F6,PV3F6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PV2F6,PV2F6" "0,1"
|
|
bitfld.long 0x00 1. "PV1F6,PV1F6" "0,1"
|
|
bitfld.long 0x00 0. "PV0F6,PV0F6" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port V Function Register 7"
|
|
bitfld.long 0x00 7. "PV7F7,PV7F7" "0,1"
|
|
bitfld.long 0x00 6. "PV6F7,PV6F7" "0,1"
|
|
bitfld.long 0x00 5. "PV5F7,PV5F7" "0,1"
|
|
bitfld.long 0x00 4. "PV4F7,PV4F7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PV3F7,PV3F7" "0,1"
|
|
bitfld.long 0x00 2. "PV2F7,PV2F7" "0,1"
|
|
bitfld.long 0x00 1. "PV1F7,PV1F7" "0,1"
|
|
bitfld.long 0x00 0. "PV0F7,PV0F7" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port V Open Drain Control Register"
|
|
bitfld.long 0x00 1. "PV1OD,PV1OD" "0,1"
|
|
bitfld.long 0x00 0. "PV0OD,PV0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port V Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PV7OD,PV7OD" "0,1"
|
|
bitfld.long 0x00 6. "PV6OD,PV6OD" "0,1"
|
|
bitfld.long 0x00 5. "PV5OD,PV5OD" "0,1"
|
|
bitfld.long 0x00 4. "PV4OD,PV4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PV3OD,PV3OD" "0,1"
|
|
bitfld.long 0x00 2. "PV2OD,PV2OD" "0,1"
|
|
bitfld.long 0x00 1. "PV1OD,PV1OD" "0,1"
|
|
bitfld.long 0x00 0. "PV0OD,PV0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port V Open Drain Control Register"
|
|
bitfld.long 0x00 3. "PV3OD,PV3OD" "0,1"
|
|
bitfld.long 0x00 2. "PV2OD,PV2OD" "0,1"
|
|
bitfld.long 0x00 1. "PV1OD,PV1OD" "0,1"
|
|
bitfld.long 0x00 0. "PV0OD,PV0OD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port V Pull-up Control Register"
|
|
bitfld.long 0x00 1. "PV1UP,PV1UP" "0,1"
|
|
bitfld.long 0x00 0. "PV0UP,PV0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port V Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PV7UP,PV7UP" "0,1"
|
|
bitfld.long 0x00 6. "PV6UP,PV6UP" "0,1"
|
|
bitfld.long 0x00 5. "PV5UP,PV5UP" "0,1"
|
|
bitfld.long 0x00 4. "PV4UP,PV4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PV3UP,PV3UP" "0,1"
|
|
bitfld.long 0x00 2. "PV2UP,PV2UP" "0,1"
|
|
bitfld.long 0x00 1. "PV1UP,PV1UP" "0,1"
|
|
bitfld.long 0x00 0. "PV0UP,PV0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port V Pull-up Control Register"
|
|
bitfld.long 0x00 3. "PV3UP,PV3UP" "0,1"
|
|
bitfld.long 0x00 2. "PV2UP,PV2UP" "0,1"
|
|
bitfld.long 0x00 1. "PV1UP,PV1UP" "0,1"
|
|
bitfld.long 0x00 0. "PV0UP,PV0UP" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port V Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PV7DN,PV7DN" "0,1"
|
|
bitfld.long 0x00 6. "PV6DN,PV6DN" "0,1"
|
|
bitfld.long 0x00 5. "PV5DN,PV5DN" "0,1"
|
|
bitfld.long 0x00 4. "PV4DN,PV4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PV3DN,PV3DN" "0,1"
|
|
bitfld.long 0x00 2. "PV2DN,PV2DN" "0,1"
|
|
bitfld.long 0x00 1. "PV1DN,PV1DN" "0,1"
|
|
bitfld.long 0x00 0. "PV0DN,PV0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port V Pull-down Control Register"
|
|
bitfld.long 0x00 3. "PV3DN,PV3DN" "0,1"
|
|
bitfld.long 0x00 2. "PV2DN,PV2DN" "0,1"
|
|
bitfld.long 0x00 1. "PV1DN,PV1DN" "0,1"
|
|
bitfld.long 0x00 0. "PV0DN,PV0DN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KN*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port V Pull-down Control Register"
|
|
bitfld.long 0x00 1. "PV1DN,PV1DN" "0,1"
|
|
bitfld.long 0x00 0. "PV0DN,PV0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port V InPut Control Register"
|
|
bitfld.long 0x00 1. "PV1IE,PV1IE" "0,1"
|
|
bitfld.long 0x00 0. "PV0IE,PV0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port V InPut Control Register"
|
|
bitfld.long 0x00 7. "PV7IE,PV7IE" "0,1"
|
|
bitfld.long 0x00 6. "PV6IE,PV6IE" "0,1"
|
|
bitfld.long 0x00 5. "PV5IE,PV5IE" "0,1"
|
|
bitfld.long 0x00 4. "PV4IE,PV4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PV3IE,PV3IE" "0,1"
|
|
bitfld.long 0x00 2. "PV2IE,PV2IE" "0,1"
|
|
bitfld.long 0x00 1. "PV1IE,PV1IE" "0,1"
|
|
bitfld.long 0x00 0. "PV0IE,PV0IE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port V InPut Control Register"
|
|
bitfld.long 0x00 3. "PV3IE,PV3IE" "0,1"
|
|
bitfld.long 0x00 2. "PV2IE,PV2IE" "0,1"
|
|
bitfld.long 0x00 1. "PV1IE,PV1IE" "0,1"
|
|
bitfld.long 0x00 0. "PV0IE,PV0IE" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4KQ*")
|
|
tree "PW (Port W)"
|
|
base ad:0x400E1200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port W Data Register"
|
|
bitfld.long 0x00 7. "PW7,PW7" "0,1"
|
|
bitfld.long 0x00 6. "PW6,PW6" "0,1"
|
|
bitfld.long 0x00 5. "PW5,PW5" "0,1"
|
|
bitfld.long 0x00 4. "PW4,PW4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PW3,PW3" "0,1"
|
|
bitfld.long 0x00 2. "PW2,PW2" "0,1"
|
|
bitfld.long 0x00 1. "PW1,PW1" "0,1"
|
|
bitfld.long 0x00 0. "PW0,PW0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port W OutPut Control Register"
|
|
bitfld.long 0x00 7. "PW7C,PW7C" "0,1"
|
|
bitfld.long 0x00 6. "PW6C,PW6C" "0,1"
|
|
bitfld.long 0x00 5. "PW5C,PW5C" "0,1"
|
|
bitfld.long 0x00 4. "PW4C,PW4C" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PW3C,PW3C" "0,1"
|
|
bitfld.long 0x00 2. "PW2C,PW2C" "0,1"
|
|
bitfld.long 0x00 1. "PW1C,PW1C" "0,1"
|
|
bitfld.long 0x00 0. "PW0C,PW0C" "0,1"
|
|
sif cpuis("TMPM4KQ*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port W Function Register 1"
|
|
bitfld.long 0x00 7. "PW7F1,PW7F1" "0,1"
|
|
bitfld.long 0x00 6. "PW6F1,PW6F1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FR3,Port W Function Register 3"
|
|
bitfld.long 0x00 7. "PW7F3,PW7F3" "0,1"
|
|
bitfld.long 0x00 4. "PW4F3,PW4F3" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port W Function Register 4"
|
|
bitfld.long 0x00 3. "PW3F4,PW3F4" "0,1"
|
|
bitfld.long 0x00 2. "PW2F4,PW2F4" "0,1"
|
|
bitfld.long 0x00 1. "PW1F4,PW1F4" "0,1"
|
|
bitfld.long 0x00 0. "PW0F4,PW0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KQ*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port W Function Register 4"
|
|
bitfld.long 0x00 5. "PW5F4,PW5F4" "0,1"
|
|
bitfld.long 0x00 4. "PW4F4,PW4F4" "0,1"
|
|
bitfld.long 0x00 3. "PW3F4,PW3F4" "0,1"
|
|
bitfld.long 0x00 2. "PW2F4,PW2F4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PW1F4,PW1F4" "0,1"
|
|
bitfld.long 0x00 0. "PW0F4,PW0F4" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port W Function Register 5"
|
|
bitfld.long 0x00 7. "PW7F5,PW7F5" "0,1"
|
|
bitfld.long 0x00 6. "PW6F5,PW6F5" "0,1"
|
|
bitfld.long 0x00 5. "PW5F5,PW5F5" "0,1"
|
|
bitfld.long 0x00 4. "PW4F5,PW4F5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PW3F5,PW3F5" "0,1"
|
|
bitfld.long 0x00 2. "PW2F5,PW2F5" "0,1"
|
|
bitfld.long 0x00 1. "PW1F5,PW1F5" "0,1"
|
|
bitfld.long 0x00 0. "PW0F5,PW0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4KQ*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR5,Port W Function Register 5"
|
|
bitfld.long 0x00 2. "PW2F5,PW2F5" "0,1"
|
|
bitfld.long 0x00 1. "PW1F5,PW1F5" "0,1"
|
|
bitfld.long 0x00 0. "PW0F5,PW0F5" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G9*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FR6,Port W Function Register 6"
|
|
bitfld.long 0x00 0. "PW0F6,PW0F6" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FR7,Port W Function Register 7"
|
|
bitfld.long 0x00 7. "PW7F7,PW7F7" "0,1"
|
|
bitfld.long 0x00 6. "PW6F7,PW6F7" "0,1"
|
|
bitfld.long 0x00 5. "PW5F7,PW5F7" "0,1"
|
|
bitfld.long 0x00 4. "PW4F7,PW4F7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PW2F7,PW2F7" "0,1"
|
|
bitfld.long 0x00 1. "PW1F7,PW1F7" "0,1"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port W Open Drain Control Register"
|
|
bitfld.long 0x00 7. "PW7OD,PW7OD" "0,1"
|
|
bitfld.long 0x00 6. "PW6OD,PW6OD" "0,1"
|
|
bitfld.long 0x00 5. "PW5OD,PW5OD" "0,1"
|
|
bitfld.long 0x00 4. "PW4OD,PW4OD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PW3OD,PW3OD" "0,1"
|
|
bitfld.long 0x00 2. "PW2OD,PW2OD" "0,1"
|
|
bitfld.long 0x00 1. "PW1OD,PW1OD" "0,1"
|
|
bitfld.long 0x00 0. "PW0OD,PW0OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port W Pull-up Control Register"
|
|
bitfld.long 0x00 7. "PW7UP,PW7UP" "0,1"
|
|
bitfld.long 0x00 6. "PW6UP,PW6UP" "0,1"
|
|
bitfld.long 0x00 5. "PW5UP,PW5UP" "0,1"
|
|
bitfld.long 0x00 4. "PW4UP,PW4UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PW3UP,PW3UP" "0,1"
|
|
bitfld.long 0x00 2. "PW2UP,PW2UP" "0,1"
|
|
bitfld.long 0x00 1. "PW1UP,PW1UP" "0,1"
|
|
bitfld.long 0x00 0. "PW0UP,PW0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port W Pull-down Control Register"
|
|
bitfld.long 0x00 7. "PW7DN,PW7DN" "0,1"
|
|
bitfld.long 0x00 6. "PW6DN,PW6DN" "0,1"
|
|
bitfld.long 0x00 5. "PW5DN,PW5DN" "0,1"
|
|
bitfld.long 0x00 4. "PW4DN,PW4DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PW3DN,PW3DN" "0,1"
|
|
bitfld.long 0x00 2. "PW2DN,PW2DN" "0,1"
|
|
bitfld.long 0x00 1. "PW1DN,PW1DN" "0,1"
|
|
bitfld.long 0x00 0. "PW0DN,PW0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port W InPut Control Register"
|
|
bitfld.long 0x00 7. "PW7IE,PW7IE" "0,1"
|
|
bitfld.long 0x00 6. "PW6IE,PW6IE" "0,1"
|
|
bitfld.long 0x00 5. "PW5IE,PW5IE" "0,1"
|
|
bitfld.long 0x00 4. "PW4IE,PW4IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PW3IE,PW3IE" "0,1"
|
|
bitfld.long 0x00 2. "PW2IE,PW2IE" "0,1"
|
|
bitfld.long 0x00 1. "PW1IE,PW1IE" "0,1"
|
|
bitfld.long 0x00 0. "PW0IE,PW0IE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
tree "PY (Port Y)"
|
|
base ad:0x400E1300
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Port Y Data Register"
|
|
bitfld.long 0x00 4. "PY4,PY4" "0,1"
|
|
bitfld.long 0x00 3. "PY3,PY3" "0,1"
|
|
bitfld.long 0x00 2. "PY2,PY2" "0,1"
|
|
bitfld.long 0x00 1. "PY1,PY1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PY0,PY0" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Port Y OutPut Control Register"
|
|
bitfld.long 0x00 4. "PY4C,PY4C" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FR1,Port Y Function Register 1"
|
|
bitfld.long 0x00 4. "PY4F1,PY4F1" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FR4,Port Y Function Register 4"
|
|
bitfld.long 0x00 4. "PY4F4,PY4F4" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OD,Port Y Open Drain Control Register"
|
|
bitfld.long 0x00 4. "PY4OD,PY4OD" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PUP,Port Y Pull-up Control Register"
|
|
bitfld.long 0x00 4. "PY4UP,PY4UP" "0,1"
|
|
bitfld.long 0x00 3. "PY3UP,PY3UP" "0,1"
|
|
bitfld.long 0x00 2. "PY2UP,PY2UP" "0,1"
|
|
bitfld.long 0x00 1. "PY1UP,PY1UP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PY0UP,PY0UP" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDN,Port Y Pull-down Control Register"
|
|
bitfld.long 0x00 4. "PY4DN,PY4DN" "0,1"
|
|
bitfld.long 0x00 3. "PY3DN,PY3DN" "0,1"
|
|
bitfld.long 0x00 2. "PY2DN,PY2DN" "0,1"
|
|
bitfld.long 0x00 1. "PY1DN,PY1DN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PY0DN,PY0DN" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IE,Port Y InPut Control Register"
|
|
bitfld.long 0x00 4. "PY4IE,PY4IE" "0,1"
|
|
bitfld.long 0x00 3. "PY3IE,PY3IE" "0,1"
|
|
bitfld.long 0x00 2. "PY2IE,PY2IE" "0,1"
|
|
bitfld.long 0x00 1. "PY1IE,PY1IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PY0IE,PY0IE" "0,1"
|
|
tree.end
|
|
tree "TRMOSC (Internal High-speed Oscillation Adjustment)"
|
|
base ad:0x400E3100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PRO,Protection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PROTECT,PROTECT"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EN,Enable Register"
|
|
bitfld.long 0x00 0. "TRIMEN,TRIMEN" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "INIT,Initial Trimming Level Monitor Register"
|
|
bitfld.long 0x00 8.--13. "INITC,INITC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "INITF,INITF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SET,Trimming Level Setting Register"
|
|
bitfld.long 0x00 8.--13. "SETC,SETC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "SETF,SETF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
endif
|
|
tree "OFD (Oscillation Frequency Detector (OFD))"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E4000
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40084000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,OFD Control Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OFDWEN,OFDWEN"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,OFD Control Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OFDEN,OFDEN"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MN0,OFD Lower Detection Frequency Setting Register0"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFDMN0,OFDMN0"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MN1,OFD Lower Detection Frequency Setting Register1"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFDMN1,OFDMN1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MX0,OFD Higher Detection Frequency Setting Register0"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFDMX0,OFDMX0"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MX1,OFD Higher Detection Frequency Setting Register1"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFDMX1,OFDMX1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RST,OFD Reset Enable Control Register"
|
|
bitfld.long 0x00 0. "OFDRSTEN,OFDRSTEN" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "STAT,OFD Status Register"
|
|
bitfld.long 0x00 1. "OFDBUSY,OFDBUSY" "0,1"
|
|
bitfld.long 0x00 0. "FRQERR,FRQERR" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MON,OFD External high frequency oscillaion clock monitor register"
|
|
bitfld.long 0x00 0. "OFDMON,OFDMON" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400F1000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,OFD Control Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OFDWEN,OFDWEN"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,OFD Control Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OFDEN,OFDEN"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MN0,OFD Lower Detection Frequency Setting Register0"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFDMN0,OFDMN0"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MN1,OFD Lower Detection Frequency Setting Register1"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFDMN1,OFDMN1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MX0,OFD Higher Detection Frequency Setting Register0"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFDMX0,OFDMX0"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MX1,OFD Higher Detection Frequency Setting Register1"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFDMX1,OFDMX1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RST,OFD Reset Enable Control Register"
|
|
bitfld.long 0x00 0. "OFDRSTEN,OFDRSTEN" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "STAT,OFD Status Register"
|
|
bitfld.long 0x00 1. "OFDBUSY,OFDBUSY" "0,1"
|
|
bitfld.long 0x00 0. "FRQERR,FRQERR" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MON,OFD detection target clock 1 monitor setting register"
|
|
bitfld.long 0x00 0. "OFDMON,OFDMON" "0,1"
|
|
endif
|
|
tree.end
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
tree "RTC (Real-time Counter)"
|
|
base ad:0x400E4800
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SECR,RTC Sec setting register"
|
|
hexmask.byte 0x00 0.--6. 1. "SE,SE"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MINR,RTC Min settging register"
|
|
hexmask.byte 0x00 0.--6. 1. "MI,MI"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "HOURR,RTC Hour setting register"
|
|
bitfld.byte 0x00 0.--5. "HO,HO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "DAYR,RTC Day setting register"
|
|
bitfld.byte 0x00 0.--2. "WE,WE" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "DATER,RTC Date setting register"
|
|
bitfld.byte 0x00 0.--5. "DA,DA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "MONTHR_A,RTC Month settging register PAGE0"
|
|
bitfld.byte 0x00 0.--4. "MO,MO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "MONTHR_B,RTC Month settging register PAGE0"
|
|
bitfld.byte 0x00 0. "MO0,MO0" "0,1"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "YEARR_A,RTC Year setting register PAGE0"
|
|
hexmask.byte 0x00 0.--7. 1. "YE,YE"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "YEARR_B,RTC Leap year register PAGE1"
|
|
bitfld.byte 0x00 0.--1. "LEAP,LEAP" "0,1,2,3"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "PAGER,RTC Page register"
|
|
bitfld.byte 0x00 7. "INTENA,INTENA" "0,1"
|
|
bitfld.byte 0x00 4. "ADJUST,ADJUST" "0,1"
|
|
bitfld.byte 0x00 3. "ENATMR,ENATMR" "0,1"
|
|
bitfld.byte 0x00 2. "ENAALM,ENAALM" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "PAGE,PAGE" "0,1"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "RESTR,RTC Reset register"
|
|
bitfld.byte 0x00 7. "DIS1HZ,DIS1HZ" "0,1"
|
|
bitfld.byte 0x00 6. "DIS16HZ,DIS16HZ" "0,1"
|
|
bitfld.byte 0x00 5. "RSTTMR,RSTTMR" "0,1"
|
|
bitfld.byte 0x00 4. "RSTALM,RSTALM" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "DIS2HZ,DIS2HZ" "0,1"
|
|
bitfld.byte 0x00 1. "DIS4HZ,DIS4HZ" "0,1"
|
|
bitfld.byte 0x00 0. "DIS8HZ,DIS8HZ" "0,1"
|
|
group.byte 0x0E++0x00
|
|
line.byte 0x00 "PROTECT,RTC clock adjust control register"
|
|
hexmask.byte 0x00 0.--7. 1. "PROTECT,PROTECT"
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "ADJCTL,RTC protect register"
|
|
bitfld.byte 0x00 1.--3. "AJSEL,AJSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0. "AJEN,AJEN" "0,1"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "ADJDAT,RTC clock adjust data register"
|
|
hexmask.byte 0x00 0.--7. 1. "ADJDAT,ADJDAT"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "ADJSIGN,ADJSIGN"
|
|
bitfld.byte 0x00 0. "ADJSIGN,ADJSIGN" "0,1"
|
|
tree.end
|
|
tree "CEC (Consumer Electronics Control (CEC))"
|
|
base ad:0x400E8000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EN,CEC Enable Register"
|
|
bitfld.long 0x00 0. "CECEN,CECEN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADD,CEC Logical Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CECADD,CECADD"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "RESET,CEC Software Reset Register"
|
|
bitfld.long 0x00 0. "CECRESET,CECRESET" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "REN,CEC Receive Enable Register"
|
|
bitfld.long 0x00 0. "CECREN,CECREN" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RBUF,CEC Receive Buffer Register"
|
|
bitfld.long 0x00 9. "CECACK,CECACK" "0,1"
|
|
bitfld.long 0x00 8. "CECEOM,CECEOM" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CECRBUF,CECRBUF"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RCR1,CEC Receive Control Register 1"
|
|
bitfld.long 0x00 24. "CECACKDIS,CECACKDIS" "0,1"
|
|
bitfld.long 0x00 20.--21. "CECHNC,CECHNC" "0,1,2,3"
|
|
bitfld.long 0x00 16.--18. "CECLNC,CECLNC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "CECMIN,CECMIN" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "CECMAX,CECMAX" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "CECDAT,CECDAT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--3. "CECTOUT,CECTOUT" "0,1,2,3"
|
|
bitfld.long 0x00 1. "CECRIHLD,CECRIHLD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CECOTH,CECOTH" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RCR2,CEC Receive Control Register 2"
|
|
bitfld.long 0x00 12.--14. "CECSWAV3,CECSWAV3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "CECSWAV2,CECSWAV2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "CECSWAV1,CECSWAV1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CECSWAV0,CECSWAV0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RCR3,CEC Receive Control Register 3"
|
|
bitfld.long 0x00 20.--22. "CECWAV3,CECWAV3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "CECWAV2,CECWAV2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "CECWAV1,CECWAV1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "CECWAV0,CECWAV0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 1. "CECRSTAEN,CECRSTAEN" "0,1"
|
|
bitfld.long 0x00 0. "CECWAVEN,CECWAVEN" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TEN,CEC Transmit Enable Register"
|
|
rbitfld.long 0x00 1. "CECTRANS,CECTRANS" "0,1"
|
|
bitfld.long 0x00 0. "CECTEN,CECTEN" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TBUF,CEC Transmit Buffer Register"
|
|
bitfld.long 0x00 8. "CECTEOM,CECTEOM" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CECTBUF,CECTBUF"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TCR,CEC Transmit Control Register"
|
|
bitfld.long 0x00 20.--22. "CECSTRS,CECSTRS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "CECSPRD,CECSPRD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "CECDTRS,CECDTRS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "CECDPRD,CECDPRD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4. "CECBRD,CECBRD" "0,1"
|
|
bitfld.long 0x00 0.--3. "CECFREE,CECFREE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RSTAT,CEC Receive Interrupt Status Register"
|
|
bitfld.long 0x00 6. "CECRIWAV,CECRIWAV" "0,1"
|
|
bitfld.long 0x00 5. "CECRIOR,CECRIOR" "0,1"
|
|
bitfld.long 0x00 4. "CECRIACK,CECRIACK" "0,1"
|
|
bitfld.long 0x00 3. "CECRIMIN,CECRIMIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CECRIMAX,CECRIMAX" "0,1"
|
|
bitfld.long 0x00 1. "CECRISTA,CECRISTA" "0,1"
|
|
bitfld.long 0x00 0. "CECRIEND,CECRIEND" "0,1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TSTAT,CEC Transmit Interrupt Status Register"
|
|
bitfld.long 0x00 4. "CECTIUR,CECTIUR" "0,1"
|
|
bitfld.long 0x00 3. "CECTIACK,CECTIACK" "0,1"
|
|
bitfld.long 0x00 2. "CECTIAL,CECTIAL" "0,1"
|
|
bitfld.long 0x00 1. "CECTIEND,CECTIEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CECTISTA,CECTISTA" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FSSEL,CEC sampling clock selection Register"
|
|
bitfld.long 0x00 0. "CECCLK,CECCLK" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")
|
|
tree "RMC (Remote Control Signal Preprocessor (RMC))"
|
|
repeat 2. (list 0. 1.) (list ad:0x400E8100 ad:0x400E8200)
|
|
tree "RMC$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EN,RMC Enable Register"
|
|
bitfld.long 0x00 0. "RMCEN,RMCEN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "REN,RMC Receive Enable Register"
|
|
bitfld.long 0x00 0. "RMCREN,RMCREN" "0,1"
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
rgroup.long ($2+0x08)++0x03
|
|
line.long 0x00 "RBUF$1,RMC Receive Data Buffer Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "RMCRBUF,RMCRBUF"
|
|
repeat.end
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RBUF3,RMC Receive Data Buffer Register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RMCRBUF,RMCRBUF"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RCR1,RMC Receive Control Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RMCLCMAX,RMCLCMAX"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RMCLCMIN,RMCLCMIN"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RMCLLMAX,RMCLLMAX"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RMCLLMIN,RMCLLMIN"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RCR2,RMC Receive Control Register 2"
|
|
bitfld.long 0x00 31. "RMCLIEN,RMCLIEN" "0,1"
|
|
bitfld.long 0x00 30. "RMCEDIEN,RMCEDIEN" "0,1"
|
|
bitfld.long 0x00 25. "RMCLD,RMCLD" "0,1"
|
|
bitfld.long 0x00 24. "RMCPHM,RMCPHM" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RMCLL,RMCLL"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RMCDMAX,RMCDMAX"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RCR3,RMC Receive Control Register 3"
|
|
hexmask.long.byte 0x00 8.--14. 1. "RMCDATH,RMCDATH"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RMCDATL,RMCDATL"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RCR4,RMC Receive Control Register 4"
|
|
bitfld.long 0x00 7. "RMCPO,RMCPO" "0,1"
|
|
bitfld.long 0x00 0.--3. "RMCNC,RMCNC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RSTAT,RMC Receive Status Register"
|
|
bitfld.long 0x00 15. "RMCRLIF,RMCRLIF" "0,1"
|
|
bitfld.long 0x00 14. "RMCLOIF,RMCLOIF" "0,1"
|
|
bitfld.long 0x00 13. "RMCDMAXIF,RMCDMAXIF" "0,1"
|
|
bitfld.long 0x00 12. "RMCEDIF,RMCEDIF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RMCRLDR,RMCRLDR" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RMCRNUM,RMCRNUM"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "END1,RMC Receive End Bit Number Register 1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RMCEND1,RMCEND1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "END2,RMC Receive End Bit Number Register 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RMCEND2,RMCEND2"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "END3,RMC Receive End Bit Number Register 3"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RMCEND3,RMCEND3"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FSSEL,RMC Frequency Selection Register"
|
|
bitfld.long 0x00 0. "RMCCLK,RMCCLK" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "PMD"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
base ad:0x400E9000
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40089000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MDEN,PMD Enable Register"
|
|
bitfld.long 0x00 0. "PWMEN,PWMEN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PORTMD,PMD Port Output Mode Register"
|
|
bitfld.long 0x00 0.--1. "PORTMD,PORTMD" "0,1,2,3"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MDCR,PMD Control Register"
|
|
bitfld.long 0x00 14.--15. "WPWMES,WPWMES" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "VPWMES,VPWMES" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "UPWMES,UPWMES" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "DSYNCS,DSYNCS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "DTCREN,DTCREN" "0,1"
|
|
bitfld.long 0x00 6. "PWMCK,PWMCK" "0,1"
|
|
bitfld.long 0x00 5. "SYNTMD,SYNTMD" "0,1"
|
|
bitfld.long 0x00 4. "DTYMD,DTYMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PINT,PINT" "0,1"
|
|
bitfld.long 0x00 1.--2. "INTPRD,INTPRD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "PWMMD,PWMMD" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MDCR,PMD Control Register"
|
|
bitfld.long 0x00 14.--15. "WPWMMD,WPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "VPWMMD,VPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "UPWMMD,UPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "DSYNCS,DSYNCS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "DTCREN,DTCREN" "0,1"
|
|
bitfld.long 0x00 6. "DCMEN,DCMEN" "0,1"
|
|
bitfld.long 0x00 5. "SYNTMD,SYNTMD" "0,1"
|
|
bitfld.long 0x00 4. "DTYMD,DTYMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PINT,PINT" "0,1"
|
|
bitfld.long 0x00 1.--2. "INTPRD,INTPRD" "0,1,2,3"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CNTSTA,PMD PWM Counter Status Register"
|
|
bitfld.long 0x00 0. "UPDWN,UPDWN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CARSTA,PWM Carrier Status Register"
|
|
bitfld.long 0x00 2. "PWMWST,PWMWST" "0,1"
|
|
bitfld.long 0x00 1. "PWMVST,PWMVST" "0,1"
|
|
bitfld.long 0x00 0. "PWMUST,PWMUST" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "MDCNT,PMD PWM Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MDCNT,MDCNT"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BCARI,PWM Basic Carrier Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "BCARI,BCARI"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MDPRD,PMD PWM Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MDPRD,MDPRD"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RATE,PWM Frequency Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "RATE,RATE"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CMPU,PMD PWM Compare U Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPU,CMPU"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CMPV,PMD PWM Compare V Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPV,CMPV"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPW,PMD PWM Compare W Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPW,CMPW"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODESEL,PMD Mode Select Register"
|
|
bitfld.long 0x00 7. "DCMPEN,DCMPEN" "0,1"
|
|
bitfld.long 0x00 3. "MDSEL3,MDSEL3" "0,1"
|
|
bitfld.long 0x00 2. "MDSEL2,MDSEL2" "0,1"
|
|
bitfld.long 0x00 1. "MDSEL1,MDSEL1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MDSEL0,MDSEL0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODESEL,PMD Mode Selection Register"
|
|
bitfld.long 0x00 7. "DCMPEN,DCMPEN" "0,1"
|
|
bitfld.long 0x00 3. "MDSEL3,MDSEL3" "0,1"
|
|
bitfld.long 0x00 2. "MDSEL2,MDSEL2" "0,1"
|
|
bitfld.long 0x00 1. "MDSEL1,MDSEL1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MDSEL0,MDSEL0" "0,1"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MDOUT,PMD Conduction Control Register"
|
|
bitfld.long 0x00 10. "WPWM,WPWM" "0,1"
|
|
bitfld.long 0x00 9. "VPWM,VPWM" "0,1"
|
|
bitfld.long 0x00 8. "UPWM,UPWM" "0,1"
|
|
bitfld.long 0x00 4.--5. "WOC,WOC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "VOC,VOC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "UOC,UOC" "0,1,2,3"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MDPOT,PMD Output Setting Register"
|
|
bitfld.long 0x00 8.--9. "SYNCS,SYNCS" "0,1,2,3"
|
|
bitfld.long 0x00 3. "POLH,POLH" "0,1"
|
|
bitfld.long 0x00 2. "POLL,POLL" "0,1"
|
|
bitfld.long 0x00 0.--1. "PSYNCS,PSYNCS" "0,1,2,3"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "EMGREL,PMD EMG Release Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EMGREL,EMGREL"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EMGCR,PMD EMG Control Register"
|
|
bitfld.long 0x00 8.--11. "EMGCNT,EMGCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. "INHEN,INHEN" "0,1"
|
|
bitfld.long 0x00 3.--4. "EMGMD,EMGMD" "0,1,2,3"
|
|
bitfld.long 0x00 1. "EMGRS,EMGRS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "EMGEN,EMGEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EMGCR,PMD EMG Control Register"
|
|
bitfld.long 0x00 15. "CPCIEN,CPCIEN" "0,1"
|
|
bitfld.long 0x00 14. "CPBIEN,CPBIEN" "0,1"
|
|
bitfld.long 0x00 13. "CPAIEN,CPAIEN" "0,1"
|
|
bitfld.long 0x00 8.--12. "EMGCNT,EMGCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 7. "EMGPOL,EMGPOL" "0,1"
|
|
bitfld.long 0x00 5. "INHEN,INHEN" "0,1"
|
|
bitfld.long 0x00 3.--4. "EMGMD,EMGMD" "0,1,2,3"
|
|
bitfld.long 0x00 2. "EMGISEL,EMGISEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EMGRS,EMGRS" "0,1"
|
|
bitfld.long 0x00 0. "EMGEN,EMGEN" "0,1"
|
|
endif
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EMGSTA,PMD EMG Status Register"
|
|
bitfld.long 0x00 1. "EMGI,EMGI" "0,1"
|
|
bitfld.long 0x00 0. "EMGST,EMGST" "0,1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "OVVCR,PMD OVV Control Register"
|
|
bitfld.long 0x00 15. "OVVRSMD,OVVRSMD" "0,1"
|
|
bitfld.long 0x00 8.--12. "OVVCNT,OVVCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 7. "OVVIPOL,OVVIPOL" "0,1"
|
|
bitfld.long 0x00 6. "ADIN1EN,ADIN1EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ADIN0EN,ADIN0EN" "0,1"
|
|
bitfld.long 0x00 3.--4. "OVVMD,OVVMD" "0,1,2,3"
|
|
bitfld.long 0x00 2. "OVVISEL,OVVISEL" "0,1"
|
|
bitfld.long 0x00 1. "OVVRS,OVVRS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OVVEN,OVVEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "OVVCR,PMD OVV Control Register"
|
|
bitfld.long 0x00 8.--11. "OVVCNT,OVVCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "ADIN1EN,ADIN1EN" "0,1"
|
|
bitfld.long 0x00 5. "ADIN0EN,ADIN0EN" "0,1"
|
|
bitfld.long 0x00 3.--4. "OVVMD,OVVMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2. "OVVISEL,OVVISEL" "0,1"
|
|
bitfld.long 0x00 1. "OVVRS,OVVRS" "0,1"
|
|
bitfld.long 0x00 0. "OVVEN,OVVEN" "0,1"
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "OVVSTA,PMD OVV Status Register"
|
|
bitfld.long 0x00 1. "OVVI,OVVI" "0,1"
|
|
bitfld.long 0x00 0. "OVVST,OVVST" "0,1"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DTR,PMD Dead Time Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTR,DTR"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DTR,PMD Dead Time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "DTR,DTR"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRGCMP0,PMD Trigger Compare Register 0"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP0,TRGCMP0"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRGCMP0,PMD Trigger Compare Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "TRGCMP0,TRGCMP0"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRGCMP1,PMD Trigger Compare Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "TRGCMP1,TRGCMP1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRGCMP1,PMD Trigger Compare Register 1"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP1,TRGCMP1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRGCMP2,PMD Trigger Compare Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "TRGCMP2,TRGCMP2"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRGCMP2,PMD Trigger Compare Register 2"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP2,TRGCMP2"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRGCMP3,PMD Trigger Compare Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "TRGCMP3,TRGCMP3"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRGCMP3,PMD Trigger Compare Register 3"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP3,TRGCMP3"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRGCR,PMD Trigger Control Register"
|
|
bitfld.long 0x00 16. "CARSEL,CARSEL" "0,1"
|
|
bitfld.long 0x00 15. "TRG3BE,TRG3BE" "0,1"
|
|
bitfld.long 0x00 12.--14. "TRG3MD,TRG3MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "TRG2BE,TRG2BE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TRG2MD,TRG2MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "TRG1BE,TRG1BE" "0,1"
|
|
bitfld.long 0x00 4.--6. "TRG1MD,TRG1MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "TRG0BE,TRG0BE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "TRG0MD,TRG0MD" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRGCR,PMD Trigger Control Register"
|
|
bitfld.long 0x00 15. "TRG3BE,TRG3BE" "0,1"
|
|
bitfld.long 0x00 12.--14. "TRG3MD,TRG3MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "TRG2BE,TRG2BE" "0,1"
|
|
bitfld.long 0x00 8.--10. "TRG2MD,TRG2MD" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. "TRG1BE,TRG1BE" "0,1"
|
|
bitfld.long 0x00 4.--6. "TRG1MD,TRG1MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "TRG0BE,TRG0BE" "0,1"
|
|
bitfld.long 0x00 0.--2. "TRG0MD,TRG0MD" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRGMD,PMD Trigger Output Mode Setting Register"
|
|
bitfld.long 0x00 1. "TRGOUT,TRGOUT" "0,1"
|
|
bitfld.long 0x00 0. "EMGTGE,EMGTGE" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRGSEL,PMD Trigger Output Select Register"
|
|
bitfld.long 0x00 0.--2. "TRGSEL,TRGSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRGSYNCR,PMD Trigger Update Timing Setting Register"
|
|
bitfld.long 0x00 0.--1. "TSYNCS,TSYNCS" "0,1,2,3"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "VPWMPH,Phase difference setting of the V-phase PWM"
|
|
hexmask.long.word 0x00 0.--14. 1. "VPWMPH,VPWMPH"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "WPWMPH,Phase difference setting of the W-phase PWM"
|
|
hexmask.long.word 0x00 0.--14. 1. "WPWMPH,WPWMPH"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MBUFCR,Update timing of the triple buffer"
|
|
bitfld.long 0x00 0.--2. "BUFCTR,BUFCTR" "0,1,2,3,4,5,6,7"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "SYNCCR,Synchronization control between the PMD channel"
|
|
bitfld.long 0x00 6.--7. "OVVSMD,OVVSMD" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "EMGSMD,EMGSMD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "PWMSMD,PWMSMD" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DBGOUTCR,Debug output control"
|
|
bitfld.long 0x00 31. "INIFF,INIFF" "0,1"
|
|
bitfld.long 0x00 21. "TRG5EN,TRG5EN" "0,1"
|
|
bitfld.long 0x00 20. "TRG4EN,TRG4EN" "0,1"
|
|
bitfld.long 0x00 19. "TRG3EN,TRG3EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TRG2EN,TRG2EN" "0,1"
|
|
bitfld.long 0x00 17. "TRG1EN,TRG1EN" "0,1"
|
|
bitfld.long 0x00 16. "TRG0EN,TRG0EN" "0,1"
|
|
bitfld.long 0x00 12. "IENCEN,IENCEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IVEEN,IVEEN" "0,1"
|
|
bitfld.long 0x00 10. "IOVVEN,IOVVEN" "0,1"
|
|
bitfld.long 0x00 9. "IADGEN,IADGEN" "0,1"
|
|
bitfld.long 0x00 8. "IADFEN,IADFEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IADEEN,IADEEN" "0,1"
|
|
bitfld.long 0x00 6. "IADDEN,IADDEN" "0,1"
|
|
bitfld.long 0x00 5. "IADCEN,IADCEN" "0,1"
|
|
bitfld.long 0x00 4. "IADBEN,IADBEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IADAEN,IADAEN" "0,1"
|
|
bitfld.long 0x00 1.--2. "DBGMD,DBGMD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "DBGEN,DBGEN" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G9*")||cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")
|
|
tree "SDA (SD)"
|
|
base ad:0x400F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EN,Interval Sencing Detector(ISD)"
|
|
bitfld.long 0x00 0. "EN,EN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CLKCR,Clock Control Register"
|
|
bitfld.long 0x00 2.--3. "DIV,DIV" "0,1,2,3"
|
|
bitfld.long 0x00 1. "SC,SC" "0,1"
|
|
bitfld.long 0x00 0. "MS,MS" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OCR0,Output Control Register 0"
|
|
bitfld.long 0x00 0. "SDOP,SDOP" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OCR1,Output Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "T2,T2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "T1,T1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "T0,T0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ICR,Input Control Register"
|
|
bitfld.long 0x00 12.--14. "I3M,I3M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "I2M,I2M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "I1M,I1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "I0M,I0M" "0,1,2,3,4,5,6,7"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 0. "START,START" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BR,Buffer Register"
|
|
bitfld.long 0x00 0.--3. "B0,B0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 0.--3. "S0,S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "INTCR,Interrupu Control Register"
|
|
bitfld.long 0x00 0. "INTEN,INTEN" "0,1"
|
|
tree.end
|
|
tree "SDB (SD)"
|
|
base ad:0x400F0100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EN,Interval Sencing Detector(ISD)"
|
|
bitfld.long 0x00 0. "EN,EN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CLKCR,Clock Control Register"
|
|
bitfld.long 0x00 2.--3. "DIV,DIV" "0,1,2,3"
|
|
bitfld.long 0x00 1. "SC,SC" "0,1"
|
|
bitfld.long 0x00 0. "MS,MS" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OCR0,Output Control Register 0"
|
|
bitfld.long 0x00 0. "SDOP,SDOP" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OCR1,Output Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "T2,T2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "T1,T1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "T0,T0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ICR,Input Control Register"
|
|
bitfld.long 0x00 12.--14. "I3M,I3M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "I2M,I2M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "I1M,I1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "I0M,I0M" "0,1,2,3,4,5,6,7"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 0. "START,START" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BR,Buffer Register"
|
|
bitfld.long 0x00 0.--3. "B0,B0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 0.--3. "S0,S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "INTCR,Interrupu Control Register"
|
|
bitfld.long 0x00 0. "INTEN,INTEN" "0,1"
|
|
tree.end
|
|
tree "SDC (SD)"
|
|
base ad:0x400F0200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EN,Interval Sencing Detector(ISD)"
|
|
bitfld.long 0x00 0. "EN,EN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CLKCR,Clock Control Register"
|
|
bitfld.long 0x00 2.--3. "DIV,DIV" "0,1,2,3"
|
|
bitfld.long 0x00 1. "SC,SC" "0,1"
|
|
bitfld.long 0x00 0. "MS,MS" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OCR0,Output Control Register 0"
|
|
bitfld.long 0x00 0. "SDOP,SDOP" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OCR1,Output Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "T2,T2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "T1,T1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "T0,T0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ICR,Input Control Register"
|
|
bitfld.long 0x00 12.--14. "I3M,I3M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "I2M,I2M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "I1M,I1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "I0M,I0M" "0,1,2,3,4,5,6,7"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 0. "START,START" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BR,Buffer Register"
|
|
bitfld.long 0x00 0.--3. "B0,B0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 0.--3. "S0,S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "INTCR,Interrupu Control Register"
|
|
bitfld.long 0x00 0. "INTEN,INTEN" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "FC"
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")||cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x5DFF0000
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SBMR,Flash Security Bit Mask Register"
|
|
bitfld.long 0x00 0. "SMB,SMB" "0,1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SSR,Flash Security Status Register"
|
|
rbitfld.long 0x00 0. "SEC,SEC" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SSR,Flash Security Status Register"
|
|
bitfld.long 0x00 0. "SEC,SEC" "0,1"
|
|
endif
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "KCR,Flash Key Code Register"
|
|
hexmask.long 0x00 0.--31. 1. "KEYCODE,KEYCODE"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SR0,Flash Status Register 0"
|
|
rbitfld.long 0x00 10. "RDYBSY2,RDYBSY2" "0,1"
|
|
rbitfld.long 0x00 9. "RDYBSY1,RDYBSY1" "0,1"
|
|
rbitfld.long 0x00 8. "RDYBSY0,RDYBSY0" "0,1"
|
|
rbitfld.long 0x00 0. "RDYBSY,RDYBSY" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SR0,Flash Status Register 0"
|
|
rbitfld.long 0x00 8. "RDYBSY0,RDYBSY0" "0,1"
|
|
rbitfld.long 0x00 0. "RDYBSY,RDYBSY" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SR0,Flash Status Register 0"
|
|
bitfld.long 0x00 8. "RDYBSY0,RDYBSY0" "0,1"
|
|
bitfld.long 0x00 0. "RDYBSY,RDYBSY" "0,1"
|
|
endif
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "PSR0,Flash Protect Status Register 0"
|
|
bitfld.long 0x00 7. "PG7,PG7" "0,1"
|
|
bitfld.long 0x00 6. "PG6,PG6" "0,1"
|
|
bitfld.long 0x00 5. "PG5,PG5" "0,1"
|
|
bitfld.long 0x00 4. "PG4,PG4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PG3,PG3" "0,1"
|
|
bitfld.long 0x00 2. "PG2,PG2" "0,1"
|
|
bitfld.long 0x00 1. "PG1,PG1" "0,1"
|
|
bitfld.long 0x00 0. "PG0,PG0" "0,1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "PSR1,Flash Protect Status Register 1"
|
|
bitfld.long 0x00 31. "BLK31,BLK31" "0,1"
|
|
bitfld.long 0x00 30. "BLK30,BLK30" "0,1"
|
|
bitfld.long 0x00 29. "BLK29,BLK29" "0,1"
|
|
bitfld.long 0x00 28. "BLK28,BLK28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "BLK27,BLK27" "0,1"
|
|
bitfld.long 0x00 26. "BLK26,BLK26" "0,1"
|
|
bitfld.long 0x00 25. "BLK25,BLK25" "0,1"
|
|
bitfld.long 0x00 24. "BLK24,BLK24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "BLK23,BLK23" "0,1"
|
|
bitfld.long 0x00 22. "BLK22,BLK22" "0,1"
|
|
bitfld.long 0x00 21. "BLK21,BLK21" "0,1"
|
|
bitfld.long 0x00 20. "BLK20,BLK20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "BLK19,BLK19" "0,1"
|
|
bitfld.long 0x00 18. "BLK18,BLK18" "0,1"
|
|
bitfld.long 0x00 17. "BLK17,BLK17" "0,1"
|
|
bitfld.long 0x00 16. "BLK16,BLK16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "BLK15,BLK15" "0,1"
|
|
bitfld.long 0x00 14. "BLK14,BLK14" "0,1"
|
|
bitfld.long 0x00 13. "BLK13,BLK13" "0,1"
|
|
bitfld.long 0x00 12. "BLK12,BLK12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BLK11,BLK11" "0,1"
|
|
bitfld.long 0x00 10. "BLK10,BLK10" "0,1"
|
|
bitfld.long 0x00 9. "BLK9,BLK9" "0,1"
|
|
bitfld.long 0x00 8. "BLK8,BLK8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BLK7,BLK7" "0,1"
|
|
bitfld.long 0x00 6. "BLK6,BLK6" "0,1"
|
|
bitfld.long 0x00 5. "BLK5,BLK5" "0,1"
|
|
bitfld.long 0x00 4. "BLK4,BLK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BLK3,BLK3" "0,1"
|
|
bitfld.long 0x00 2. "BLK2,BLK2" "0,1"
|
|
bitfld.long 0x00 1. "BLK1,BLK1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "PSR1,Flash Protect Status Register 1"
|
|
bitfld.long 0x00 7. "BLK7,BLK7" "0,1"
|
|
bitfld.long 0x00 6. "BLK6,BLK6" "0,1"
|
|
bitfld.long 0x00 5. "BLK5,BLK5" "0,1"
|
|
bitfld.long 0x00 4. "BLK4,BLK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BLK3,BLK3" "0,1"
|
|
bitfld.long 0x00 2. "BLK2,BLK2" "0,1"
|
|
bitfld.long 0x00 1. "BLK1,BLK1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "PSR1,Flash Protect Status Register 1"
|
|
bitfld.long 0x00 3. "BLK3,BLK3" "0,1"
|
|
bitfld.long 0x00 2. "BLK2,BLK2" "0,1"
|
|
bitfld.long 0x00 1. "BLK1,BLK1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "PSR1,Flash Protect Status Register 1"
|
|
bitfld.long 0x00 1. "BLK1,BLK1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PSR3,Flash Protect Status Register 3"
|
|
bitfld.long 0x00 7. "PG7,PG7" "0,1"
|
|
bitfld.long 0x00 6. "PG6,PG6" "0,1"
|
|
bitfld.long 0x00 5. "PG5,PG5" "0,1"
|
|
bitfld.long 0x00 4. "PG4,PG4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PG3,PG3" "0,1"
|
|
bitfld.long 0x00 2. "PG2,PG2" "0,1"
|
|
bitfld.long 0x00 1. "PG1,PG1" "0,1"
|
|
bitfld.long 0x00 0. "PG0,PG0" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "PSR4,Flash Protect Status Register 4"
|
|
bitfld.long 0x00 15. "BLK15,BLK15" "0,1"
|
|
bitfld.long 0x00 14. "BLK14,BLK14" "0,1"
|
|
bitfld.long 0x00 13. "BLK13,BLK13" "0,1"
|
|
bitfld.long 0x00 12. "BLK12,BLK12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BLK11,BLK11" "0,1"
|
|
bitfld.long 0x00 10. "BLK10,BLK10" "0,1"
|
|
bitfld.long 0x00 9. "BLK9,BLK9" "0,1"
|
|
bitfld.long 0x00 8. "BLK8,BLK8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BLK7,BLK7" "0,1"
|
|
bitfld.long 0x00 6. "BLK6,BLK6" "0,1"
|
|
bitfld.long 0x00 5. "BLK5,BLK5" "0,1"
|
|
bitfld.long 0x00 4. "BLK4,BLK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BLK3,BLK3" "0,1"
|
|
bitfld.long 0x00 2. "BLK2,BLK2" "0,1"
|
|
bitfld.long 0x00 1. "BLK1,BLK1" "0,1"
|
|
bitfld.long 0x00 0. "BLK0,BLK0" "0,1"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "PSR6,Flash Protect Status Register 6"
|
|
bitfld.long 0x00 7. "DBLK7,DBLK7" "0,1"
|
|
bitfld.long 0x00 6. "DBLK6,DBLK6" "0,1"
|
|
bitfld.long 0x00 5. "DBLK5,DBLK5" "0,1"
|
|
bitfld.long 0x00 4. "DBLK4,DBLK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DBLK3,DBLK3" "0,1"
|
|
bitfld.long 0x00 2. "DBLK2,DBLK2" "0,1"
|
|
bitfld.long 0x00 1. "DBLK1,DBLK1" "0,1"
|
|
bitfld.long 0x00 0. "DBLK0,DBLK0" "0,1"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PMR0,Flash Protect Mask Register 0"
|
|
bitfld.long 0x00 7. "PM7,PM7" "0,1"
|
|
bitfld.long 0x00 6. "PM6,PM6" "0,1"
|
|
bitfld.long 0x00 5. "PM5,PM5" "0,1"
|
|
bitfld.long 0x00 4. "PM4,PM4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PM3,PM3" "0,1"
|
|
bitfld.long 0x00 2. "PM2,PM2" "0,1"
|
|
bitfld.long 0x00 1. "PM1,PM1" "0,1"
|
|
bitfld.long 0x00 0. "PM0,PM0" "0,1"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PMR1,Flash Protect Mask Register 1"
|
|
bitfld.long 0x00 31. "MSK31,MSK31" "0,1"
|
|
bitfld.long 0x00 30. "MSK30,MSK30" "0,1"
|
|
bitfld.long 0x00 29. "MSK29,MSK29" "0,1"
|
|
bitfld.long 0x00 28. "MSK28,MSK28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "MSK27,MSK27" "0,1"
|
|
bitfld.long 0x00 26. "MSK26,MSK26" "0,1"
|
|
bitfld.long 0x00 25. "MSK25,MSK25" "0,1"
|
|
bitfld.long 0x00 24. "MSK24,MSK24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "MSK23,MSK23" "0,1"
|
|
bitfld.long 0x00 22. "MSK22,MSK22" "0,1"
|
|
bitfld.long 0x00 21. "MSK21,MSK21" "0,1"
|
|
bitfld.long 0x00 20. "MSK20,MSK20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "MSK19,MSK19" "0,1"
|
|
bitfld.long 0x00 18. "MSK18,MSK18" "0,1"
|
|
bitfld.long 0x00 17. "MSK17,MSK17" "0,1"
|
|
bitfld.long 0x00 16. "MSK16,MSK16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "MSK15,MSK15" "0,1"
|
|
bitfld.long 0x00 14. "MSK14,MSK14" "0,1"
|
|
bitfld.long 0x00 13. "MSK13,MSK13" "0,1"
|
|
bitfld.long 0x00 12. "MSK12,MSK12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "MSK11,MSK11" "0,1"
|
|
bitfld.long 0x00 10. "MSK10,MSK10" "0,1"
|
|
bitfld.long 0x00 9. "MSK9,MSK9" "0,1"
|
|
bitfld.long 0x00 8. "MSK8,MSK8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "MSK7,MSK7" "0,1"
|
|
bitfld.long 0x00 6. "MSK6,MSK6" "0,1"
|
|
bitfld.long 0x00 5. "MSK5,MSK5" "0,1"
|
|
bitfld.long 0x00 4. "MSK4,MSK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MSK3,MSK3" "0,1"
|
|
bitfld.long 0x00 2. "MSK2,MSK2" "0,1"
|
|
bitfld.long 0x00 1. "MSK1,MSK1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PMR1,Flash Protect Mask Register 1"
|
|
bitfld.long 0x00 7. "MSK7,MSK7" "0,1"
|
|
bitfld.long 0x00 6. "MSK6,MSK6" "0,1"
|
|
bitfld.long 0x00 5. "MSK5,MSK5" "0,1"
|
|
bitfld.long 0x00 4. "MSK4,MSK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MSK3,MSK3" "0,1"
|
|
bitfld.long 0x00 2. "MSK2,MSK2" "0,1"
|
|
bitfld.long 0x00 1. "MSK1,MSK1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PMR1,Flash Protect Mask Register 1"
|
|
bitfld.long 0x00 3. "MSK3,MSK3" "0,1"
|
|
bitfld.long 0x00 2. "MSK2,MSK2" "0,1"
|
|
bitfld.long 0x00 1. "MSK1,MSK1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PMR1,Flash Protect Mask Register 1"
|
|
bitfld.long 0x00 1. "MSK1,MSK1" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PMR3,Flash Protect Mask Register 3"
|
|
bitfld.long 0x00 7. "MSK7,MSK7" "0,1"
|
|
bitfld.long 0x00 6. "MSK6,MSK6" "0,1"
|
|
bitfld.long 0x00 5. "MSK5,MSK5" "0,1"
|
|
bitfld.long 0x00 4. "MSK4,MSK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MSK3,MSK3" "0,1"
|
|
bitfld.long 0x00 2. "MSK2,MSK2" "0,1"
|
|
bitfld.long 0x00 1. "MSK1,MSK1" "0,1"
|
|
bitfld.long 0x00 0. "MSK0,MSK0" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PMR4,Flash Protect Mask Register 4"
|
|
bitfld.long 0x00 15. "MSK15,MSK15" "0,1"
|
|
bitfld.long 0x00 14. "MSK14,MSK14" "0,1"
|
|
bitfld.long 0x00 13. "MSK13,MSK13" "0,1"
|
|
bitfld.long 0x00 12. "MSK12,MSK12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "MSK11,MSK11" "0,1"
|
|
bitfld.long 0x00 10. "MSK10,MSK10" "0,1"
|
|
bitfld.long 0x00 9. "MSK9,MSK9" "0,1"
|
|
bitfld.long 0x00 8. "MSK8,MSK8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "MSK7,MSK7" "0,1"
|
|
bitfld.long 0x00 6. "MSK6,MSK6" "0,1"
|
|
bitfld.long 0x00 5. "MSK5,MSK5" "0,1"
|
|
bitfld.long 0x00 4. "MSK4,MSK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MSK3,MSK3" "0,1"
|
|
bitfld.long 0x00 2. "MSK2,MSK2" "0,1"
|
|
bitfld.long 0x00 1. "MSK1,MSK1" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PMR6,Flash Protect Mask Register 6"
|
|
bitfld.long 0x00 7. "DMSK7,DMSK7" "0,1"
|
|
bitfld.long 0x00 6. "DMSK6,DMSK6" "0,1"
|
|
bitfld.long 0x00 5. "DMSK5,DMSK5" "0,1"
|
|
bitfld.long 0x00 4. "DMSK4,DMSK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DMSK3,DMSK3" "0,1"
|
|
bitfld.long 0x00 2. "DMSK2,DMSK2" "0,1"
|
|
bitfld.long 0x00 1. "DMSK1,DMSK1" "0,1"
|
|
bitfld.long 0x00 0. "DMSK0,DMSK0" "0,1"
|
|
endif
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "SR1,Flash Status Register 1"
|
|
bitfld.long 0x00 24. "WEABORT,WEABORT" "0,1"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "SWPSR,Flash Memory SWP Status Register"
|
|
bitfld.long 0x00 8.--13. "SIZE,SIZE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. "SWP,SWP" "0,1,2,3"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "AREASEL,Flash Area Selection Register"
|
|
rbitfld.long 0x00 30. "SSF4,SSF4" "0,1"
|
|
rbitfld.long 0x00 28. "SSF2,SSF2" "0,1"
|
|
rbitfld.long 0x00 27. "SSF1,SSF1" "0,1"
|
|
rbitfld.long 0x00 26. "SSF0,SSF0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "AREA4,AREA4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "AREA2,AREA2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "AREA1,AREA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "AREA0,AREA0" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "AREASEL,Flash Area Selection Register"
|
|
rbitfld.long 0x00 26. "SSF0,SSF0" "0,1"
|
|
bitfld.long 0x00 0.--2. "AREA0,AREA0" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "CR,Flash Control Register"
|
|
bitfld.long 0x00 0.--2. "WEABORT,WEABORT" "0,1,2,3,4,5,6,7"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "STSCLR,Flash Status Clear Register"
|
|
bitfld.long 0x00 0.--2. "WEABORT,WEABORT" "0,1,2,3,4,5,6,7"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "BNKCR,Flash Bank Change Register"
|
|
bitfld.long 0x00 0.--2. "BANK0,BANK0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "BUFDISCLR,Flash Buffer Disable and Clear Register"
|
|
bitfld.long 0x00 0.--2. "BUFDISCLR,BUFDISCLR" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x5DFF0000
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SBMR,Flash Security Bit Mask Register"
|
|
bitfld.long 0x00 0. "SMB,SMB" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SSR,Flash Security Status Register"
|
|
bitfld.long 0x00 0. "SEC,SEC" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "KCR,Flash Key Code Register"
|
|
hexmask.long 0x00 0.--31. 1. "KEYCODE,KEYCODE"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SR0,Flash Status Register 0"
|
|
bitfld.long 0x00 10. "RDYBSY2,RDYBSY2" "0,1"
|
|
bitfld.long 0x00 8. "RDYBSY0,RDYBSY0" "0,1"
|
|
bitfld.long 0x00 0. "RDYBSY,RDYBSY" "0,1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "PSR0,Flash Protect Status Register 0"
|
|
bitfld.long 0x00 7. "PG7,PG7" "0,1"
|
|
bitfld.long 0x00 6. "PG6,PG6" "0,1"
|
|
bitfld.long 0x00 5. "PG5,PG5" "0,1"
|
|
bitfld.long 0x00 4. "PG4,PG4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PG3,PG3" "0,1"
|
|
bitfld.long 0x00 2. "PG2,PG2" "0,1"
|
|
bitfld.long 0x00 1. "PG1,PG1" "0,1"
|
|
bitfld.long 0x00 0. "PG0,PG0" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "PSR1,Flash Protect Status Register 1"
|
|
bitfld.long 0x00 15. "BLK15,BLK15" "0,1"
|
|
bitfld.long 0x00 14. "BLK14,BLK14" "0,1"
|
|
bitfld.long 0x00 13. "BLK13,BLK13" "0,1"
|
|
bitfld.long 0x00 12. "BLK12,BLK12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BLK11,BLK11" "0,1"
|
|
bitfld.long 0x00 10. "BLK10,BLK10" "0,1"
|
|
bitfld.long 0x00 9. "BLK9,BLK9" "0,1"
|
|
bitfld.long 0x00 8. "BLK8,BLK8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BLK7,BLK7" "0,1"
|
|
bitfld.long 0x00 6. "BLK6,BLK6" "0,1"
|
|
bitfld.long 0x00 5. "BLK5,BLK5" "0,1"
|
|
bitfld.long 0x00 4. "BLK4,BLK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BLK3,BLK3" "0,1"
|
|
bitfld.long 0x00 2. "BLK2,BLK2" "0,1"
|
|
bitfld.long 0x00 1. "BLK1,BLK1" "0,1"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "PSR6,Flash Protect Status Register 6"
|
|
bitfld.long 0x00 7. "DBLK7,DBLK7" "0,1"
|
|
bitfld.long 0x00 6. "DBLK6,DBLK6" "0,1"
|
|
bitfld.long 0x00 5. "DBLK5,DBLK5" "0,1"
|
|
bitfld.long 0x00 4. "DBLK4,DBLK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DBLK3,DBLK3" "0,1"
|
|
bitfld.long 0x00 2. "DBLK2,DBLK2" "0,1"
|
|
bitfld.long 0x00 1. "DBLK1,DBLK1" "0,1"
|
|
bitfld.long 0x00 0. "DBLK0,DBLK0" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PMR0,Flash Protect Mask Register 0"
|
|
bitfld.long 0x00 7. "PM7,PM7" "0,1"
|
|
bitfld.long 0x00 6. "PM6,PM6" "0,1"
|
|
bitfld.long 0x00 5. "PM5,PM5" "0,1"
|
|
bitfld.long 0x00 4. "PM4,PM4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PM3,PM3" "0,1"
|
|
bitfld.long 0x00 2. "PM2,PM2" "0,1"
|
|
bitfld.long 0x00 1. "PM1,PM1" "0,1"
|
|
bitfld.long 0x00 0. "PM0,PM0" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PMR1,Flash Protect Mask Register 1"
|
|
bitfld.long 0x00 15. "MSK15,MSK15" "0,1"
|
|
bitfld.long 0x00 14. "MSK14,MSK14" "0,1"
|
|
bitfld.long 0x00 13. "MSK13,MSK13" "0,1"
|
|
bitfld.long 0x00 12. "MSK12,MSK12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "MSK11,MSK11" "0,1"
|
|
bitfld.long 0x00 10. "MSK10,MSK10" "0,1"
|
|
bitfld.long 0x00 9. "MSK9,MSK9" "0,1"
|
|
bitfld.long 0x00 8. "MSK8,MSK8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "MSK7,MSK7" "0,1"
|
|
bitfld.long 0x00 6. "MSK6,MSK6" "0,1"
|
|
bitfld.long 0x00 5. "MSK5,MSK5" "0,1"
|
|
bitfld.long 0x00 4. "MSK4,MSK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MSK3,MSK3" "0,1"
|
|
bitfld.long 0x00 2. "MSK2,MSK2" "0,1"
|
|
bitfld.long 0x00 1. "MSK1,MSK1" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PMR6,Flash Protect Mask Register 6"
|
|
bitfld.long 0x00 7. "DMSK7,DMSK7" "0,1"
|
|
bitfld.long 0x00 6. "DMSK6,DMSK6" "0,1"
|
|
bitfld.long 0x00 5. "DMSK5,DMSK5" "0,1"
|
|
bitfld.long 0x00 4. "DMSK4,DMSK4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DMSK3,DMSK3" "0,1"
|
|
bitfld.long 0x00 2. "DMSK2,DMSK2" "0,1"
|
|
bitfld.long 0x00 1. "DMSK1,DMSK1" "0,1"
|
|
bitfld.long 0x00 0. "DMSK0,DMSK0" "0,1"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "SR1,Flash Status Register 1"
|
|
bitfld.long 0x00 24. "WEABORT,WEABORT" "0,1"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "SWPSR,Flash Memory SWAP Status Register"
|
|
bitfld.long 0x00 8.--13. "SIZE,SIZE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. "SWP,SWP" "0,1,2,3"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "AREASEL,Flash Area Selection Register"
|
|
rbitfld.long 0x00 30. "SSF4,SSF4" "0,1"
|
|
rbitfld.long 0x00 26. "SSF0,SSF0" "0,1"
|
|
bitfld.long 0x00 16.--18. "AREA4,AREA4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "AREA0,AREA0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "CR,Flash Control Register"
|
|
bitfld.long 0x00 0.--2. "WEABORT,WEABORT" "0,1,2,3,4,5,6,7"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "STSCLR,Flash Status Clear Register"
|
|
bitfld.long 0x00 0.--2. "WEABORT,WEABORT" "0,1,2,3,4,5,6,7"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "BNKCR,Flash Bank Change Register"
|
|
bitfld.long 0x00 0.--2. "BANK0,BANK0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "BUFDISCLR,Flash Buffer Disable and Clear Register"
|
|
bitfld.long 0x00 0.--2. "BUFDISCLR,BUFDISCLR" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
tree.end
|
|
sif cpuis("TMPM4G6*")||cpuis("TMPM4G7*")
|
|
tree "FURT (ARM Prime Cell PL011)"
|
|
base ad:0x400A8000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Data Register"
|
|
rbitfld.long 0x00 11. "OE,OE" "0,1"
|
|
rbitfld.long 0x00 10. "BE,BE" "0,1"
|
|
rbitfld.long 0x00 9. "PE,PE" "0,1"
|
|
rbitfld.long 0x00 8. "FE,FE" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,DATA"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 3. "OE,OE" "0,1"
|
|
bitfld.long 0x00 2. "BE,BE" "0,1"
|
|
bitfld.long 0x00 1. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0. "FE,FE" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "ECR,Error Clear Register"
|
|
bitfld.long 0x00 3. "OE,OE" "0,1"
|
|
bitfld.long 0x00 2. "BE,BE" "0,1"
|
|
bitfld.long 0x00 1. "PE,PE" "0,1"
|
|
bitfld.long 0x00 0. "FE,FE" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FR,Flag Register"
|
|
bitfld.long 0x00 8. "RI,RI" "0,1"
|
|
bitfld.long 0x00 7. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x00 6. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x00 5. "TXFF,TXFF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RXFE,RXFE" "0,1"
|
|
bitfld.long 0x00 3. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x00 2. "DCD,DCD" "0,1"
|
|
bitfld.long 0x00 1. "DSR,DSR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CTS,CTS" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ILPR,IrDA Low-power Counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IPLDVSR,IPLDVSR"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IBDR,Integer Baud Rate Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "BAUDDIVINT,BAUDDIVINT"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FBDR,Fractional Baud Rate Register"
|
|
bitfld.long 0x00 0.--5. "BAUDDIVFRAC,BAUDDIVFRAC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "LCR_H,Line Control Register"
|
|
bitfld.long 0x00 7. "SPS,SPS" "0,1"
|
|
bitfld.long 0x00 5.--6. "WLEN,WLEN" "0,1,2,3"
|
|
bitfld.long 0x00 4. "FEN,FEN" "0,1"
|
|
bitfld.long 0x00 3. "STP2,STP2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "EPS,EPS" "0,1"
|
|
bitfld.long 0x00 1. "PEN,PEN" "0,1"
|
|
bitfld.long 0x00 0. "BRK,BRK" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CR,Cntrol Register"
|
|
bitfld.long 0x00 15. "CTSEN,CTSEN" "0,1"
|
|
bitfld.long 0x00 14. "RTSEN,RTSEN" "0,1"
|
|
bitfld.long 0x00 13. "OUT2,OUT2" "0,1"
|
|
bitfld.long 0x00 12. "OUT1,OUT1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RTS,RTS" "0,1"
|
|
bitfld.long 0x00 10. "DTR,DTR" "0,1"
|
|
bitfld.long 0x00 9. "RXE,RXE" "0,1"
|
|
bitfld.long 0x00 8. "TXE,TXE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "LBE,LBE" "0,1"
|
|
bitfld.long 0x00 2. "SIRLP,SIRLP" "0,1"
|
|
bitfld.long 0x00 1. "SIREN,SIREN" "0,1"
|
|
bitfld.long 0x00 0. "UARTEN,UARTEN" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IFLS,Interrupt FIFO Level Select Register"
|
|
bitfld.long 0x00 3.--5. "RXIFLSEL,RXIFLSEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TXIFLSEL,TXIFLSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IMSC,Interrupt Mask set_Clear Register"
|
|
bitfld.long 0x00 10. "OEIM,OEIM" "0,1"
|
|
bitfld.long 0x00 9. "BEIM,BEIM" "0,1"
|
|
bitfld.long 0x00 8. "PEIM,PEIM" "0,1"
|
|
bitfld.long 0x00 7. "FEIM,FEIM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTIM,RTIM" "0,1"
|
|
bitfld.long 0x00 5. "TXIM,TXIM" "0,1"
|
|
bitfld.long 0x00 4. "RXIM,RXIM" "0,1"
|
|
bitfld.long 0x00 3. "DSRMIM,DSRMIM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDMIM,DCDMIM" "0,1"
|
|
bitfld.long 0x00 1. "CTSMIM,CTSMIM" "0,1"
|
|
bitfld.long 0x00 0. "RIMIM,RIMIM" "0,1"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 10. "OERIS,OERIS" "0,1"
|
|
bitfld.long 0x00 9. "BERIS,BERIS" "0,1"
|
|
bitfld.long 0x00 8. "PERIS,PERIS" "0,1"
|
|
bitfld.long 0x00 7. "FERIS,FERIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTRIS,RTRIS" "0,1"
|
|
bitfld.long 0x00 5. "TXRIS,TXRIS" "0,1"
|
|
bitfld.long 0x00 4. "RXRIS,RXRIS" "0,1"
|
|
bitfld.long 0x00 3. "DSRRMIS,DSRRMIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDRMIS,DCDRMIS" "0,1"
|
|
bitfld.long 0x00 1. "CTSRMIS,CTSRMIS" "0,1"
|
|
bitfld.long 0x00 0. "RIRMIS,RIRMIS" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x00 10. "OEMIS,OEMIS" "0,1"
|
|
bitfld.long 0x00 9. "BEMIS,BEMIS" "0,1"
|
|
bitfld.long 0x00 8. "PEMIS,PEMIS" "0,1"
|
|
bitfld.long 0x00 7. "FEMIS,FEMIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTMIS,RTMIS" "0,1"
|
|
bitfld.long 0x00 5. "TXMIS,TXMIS" "0,1"
|
|
bitfld.long 0x00 4. "RXMIS,RXMIS" "0,1"
|
|
bitfld.long 0x00 3. "DSRMMIS,DSRMMIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDMMIS,DCDMMIS" "0,1"
|
|
bitfld.long 0x00 1. "CTSMMIS,CTSMMIS" "0,1"
|
|
bitfld.long 0x00 0. "RIMMIS,RIMMIS" "0,1"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 10. "OEIC,OEIC" "0,1"
|
|
bitfld.long 0x00 9. "BEIC,BEIC" "0,1"
|
|
bitfld.long 0x00 8. "PEIC,PEIC" "0,1"
|
|
bitfld.long 0x00 7. "FEIC,FEIC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RTIC,RTIC" "0,1"
|
|
bitfld.long 0x00 5. "TXIC,TXIC" "0,1"
|
|
bitfld.long 0x00 4. "RXIC,RXIC" "0,1"
|
|
bitfld.long 0x00 3. "DSRMIC,DSRMIC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDMIC,DCDMIC" "0,1"
|
|
bitfld.long 0x00 1. "CTSMIC,CTSMIC" "0,1"
|
|
bitfld.long 0x00 0. "RIMIC,RIMIC" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMACR,DMA Control Register"
|
|
bitfld.long 0x00 2. "DMAONERR,DMAONERR" "0,1"
|
|
bitfld.long 0x00 1. "TXDMAE,TXDMAE" "0,1"
|
|
bitfld.long 0x00 0. "RXDMAE,RXDMAE" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4G8*")
|
|
tree "RMC (Remote Control Signal Preprocessor (RMC))"
|
|
base ad:0x400E8100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EN,RMC Enable Register"
|
|
bitfld.long 0x00 0. "RMCEN,RMCEN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "REN,RMC Receive Enable Register"
|
|
bitfld.long 0x00 0. "RMCREN,RMCREN" "0,1"
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
rgroup.long ($2+0x08)++0x03
|
|
line.long 0x00 "RBUF$1,RMC Receive Data Buffer Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "RMCRBUF,RMCRBUF"
|
|
repeat.end
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RBUF3,RMC Receive Data Buffer Register 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RMCRBUF,RMCRBUF"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RCR1,RMC Receive Control Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RMCLCMAX,RMCLCMAX"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RMCLCMIN,RMCLCMIN"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RMCLLMAX,RMCLLMAX"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RMCLLMIN,RMCLLMIN"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RCR2,RMC Receive Control Register 2"
|
|
bitfld.long 0x00 31. "RMCLIEN,RMCLIEN" "0,1"
|
|
bitfld.long 0x00 30. "RMCEDIEN,RMCEDIEN" "0,1"
|
|
bitfld.long 0x00 25. "RMCLD,RMCLD" "0,1"
|
|
bitfld.long 0x00 24. "RMCPHM,RMCPHM" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RMCLL,RMCLL"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RMCDMAX,RMCDMAX"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RCR3,RMC Receive Control Register 3"
|
|
hexmask.long.byte 0x00 8.--14. 1. "RMCDATH,RMCDATH"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RMCDATL,RMCDATL"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RCR4,RMC Receive Control Register 4"
|
|
bitfld.long 0x00 7. "RMCPO,RMCPO" "0,1"
|
|
bitfld.long 0x00 0.--3. "RMCNC,RMCNC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RSTAT,RMC Receive Status Register"
|
|
bitfld.long 0x00 15. "RMCRLIF,RMCRLIF" "0,1"
|
|
bitfld.long 0x00 14. "RMCLOIF,RMCLOIF" "0,1"
|
|
bitfld.long 0x00 13. "RMCDMAXIF,RMCDMAXIF" "0,1"
|
|
bitfld.long 0x00 12. "RMCEDIF,RMCEDIF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RMCRLDR,RMCRLDR" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RMCRNUM,RMCRNUM"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "END1,RMC Receive End Bit Number Register 1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RMCEND1,RMCEND1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "END2,RMC Receive End Bit Number Register 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RMCEND2,RMCEND2"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "END3,RMC Receive End Bit Number Register 3"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RMCEND3,RMCEND3"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FSSEL,RMC Frequency Selection Register"
|
|
bitfld.long 0x00 0. "RMCCLK,RMCCLK" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "DMA (DMA Controller)"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x4004C000
|
|
elif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400A4000
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "STATUS,DMA Status Register"
|
|
bitfld.long 0x00 0. "MASTER_ENABLE,MASTER_ENABLE" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. "MASTER_ENABLE,MASTER_ENABLE" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRLBASEPTR,DMA Control Data Base Pointer Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "CTRL_BASE_PTR,CTRL_BASE_PTR"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ALTCTRLBASEPTR,DMA Channel Alternate Control Data Base Pointer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ALT_CTRL_BASE_PTR,ALT_CTRL_BASE_PTR"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "CHNLSWREQUEST,DMA Channel Software Request Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHNL_SW_REQUEST,CHNL_SW_REQUEST"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CHNLUSEBURSTSET,DMA Channel Useburst Set Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHNL_USEBURST_SET,CHNL_USEBURST_SET"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CHNLUSEBURSTCLR,DMA Channel Useburst Clear Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHNL_USEBURST_CLR,CHNL_USEBURST_CLR"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CHNLREQMASKSET,DMA Channel Request Mask Set Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHNL_REQ_MASK_SET,CHNL_REQ_MASK_SET"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "CHNLREQMASKCLR,DMA Channel Request Mask Clear Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHNL_REQ_MASK_CLR,CHNL_REQ_MASK_CLR"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CHNLENABLESET,DMA Channel Enable Set Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHNL_ENABLE_SET,CHNL_ENABLE_SET"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "CHNLENABLECLR,DMA Channel Enable Clear Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHNL_ENABLE_CLR,CHNL_ENABLE_CLR"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CHNLPRIALTSET,DMA Channel Primary-Alternate Set Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHNL_PRI_ALT_SET,CHNL_PRI_ALT_SET"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "CHNLPRIALTCLR,DMA Channel Primary-Alternate Clear Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHNL_PRI_ALT_CLR,CHNL_PRI_ALT_CLR"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CHNLPRIORITYSET,DMA Channel Priority Set Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHNL_PRIORITY_SET,CHNL_PRIORITY_SET"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "CHNLPRIORITYCLR,DMA Channel Priority Clear Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHNL_PRIORITY_CLR,CHNL_PRIORITY_CLR"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ERRCLR,DMA Bus Error Clear Register"
|
|
bitfld.long 0x00 0. "ERR_CLR,ERR_CLR" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")
|
|
tree "TSPI (Serial Interface (TSPI))"
|
|
base ad:0x4009A000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,TSPI Control Register 0"
|
|
bitfld.long 0x00 6.--7. "SWRST,SWRST" "0,1,2,3"
|
|
bitfld.long 0x00 0. "TSPIE,TSPIE" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,TSPI Control Register 1"
|
|
bitfld.long 0x00 15. "TRGEN,TRGEN" "0,1"
|
|
bitfld.long 0x00 14. "TRXE,TRXE" "0,1"
|
|
bitfld.long 0x00 13. "TSPIMS,TSPIMS" "0,1"
|
|
bitfld.long 0x00 12. "MSTR,MSTR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "TMMD,TMMD" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CSSEL,CSSEL" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FC,FC"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,TSPI Control Register 2"
|
|
bitfld.long 0x00 22.--23. "TIDLE,TIDLE" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TXDEMP,TXDEMP" "0,1"
|
|
bitfld.long 0x00 16. "RXDLY,RXDLY" "0,1"
|
|
bitfld.long 0x00 12.--15. "TIL,TIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RIL,RIL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "INTTXFE,INTTXFE" "0,1"
|
|
bitfld.long 0x00 6. "INTTXWE,INTTXWE" "0,1"
|
|
bitfld.long 0x00 5. "INTRXFE,INTRXFE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "INTRXWE,INTRXWE" "0,1"
|
|
bitfld.long 0x00 2. "INTERR,INTERR" "0,1"
|
|
bitfld.long 0x00 1. "DMATE,DMATE" "0,1"
|
|
bitfld.long 0x00 0. "DMARE,DMARE" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR3,TSPI Control Register 3"
|
|
bitfld.long 0x00 1. "TFEMPCLR,TFEMPCLR" "0,1"
|
|
bitfld.long 0x00 0. "RFFLLCLR,RFFLLCLR" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BR,TSPI Baud Rate Generator Control Register"
|
|
bitfld.long 0x00 4.--7. "BRCK,BRCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "BRS,BRS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMTR0,TSPI Format Control Register 0"
|
|
bitfld.long 0x00 31. "DIR,DIR" "0,1"
|
|
bitfld.long 0x00 24.--29. "FL,FL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. "FINT,FINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "CS3POL,CS3POL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CS2POL,CS2POL" "0,1"
|
|
bitfld.long 0x00 17. "CS1POL,CS1POL" "0,1"
|
|
bitfld.long 0x00 16. "CS0POL,CS0POL" "0,1"
|
|
bitfld.long 0x00 15. "CKPHA,CKPHA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CKPOL,CKPOL" "0,1"
|
|
bitfld.long 0x00 10.--13. "CSINT,CSINT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "CSSCKDL,CSSCKDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCKCSDL,SCKCSDL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FMTR1,TSPI Format Control Register 1"
|
|
bitfld.long 0x00 4.--6. "EHOLD,EHOLD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "VPE,VPE" "0,1"
|
|
bitfld.long 0x00 0. "VPM,VPM" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DR,TSPI Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSPIDR,TSPIDR"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SR,TSPI Status Register"
|
|
rbitfld.long 0x00 31. "TSPISUE,TSPISUE" "0,1"
|
|
rbitfld.long 0x00 23. "TXRUN,TXRUN" "0,1"
|
|
bitfld.long 0x00 22. "TXEND,TXEND" "0,1"
|
|
bitfld.long 0x00 21. "INTTXWF,INTTXWF" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "TFEMP,TFEMP" "0,1"
|
|
rbitfld.long 0x00 16.--19. "TLVL,TLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 7. "RXRUN,RXRUN" "0,1"
|
|
bitfld.long 0x00 6. "RXEND,RXEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "INTRXFF,INTRXFF" "0,1"
|
|
rbitfld.long 0x00 4. "RFFLL,RFFLL" "0,1"
|
|
rbitfld.long 0x00 0.--3. "RLVL,RLVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ERR,TSPI Parity Error Flag Register"
|
|
bitfld.long 0x00 3. "TRGERR,TRGERR" "0,1"
|
|
bitfld.long 0x00 2. "UDRERR,UDRERR" "0,1"
|
|
bitfld.long 0x00 1. "OVRERR,OVRERR" "0,1"
|
|
bitfld.long 0x00 0. "PERR,PERR" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
tree "SH (Sampl-and-hold circuit)"
|
|
base ad:0x400B8700
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TRGPAT,Trigger input switching control"
|
|
bitfld.long 0x00 2.--3. "TRGPAT1,TRGPAT1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "TRGPAT0,TRGPAT0" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "DNF"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400BB600
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40040200
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CKCR,DNF clock Control register"
|
|
bitfld.long 0x00 0.--2. "NFCKS,NFCKS" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("TMPM4K0A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ENCR,DNF Enable register"
|
|
bitfld.long 0x00 5. "NFEN5,NFEN5" "0,1"
|
|
bitfld.long 0x00 4. "NFEN4,NFEN4" "0,1"
|
|
bitfld.long 0x00 3. "NFEN3,NFEN3" "0,1"
|
|
bitfld.long 0x00 2. "NFEN2,NFEN2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "NFEN1,NFEN1" "0,1"
|
|
bitfld.long 0x00 0. "NFEN0,NFEN0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K2A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ENCR,DNF Enable register"
|
|
bitfld.long 0x00 14. "NFEN14,NFEN14" "0,1"
|
|
bitfld.long 0x00 13. "NFEN13,NFEN13" "0,1"
|
|
bitfld.long 0x00 9. "NFEN9,NFEN9" "0,1"
|
|
bitfld.long 0x00 8. "NFEN8,NFEN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "NFEN7,NFEN7" "0,1"
|
|
bitfld.long 0x00 6. "NFEN6,NFEN6" "0,1"
|
|
bitfld.long 0x00 5. "NFEN5,NFEN5" "0,1"
|
|
bitfld.long 0x00 4. "NFEN4,NFEN4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "NFEN3,NFEN3" "0,1"
|
|
bitfld.long 0x00 2. "NFEN2,NFEN2" "0,1"
|
|
bitfld.long 0x00 1. "NFEN1,NFEN1" "0,1"
|
|
bitfld.long 0x00 0. "NFEN0,NFEN0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K4A*")||cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ENCR,DNF Enable register"
|
|
bitfld.long 0x00 15. "NFEN15,NFEN15" "0,1"
|
|
bitfld.long 0x00 14. "NFEN14,NFEN14" "0,1"
|
|
bitfld.long 0x00 13. "NFEN13,NFEN13" "0,1"
|
|
bitfld.long 0x00 12. "NFEN12,NFEN12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "NFEN11,NFEN11" "0,1"
|
|
bitfld.long 0x00 10. "NFEN10,NFEN10" "0,1"
|
|
bitfld.long 0x00 9. "NFEN9,NFEN9" "0,1"
|
|
bitfld.long 0x00 8. "NFEN8,NFEN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "NFEN7,NFEN7" "0,1"
|
|
bitfld.long 0x00 6. "NFEN6,NFEN6" "0,1"
|
|
bitfld.long 0x00 5. "NFEN5,NFEN5" "0,1"
|
|
bitfld.long 0x00 4. "NFEN4,NFEN4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "NFEN3,NFEN3" "0,1"
|
|
bitfld.long 0x00 2. "NFEN2,NFEN2" "0,1"
|
|
bitfld.long 0x00 1. "NFEN1,NFEN1" "0,1"
|
|
bitfld.long 0x00 0. "NFEN0,NFEN0" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ENCR,DNF Enable register"
|
|
bitfld.long 0x00 14. "NFEN14,NFEN14" "0,1"
|
|
bitfld.long 0x00 13. "NFEN13,NFEN13" "0,1"
|
|
bitfld.long 0x00 8. "NFEN8,NFEN8" "0,1"
|
|
bitfld.long 0x00 7. "NFEN7,NFEN7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "NFEN6,NFEN6" "0,1"
|
|
bitfld.long 0x00 5. "NFEN5,NFEN5" "0,1"
|
|
bitfld.long 0x00 4. "NFEN4,NFEN4" "0,1"
|
|
bitfld.long 0x00 3. "NFEN3,NFEN3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "NFEN2,NFEN2" "0,1"
|
|
bitfld.long 0x00 1. "NFEN1,NFEN1" "0,1"
|
|
bitfld.long 0x00 0. "NFEN0,NFEN0" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "RPAR (RAM Parity)"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400BBB00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,RAMM Parity control register"
|
|
bitfld.long 0x00 1. "RPARF,RPARF" "0,1"
|
|
bitfld.long 0x00 0. "RPAREN,RPAREN" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ST,RAMM Parity status register"
|
|
bitfld.long 0x00 2. "RPARFG2,RPARFG2" "0,1"
|
|
bitfld.long 0x00 1. "RPARFG1,RPARFG1" "0,1"
|
|
bitfld.long 0x00 0. "RPARFG0,RPARFG0" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CLR,RAMM Parity status clear register"
|
|
bitfld.long 0x00 2. "RPARCLR2,RPARCLR2" "0,1"
|
|
bitfld.long 0x00 1. "RPARCLR1,RPARCLR1" "0,1"
|
|
bitfld.long 0x00 0. "RPARCLR0,RPARCLR0" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "EAD0,RAMM Parity Error address register 0"
|
|
hexmask.long 0x00 0.--31. 1. "RPAREADD0,RPAREADD0"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "EAD1,RAMM Parity Error address register 1"
|
|
hexmask.long 0x00 0.--31. 1. "RPAREADD1,RPAREADD1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "EAD2,RAMM Parity Error address register 2"
|
|
hexmask.long 0x00 0.--31. 1. "RPAREADD2,RPAREADD2"
|
|
endif
|
|
sif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40043000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,RAMM Parity control register"
|
|
bitfld.long 0x00 1. "RPARF,RPARF" "0,1"
|
|
bitfld.long 0x00 0. "RPAREN,RPAREN" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ST,RAMM Parity status register"
|
|
bitfld.long 0x00 1. "RPARFG1,RPARFG1" "0,1"
|
|
bitfld.long 0x00 0. "RPARFG0,RPARFG0" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CLR,RAMM Parity status clear register"
|
|
bitfld.long 0x00 1. "RPARCLR1,RPARCLR1" "0,1"
|
|
bitfld.long 0x00 0. "RPARCLR0,RPARCLR0" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "EAD0,RAMM Parity Error address register 0"
|
|
hexmask.long 0x00 0.--31. 1. "RPAREADD0,RPAREADD0"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "CRC"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400BBC00
|
|
elif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40043100
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DIN,CRC input data register"
|
|
hexmask.long 0x00 0.--31. 1. "CRCDIN,CRCDIN"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TYP,CRC data type register"
|
|
bitfld.long 0x00 2.--3. "CFMT,CFMT" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "DBIT,DBIT" "0,1,2,3"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CLC,CRC calculation result register"
|
|
hexmask.long 0x00 0.--31. 1. "CRCCLC,CRCCLC"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "AMP"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400BC000
|
|
elif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400BD000
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTLA,AMP control register A"
|
|
bitfld.long 0x00 1.--4. "AMPGAIN,AMPGAIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "AMPEN,AMPEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTLB,AMP control register B"
|
|
bitfld.long 0x00 1.--4. "AMPGAIN,AMPGAIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "AMPEN,AMPEN" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTLC,AMP control register C"
|
|
bitfld.long 0x00 1.--4. "AMPGAIN,AMPGAIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "AMPEN,AMPEN" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "TRM (TRIM)"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400F3200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "OSCPRO,TRM Protect register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PROTECT,PROTECT"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OSCEN,TRM Enable register"
|
|
bitfld.long 0x00 0. "TRIMEN,TRIMEN" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "OSCINIT,TRM Initial trimming level monitor register"
|
|
bitfld.long 0x00 8.--13. "TRIMINITC,TRIMINITC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "TRIMINITF,TRIMINITF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OSCSET,TRM Trimming level setting register"
|
|
bitfld.long 0x00 8.--13. "TRIMSETC,TRIMSETC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "TRIMSETF,TRIMSETF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400E3100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "OSCPRO,Protection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PROTECT,PROTECT"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OSCEN,TRM Enable Register"
|
|
bitfld.long 0x00 0. "TRIMEN,TRIMEN" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "OSCINIT,TRM Initial Trimming Level Monitor Register"
|
|
bitfld.long 0x00 8.--13. "TRIMINITC,TRIMINITC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "TRIMINITF,TRIMINITF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OSCSET,TRM Trimming Level Setting Register"
|
|
bitfld.long 0x00 8.--13. "TRIMSETC,TRIMSETC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "TRIMSETF,TRIMSETF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x40083100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "OSCPRO,TRM Protection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PROTECT,PROTECT"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OSCEN,TRM Enable Register"
|
|
bitfld.long 0x00 0. "TRIMEN,TRIMEN" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "OSCINIT,TRM Initial Trimming Level Monitor Register"
|
|
bitfld.long 0x00 8.--13. "TRIMINITC,TRIMINITC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "TRIMINITF,TRIMINITF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OSCSET,TRM Trimming Level Setting Register"
|
|
bitfld.long 0x00 8.--13. "TRIMSETC,TRIMSETC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "TRIMSETF,TRIMSETF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "PMD (A-PMD)"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
tree "PMD0"
|
|
base ad:0x400F6000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MDEN,PMD Enable Register"
|
|
bitfld.long 0x00 0. "PWMEN,PWMEN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PORTMD,PMD Port Output Mode Register"
|
|
bitfld.long 0x00 0.--1. "PORTMD,PORTMD" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MDCR,PMD Control Register"
|
|
bitfld.long 0x00 14.--15. "WPWMMD,WPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "VPWMMD,VPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "UPWMMD,UPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "DSYNCS,DSYNCS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "DTCREN,DTCREN" "0,1"
|
|
bitfld.long 0x00 6. "DCMEN,DCMEN" "0,1"
|
|
bitfld.long 0x00 5. "SYNTMD,SYNTMD" "0,1"
|
|
bitfld.long 0x00 4. "DTYMD,DTYMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PINT,PINT" "0,1"
|
|
bitfld.long 0x00 1.--2. "INTPRD,INTPRD" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CARSTA,PWM Carrier Status Register"
|
|
bitfld.long 0x00 2. "PWMWST,PWMWST" "0,1"
|
|
bitfld.long 0x00 1. "PWMVST,PWMVST" "0,1"
|
|
bitfld.long 0x00 0. "PWMUST,PWMUST" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BCARI,PWM Basic Carrier Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "BCARI,BCARI"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RATE,PWM Frequency Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "RATE,RATE"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CMPU,PMD PWM Compare U Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPU,CMPU"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CMPV,PMD PWM Compare V Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPV,CMPV"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPW,PMD PWM Compare W Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPW,CMPW"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODESEL,PMD Mode Select Register"
|
|
bitfld.long 0x00 7. "DCMPEN,DCMPEN" "0,1"
|
|
bitfld.long 0x00 3. "MDSEL3,MDSEL3" "0,1"
|
|
bitfld.long 0x00 2. "MDSEL2,MDSEL2" "0,1"
|
|
bitfld.long 0x00 1. "MDSEL1,MDSEL1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MDSEL0,MDSEL0" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MDOUT,PMD Conduction Control Register"
|
|
bitfld.long 0x00 10. "WPWM,WPWM" "0,1"
|
|
bitfld.long 0x00 9. "VPWM,VPWM" "0,1"
|
|
bitfld.long 0x00 8. "UPWM,UPWM" "0,1"
|
|
bitfld.long 0x00 4.--5. "WOC,WOC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "VOC,VOC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "UOC,UOC" "0,1,2,3"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MDPOT,PMD Output Setting Register"
|
|
bitfld.long 0x00 8.--9. "SYNCS,SYNCS" "0,1,2,3"
|
|
bitfld.long 0x00 3. "POLH,POLH" "0,1"
|
|
bitfld.long 0x00 2. "POLL,POLL" "0,1"
|
|
bitfld.long 0x00 0.--1. "PSYNCS,PSYNCS" "0,1,2,3"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "EMGREL,PMD EMG Release Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EMGREL,EMGREL"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EMGCR,PMD EMG Control Register"
|
|
bitfld.long 0x00 15. "CPCIEN,CPCIEN" "0,1"
|
|
bitfld.long 0x00 14. "CPBIEN,CPBIEN" "0,1"
|
|
bitfld.long 0x00 13. "CPAIEN,CPAIEN" "0,1"
|
|
bitfld.long 0x00 8.--12. "EMGCNT,EMGCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5. "INHEN,INHEN" "0,1"
|
|
bitfld.long 0x00 3.--4. "EMGMD,EMGMD" "0,1,2,3"
|
|
bitfld.long 0x00 1. "EMGRS,EMGRS" "0,1"
|
|
bitfld.long 0x00 0. "EMGEN,EMGEN" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EMGSTA,PMD EMG Status Register"
|
|
bitfld.long 0x00 1. "EMGI,EMGI" "0,1"
|
|
bitfld.long 0x00 0. "EMGST,EMGST" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "OVVCR,PMD OVV Control Register"
|
|
bitfld.long 0x00 15. "OVVRSMD,OVVRSMD" "0,1"
|
|
bitfld.long 0x00 8.--12. "OVVCNT,OVVCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "OVVIPOL,OVVIPOL" "0,1"
|
|
bitfld.long 0x00 6. "ADIN1EN,ADIN1EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ADIN0EN,ADIN0EN" "0,1"
|
|
bitfld.long 0x00 3.--4. "OVVMD,OVVMD" "0,1,2,3"
|
|
bitfld.long 0x00 2. "OVVISEL,OVVISEL" "0,1"
|
|
bitfld.long 0x00 1. "OVVRS,OVVRS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OVVEN,OVVEN" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "OVVSTA,PMD OVV Status Register"
|
|
bitfld.long 0x00 1. "OVVI,OVVI" "0,1"
|
|
bitfld.long 0x00 0. "OVVST,OVVST" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DTR,PMD Dead Time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "DTR,DTR"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRGCMP0,PMD Trigger Compare Register 0"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP0,TRGCMP0"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRGCMP1,PMD Trigger Compare Register 1"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP1,TRGCMP1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRGCMP2,PMD Trigger Compare Register 2"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP2,TRGCMP2"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRGCMP3,PMD Trigger Compare Register 3"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP3,TRGCMP3"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRGCR,PMD Trigger Control Register"
|
|
bitfld.long 0x00 16. "CARSEL,CARSEL" "0,1"
|
|
bitfld.long 0x00 15. "TRG3BE,TRG3BE" "0,1"
|
|
bitfld.long 0x00 12.--14. "TRG3MD,TRG3MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "TRG2BE,TRG2BE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TRG2MD,TRG2MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "TRG1BE,TRG1BE" "0,1"
|
|
bitfld.long 0x00 4.--6. "TRG1MD,TRG1MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "TRG0BE,TRG0BE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "TRG0MD,TRG0MD" "0,1,2,3,4,5,6,7"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRGMD,PMD Trigger Output Mode Setting Register"
|
|
bitfld.long 0x00 1. "TRGOUT,TRGOUT" "0,1"
|
|
bitfld.long 0x00 0. "EMGTGE,EMGTGE" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRGSEL,PMD Trigger Output Select Register"
|
|
bitfld.long 0x00 0.--2. "TRGSEL,TRGSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRGSYNCR,PMD Trigger Update Timing Setting Register"
|
|
bitfld.long 0x00 0.--1. "TSYNCS,TSYNCS" "0,1,2,3"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "VPWMPH,Phase difference setting of the V-phase PWM"
|
|
hexmask.long.word 0x00 0.--14. 1. "VPWMPH,VPWMPH"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "WPWMPH,Phase difference setting of the W-phase PWM"
|
|
hexmask.long.word 0x00 0.--14. 1. "WPWMPH,WPWMPH"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MBUFCR,Update timing of the triple buffer"
|
|
bitfld.long 0x00 0.--2. "BUFCTR,BUFCTR" "0,1,2,3,4,5,6,7"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "SYNCCR,Synchronization control between the PMD channel"
|
|
bitfld.long 0x00 6.--7. "OVVSMD,OVVSMD" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "EMGSMD,EMGSMD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "PWMSMD,PWMSMD" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DBGOUTCR,Debug output control"
|
|
bitfld.long 0x00 31. "INIFF,INIFF" "0,1"
|
|
bitfld.long 0x00 21. "TRG5EN,TRG5EN" "0,1"
|
|
bitfld.long 0x00 20. "TRG4EN,TRG4EN" "0,1"
|
|
bitfld.long 0x00 19. "TRG3EN,TRG3EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TRG2EN,TRG2EN" "0,1"
|
|
bitfld.long 0x00 17. "TRG1EN,TRG1EN" "0,1"
|
|
bitfld.long 0x00 16. "TRG0EN,TRG0EN" "0,1"
|
|
bitfld.long 0x00 12. "IENCEN,IENCEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IVEEN,IVEEN" "0,1"
|
|
bitfld.long 0x00 10. "IOVVEN,IOVVEN" "0,1"
|
|
bitfld.long 0x00 9. "IEMGEN,IEMGEN" "0,1"
|
|
bitfld.long 0x00 8. "IPMDEN,IPMDEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IADEEN,IADEEN" "0,1"
|
|
bitfld.long 0x00 6. "IADDEN,IADDEN" "0,1"
|
|
bitfld.long 0x00 5. "IADCEN,IADCEN" "0,1"
|
|
bitfld.long 0x00 4. "IADBEN,IADBEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IADAEN,IADAEN" "0,1"
|
|
bitfld.long 0x00 1.--2. "DBGMD,DBGMD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "DBGEN,DBGEN" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "PMD0"
|
|
base ad:0x400E9000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MDEN,PMD Enable Register"
|
|
bitfld.long 0x00 0. "PWMEN,PWMEN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PORTMD,PMD Port Output Mode Register"
|
|
bitfld.long 0x00 0.--1. "PORTMD,PORTMD" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MDCR,PMD Control Register"
|
|
bitfld.long 0x00 14.--15. "WPWMMD,WPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "VPWMMD,VPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "UPWMMD,UPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "DSYNCS,DSYNCS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "DTCREN,DTCREN" "0,1"
|
|
bitfld.long 0x00 6. "DCMEN,DCMEN" "0,1"
|
|
bitfld.long 0x00 5. "SYNTMD,SYNTMD" "0,1"
|
|
bitfld.long 0x00 4. "DTYMD,DTYMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PINT,PINT" "0,1"
|
|
bitfld.long 0x00 1.--2. "INTPRD,INTPRD" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CARSTA,PWM Carrier Status Register"
|
|
bitfld.long 0x00 2. "PWMWST,PWMWST" "0,1"
|
|
bitfld.long 0x00 1. "PWMVST,PWMVST" "0,1"
|
|
bitfld.long 0x00 0. "PWMUST,PWMUST" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BCARI,PWM Basic Carrier Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "BCARI,BCARI"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RATE,PWM Frequency Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "RATE,RATE"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CMPU,PMD PWM Compare U Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPU,CMPU"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CMPV,PMD PWM Compare V Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPV,CMPV"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPW,PMD PWM Compare W Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPW,CMPW"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODESEL,PMD Mode Select Register"
|
|
bitfld.long 0x00 7. "DCMPEN,DCMPEN" "0,1"
|
|
bitfld.long 0x00 3. "MDSEL3,MDSEL3" "0,1"
|
|
bitfld.long 0x00 2. "MDSEL2,MDSEL2" "0,1"
|
|
bitfld.long 0x00 1. "MDSEL1,MDSEL1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MDSEL0,MDSEL0" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MDOUT,PMD Conduction Control Register"
|
|
bitfld.long 0x00 10. "WPWM,WPWM" "0,1"
|
|
bitfld.long 0x00 9. "VPWM,VPWM" "0,1"
|
|
bitfld.long 0x00 8. "UPWM,UPWM" "0,1"
|
|
bitfld.long 0x00 4.--5. "WOC,WOC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "VOC,VOC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "UOC,UOC" "0,1,2,3"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MDPOT,PMD Output Setting Register"
|
|
bitfld.long 0x00 8.--9. "SYNCS,SYNCS" "0,1,2,3"
|
|
bitfld.long 0x00 3. "POLH,POLH" "0,1"
|
|
bitfld.long 0x00 2. "POLL,POLL" "0,1"
|
|
bitfld.long 0x00 0.--1. "PSYNCS,PSYNCS" "0,1,2,3"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "EMGREL,PMD EMG Release Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EMGREL,EMGREL"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EMGCR,PMD EMG Control Register"
|
|
bitfld.long 0x00 15. "CPCIEN,CPCIEN" "0,1"
|
|
bitfld.long 0x00 14. "CPBIEN,CPBIEN" "0,1"
|
|
bitfld.long 0x00 13. "CPAIEN,CPAIEN" "0,1"
|
|
bitfld.long 0x00 8.--12. "EMGCNT,EMGCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 7. "EMGIPOL,EMGIPOL" "0,1"
|
|
bitfld.long 0x00 5. "INHEN,INHEN" "0,1"
|
|
bitfld.long 0x00 3.--4. "EMGMD,EMGMD" "0,1,2,3"
|
|
bitfld.long 0x00 2. "EMGISEL,EMGISEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EMGRS,EMGRS" "0,1"
|
|
bitfld.long 0x00 0. "EMGEN,EMGEN" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EMGSTA,PMD EMG Status Register"
|
|
bitfld.long 0x00 1. "EMGI,EMGI" "0,1"
|
|
bitfld.long 0x00 0. "EMGST,EMGST" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "OVVCR,PMD OVV Control Register"
|
|
bitfld.long 0x00 15. "OVVRSMD,OVVRSMD" "0,1"
|
|
bitfld.long 0x00 8.--12. "OVVCNT,OVVCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "OVVIPOL,OVVIPOL" "0,1"
|
|
bitfld.long 0x00 6. "ADIN1EN,ADIN1EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ADIN0EN,ADIN0EN" "0,1"
|
|
bitfld.long 0x00 3.--4. "OVVMD,OVVMD" "0,1,2,3"
|
|
bitfld.long 0x00 2. "OVVISEL,OVVISEL" "0,1"
|
|
bitfld.long 0x00 1. "OVVRS,OVVRS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OVVEN,OVVEN" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "OVVSTA,PMD OVV Status Register"
|
|
bitfld.long 0x00 1. "OVVI,OVVI" "0,1"
|
|
bitfld.long 0x00 0. "OVVST,OVVST" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DTR,PMD Dead Time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "DTR,DTR"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRGCMP0,PMD Trigger Compare Register 0"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP0,TRGCMP0"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRGCMP1,PMD Trigger Compare Register 1"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP1,TRGCMP1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRGCMP2,PMD Trigger Compare Register 2"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP2,TRGCMP2"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRGCMP3,PMD Trigger Compare Register 3"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP3,TRGCMP3"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRGCR,PMD Trigger Control Register"
|
|
bitfld.long 0x00 16. "CARSEL,CARSEL" "0,1"
|
|
bitfld.long 0x00 15. "TRG3BE,TRG3BE" "0,1"
|
|
bitfld.long 0x00 12.--14. "TRG3MD,TRG3MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "TRG2BE,TRG2BE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TRG2MD,TRG2MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "TRG1BE,TRG1BE" "0,1"
|
|
bitfld.long 0x00 4.--6. "TRG1MD,TRG1MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "TRG0BE,TRG0BE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "TRG0MD,TRG0MD" "0,1,2,3,4,5,6,7"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRGMD,PMD Trigger Output Mode Setting Register"
|
|
bitfld.long 0x00 1. "TRGOUT,TRGOUT" "0,1"
|
|
bitfld.long 0x00 0. "EMGTGE,EMGTGE" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRGSEL,PMD Trigger Output Select Register"
|
|
bitfld.long 0x00 0.--2. "TRGSEL,TRGSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRGSYNCR,PMD Trigger Update Timing Setting Register"
|
|
bitfld.long 0x00 0.--1. "TSYNCS,TSYNCS" "0,1,2,3"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "VPWMPH,PMD Phase difference setting of the V-phase PWM"
|
|
hexmask.long.word 0x00 0.--14. 1. "VPWMPH,VPWMPH"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "WPWMPH,PMD Phase difference setting of the W-phase PWM"
|
|
hexmask.long.word 0x00 0.--14. 1. "WPWMPH,WPWMPH"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MBUFCR,PMD Update timing of the triple buffer"
|
|
bitfld.long 0x00 0.--2. "BUFCTR,BUFCTR" "0,1,2,3,4,5,6,7"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "SYNCCR,PMD Synchronization control between the PMD channel"
|
|
bitfld.long 0x00 6.--7. "OVVSMD,OVVSMD" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "EMGSMD,EMGSMD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "PWMSMD,PWMSMD" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DBGOUTCR,PMD Debug output control"
|
|
bitfld.long 0x00 31. "INIFF,INIFF" "0,1"
|
|
bitfld.long 0x00 21. "TRG5EN,TRG5EN" "0,1"
|
|
bitfld.long 0x00 20. "TRG4EN,TRG4EN" "0,1"
|
|
bitfld.long 0x00 19. "TRG3EN,TRG3EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TRG2EN,TRG2EN" "0,1"
|
|
bitfld.long 0x00 17. "TRG1EN,TRG1EN" "0,1"
|
|
bitfld.long 0x00 16. "TRG0EN,TRG0EN" "0,1"
|
|
bitfld.long 0x00 12. "IENCEN,IENCEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IVEEN,IVEEN" "0,1"
|
|
bitfld.long 0x00 10. "IOVVEN,IOVVEN" "0,1"
|
|
bitfld.long 0x00 9. "IEMGEN,IEMGEN" "0,1"
|
|
bitfld.long 0x00 8. "IPMDEN,IPMDEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IADEEN,IADEEN" "0,1"
|
|
bitfld.long 0x00 6. "IADDEN,IADDEN" "0,1"
|
|
bitfld.long 0x00 5. "IADCEN,IADCEN" "0,1"
|
|
bitfld.long 0x00 4. "IADBEN,IADBEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IADAEN,IADAEN" "0,1"
|
|
bitfld.long 0x00 1.--2. "DBGMD,DBGMD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "DBGEN,DBGEN" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
tree "PMD1"
|
|
base ad:0x400F6100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MDEN,PMD Enable Register"
|
|
bitfld.long 0x00 0. "PWMEN,PWMEN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PORTMD,PMD Port Output Mode Register"
|
|
bitfld.long 0x00 0.--1. "PORTMD,PORTMD" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MDCR,PMD Control Register"
|
|
bitfld.long 0x00 14.--15. "WPWMMD,WPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "VPWMMD,VPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "UPWMMD,UPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "DSYNCS,DSYNCS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "DTCREN,DTCREN" "0,1"
|
|
bitfld.long 0x00 6. "DCMEN,DCMEN" "0,1"
|
|
bitfld.long 0x00 5. "SYNTMD,SYNTMD" "0,1"
|
|
bitfld.long 0x00 4. "DTYMD,DTYMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PINT,PINT" "0,1"
|
|
bitfld.long 0x00 1.--2. "INTPRD,INTPRD" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CARSTA,PWM Carrier Status Register"
|
|
bitfld.long 0x00 2. "PWMWST,PWMWST" "0,1"
|
|
bitfld.long 0x00 1. "PWMVST,PWMVST" "0,1"
|
|
bitfld.long 0x00 0. "PWMUST,PWMUST" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BCARI,PWM Basic Carrier Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "BCARI,BCARI"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RATE,PWM Frequency Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "RATE,RATE"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CMPU,PMD PWM Compare U Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPU,CMPU"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CMPV,PMD PWM Compare V Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPV,CMPV"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPW,PMD PWM Compare W Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPW,CMPW"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODESEL,PMD Mode Select Register"
|
|
bitfld.long 0x00 7. "DCMPEN,DCMPEN" "0,1"
|
|
bitfld.long 0x00 3. "MDSEL3,MDSEL3" "0,1"
|
|
bitfld.long 0x00 2. "MDSEL2,MDSEL2" "0,1"
|
|
bitfld.long 0x00 1. "MDSEL1,MDSEL1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MDSEL0,MDSEL0" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MDOUT,PMD Conduction Control Register"
|
|
bitfld.long 0x00 10. "WPWM,WPWM" "0,1"
|
|
bitfld.long 0x00 9. "VPWM,VPWM" "0,1"
|
|
bitfld.long 0x00 8. "UPWM,UPWM" "0,1"
|
|
bitfld.long 0x00 4.--5. "WOC,WOC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "VOC,VOC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "UOC,UOC" "0,1,2,3"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MDPOT,PMD Output Setting Register"
|
|
bitfld.long 0x00 8.--9. "SYNCS,SYNCS" "0,1,2,3"
|
|
bitfld.long 0x00 3. "POLH,POLH" "0,1"
|
|
bitfld.long 0x00 2. "POLL,POLL" "0,1"
|
|
bitfld.long 0x00 0.--1. "PSYNCS,PSYNCS" "0,1,2,3"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "EMGREL,PMD EMG Release Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EMGREL,EMGREL"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EMGCR,PMD EMG Control Register"
|
|
bitfld.long 0x00 15. "CPCIEN,CPCIEN" "0,1"
|
|
bitfld.long 0x00 14. "CPBIEN,CPBIEN" "0,1"
|
|
bitfld.long 0x00 13. "CPAIEN,CPAIEN" "0,1"
|
|
bitfld.long 0x00 8.--12. "EMGCNT,EMGCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5. "INHEN,INHEN" "0,1"
|
|
bitfld.long 0x00 3.--4. "EMGMD,EMGMD" "0,1,2,3"
|
|
bitfld.long 0x00 1. "EMGRS,EMGRS" "0,1"
|
|
bitfld.long 0x00 0. "EMGEN,EMGEN" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EMGSTA,PMD EMG Status Register"
|
|
bitfld.long 0x00 1. "EMGI,EMGI" "0,1"
|
|
bitfld.long 0x00 0. "EMGST,EMGST" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "OVVCR,PMD OVV Control Register"
|
|
bitfld.long 0x00 15. "OVVRSMD,OVVRSMD" "0,1"
|
|
bitfld.long 0x00 8.--12. "OVVCNT,OVVCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "OVVIPOL,OVVIPOL" "0,1"
|
|
bitfld.long 0x00 6. "ADIN1EN,ADIN1EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ADIN0EN,ADIN0EN" "0,1"
|
|
bitfld.long 0x00 3.--4. "OVVMD,OVVMD" "0,1,2,3"
|
|
bitfld.long 0x00 2. "OVVISEL,OVVISEL" "0,1"
|
|
bitfld.long 0x00 1. "OVVRS,OVVRS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OVVEN,OVVEN" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "OVVSTA,PMD OVV Status Register"
|
|
bitfld.long 0x00 1. "OVVI,OVVI" "0,1"
|
|
bitfld.long 0x00 0. "OVVST,OVVST" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DTR,PMD Dead Time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "DTR,DTR"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRGCMP0,PMD Trigger Compare Register 0"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP0,TRGCMP0"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRGCMP1,PMD Trigger Compare Register 1"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP1,TRGCMP1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRGCMP2,PMD Trigger Compare Register 2"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP2,TRGCMP2"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRGCMP3,PMD Trigger Compare Register 3"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP3,TRGCMP3"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRGCR,PMD Trigger Control Register"
|
|
bitfld.long 0x00 16. "CARSEL,CARSEL" "0,1"
|
|
bitfld.long 0x00 15. "TRG3BE,TRG3BE" "0,1"
|
|
bitfld.long 0x00 12.--14. "TRG3MD,TRG3MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "TRG2BE,TRG2BE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TRG2MD,TRG2MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "TRG1BE,TRG1BE" "0,1"
|
|
bitfld.long 0x00 4.--6. "TRG1MD,TRG1MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "TRG0BE,TRG0BE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "TRG0MD,TRG0MD" "0,1,2,3,4,5,6,7"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRGMD,PMD Trigger Output Mode Setting Register"
|
|
bitfld.long 0x00 1. "TRGOUT,TRGOUT" "0,1"
|
|
bitfld.long 0x00 0. "EMGTGE,EMGTGE" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRGSEL,PMD Trigger Output Select Register"
|
|
bitfld.long 0x00 0.--2. "TRGSEL,TRGSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRGSYNCR,PMD Trigger Update Timing Setting Register"
|
|
bitfld.long 0x00 0.--1. "TSYNCS,TSYNCS" "0,1,2,3"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "VPWMPH,Phase difference setting of the V-phase PWM"
|
|
hexmask.long.word 0x00 0.--14. 1. "VPWMPH,VPWMPH"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "WPWMPH,Phase difference setting of the W-phase PWM"
|
|
hexmask.long.word 0x00 0.--14. 1. "WPWMPH,WPWMPH"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MBUFCR,Update timing of the triple buffer"
|
|
bitfld.long 0x00 0.--2. "BUFCTR,BUFCTR" "0,1,2,3,4,5,6,7"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "SYNCCR,Synchronization control between the PMD channel"
|
|
bitfld.long 0x00 6.--7. "OVVSMD,OVVSMD" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "EMGSMD,EMGSMD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "PWMSMD,PWMSMD" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DBGOUTCR,Debug output control"
|
|
bitfld.long 0x00 31. "INIFF,INIFF" "0,1"
|
|
bitfld.long 0x00 21. "TRG5EN,TRG5EN" "0,1"
|
|
bitfld.long 0x00 20. "TRG4EN,TRG4EN" "0,1"
|
|
bitfld.long 0x00 19. "TRG3EN,TRG3EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TRG2EN,TRG2EN" "0,1"
|
|
bitfld.long 0x00 17. "TRG1EN,TRG1EN" "0,1"
|
|
bitfld.long 0x00 16. "TRG0EN,TRG0EN" "0,1"
|
|
bitfld.long 0x00 12. "IENCEN,IENCEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IVEEN,IVEEN" "0,1"
|
|
bitfld.long 0x00 10. "IOVVEN,IOVVEN" "0,1"
|
|
bitfld.long 0x00 9. "IEMGEN,IEMGEN" "0,1"
|
|
bitfld.long 0x00 8. "IPMDEN,IPMDEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IADEEN,IADEEN" "0,1"
|
|
bitfld.long 0x00 6. "IADDEN,IADDEN" "0,1"
|
|
bitfld.long 0x00 5. "IADCEN,IADCEN" "0,1"
|
|
bitfld.long 0x00 4. "IADBEN,IADBEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IADAEN,IADAEN" "0,1"
|
|
bitfld.long 0x00 1.--2. "DBGMD,DBGMD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "DBGEN,DBGEN" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "PMD1"
|
|
base ad:0x400E9400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MDEN,PMD Enable Register"
|
|
bitfld.long 0x00 0. "PWMEN,PWMEN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PORTMD,PMD Port Output Mode Register"
|
|
bitfld.long 0x00 0.--1. "PORTMD,PORTMD" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MDCR,PMD Control Register"
|
|
bitfld.long 0x00 14.--15. "WPWMMD,WPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "VPWMMD,VPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "UPWMMD,UPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "DSYNCS,DSYNCS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "DTCREN,DTCREN" "0,1"
|
|
bitfld.long 0x00 6. "DCMEN,DCMEN" "0,1"
|
|
bitfld.long 0x00 5. "SYNTMD,SYNTMD" "0,1"
|
|
bitfld.long 0x00 4. "DTYMD,DTYMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PINT,PINT" "0,1"
|
|
bitfld.long 0x00 1.--2. "INTPRD,INTPRD" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CARSTA,PWM Carrier Status Register"
|
|
bitfld.long 0x00 2. "PWMWST,PWMWST" "0,1"
|
|
bitfld.long 0x00 1. "PWMVST,PWMVST" "0,1"
|
|
bitfld.long 0x00 0. "PWMUST,PWMUST" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BCARI,PWM Basic Carrier Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "BCARI,BCARI"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RATE,PWM Frequency Register"
|
|
hexmask.long.word 0x00 0.--14. 1. "RATE,RATE"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CMPU,PMD PWM Compare U Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPU,CMPU"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CMPV,PMD PWM Compare V Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPV,CMPV"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPW,PMD PWM Compare W Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPW,CMPW"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODESEL,PMD Mode Select Register"
|
|
bitfld.long 0x00 7. "DCMPEN,DCMPEN" "0,1"
|
|
bitfld.long 0x00 3. "MDSEL3,MDSEL3" "0,1"
|
|
bitfld.long 0x00 2. "MDSEL2,MDSEL2" "0,1"
|
|
bitfld.long 0x00 1. "MDSEL1,MDSEL1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MDSEL0,MDSEL0" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MDOUT,PMD Conduction Control Register"
|
|
bitfld.long 0x00 10. "WPWM,WPWM" "0,1"
|
|
bitfld.long 0x00 9. "VPWM,VPWM" "0,1"
|
|
bitfld.long 0x00 8. "UPWM,UPWM" "0,1"
|
|
bitfld.long 0x00 4.--5. "WOC,WOC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "VOC,VOC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "UOC,UOC" "0,1,2,3"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MDPOT,PMD Output Setting Register"
|
|
bitfld.long 0x00 8.--9. "SYNCS,SYNCS" "0,1,2,3"
|
|
bitfld.long 0x00 3. "POLH,POLH" "0,1"
|
|
bitfld.long 0x00 2. "POLL,POLL" "0,1"
|
|
bitfld.long 0x00 0.--1. "PSYNCS,PSYNCS" "0,1,2,3"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "EMGREL,PMD EMG Release Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EMGREL,EMGREL"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EMGCR,PMD EMG Control Register"
|
|
bitfld.long 0x00 15. "CPCIEN,CPCIEN" "0,1"
|
|
bitfld.long 0x00 14. "CPBIEN,CPBIEN" "0,1"
|
|
bitfld.long 0x00 13. "CPAIEN,CPAIEN" "0,1"
|
|
bitfld.long 0x00 8.--12. "EMGCNT,EMGCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 7. "EMGIPOL,EMGIPOL" "0,1"
|
|
bitfld.long 0x00 5. "INHEN,INHEN" "0,1"
|
|
bitfld.long 0x00 3.--4. "EMGMD,EMGMD" "0,1,2,3"
|
|
bitfld.long 0x00 2. "EMGISEL,EMGISEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EMGRS,EMGRS" "0,1"
|
|
bitfld.long 0x00 0. "EMGEN,EMGEN" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "EMGSTA,PMD EMG Status Register"
|
|
bitfld.long 0x00 1. "EMGI,EMGI" "0,1"
|
|
bitfld.long 0x00 0. "EMGST,EMGST" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "OVVCR,PMD OVV Control Register"
|
|
bitfld.long 0x00 15. "OVVRSMD,OVVRSMD" "0,1"
|
|
bitfld.long 0x00 8.--12. "OVVCNT,OVVCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "OVVIPOL,OVVIPOL" "0,1"
|
|
bitfld.long 0x00 6. "ADIN1EN,ADIN1EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ADIN0EN,ADIN0EN" "0,1"
|
|
bitfld.long 0x00 3.--4. "OVVMD,OVVMD" "0,1,2,3"
|
|
bitfld.long 0x00 2. "OVVISEL,OVVISEL" "0,1"
|
|
bitfld.long 0x00 1. "OVVRS,OVVRS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OVVEN,OVVEN" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "OVVSTA,PMD OVV Status Register"
|
|
bitfld.long 0x00 1. "OVVI,OVVI" "0,1"
|
|
bitfld.long 0x00 0. "OVVST,OVVST" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DTR,PMD Dead Time Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "DTR,DTR"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRGCMP0,PMD Trigger Compare Register 0"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP0,TRGCMP0"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRGCMP1,PMD Trigger Compare Register 1"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP1,TRGCMP1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRGCMP2,PMD Trigger Compare Register 2"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP2,TRGCMP2"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRGCMP3,PMD Trigger Compare Register 3"
|
|
hexmask.long.word 0x00 0.--14. 1. "TRGCMP3,TRGCMP3"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRGCR,PMD Trigger Control Register"
|
|
bitfld.long 0x00 16. "CARSEL,CARSEL" "0,1"
|
|
bitfld.long 0x00 15. "TRG3BE,TRG3BE" "0,1"
|
|
bitfld.long 0x00 12.--14. "TRG3MD,TRG3MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "TRG2BE,TRG2BE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TRG2MD,TRG2MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "TRG1BE,TRG1BE" "0,1"
|
|
bitfld.long 0x00 4.--6. "TRG1MD,TRG1MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "TRG0BE,TRG0BE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "TRG0MD,TRG0MD" "0,1,2,3,4,5,6,7"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRGMD,PMD Trigger Output Mode Setting Register"
|
|
bitfld.long 0x00 1. "TRGOUT,TRGOUT" "0,1"
|
|
bitfld.long 0x00 0. "EMGTGE,EMGTGE" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRGSEL,PMD Trigger Output Select Register"
|
|
bitfld.long 0x00 0.--2. "TRGSEL,TRGSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRGSYNCR,PMD Trigger Update Timing Setting Register"
|
|
bitfld.long 0x00 0.--1. "TSYNCS,TSYNCS" "0,1,2,3"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "VPWMPH,PMD Phase difference setting of the V-phase PWM"
|
|
hexmask.long.word 0x00 0.--14. 1. "VPWMPH,VPWMPH"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "WPWMPH,PMD Phase difference setting of the W-phase PWM"
|
|
hexmask.long.word 0x00 0.--14. 1. "WPWMPH,WPWMPH"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MBUFCR,PMD Update timing of the triple buffer"
|
|
bitfld.long 0x00 0.--2. "BUFCTR,BUFCTR" "0,1,2,3,4,5,6,7"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "SYNCCR,PMD Synchronization control between the PMD channel"
|
|
bitfld.long 0x00 6.--7. "OVVSMD,OVVSMD" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "EMGSMD,EMGSMD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "PWMSMD,PWMSMD" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DBGOUTCR,PMD Debug output control"
|
|
bitfld.long 0x00 31. "INIFF,INIFF" "0,1"
|
|
bitfld.long 0x00 21. "TRG5EN,TRG5EN" "0,1"
|
|
bitfld.long 0x00 20. "TRG4EN,TRG4EN" "0,1"
|
|
bitfld.long 0x00 19. "TRG3EN,TRG3EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TRG2EN,TRG2EN" "0,1"
|
|
bitfld.long 0x00 17. "TRG1EN,TRG1EN" "0,1"
|
|
bitfld.long 0x00 16. "TRG0EN,TRG0EN" "0,1"
|
|
bitfld.long 0x00 12. "IENCEN,IENCEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IVEEN,IVEEN" "0,1"
|
|
bitfld.long 0x00 10. "IOVVEN,IOVVEN" "0,1"
|
|
bitfld.long 0x00 9. "IEMGEN,IEMGEN" "0,1"
|
|
bitfld.long 0x00 8. "IPMDEN,IPMDEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IADEEN,IADEEN" "0,1"
|
|
bitfld.long 0x00 6. "IADDEN,IADDEN" "0,1"
|
|
bitfld.long 0x00 5. "IADCEN,IADCEN" "0,1"
|
|
bitfld.long 0x00 4. "IADBEN,IADBEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IADAEN,IADAEN" "0,1"
|
|
bitfld.long 0x00 1.--2. "DBGMD,DBGMD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "DBGEN,DBGEN" "0,1"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "EN (Encoder Input (ENC))"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400F7000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TNCR,ENC Control Register"
|
|
bitfld.long 0x00 28. "CMPSEL,CMPSEL" "0,1"
|
|
bitfld.long 0x00 26.--27. "UDMD,UDMD" "0,1,2,3"
|
|
bitfld.long 0x00 25. "TOVMD,TOVMD" "0,1"
|
|
bitfld.long 0x00 24. "MCMPMD,MCMPMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "DECMD,DECMD" "0,1,2,3"
|
|
bitfld.long 0x00 21. "SDTEN,SDTEN" "0,1"
|
|
bitfld.long 0x00 17.--19. "MODE,MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. "P3EN,P3EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "TRGCAPMD,TRGCAPMD" "0,1"
|
|
bitfld.long 0x00 11. "SFTCAP,SFTCAP" "0,1"
|
|
bitfld.long 0x00 10. "ENCLR,ENCLR" "0,1"
|
|
bitfld.long 0x00 8.--9. "ZESEL,ZESEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "ZEN,ZEN" "0,1"
|
|
bitfld.long 0x00 6. "ENRUN,ENRUN" "0,1"
|
|
bitfld.long 0x00 0.--2. "ENDEV,ENDEV" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RELOAD,ENC Reload Compare Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "RELOADH,RELOADH"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELOADL,RELOADL"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "INT,ENC INT Compare Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "INTH,INTH"
|
|
hexmask.long.word 0x00 0.--15. 1. "INTL,INTL"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNT,ENC Counter_Capture Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "CNTH,CNTH"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNTL,CNTL"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCMP,ENC MCMP Compare Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "MCMPH,MCMPH"
|
|
hexmask.long.word 0x00 0.--15. 1. "MCMPL,MCMPL"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RATE,ENC Phase Count Rate Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RATE,RATE"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "STS,ENC Status Register"
|
|
bitfld.long 0x00 14. "REVERR,REVERR" "0,1"
|
|
bitfld.long 0x00 13. "UD,UD" "0,1"
|
|
bitfld.long 0x00 12. "ZDET,ZDET" "0,1"
|
|
bitfld.long 0x00 2. "SKPDT,SKPDT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PDERR,PDERR" "0,1"
|
|
bitfld.long 0x00 0. "INERR,INERR" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "INPCR,ENC Input Process Cntrol Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. "NCT,NCT"
|
|
bitfld.long 0x00 7. "PDSTP,PDSTP" "0,1"
|
|
bitfld.long 0x00 6. "PDSTT,PDSTT" "0,1"
|
|
bitfld.long 0x00 2. "SYNCNCZEN,SYNCNCZEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SYNCSPLMD,SYNCSPLMD" "0,1"
|
|
bitfld.long 0x00 0. "SYNCSPLEN,SYNCSPLEN" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SMPDLY,ENC Sample Delay Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SMPDLY,SMPDLY"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INPMON,ENC Input Moniter Register"
|
|
bitfld.long 0x00 6. "DETMONZ,DETMONZ" "0,1"
|
|
bitfld.long 0x00 5. "DETMONB,DETMONB" "0,1"
|
|
bitfld.long 0x00 4. "DETMONA,DETMONA" "0,1"
|
|
bitfld.long 0x00 2. "SPLMONZ,SPLMONZ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SPLMONB,SPLMONB" "0,1"
|
|
bitfld.long 0x00 0. "SPLMONA,SPLMONA" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CLKCR,ENC Sample Clock Control Register"
|
|
bitfld.long 0x00 0.--1. "SPLCKS,SPLCKS" "0,1,2,3"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTCR,ENC Interrupt Reqyest Control Register"
|
|
bitfld.long 0x00 5. "MCMPIE,MCMPIE" "0,1"
|
|
bitfld.long 0x00 4. "RLDIE,RLDIE" "0,1"
|
|
bitfld.long 0x00 3. "CMPIE,CMPIE" "0,1"
|
|
bitfld.long 0x00 2. "ERRIE,ERRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CAPIE,CAPIE" "0,1"
|
|
bitfld.long 0x00 0. "TPLSIE,TPLSIE" "0,1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INTF,ENC Interrupt Event Flag Register"
|
|
bitfld.long 0x00 5. "MCMPF,MCMPF" "0,1"
|
|
bitfld.long 0x00 4. "RLDCPF,RLDCPF" "0,1"
|
|
bitfld.long 0x00 3. "INTCPF,INTCPF" "0,1"
|
|
bitfld.long 0x00 2. "ERRF,ERRF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CAPF,CAPF" "0,1"
|
|
bitfld.long 0x00 0. "TPLSF,TPLSF" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4L*")
|
|
base ad:0x400EA800
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x4008A000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TNCR,ENC Control Register"
|
|
bitfld.long 0x00 28. "CMPSEL,CMPSEL" "0,1"
|
|
bitfld.long 0x00 26.--27. "UDMD,UDMD" "0,1,2,3"
|
|
bitfld.long 0x00 25. "TOVMD,TOVMD" "0,1"
|
|
bitfld.long 0x00 24. "MCMPMD,MCMPMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "DECMD,DECMD" "0,1,2,3"
|
|
bitfld.long 0x00 21. "SDTEN,SDTEN" "0,1"
|
|
bitfld.long 0x00 17.--19. "MODE,MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. "P3EN,P3EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "TRGCAPMD,TRGCAPMD" "0,1"
|
|
bitfld.long 0x00 11. "SFTCAP,SFTCAP" "0,1"
|
|
bitfld.long 0x00 10. "ENCLR,ENCLR" "0,1"
|
|
bitfld.long 0x00 8.--9. "ZESEL,ZESEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "ZEN,ZEN" "0,1"
|
|
bitfld.long 0x00 6. "ENRUN,ENRUN" "0,1"
|
|
bitfld.long 0x00 5. "ZEACT,ZEACT" "0,1"
|
|
bitfld.long 0x00 0.--2. "ENDEV,ENDEV" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RELOAD,ENC Reload Compare Register"
|
|
hexmask.long 0x00 0.--31. 1. "RELOAD,RELOAD"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "INT,ENC INT Compare Register"
|
|
hexmask.long 0x00 0.--31. 1. "INT,INT"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CNT,ENC Counter_Capture Register"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,CNT"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCMP,ENC MCMP Compare Register"
|
|
hexmask.long 0x00 0.--31. 1. "MCMP,MCMP"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RATE,ENC Phase Count Rate Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RATE,RATE"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "STS,ENC Status Register"
|
|
bitfld.long 0x00 14. "REVERR,REVERR" "0,1"
|
|
bitfld.long 0x00 13. "UD,UD" "0,1"
|
|
bitfld.long 0x00 12. "ZDET,ZDET" "0,1"
|
|
bitfld.long 0x00 2. "SKPDT,SKPDT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PDERR,PDERR" "0,1"
|
|
bitfld.long 0x00 0. "INERR,INERR" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "INPCR,ENC Input Process Cntrol Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. "NCT,NCT"
|
|
bitfld.long 0x00 7. "PDSTP,PDSTP" "0,1"
|
|
bitfld.long 0x00 6. "PDSTT,PDSTT" "0,1"
|
|
bitfld.long 0x00 2. "SYNCNCZEN,SYNCNCZEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SYNCSPLMD,SYNCSPLMD" "0,1"
|
|
bitfld.long 0x00 0. "SYNCSPLEN,SYNCSPLEN" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SMPDLY,ENC Sample Delay Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SMPDLY,SMPDLY"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INPMON,ENC Input Moniter Register"
|
|
bitfld.long 0x00 6. "DETMONZ,DETMONZ" "0,1"
|
|
bitfld.long 0x00 5. "DETMONB,DETMONB" "0,1"
|
|
bitfld.long 0x00 4. "DETMONA,DETMONA" "0,1"
|
|
bitfld.long 0x00 2. "SPLMONZ,SPLMONZ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SPLMONB,SPLMONB" "0,1"
|
|
bitfld.long 0x00 0. "SPLMONA,SPLMONA" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CLKCR,ENC Sample Clock Control Register"
|
|
bitfld.long 0x00 0.--1. "SPLCKS,SPLCKS" "0,1,2,3"
|
|
sif cpuis("TMPM4L*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTCR,ENC Interrupt Control Register"
|
|
bitfld.long 0x00 5. "MCMPIE,MCMPIE" "0,1"
|
|
bitfld.long 0x00 4. "RLDIE,RLDIE" "0,1"
|
|
bitfld.long 0x00 3. "CMPIE,CMPIE" "0,1"
|
|
bitfld.long 0x00 2. "ERRIE,ERRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CAPIE,CAPIE" "0,1"
|
|
bitfld.long 0x00 0. "TPLSIE,TPLSIE" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTCR,ENC Interrupt Reqyest Control Register"
|
|
bitfld.long 0x00 5. "MCMPIE,MCMPIE" "0,1"
|
|
bitfld.long 0x00 4. "RLDIE,RLDIE" "0,1"
|
|
bitfld.long 0x00 3. "CMPIE,CMPIE" "0,1"
|
|
bitfld.long 0x00 2. "ERRIE,ERRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CAPIE,CAPIE" "0,1"
|
|
bitfld.long 0x00 0. "TPLSIE,TPLSIE" "0,1"
|
|
endif
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INTF,ENC Interrupt Event Flag Register"
|
|
bitfld.long 0x00 5. "MCMPF,MCMPF" "0,1"
|
|
bitfld.long 0x00 4. "RLDCPF,RLDCPF" "0,1"
|
|
bitfld.long 0x00 3. "INTCPF,INTCPF" "0,1"
|
|
bitfld.long 0x00 2. "ERRF,ERRF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CAPF,CAPF" "0,1"
|
|
bitfld.long 0x00 0. "TPLSF,TPLSF" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")||cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "VE"
|
|
sif cpuis("TMPM4K0A*")||cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
base ad:0x400F8000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EN,VE enable_disable"
|
|
bitfld.long 0x00 0. "VEEN,VEEN" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CPURUNTRG,CPU start trigger selection"
|
|
bitfld.long 0x00 0. "VCPURT,VCPURT" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TASKAPP,Task selection"
|
|
bitfld.long 0x00 8.--11. "VITASK,VITASK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "VTASK,VTASK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ACTSCH,Operation schedule selection"
|
|
bitfld.long 0x00 0.--3. "VACT,VACT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "REPTIME,Schedule repeat count"
|
|
bitfld.long 0x00 0.--3. "VREP,VREP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRGMODE,Start trigger mode"
|
|
bitfld.long 0x00 0.--1. "VTRG,VTRG" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ERRINTEN,Error interrupt enable_disable"
|
|
bitfld.long 0x00 2. "INTTEN,INTTEN" "0,1"
|
|
bitfld.long 0x00 0. "VERREN,VERREN" "0,1"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "COMPEND,VE forced termination"
|
|
bitfld.long 0x00 0. "VCEND,VCEND" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ERRDET,Error detection"
|
|
bitfld.long 0x00 0. "VERRD,VERRD" "0,1"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SCHTASKRUN,Schedule executing flag_executing task"
|
|
bitfld.long 0x00 1.--4. "VRTASK,VRTASK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "VRSCH,VRSCH" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TMPREG0,Temporary register"
|
|
hexmask.long 0x00 0.--31. 1. "TMPREG0,TMPREG0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TMPREG1,Temporary register"
|
|
hexmask.long 0x00 0.--31. 1. "TMPREG1,TMPREG1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TMPREG2,Temporary register"
|
|
hexmask.long 0x00 0.--31. 1. "TMPREG2,TMPREG2"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TMPREG3,Temporary register"
|
|
hexmask.long 0x00 0.--31. 1. "TMPREG3,TMPREG3"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TMPREG4,Temporary register"
|
|
hexmask.long 0x00 0.--31. 1. "TMPREG4,TMPREG4"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TMPREG5,Temporary register"
|
|
hexmask.long 0x00 0.--31. 1. "TMPREG5,TMPREG5"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MCTLF,Status flags"
|
|
bitfld.long 0x00 15. "SFT2STM,SFT2STM" "0,1"
|
|
bitfld.long 0x00 14. "SFT2ST,SFT2ST" "0,1"
|
|
bitfld.long 0x00 11. "PWMOVF,PWMOVF" "0,1"
|
|
bitfld.long 0x00 10. "VSOVF,VSOVF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PIQOVF,PIQOVF" "0,1"
|
|
bitfld.long 0x00 8. "PIDOVF,PIDOVF" "0,1"
|
|
bitfld.long 0x00 5. "PLSLFM,PLSLFM" "0,1"
|
|
bitfld.long 0x00 4. "PLSLF,PLSLF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "LVTF,LVTF" "0,1"
|
|
bitfld.long 0x00 1. "LAVFM,LAVFM" "0,1"
|
|
bitfld.long 0x00 0. "LAVF,LAVF" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MODE,Task control mode"
|
|
bitfld.long 0x00 15. "IPDEN,IPDEN" "0,1"
|
|
bitfld.long 0x00 14. "PMDDTCEN,PMDDTCEN" "0,1"
|
|
bitfld.long 0x00 13. "PWMFLEN,PWMFLEN" "0,1"
|
|
bitfld.long 0x00 12. "PWMBLEN,PWMBLEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "NICEN,NICEN" "0,1"
|
|
bitfld.long 0x00 10. "T5ECEN,T5ECEN" "0,1"
|
|
bitfld.long 0x00 8.--9. "AWUMD,AWUMD" "0,1,2,3"
|
|
bitfld.long 0x00 7. "CLPEN,CLPEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "ATANMD,ATANMD" "0,1,2,3"
|
|
bitfld.long 0x00 4. "VDCSEL,VDCSEL" "0,1"
|
|
bitfld.long 0x00 2.--3. "OCRMD,OCRMD" "0,1,2,3"
|
|
bitfld.long 0x00 1. "ZIEN,ZIEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PVIEN,PVIEN" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FMODE,Flow control"
|
|
bitfld.long 0x00 14.--15. "SPWMMD,SPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 13. "CCVMD,CCVMD" "0,1"
|
|
bitfld.long 0x00 12. "PHCVDIS,PHCVDIS" "0,1"
|
|
bitfld.long 0x00 10.--11. "VSLIMMD,VSLIMMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "MREGDIS,MREGDIS" "0,1"
|
|
bitfld.long 0x00 8. "CRCEN,CRCEN" "0,1"
|
|
bitfld.long 0x00 7. "ICPLMD,ICPLMD" "0,1"
|
|
bitfld.long 0x00 6. "IBPLMD,IBPLMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IAPLMD,IAPLMD" "0,1"
|
|
bitfld.long 0x00 4. "IDQSEL,IDQSEL" "0,1"
|
|
bitfld.long 0x00 2.--3. "IDMODE,IDMODE" "0,1,2,3"
|
|
bitfld.long 0x00 1. "SPWMEN,SPWMEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "C2PEN,C2PEN" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPWM,PWM period rate (PWM period _s_ * maximum speed * 2^16) setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "TPWM,TPWM"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "OMEGA,Rotation speed (speed _Hz_ _ maximum speed * 2^15) setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "OMEGA,OMEGA"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "THETA,Motor phase (motor phase _deg_ _ 360 * 2^16) setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "THETA,THETA"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "IDREF,d-axis reference value (current _A_ _ maximum current * 2^15)"
|
|
hexmask.long.word 0x00 0.--15. 1. "IDREF,IDREF"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "IQREF,q-axis reference value (current _A_ _ maximum current * 2^15)"
|
|
hexmask.long.word 0x00 0.--15. 1. "IQREF,IQREF"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "VD,d-axis voltage (voltage _V_ _ maximum voltage * 2^31)"
|
|
hexmask.long 0x00 0.--31. 1. "VD,VD"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "VQ,q-axis voltage (voltage _V_ _ maximum voltage * 2^31)"
|
|
hexmask.long 0x00 0.--31. 1. "VQ,VQ"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CIDKI,Integral coefficient for PI control of d-axis"
|
|
hexmask.long.word 0x00 0.--15. 1. "CIDKI,CIDKI"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CIDKP,Proportional coefficient for PI control of d-axis"
|
|
hexmask.long.word 0x00 0.--15. 1. "CIDKP,CIDKP"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CIQKI,Integral coefficient for PI control of q-axis"
|
|
hexmask.long.word 0x00 0.--15. 1. "CIQKI,CIQKI"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CIQKP,Proportional coefficient for PI control of q-axis"
|
|
hexmask.long.word 0x00 0.--15. 1. "CIQKP,CIQKP"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "VDIH,Upper 32 bits of integral term (VDI ) of d-axis voltage"
|
|
hexmask.long 0x00 0.--31. 1. "VDIH,VDIH"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "VDILH,Lower 32 bits of integral term (VDI) of d-axis voltage"
|
|
hexmask.long.word 0x00 16.--31. 1. "VDILH,VDILH"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "VQIH,Upper 32 bits of integral term (VQI) of q-axis voltage"
|
|
hexmask.long 0x00 0.--31. 1. "VQIH,VQIH"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "VQILH,Lower 32 bits of integral term (VQI) of q-axis voltage"
|
|
hexmask.long.word 0x00 16.--31. 1. "VQILH,VQILH"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FPWMCHG,Switching speed (for 2-phase modulation and shift PWM)"
|
|
hexmask.long.word 0x00 0.--15. 1. "FPWMCHG,FPWMCHG"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PWMOFS,SHIFT2 PWM Offset register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PWMOFS,PWMOFS"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "MINPLS,Minimum pulse width"
|
|
hexmask.long.word 0x00 0.--15. 1. "MINPLS,MINPLS"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TRGCRC,Synchronizing trigger correction value"
|
|
hexmask.long.word 0x00 0.--15. 1. "TRGCRC,TRGCRC"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "VDCL,Cosine value at THETA for output conversion (Q15 data)"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDCL,VDCL"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "COS,Cosine value at THETA for output conversion (Q15 data)"
|
|
hexmask.long.word 0x00 0.--15. 1. "COS,COS"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SIN,Sine value at THETA for output conversion (Q15 data)"
|
|
hexmask.long.word 0x00 0.--15. 1. "SIN,SIN"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "COSM,Previous cosine value for input processing (Q15 data)"
|
|
hexmask.long.word 0x00 0.--15. 1. "COSM,COSM"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "SINM,Previous sine value for input processing (Q15 data)"
|
|
hexmask.long.word 0x00 0.--15. 1. "SINM,SINM"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "SECTOR,Sector information (0-11)"
|
|
bitfld.long 0x00 0.--3. "SECTOR,SECTOR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "SECTORM,Previous sector information for input processing (0-11)"
|
|
bitfld.long 0x00 0.--3. "SECTORM,SECTORM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "IAO,AD conversion result of a-phase zero-current"
|
|
hexmask.long.word 0x00 0.--15. 1. "IAO,IAO"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "IBO,AD conversion result of b-phase zero-current"
|
|
hexmask.long.word 0x00 0.--15. 1. "IBO,IBO"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "ICO,AD conversion result of c-phase zero-current"
|
|
hexmask.long.word 0x00 0.--15. 1. "ICO,ICO"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "IAADC,AD conversion result of a-phase current"
|
|
hexmask.long.word 0x00 0.--15. 1. "IAADC,IAADC"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "IBADC,AD conversion result of b-phase current"
|
|
hexmask.long.word 0x00 0.--15. 1. "IBADC,IBADC"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "ICADC,AD conversion result of c-phase current"
|
|
hexmask.long.word 0x00 0.--15. 1. "ICADC,ICADC"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "VDC,DC supply voltage (voltage _V_ _ maximum voltage * 2^15)"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDC,VDC"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "ID,d-axis current (current _A_ _ maximum current * 2^31)"
|
|
hexmask.long 0x00 0.--31. 1. "ID,ID"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IQ,q-axis current (current _A_ _ maximum current * 2^31)"
|
|
hexmask.long 0x00 0.--31. 1. "IQ,IQ"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "TADC,ADC start wait setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "TADC,TADC"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "CMPU,PMD control_ CMPU setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "VCMPU,VCMPU"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CMPV,PMD control_ CMPV setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "VCMPV,VCMPV"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "CMPW,PMD control_ CMPW setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "VCMPW,VCMPW"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "OUTCR,PMD control_ Output control (MDOUT)"
|
|
bitfld.long 0x00 8. "WPWM,WPWM" "0,1"
|
|
bitfld.long 0x00 7. "VPWM,VPWM" "0,1"
|
|
bitfld.long 0x00 6. "UPWM,UPWM" "0,1"
|
|
bitfld.long 0x00 4.--5. "WOC,WOC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "VOC,VOC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "UOC,UOC" "0,1,2,3"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "TRGCMP0,PMD control_ TRGCMP0 setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "VTRGCMP0,VTRGCMP0"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TRGCMP1,PMD control_ TRGCMP1 setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "VTRGCMP1,VTRGCMP1"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TRGSEL,PMD control_ Trigger selection"
|
|
bitfld.long 0x00 0.--2. "VTRGSEL,VTRGSEL" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x198++0x03
|
|
line.long 0x00 "EMGRS,PMD control_ EMG return (EMGCR_EMGRS_)"
|
|
bitfld.long 0x00 0. "EMGRS,EMGRS" "0,1"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "PIOLIM,PI controled output limit value setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "PIOLIM,PIOLIM"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CIDKG,PI controled d-axis coefficient range setting"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CIDKPG,CIDKPG"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CIDKIG,CIDKIG"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "CIQKG,PI controled q-axis coefficient range setting"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CIQKPG,CIQKPG"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CIQKIG,CIQKIG"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "VSLIM,Voltage scalar limits"
|
|
hexmask.long.word 0x00 0.--15. 1. "VSLIM,VSLIM"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "VDQ,Voltage scalar"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDQ,VDQ"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "DELTA,Declination angle"
|
|
hexmask.long.word 0x00 0.--15. 1. "DELTA,DELTA"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "CPHI,Motor interlinkage magnetic flux"
|
|
hexmask.long.word 0x00 0.--15. 1. "CPHI,CPHI"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "CLD,Motor q-axis inductance"
|
|
hexmask.long.word 0x00 0.--15. 1. "CLD,CLD"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "CLQ,Motor d-axis inductance"
|
|
hexmask.long.word 0x00 0.--15. 1. "CLQ,CLQ"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "CR,Motor resistance value"
|
|
hexmask.long.word 0x00 0.--15. 1. "CR,CR"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "CPHIG,Motor magnetic flux range setting"
|
|
bitfld.long 0x00 0.--2. "CPHIG,CPHIG" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "CLG,Motor inductance range setting"
|
|
bitfld.long 0x00 0.--2. "CLG,CLG" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "CRG,Motor resistance range setting"
|
|
bitfld.long 0x00 0.--2. "CRG,CRG" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "VDE,Non-interference controled d-axis voltage"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDE,VDE"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "VQE,Non-interference controled q-axis voltage"
|
|
hexmask.long.word 0x00 0.--15. 1. "VQE,VQE"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "DTC,Dead time compensation"
|
|
hexmask.long.word 0x00 0.--15. 1. "DTC,DTC"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "HYS,Hysteresis width for current discrimination"
|
|
hexmask.long.word 0x00 0.--15. 1. "HYS,HYS"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DTCS,Dead time compensation control _ status"
|
|
bitfld.long 0x00 8.--10. "ICSTS,ICSTS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "IBSTS,IBSTS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "IASTS,IASTS" "0,1,2,3,4,5,6,7"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "PWMMAX,PWM upper limit setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "PWMMAX,PWMMAX"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "PWMMIN,PWM lower limit setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "PWMMIN,PWMMIN"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "THTCLP,Clipped phase value setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "THTCLP,THTCLP"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "HYS2,The second threshold value for determining the current polarity"
|
|
hexmask.long.word 0x00 0.--15. 1. "HYS2,HYS2"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "VALPHA,ALPHA-phase voltage"
|
|
hexmask.long 0x00 0.--31. 1. "VALPHA,VALPHA"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "VBETA,BETA-phase voltage"
|
|
hexmask.long 0x00 0.--31. 1. "VBETA,VBETA"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "VDUTYA,A-phase duty"
|
|
hexmask.long 0x00 0.--31. 1. "VDUTYA,VDUTYA"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "VDUTYB,B-phase duty"
|
|
hexmask.long 0x00 0.--31. 1. "VDUTYB,VDUTYB"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "VDUTYC,C-phase duty"
|
|
hexmask.long 0x00 0.--31. 1. "VDUTYC,VDUTYC"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "IALPHA,ALPHA-phase current"
|
|
hexmask.long 0x00 0.--31. 1. "IALPHA,IALPHA"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "IBETA,BETA-phase current"
|
|
hexmask.long 0x00 0.--31. 1. "IBETA,IBETA"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "IA,A-phase current"
|
|
hexmask.long 0x00 0.--31. 1. "IA,IA"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "IB,B-phase current"
|
|
hexmask.long 0x00 0.--31. 1. "IB,IB"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "IC,C-phase current"
|
|
hexmask.long 0x00 0.--31. 1. "IC,IC"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "VDELTA,VDQ Declination angle"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDELTA,VDELTA"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "VDCRC,d-axis voltage correction value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDCRC,VDCRC"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "VQCRC,q-axis voltage correction value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VQCRC,VQCRC"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")||cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
base ad:0x400EB000
|
|
elif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
base ad:0x4008B000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EN,VE enable_disable"
|
|
bitfld.long 0x00 0. "VEEN,VEEN" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CPURUNTRG,CPU start trigger selection"
|
|
bitfld.long 0x00 0. "VCPURT,VCPURT" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TASKAPP,Task selection"
|
|
bitfld.long 0x00 8.--11. "VITASK,VITASK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "VTASK,VTASK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ACTSCH,Operation schedule selection"
|
|
bitfld.long 0x00 0.--3. "VACT,VACT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "REPTIME,Schedule repeat count"
|
|
bitfld.long 0x00 0.--3. "VREP,VREP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TRGMODE,Start trigger mode"
|
|
bitfld.long 0x00 0.--1. "VTRG,VTRG" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ERRINTEN,Error interrupt enable_disable"
|
|
bitfld.long 0x00 2. "INTTEN,INTTEN" "0,1"
|
|
bitfld.long 0x00 0. "VERREN,VERREN" "0,1"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "COMPEND,VE forced termination"
|
|
bitfld.long 0x00 0. "VCEND,VCEND" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ERRDET,Error detection"
|
|
bitfld.long 0x00 0. "VERRD,VERRD" "0,1"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SCHTASKRUN,Schedule executing flag_executing task"
|
|
bitfld.long 0x00 1.--4. "VRTASK,VRTASK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "VRSCH,VRSCH" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TMPREG0,Temporary register"
|
|
hexmask.long 0x00 0.--31. 1. "TMPREG0,TMPREG0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TMPREG1,Temporary register"
|
|
hexmask.long 0x00 0.--31. 1. "TMPREG1,TMPREG1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TMPREG2,Temporary register"
|
|
hexmask.long 0x00 0.--31. 1. "TMPREG2,TMPREG2"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TMPREG3,Temporary register"
|
|
hexmask.long 0x00 0.--31. 1. "TMPREG3,TMPREG3"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TMPREG4,Temporary register"
|
|
hexmask.long 0x00 0.--31. 1. "TMPREG4,TMPREG4"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TMPREG5,Temporary register"
|
|
hexmask.long 0x00 0.--31. 1. "TMPREG5,TMPREG5"
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MCTLF,Status flags"
|
|
bitfld.long 0x00 11. "PWMOVF,PWMOVF" "0,1"
|
|
bitfld.long 0x00 10. "VSOVF,VSOVF" "0,1"
|
|
bitfld.long 0x00 9. "PIQOVF,PIQOVF" "0,1"
|
|
bitfld.long 0x00 8. "PIDOVF,PIDOVF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PLSLFM,PLSLFM" "0,1"
|
|
bitfld.long 0x00 4. "PLSLF,PLSLF" "0,1"
|
|
bitfld.long 0x00 2. "LVTF,LVTF" "0,1"
|
|
bitfld.long 0x00 1. "LAVFM,LAVFM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "LAVF,LAVF" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MCTLF,Status flags"
|
|
bitfld.long 0x00 15. "SFT2STM,SFT2STM" "0,1"
|
|
bitfld.long 0x00 14. "SFT2ST,SFT2ST" "0,1"
|
|
bitfld.long 0x00 11. "PWMOVF,PWMOVF" "0,1"
|
|
bitfld.long 0x00 10. "VSOVF,VSOVF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PIQOVF,PIQOVF" "0,1"
|
|
bitfld.long 0x00 8. "PIDOVF,PIDOVF" "0,1"
|
|
bitfld.long 0x00 5. "PLSLFM,PLSLFM" "0,1"
|
|
bitfld.long 0x00 4. "PLSLF,PLSLF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "LVTF,LVTF" "0,1"
|
|
bitfld.long 0x00 1. "LAVFM,LAVFM" "0,1"
|
|
bitfld.long 0x00 0. "LAVF,LAVF" "0,1"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MODE,Task control mode"
|
|
bitfld.long 0x00 15. "IPDEN,IPDEN" "0,1"
|
|
bitfld.long 0x00 14. "PMDDTCEN,PMDDTCEN" "0,1"
|
|
bitfld.long 0x00 13. "PWMFLEN,PWMFLEN" "0,1"
|
|
bitfld.long 0x00 12. "PWMBLEN,PWMBLEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "NICEN,NICEN" "0,1"
|
|
bitfld.long 0x00 10. "T5ECEN,T5ECEN" "0,1"
|
|
bitfld.long 0x00 8.--9. "AWUMD,AWUMD" "0,1,2,3"
|
|
bitfld.long 0x00 7. "CLPEN,CLPEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "ATANMD,ATANMD" "0,1,2,3"
|
|
bitfld.long 0x00 4. "VDCSEL,VDCSEL" "0,1"
|
|
bitfld.long 0x00 2.--3. "OCRMD,OCRMD" "0,1,2,3"
|
|
bitfld.long 0x00 1. "ZIEN,ZIEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PVIEN,PVIEN" "0,1"
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FMODE,Flow control"
|
|
bitfld.long 0x00 14.--15. "SPWMMD,SPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 13. "CCVMD,CCVMD" "0,1"
|
|
bitfld.long 0x00 12. "PHCVDIS,PHCVDIS" "0,1"
|
|
bitfld.long 0x00 10.--11. "VSLIMMD,VSLIMMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "MREGDIS,MREGDIS" "0,1"
|
|
bitfld.long 0x00 8. "CRCEN,CRCEN" "0,1"
|
|
bitfld.long 0x00 7. "ICPLMD,ICPLMD" "0,1"
|
|
bitfld.long 0x00 6. "IBPLMD,IBPLMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IAPLMD,IAPLMD" "0,1"
|
|
bitfld.long 0x00 4. "IDQSEL,IDQSEL" "0,1"
|
|
bitfld.long 0x00 2.--3. "IDMODE,IDMODE" "0,1,2,3"
|
|
bitfld.long 0x00 1. "SPWMEN,SPWMEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "C2PEN,C2PEN" "0,1"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FMODE,Flow control"
|
|
bitfld.long 0x00 14.--15. "SPWMMD,SPWMMD" "0,1,2,3"
|
|
bitfld.long 0x00 12. "PHCVDIS,PHCVDIS" "0,1"
|
|
bitfld.long 0x00 10.--11. "VSLIMMD,VSLIMMD" "0,1,2,3"
|
|
bitfld.long 0x00 9. "MREGDIS,MREGDIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CRCEN,CRCEN" "0,1"
|
|
bitfld.long 0x00 7. "ICPLMD,ICPLMD" "0,1"
|
|
bitfld.long 0x00 6. "IBPLMD,IBPLMD" "0,1"
|
|
bitfld.long 0x00 5. "IAPLMD,IAPLMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "IDMODE,IDMODE" "0,1,2,3"
|
|
bitfld.long 0x00 1. "SPWMEN,SPWMEN" "0,1"
|
|
bitfld.long 0x00 0. "C2PEN,C2PEN" "0,1"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPWM,PWM period rate (PWM period _s_ * maximum speed * 2^16) setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "TPWM,TPWM"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "OMEGA,Rotation speed (speed _Hz_ _ maximum speed * 2^15) setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "OMEGA,OMEGA"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "THETA,Motor phase (motor phase _deg_ _ 360 * 2^16) setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "THETA,THETA"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "IDREF,d-axis reference value (current _A_ _ maximum current * 2^15)"
|
|
hexmask.long.word 0x00 0.--15. 1. "IDREF,IDREF"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "IQREF,q-axis reference value (current _A_ _ maximum current * 2^15)"
|
|
hexmask.long.word 0x00 0.--15. 1. "IQREF,IQREF"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "VD,d-axis voltage (voltage _V_ _ maximum voltage * 2^31)"
|
|
hexmask.long 0x00 0.--31. 1. "VD,VD"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "VQ,q-axis voltage (voltage _V_ _ maximum voltage * 2^31)"
|
|
hexmask.long 0x00 0.--31. 1. "VQ,VQ"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CIDKI,Integral coefficient for PI control of d-axis"
|
|
hexmask.long.word 0x00 0.--15. 1. "CIDKI,CIDKI"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CIDKP,Proportional coefficient for PI control of d-axis"
|
|
hexmask.long.word 0x00 0.--15. 1. "CIDKP,CIDKP"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CIQKI,Integral coefficient for PI control of q-axis"
|
|
hexmask.long.word 0x00 0.--15. 1. "CIQKI,CIQKI"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CIQKP,Proportional coefficient for PI control of q-axis"
|
|
hexmask.long.word 0x00 0.--15. 1. "CIQKP,CIQKP"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "VDIH,Upper 32 bits of integral term (VDI ) of d-axis voltage"
|
|
hexmask.long 0x00 0.--31. 1. "VDIH,VDIH"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "VDILH,Lower 32 bits of integral term (VDI) of d-axis voltage"
|
|
hexmask.long.word 0x00 16.--31. 1. "VDILH,VDILH"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "VQIH,Upper 32 bits of integral term (VQI) of q-axis voltage"
|
|
hexmask.long 0x00 0.--31. 1. "VQIH,VQIH"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "VQILH,Lower 32 bits of integral term (VQI) of q-axis voltage"
|
|
hexmask.long.word 0x00 16.--31. 1. "VQILH,VQILH"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FPWMCHG,Switching speed (for 2-phase modulation and shift PWM)"
|
|
hexmask.long.word 0x00 0.--15. 1. "FPWMCHG,FPWMCHG"
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PWMOFS,SHIFT2 PWM Offset register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PWMOFS,PWMOFS"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "MDPRD,PWM period setting register"
|
|
hexmask.long.word 0x00 0.--15. 1. "VMDPRD,VMDPRD"
|
|
endif
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "MINPLS,Minimum pulse width"
|
|
hexmask.long.word 0x00 0.--15. 1. "MINPLS,MINPLS"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TRGCRC,Synchronizing trigger correction value"
|
|
hexmask.long.word 0x00 0.--15. 1. "TRGCRC,TRGCRC"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "VDCL,Cosine value at THETA for output conversion (Q15 data)"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDCL,VDCL"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "COS,Cosine value at THETA for output conversion (Q15 data)"
|
|
hexmask.long.word 0x00 0.--15. 1. "COS,COS"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SIN,Sine value at THETA for output conversion (Q15 data)"
|
|
hexmask.long.word 0x00 0.--15. 1. "SIN,SIN"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "COSM,Previous cosine value for input processing (Q15 data)"
|
|
hexmask.long.word 0x00 0.--15. 1. "COSM,COSM"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "SINM,Previous sine value for input processing (Q15 data)"
|
|
hexmask.long.word 0x00 0.--15. 1. "SINM,SINM"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "SECTOR,Sector information (0-11)"
|
|
bitfld.long 0x00 0.--3. "SECTOR,SECTOR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "SECTORM,Previous sector information for input processing (0-11)"
|
|
bitfld.long 0x00 0.--3. "SECTORM,SECTORM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "IAO,AD conversion result of a-phase zero-current"
|
|
hexmask.long.word 0x00 0.--15. 1. "IAO,IAO"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "IBO,AD conversion result of b-phase zero-current"
|
|
hexmask.long.word 0x00 0.--15. 1. "IBO,IBO"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "ICO,AD conversion result of c-phase zero-current"
|
|
hexmask.long.word 0x00 0.--15. 1. "ICO,ICO"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "IAADC,AD conversion result of a-phase current"
|
|
hexmask.long.word 0x00 0.--15. 1. "IAADC,IAADC"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "IBADC,AD conversion result of b-phase current"
|
|
hexmask.long.word 0x00 0.--15. 1. "IBADC,IBADC"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "ICADC,AD conversion result of c-phase current"
|
|
hexmask.long.word 0x00 0.--15. 1. "ICADC,ICADC"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "VDC,DC supply voltage (voltage _V_ _ maximum voltage * 2^15)"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDC,VDC"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "ID,d-axis current (current _A_ _ maximum current * 2^31)"
|
|
hexmask.long 0x00 0.--31. 1. "ID,ID"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "IQ,q-axis current (current _A_ _ maximum current * 2^31)"
|
|
hexmask.long 0x00 0.--31. 1. "IQ,IQ"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "TADC,ADC start wait setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "TADC,TADC"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "CMPU,PMD control_ CMPU setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "VCMPU,VCMPU"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CMPV,PMD control_ CMPV setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "VCMPV,VCMPV"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "CMPW,PMD control_ CMPW setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "VCMPW,VCMPW"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "OUTCR,PMD control_ Output control (MDOUT)"
|
|
bitfld.long 0x00 8. "WPWM,WPWM" "0,1"
|
|
bitfld.long 0x00 7. "VPWM,VPWM" "0,1"
|
|
bitfld.long 0x00 6. "UPWM,UPWM" "0,1"
|
|
bitfld.long 0x00 4.--5. "WOC,WOC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "VOC,VOC" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "UOC,UOC" "0,1,2,3"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "TRGCMP0,PMD control_ TRGCMP0 setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "VTRGCMP0,VTRGCMP0"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TRGCMP1,PMD control_ TRGCMP1 setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "VTRGCMP1,VTRGCMP1"
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TRGSEL,PMD control_ Trigger selection"
|
|
bitfld.long 0x00 0.--2. "VTRGSEL,VTRGSEL" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TRGSEL,PMD control_ Synchronous Trigger Selection setting Register"
|
|
bitfld.long 0x00 0.--2. "VTRGSEL,VTRGSEL" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
wgroup.long 0x198++0x03
|
|
line.long 0x00 "EMGRS,PMD control_ EMG return (EMGCR_EMGRS_)"
|
|
bitfld.long 0x00 0. "EMGRS,EMGRS" "0,1"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "PIOLIM,PI controled output limit value setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "PIOLIM,PIOLIM"
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CIDKG,PI controled d-axis coefficient range setting"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CIDKPG,CIDKPG"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CIDKIG,CIDKIG"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CIDKG,PI controled d-axis coefficient range setting"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CIDKIG,CIDKIG"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "CIQKG,PI controled q-axis coefficient range setting"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CIQKIG,CIQKIG"
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "CIQKG,PI controled q-axis coefficient range setting"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CIQKPG,CIQKPG"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CIQKIG,CIQKIG"
|
|
endif
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "VSLIM,Voltage scalar limits"
|
|
hexmask.long.word 0x00 0.--15. 1. "VSLIM,VSLIM"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "VDQ,Voltage scalar"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDQ,VDQ"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "DELTA,Declination angle"
|
|
hexmask.long.word 0x00 0.--15. 1. "DELTA,DELTA"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "CPHI,Motor interlinkage magnetic flux"
|
|
hexmask.long.word 0x00 0.--15. 1. "CPHI,CPHI"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "CLD,Motor q-axis inductance"
|
|
hexmask.long.word 0x00 0.--15. 1. "CLD,CLD"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "CLQ,Motor d-axis inductance"
|
|
hexmask.long.word 0x00 0.--15. 1. "CLQ,CLQ"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "CR,Motor resistance value"
|
|
hexmask.long.word 0x00 0.--15. 1. "CR,CR"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "CPHIG,Motor magnetic flux range setting"
|
|
bitfld.long 0x00 0.--2. "CPHIG,CPHIG" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "CLG,Motor inductance range setting"
|
|
bitfld.long 0x00 0.--2. "CLG,CLG" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "CRG,Motor resistance range setting"
|
|
bitfld.long 0x00 0.--2. "CRG,CRG" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "VDE,Non-interference controled d-axis voltage"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDE,VDE"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "VQE,Non-interference controled q-axis voltage"
|
|
hexmask.long.word 0x00 0.--15. 1. "VQE,VQE"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "DTC,Dead time compensation"
|
|
hexmask.long.word 0x00 0.--15. 1. "DTC,DTC"
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "HYS,Hysteresis width for current discrimination"
|
|
hexmask.long.word 0x00 0.--15. 1. "HYS,HYS"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "HYS,Hysteresis Width Register for Current Polarity Determination"
|
|
hexmask.long.word 0x00 0.--15. 1. "HYS,HYS"
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DTCS,Dead time compensation control _ status"
|
|
bitfld.long 0x00 8.--10. "ICSTS,ICSTS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "IBSTS,IBSTS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "IASTS,IASTS" "0,1,2,3,4,5,6,7"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "PWMMAX,PWM upper limit setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "PWMMAX,PWMMAX"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "PWMMIN,PWM lower limit setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "PWMMIN,PWMMIN"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "THTCLP,Clipped phase value setting"
|
|
hexmask.long.word 0x00 0.--15. 1. "THTCLP,THTCLP"
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "HYS2,The second threshold value for determining the current polarity"
|
|
hexmask.long.word 0x00 0.--15. 1. "HYS2,HYS2"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "VALPHA,ALPHA-phase voltage"
|
|
hexmask.long 0x00 0.--31. 1. "VALPHA,VALPHA"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "VBETA,BETA-phase voltage"
|
|
hexmask.long 0x00 0.--31. 1. "VBETA,VBETA"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "VDUTYA,A-phase duty"
|
|
hexmask.long 0x00 0.--31. 1. "VDUTYA,VDUTYA"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "VDUTYB,B-phase duty"
|
|
hexmask.long 0x00 0.--31. 1. "VDUTYB,VDUTYB"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "VDUTYC,C-phase duty"
|
|
hexmask.long 0x00 0.--31. 1. "VDUTYC,VDUTYC"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "IALPHA,ALPHA-phase current"
|
|
hexmask.long 0x00 0.--31. 1. "IALPHA,IALPHA"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "IBETA,BETA-phase current"
|
|
hexmask.long 0x00 0.--31. 1. "IBETA,IBETA"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "IA,A-phase current"
|
|
hexmask.long 0x00 0.--31. 1. "IA,IA"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "IB,B-phase current"
|
|
hexmask.long 0x00 0.--31. 1. "IB,IB"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "IC,C-phase current"
|
|
hexmask.long 0x00 0.--31. 1. "IC,IC"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "VDELTA,VDQ Declination angle"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDELTA,VDELTA"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "VDCRC,d-axis voltage correction value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VDCRC,VDCRC"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "VQCRC,q-axis voltage correction value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VQCRC,VQCRC"
|
|
endif
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4K1A*")||cpuis("TMPM4K2A*")||cpuis("TMPM4K4A*")
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x400A0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,I2C Control Register 1"
|
|
bitfld.long 0x00 5.--7. "BC,BC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "ACK,ACK" "0,1"
|
|
bitfld.long 0x00 3. "NOACK,NOACK" "0,1"
|
|
bitfld.long 0x00 0.--2. "SCK,SCK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DBR,I2C Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DB,DB"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "AR,I2C Bus address Register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA,SA"
|
|
bitfld.long 0x00 0. "ALS,ALS" "0,1"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CR2,I2C Control Register 2"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "I2CM,I2CM" "0,1"
|
|
bitfld.long 0x00 0.--1. "SWRES,SWRES" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,I2C Status Register"
|
|
bitfld.long 0x00 7. "MST,MST" "0,1"
|
|
bitfld.long 0x00 6. "TRX,TRX" "0,1"
|
|
bitfld.long 0x00 5. "BB,BB" "0,1"
|
|
bitfld.long 0x00 4. "PIN,PIN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AL,AL" "0,1"
|
|
bitfld.long 0x00 2. "AAS,AAS" "0,1"
|
|
bitfld.long 0x00 1. "AD0,AD0" "0,1"
|
|
bitfld.long 0x00 0. "LRB,LRB" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRS,I2C Prescaler clcok setting Register"
|
|
bitfld.long 0x00 0.--4. "PRSCK,PRSCK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IE,I2C Interrupt Enable Register"
|
|
bitfld.long 0x00 6. "SELPINCD,SELPINCD" "0,1"
|
|
bitfld.long 0x00 5. "DMARI2CTX,DMARI2CTX" "0,1"
|
|
bitfld.long 0x00 4. "DMARI2CRX,DMARI2CRX" "0,1"
|
|
bitfld.long 0x00 3. "INTNACK,INTNACK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTI2CBF,INTI2CBF" "0,1"
|
|
bitfld.long 0x00 1. "INTI2CAL,INTI2CAL" "0,1"
|
|
bitfld.long 0x00 0. "INTI2C,INTI2C" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ST,I2C Interrupt Register"
|
|
bitfld.long 0x00 3. "NACK,NACK" "0,1"
|
|
bitfld.long 0x00 2. "I2CBF,I2CBF" "0,1"
|
|
bitfld.long 0x00 1. "I2CAL,I2CAL" "0,1"
|
|
bitfld.long 0x00 0. "I2C,I2C" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "OP,I2C Optiononal Function register"
|
|
bitfld.long 0x00 7. "DISAL,DISAL" "0,1"
|
|
rbitfld.long 0x00 6. "SA2ST,SA2ST" "0,1"
|
|
rbitfld.long 0x00 5. "SAST,SAST" "0,1"
|
|
bitfld.long 0x00 4. "NFSEL,NFSEL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RSTA,RSTA" "0,1"
|
|
bitfld.long 0x00 2. "GCDI,GCDI" "0,1"
|
|
bitfld.long 0x00 1. "SREN,SREN" "0,1"
|
|
bitfld.long 0x00 0. "MFACK,MFACK" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PM,I2C Bus Monitor register"
|
|
bitfld.long 0x00 1. "SDA,SDA" "0,1"
|
|
bitfld.long 0x00 0. "SCL,SCL" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AR2,I2C Second Slave address register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA2,SA2"
|
|
bitfld.long 0x00 0. "SA2EN,SA2EN" "0,1"
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4L*")||cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "CANMB (CAN Controller Mailbox RAM (CANMB))"
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.) (list ad:0x40005000 ad:0x40005020 ad:0x40005040 ad:0x40005060 ad:0x40005080 ad:0x400050A0 ad:0x400050C0 ad:0x400050E0 ad:0x40005100 ad:0x40005120 ad:0x40005140 ad:0x40005160 ad:0x40005180 ad:0x400051A0 ad:0x400051C0 ad:0x400051E0)
|
|
tree "CANMB$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ID,CAN Mailbox ID"
|
|
bitfld.long 0x00 31. "IDE,IDE" "0,1"
|
|
bitfld.long 0x00 30. "GAME_LAME,GAME_LAME" "0,1"
|
|
bitfld.long 0x00 29. "RFH,RFH" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "ID,ID"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TSVMCF,CAN Mailbox Time Stamp Value and Message Control Field"
|
|
hexmask.long.word 0x00 16.--31. 1. "TSV,TSV"
|
|
bitfld.long 0x00 4. "RTR,RTR" "0,1"
|
|
bitfld.long 0x00 0.--3. "DLC,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DL,CAN Mailbox Lower Data Field (D3-D0)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "D3,D3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "D2,D2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "D1,D1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "D0,D0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DH,CAN Mailbox Upper Data Field (D7-D4)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "D7,D7"
|
|
hexmask.long.byte 0x00 16.--23. 1. "D6,D6"
|
|
hexmask.long.byte 0x00 8.--15. 1. "D5,D5"
|
|
hexmask.long.byte 0x00 0.--7. 1. "D4,D4"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31.) (list ad:0x40005200 ad:0x40005220 ad:0x40005240 ad:0x40005260 ad:0x40005280 ad:0x400052A0 ad:0x400052C0 ad:0x400052E0 ad:0x40005300 ad:0x40005320 ad:0x40005340 ad:0x40005360 ad:0x40005380 ad:0x400053A0 ad:0x400053C0 ad:0x400053E0)
|
|
tree "CANMB$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ID,CAN Mailbox ID"
|
|
bitfld.long 0x00 31. "IDE,IDE" "0,1"
|
|
bitfld.long 0x00 30. "GAME_LAME,GAME_LAME" "0,1"
|
|
bitfld.long 0x00 29. "RFH,RFH" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "ID,ID"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TSVMCF,CAN Mailbox Time Stamp Value and Message Control Field"
|
|
hexmask.long.word 0x00 16.--31. 1. "TSV,TSV"
|
|
bitfld.long 0x00 4. "RTR,RTR" "0,1"
|
|
bitfld.long 0x00 0.--3. "DLC,DLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DL,CAN Mailbox Lower Data Field (D3-D0)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "D3,D3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "D2,D2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "D1,D1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "D0,D0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DH,CAN Mailbox Upper Data Field (D7-D4)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "D7,D7"
|
|
hexmask.long.byte 0x00 16.--23. 1. "D6,D6"
|
|
hexmask.long.byte 0x00 8.--15. 1. "D5,D5"
|
|
hexmask.long.byte 0x00 0.--7. 1. "D4,D4"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "CAN (CAN Controller (CAN))"
|
|
base ad:0x40005400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MC,CAN Mailbox Configuration Register"
|
|
bitfld.long 0x00 31. "MC31,MC31" "0,1"
|
|
bitfld.long 0x00 30. "MC30,MC30" "0,1"
|
|
bitfld.long 0x00 29. "MC29,MC29" "0,1"
|
|
bitfld.long 0x00 28. "MC28,MC28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "MC27,MC27" "0,1"
|
|
bitfld.long 0x00 26. "MC26,MC26" "0,1"
|
|
bitfld.long 0x00 25. "MC25,MC25" "0,1"
|
|
bitfld.long 0x00 24. "MC24,MC24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "MC23,MC23" "0,1"
|
|
bitfld.long 0x00 22. "MC22,MC22" "0,1"
|
|
bitfld.long 0x00 21. "MC21,MC21" "0,1"
|
|
bitfld.long 0x00 20. "MC20,MC20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "MC19,MC19" "0,1"
|
|
bitfld.long 0x00 18. "MC18,MC18" "0,1"
|
|
bitfld.long 0x00 17. "MC17,MC17" "0,1"
|
|
bitfld.long 0x00 16. "MC16,MC16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "MC15,MC15" "0,1"
|
|
bitfld.long 0x00 14. "MC14,MC14" "0,1"
|
|
bitfld.long 0x00 13. "MC13,MC13" "0,1"
|
|
bitfld.long 0x00 12. "MC12,MC12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "MC11,MC11" "0,1"
|
|
bitfld.long 0x00 10. "MC10,MC10" "0,1"
|
|
bitfld.long 0x00 9. "MC9,MC9" "0,1"
|
|
bitfld.long 0x00 8. "MC8,MC8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "MC7,MC7" "0,1"
|
|
bitfld.long 0x00 6. "MC6,MC6" "0,1"
|
|
bitfld.long 0x00 5. "MC5,MC5" "0,1"
|
|
bitfld.long 0x00 4. "MC4,MC4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MC3,MC3" "0,1"
|
|
bitfld.long 0x00 2. "MC2,MC2" "0,1"
|
|
bitfld.long 0x00 1. "MC1,MC1" "0,1"
|
|
bitfld.long 0x00 0. "MC0,MC0" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MD,CAN Mailbox Direction Register"
|
|
rbitfld.long 0x00 31. "MD31,MD31" "0,1"
|
|
bitfld.long 0x00 30. "MD30,MD30" "0,1"
|
|
bitfld.long 0x00 29. "MD29,MD29" "0,1"
|
|
bitfld.long 0x00 28. "MD28,MD28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "MD27,MD27" "0,1"
|
|
bitfld.long 0x00 26. "MD26,MD26" "0,1"
|
|
bitfld.long 0x00 25. "MD25,MD25" "0,1"
|
|
bitfld.long 0x00 24. "MD24,MD24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "MD23,MD23" "0,1"
|
|
bitfld.long 0x00 22. "MD22,MD22" "0,1"
|
|
bitfld.long 0x00 21. "MD21,MD21" "0,1"
|
|
bitfld.long 0x00 20. "MD20,MD20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "MD19,MD19" "0,1"
|
|
bitfld.long 0x00 18. "MD18,MD18" "0,1"
|
|
bitfld.long 0x00 17. "MD17,MD17" "0,1"
|
|
bitfld.long 0x00 16. "MD16,MD16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "MD15,MD15" "0,1"
|
|
bitfld.long 0x00 14. "MD14,MD14" "0,1"
|
|
bitfld.long 0x00 13. "MD13,MD13" "0,1"
|
|
bitfld.long 0x00 12. "MD12,MD12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "MD11,MD11" "0,1"
|
|
bitfld.long 0x00 10. "MD10,MD10" "0,1"
|
|
bitfld.long 0x00 9. "MD9,MD9" "0,1"
|
|
bitfld.long 0x00 8. "MD8,MD8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "MD7,MD7" "0,1"
|
|
bitfld.long 0x00 6. "MD6,MD6" "0,1"
|
|
bitfld.long 0x00 5. "MD5,MD5" "0,1"
|
|
bitfld.long 0x00 4. "MD4,MD4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MD3,MD3" "0,1"
|
|
bitfld.long 0x00 2. "MD2,MD2" "0,1"
|
|
bitfld.long 0x00 1. "MD1,MD1" "0,1"
|
|
bitfld.long 0x00 0. "MD0,MD0" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRS,CAN Transmit Request Set Register"
|
|
bitfld.long 0x00 30. "TRS30,TRS30" "0,1"
|
|
bitfld.long 0x00 29. "TRS29,TRS29" "0,1"
|
|
bitfld.long 0x00 28. "TRS28,TRS28" "0,1"
|
|
bitfld.long 0x00 27. "TRS27,TRS27" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "TRS26,TRS26" "0,1"
|
|
bitfld.long 0x00 25. "TRS25,TRS25" "0,1"
|
|
bitfld.long 0x00 24. "TRS24,TRS24" "0,1"
|
|
bitfld.long 0x00 23. "TRS23,TRS23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "TRS22,TRS22" "0,1"
|
|
bitfld.long 0x00 21. "TRS21,TRS21" "0,1"
|
|
bitfld.long 0x00 20. "TRS20,TRS20" "0,1"
|
|
bitfld.long 0x00 19. "TRS19,TRS19" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TRS18,TRS18" "0,1"
|
|
bitfld.long 0x00 17. "TRS17,TRS17" "0,1"
|
|
bitfld.long 0x00 16. "TRS16,TRS16" "0,1"
|
|
bitfld.long 0x00 15. "TRS15,TRS15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "TRS14,TRS14" "0,1"
|
|
bitfld.long 0x00 13. "TRS13,TRS13" "0,1"
|
|
bitfld.long 0x00 12. "TRS12,TRS12" "0,1"
|
|
bitfld.long 0x00 11. "TRS11,TRS11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TRS10,TRS10" "0,1"
|
|
bitfld.long 0x00 9. "TRS9,TRS9" "0,1"
|
|
bitfld.long 0x00 8. "TRS8,TRS8" "0,1"
|
|
bitfld.long 0x00 7. "TRS7,TRS7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TRS6,TRS6" "0,1"
|
|
bitfld.long 0x00 5. "TRS5,TRS5" "0,1"
|
|
bitfld.long 0x00 4. "TRS4,TRS4" "0,1"
|
|
bitfld.long 0x00 3. "TRS3,TRS3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TRS2,TRS2" "0,1"
|
|
bitfld.long 0x00 1. "TRS1,TRS1" "0,1"
|
|
bitfld.long 0x00 0. "TRS0,TRS0" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRR,CAN Transmit Request Reset Register"
|
|
bitfld.long 0x00 30. "TRR30,TRR30" "0,1"
|
|
bitfld.long 0x00 29. "TRR29,TRR29" "0,1"
|
|
bitfld.long 0x00 28. "TRR28,TRR28" "0,1"
|
|
bitfld.long 0x00 27. "TRR27,TRR27" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "TRR26,TRR26" "0,1"
|
|
bitfld.long 0x00 25. "TRR25,TRR25" "0,1"
|
|
bitfld.long 0x00 24. "TRR24,TRR24" "0,1"
|
|
bitfld.long 0x00 23. "TRR23,TRR23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "TRR22,TRR22" "0,1"
|
|
bitfld.long 0x00 21. "TRR21,TRR21" "0,1"
|
|
bitfld.long 0x00 20. "TRR20,TRR20" "0,1"
|
|
bitfld.long 0x00 19. "TRR19,TRR19" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TRR18,TRR18" "0,1"
|
|
bitfld.long 0x00 17. "TRR17,TRR17" "0,1"
|
|
bitfld.long 0x00 16. "TRR16,TRR16" "0,1"
|
|
bitfld.long 0x00 15. "TRR15,TRR15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "TRR14,TRR14" "0,1"
|
|
bitfld.long 0x00 13. "TRR13,TRR13" "0,1"
|
|
bitfld.long 0x00 12. "TRR12,TRR12" "0,1"
|
|
bitfld.long 0x00 11. "TRR11,TRR11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TRR10,TRR10" "0,1"
|
|
bitfld.long 0x00 9. "TRR9,TRR9" "0,1"
|
|
bitfld.long 0x00 8. "TRR8,TRR8" "0,1"
|
|
bitfld.long 0x00 7. "TRR7,TRR7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TRR6,TRR6" "0,1"
|
|
bitfld.long 0x00 5. "TRR5,TRR5" "0,1"
|
|
bitfld.long 0x00 4. "TRR4,TRR4" "0,1"
|
|
bitfld.long 0x00 3. "TRR3,TRR3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TRR2,TRR2" "0,1"
|
|
bitfld.long 0x00 1. "TRR1,TRR1" "0,1"
|
|
bitfld.long 0x00 0. "TRR0,TRR0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TA,CAN Transmission Acknowledge Register"
|
|
bitfld.long 0x00 30. "TA30,TA30" "0,1"
|
|
bitfld.long 0x00 29. "TA29,TA29" "0,1"
|
|
bitfld.long 0x00 28. "TA28,TA28" "0,1"
|
|
bitfld.long 0x00 27. "TA27,TA27" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "TA26,TA26" "0,1"
|
|
bitfld.long 0x00 25. "TA25,TA25" "0,1"
|
|
bitfld.long 0x00 24. "TA24,TA24" "0,1"
|
|
bitfld.long 0x00 23. "TA23,TA23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "TA22,TA22" "0,1"
|
|
bitfld.long 0x00 21. "TA21,TA21" "0,1"
|
|
bitfld.long 0x00 20. "TA20,TA20" "0,1"
|
|
bitfld.long 0x00 19. "TA19,TA19" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TA18,TA18" "0,1"
|
|
bitfld.long 0x00 17. "TA17,TA17" "0,1"
|
|
bitfld.long 0x00 16. "TA16,TA16" "0,1"
|
|
bitfld.long 0x00 15. "TA15,TA15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "TA14,TA14" "0,1"
|
|
bitfld.long 0x00 13. "TA13,TA13" "0,1"
|
|
bitfld.long 0x00 12. "TA12,TA12" "0,1"
|
|
bitfld.long 0x00 11. "TA11,TA11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TA10,TA10" "0,1"
|
|
bitfld.long 0x00 9. "TA9,TA9" "0,1"
|
|
bitfld.long 0x00 8. "TA8,TA8" "0,1"
|
|
bitfld.long 0x00 7. "TA7,TA7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TA6,TA6" "0,1"
|
|
bitfld.long 0x00 5. "TA5,TA5" "0,1"
|
|
bitfld.long 0x00 4. "TA4,TA4" "0,1"
|
|
bitfld.long 0x00 3. "TA3,TA3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TA2,TA2" "0,1"
|
|
bitfld.long 0x00 1. "TA1,TA1" "0,1"
|
|
bitfld.long 0x00 0. "TA0,TA0" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "AA,CAN Abort Acknowledge Register"
|
|
bitfld.long 0x00 30. "AA30,AA30" "0,1"
|
|
bitfld.long 0x00 29. "AA29,AA29" "0,1"
|
|
bitfld.long 0x00 28. "AA28,AA28" "0,1"
|
|
bitfld.long 0x00 27. "AA27,AA27" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "AA26,AA26" "0,1"
|
|
bitfld.long 0x00 25. "AA25,AA25" "0,1"
|
|
bitfld.long 0x00 24. "AA24,AA24" "0,1"
|
|
bitfld.long 0x00 23. "AA23,AA23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "AA22,AA22" "0,1"
|
|
bitfld.long 0x00 21. "AA21,AA21" "0,1"
|
|
bitfld.long 0x00 20. "AA20,AA20" "0,1"
|
|
bitfld.long 0x00 19. "AA19,AA19" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "AA18,AA18" "0,1"
|
|
bitfld.long 0x00 17. "AA17,AA17" "0,1"
|
|
bitfld.long 0x00 16. "AA16,AA16" "0,1"
|
|
bitfld.long 0x00 15. "AA15,AA15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "AA14,AA14" "0,1"
|
|
bitfld.long 0x00 13. "AA13,AA13" "0,1"
|
|
bitfld.long 0x00 12. "AA12,AA12" "0,1"
|
|
bitfld.long 0x00 11. "AA11,AA11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "AA10,AA10" "0,1"
|
|
bitfld.long 0x00 9. "AA9,AA9" "0,1"
|
|
bitfld.long 0x00 8. "AA8,AA8" "0,1"
|
|
bitfld.long 0x00 7. "AA7,AA7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "AA6,AA6" "0,1"
|
|
bitfld.long 0x00 5. "AA5,AA5" "0,1"
|
|
bitfld.long 0x00 4. "AA4,AA4" "0,1"
|
|
bitfld.long 0x00 3. "AA3,AA3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "AA2,AA2" "0,1"
|
|
bitfld.long 0x00 1. "AA1,AA1" "0,1"
|
|
bitfld.long 0x00 0. "AA0,AA0" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RMP,CAN Receive Message Pending Register"
|
|
bitfld.long 0x00 31. "RMP31,RMP31" "0,1"
|
|
bitfld.long 0x00 30. "RMP30,RMP30" "0,1"
|
|
bitfld.long 0x00 29. "RMP29,RMP29" "0,1"
|
|
bitfld.long 0x00 28. "RMP28,RMP28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "RMP27,RMP27" "0,1"
|
|
bitfld.long 0x00 26. "RMP26,RMP26" "0,1"
|
|
bitfld.long 0x00 25. "RMP25,RMP25" "0,1"
|
|
bitfld.long 0x00 24. "RMP24,RMP24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RMP23,RMP23" "0,1"
|
|
bitfld.long 0x00 22. "RMP22,RMP22" "0,1"
|
|
bitfld.long 0x00 21. "RMP21,RMP21" "0,1"
|
|
bitfld.long 0x00 20. "RMP20,RMP20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "RMP19,RMP19" "0,1"
|
|
bitfld.long 0x00 18. "RMP18,RMP18" "0,1"
|
|
bitfld.long 0x00 17. "RMP17,RMP17" "0,1"
|
|
bitfld.long 0x00 16. "RMP16,RMP16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "RMP15,RMP15" "0,1"
|
|
bitfld.long 0x00 14. "RMP14,RMP14" "0,1"
|
|
bitfld.long 0x00 13. "RMP13,RMP13" "0,1"
|
|
bitfld.long 0x00 12. "RMP12,RMP12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RMP11,RMP11" "0,1"
|
|
bitfld.long 0x00 10. "RMP10,RMP10" "0,1"
|
|
bitfld.long 0x00 9. "RMP9,RMP9" "0,1"
|
|
bitfld.long 0x00 8. "RMP8,RMP8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RMP7,RMP7" "0,1"
|
|
bitfld.long 0x00 6. "RMP6,RMP6" "0,1"
|
|
bitfld.long 0x00 5. "RMP5,RMP5" "0,1"
|
|
bitfld.long 0x00 4. "RMP4,RMP4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RMP3,RMP3" "0,1"
|
|
bitfld.long 0x00 2. "RMP2,RMP2" "0,1"
|
|
bitfld.long 0x00 1. "RMP1,RMP1" "0,1"
|
|
bitfld.long 0x00 0. "RMP0,RMP0" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "RML,CAN Receive Message Lost Register"
|
|
bitfld.long 0x00 31. "RML31,RML31" "0,1"
|
|
bitfld.long 0x00 30. "RML30,RML30" "0,1"
|
|
bitfld.long 0x00 29. "RML29,RML29" "0,1"
|
|
bitfld.long 0x00 28. "RML28,RML28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "RML27,RML27" "0,1"
|
|
bitfld.long 0x00 26. "RML26,RML26" "0,1"
|
|
bitfld.long 0x00 25. "RML25,RML25" "0,1"
|
|
bitfld.long 0x00 24. "RML24,RML24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RML23,RML23" "0,1"
|
|
bitfld.long 0x00 22. "RML22,RML22" "0,1"
|
|
bitfld.long 0x00 21. "RML21,RML21" "0,1"
|
|
bitfld.long 0x00 20. "RML20,RML20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "RML19,RML19" "0,1"
|
|
bitfld.long 0x00 18. "RML18,RML18" "0,1"
|
|
bitfld.long 0x00 17. "RML17,RML17" "0,1"
|
|
bitfld.long 0x00 16. "RML16,RML16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "RML15,RML15" "0,1"
|
|
bitfld.long 0x00 14. "RML14,RML14" "0,1"
|
|
bitfld.long 0x00 13. "RML13,RML13" "0,1"
|
|
bitfld.long 0x00 12. "RML12,RML12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RML11,RML11" "0,1"
|
|
bitfld.long 0x00 10. "RML10,RML10" "0,1"
|
|
bitfld.long 0x00 9. "RML9,RML9" "0,1"
|
|
bitfld.long 0x00 8. "RML8,RML8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RML7,RML7" "0,1"
|
|
bitfld.long 0x00 6. "RML6,RML6" "0,1"
|
|
bitfld.long 0x00 5. "RML5,RML5" "0,1"
|
|
bitfld.long 0x00 4. "RML4,RML4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RML3,RML3" "0,1"
|
|
bitfld.long 0x00 2. "RML2,RML2" "0,1"
|
|
bitfld.long 0x00 1. "RML1,RML1" "0,1"
|
|
bitfld.long 0x00 0. "RML0,RML0" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "LAM,CAN Local Acceptance Mask Register"
|
|
bitfld.long 0x00 31. "LAMI,LAMI" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "LAM,LAM"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GAM,CAN Global Acceptance Mask Register"
|
|
bitfld.long 0x00 31. "GAMI,GAMI" "0,1"
|
|
hexmask.long 0x00 0.--28. 1. "GAM,GAM"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MCR,CAN Master Control Register"
|
|
bitfld.long 0x00 11. "SUR,SUR" "0,1"
|
|
bitfld.long 0x00 9. "TSTLB,TSTLB" "0,1"
|
|
bitfld.long 0x00 8. "TSTERR,TSTERR" "0,1"
|
|
bitfld.long 0x00 7. "CCR,CCR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SMR,SMR" "0,1"
|
|
bitfld.long 0x00 4. "WUBA,WUBA" "0,1"
|
|
bitfld.long 0x00 3. "MTOS,MTOS" "0,1"
|
|
bitfld.long 0x00 1. "TSCC,TSCC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SRES,SRES" "0,1"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "GSR,CAN Global Status Register"
|
|
bitfld.long 0x00 12.--16. "MIS,MIS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 11. "RM,RM" "0,1"
|
|
bitfld.long 0x00 10. "TM,TM" "0,1"
|
|
bitfld.long 0x00 8. "SUA,SUA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CCE,CCE" "0,1"
|
|
bitfld.long 0x00 6. "SMA,SMA" "0,1"
|
|
bitfld.long 0x00 3. "TSO,TSO" "0,1"
|
|
bitfld.long 0x00 2. "BO,BO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EP,EP" "0,1"
|
|
bitfld.long 0x00 0. "EW,EW" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "BCR1,CAN Bit Configuration Register 1"
|
|
hexmask.long.word 0x00 0.--9. 1. "BRP,BRP"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "BCR2,CAN Bit Configuration Register 2"
|
|
bitfld.long 0x00 8.--9. "SJW,SJW" "0,1,2,3"
|
|
bitfld.long 0x00 7. "SAM,SAM" "0,1"
|
|
bitfld.long 0x00 4.--6. "TSEG2,TSEG2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "TSEG1,TSEG1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "GIF,CAN Global Interrupt Flag Register"
|
|
bitfld.long 0x00 7. "RFPF,RFPF" "0,1"
|
|
bitfld.long 0x00 6. "WUIF,WUIF" "0,1"
|
|
bitfld.long 0x00 5. "RMLIF,RMLIF" "0,1"
|
|
bitfld.long 0x00 4. "TRMABF,TRMABF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TSOIF,TSOIF" "0,1"
|
|
bitfld.long 0x00 2. "BOIF,BOIF" "0,1"
|
|
bitfld.long 0x00 1. "EPIF,EPIF" "0,1"
|
|
bitfld.long 0x00 0. "WLIF,WLIF" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "GIM,CAN Global Interrupt Mask Register"
|
|
bitfld.long 0x00 7. "RFPM,RFPM" "0,1"
|
|
bitfld.long 0x00 6. "WUIM,WUIM" "0,1"
|
|
bitfld.long 0x00 5. "RMLIM,RMLIM" "0,1"
|
|
bitfld.long 0x00 4. "TRMABF,TRMABF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TSOIM,TSOIM" "0,1"
|
|
bitfld.long 0x00 2. "BOIM,BOIM" "0,1"
|
|
bitfld.long 0x00 1. "EPIM,EPIM" "0,1"
|
|
bitfld.long 0x00 0. "WLIM,WLIM" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MBTIF,CAN Mailbox Transmit Interrupt Flag Register"
|
|
bitfld.long 0x00 30. "MBTIF30,MBTIF30" "0,1"
|
|
bitfld.long 0x00 29. "MBTIF29,MBTIF29" "0,1"
|
|
bitfld.long 0x00 28. "MBTIF28,MBTIF28" "0,1"
|
|
bitfld.long 0x00 27. "MBTIF27,MBTIF27" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "MBTIF26,MBTIF26" "0,1"
|
|
bitfld.long 0x00 25. "MBTIF25,MBTIF25" "0,1"
|
|
bitfld.long 0x00 24. "MBTIF24,MBTIF24" "0,1"
|
|
bitfld.long 0x00 23. "MBTIF23,MBTIF23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "MBTIF22,MBTIF22" "0,1"
|
|
bitfld.long 0x00 21. "MBTIF21,MBTIF21" "0,1"
|
|
bitfld.long 0x00 20. "MBTIF20,MBTIF20" "0,1"
|
|
bitfld.long 0x00 19. "MBTIF19,MBTIF19" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "MBTIF18,MBTIF18" "0,1"
|
|
bitfld.long 0x00 17. "MBTIF17,MBTIF17" "0,1"
|
|
bitfld.long 0x00 16. "MBTIF16,MBTIF16" "0,1"
|
|
bitfld.long 0x00 15. "MBTIF15,MBTIF15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "MBTIF14,MBTIF14" "0,1"
|
|
bitfld.long 0x00 13. "MBTIF13,MBTIF13" "0,1"
|
|
bitfld.long 0x00 12. "MBTIF12,MBTIF12" "0,1"
|
|
bitfld.long 0x00 11. "MBTIF11,MBTIF11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "MBTIF10,MBTIF10" "0,1"
|
|
bitfld.long 0x00 9. "MBTIF9,MBTIF9" "0,1"
|
|
bitfld.long 0x00 8. "MBTIF8,MBTIF8" "0,1"
|
|
bitfld.long 0x00 7. "MBTIF7,MBTIF7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "MBTIF6,MBTIF6" "0,1"
|
|
bitfld.long 0x00 5. "MBTIF5,MBTIF5" "0,1"
|
|
bitfld.long 0x00 4. "MBTIF4,MBTIF4" "0,1"
|
|
bitfld.long 0x00 3. "MBTIF3,MBTIF3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "MBTIF2,MBTIF2" "0,1"
|
|
bitfld.long 0x00 1. "MBTIF1,MBTIF1" "0,1"
|
|
bitfld.long 0x00 0. "MBTIF0,MBTIF0" "0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "MBRIF,CAN Mailbox Receive Interrupt Flag Register"
|
|
bitfld.long 0x00 31. "MBRIF31,MBRIF31" "0,1"
|
|
bitfld.long 0x00 30. "MBRIF30,MBRIF30" "0,1"
|
|
bitfld.long 0x00 29. "MBRIF29,MBRIF29" "0,1"
|
|
bitfld.long 0x00 28. "MBRIF28,MBRIF28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "MBRIF27,MBRIF27" "0,1"
|
|
bitfld.long 0x00 26. "MBRIF26,MBRIF26" "0,1"
|
|
bitfld.long 0x00 25. "MBRIF25,MBRIF25" "0,1"
|
|
bitfld.long 0x00 24. "MBRIF24,MBRIF24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "MBRIF23,MBRIF23" "0,1"
|
|
bitfld.long 0x00 22. "MBRIF22,MBRIF22" "0,1"
|
|
bitfld.long 0x00 21. "MBRIF21,MBRIF21" "0,1"
|
|
bitfld.long 0x00 20. "MBRIF20,MBRIF20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "MBRIF19,MBRIF19" "0,1"
|
|
bitfld.long 0x00 18. "MBRIF18,MBRIF18" "0,1"
|
|
bitfld.long 0x00 17. "MBRIF17,MBRIF17" "0,1"
|
|
bitfld.long 0x00 16. "MBRIF16,MBRIF16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "MBRIF15,MBRIF15" "0,1"
|
|
bitfld.long 0x00 14. "MBRIF14,MBRIF14" "0,1"
|
|
bitfld.long 0x00 13. "MBRIF13,MBRIF13" "0,1"
|
|
bitfld.long 0x00 12. "MBRIF12,MBRIF12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "MBRIF11,MBRIF11" "0,1"
|
|
bitfld.long 0x00 10. "MBRIF10,MBRIF10" "0,1"
|
|
bitfld.long 0x00 9. "MBRIF9,MBRIF9" "0,1"
|
|
bitfld.long 0x00 8. "MBRIF8,MBRIF8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "MBRIF7,MBRIF7" "0,1"
|
|
bitfld.long 0x00 6. "MBRIF6,MBRIF6" "0,1"
|
|
bitfld.long 0x00 5. "MBRIF5,MBRIF5" "0,1"
|
|
bitfld.long 0x00 4. "MBRIF4,MBRIF4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MBRIF3,MBRIF3" "0,1"
|
|
bitfld.long 0x00 2. "MBRIF2,MBRIF2" "0,1"
|
|
bitfld.long 0x00 1. "MBRIF1,MBRIF1" "0,1"
|
|
bitfld.long 0x00 0. "MBRIF0,MBRIF0" "0,1"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "MBIM,CAN Mailbox Interrupt Mask Register"
|
|
bitfld.long 0x00 31. "MBIM31,MBIM31" "0,1"
|
|
bitfld.long 0x00 30. "MBIM30,MBIM30" "0,1"
|
|
bitfld.long 0x00 29. "MBIM29,MBIM29" "0,1"
|
|
bitfld.long 0x00 28. "MBIM28,MBIM28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "MBIM27,MBIM27" "0,1"
|
|
bitfld.long 0x00 26. "MBIM26,MBIM26" "0,1"
|
|
bitfld.long 0x00 25. "MBIM25,MBIM25" "0,1"
|
|
bitfld.long 0x00 24. "MBIM24,MBIM24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "MBIM23,MBIM23" "0,1"
|
|
bitfld.long 0x00 22. "MBIM22,MBIM22" "0,1"
|
|
bitfld.long 0x00 21. "MBIM21,MBIM21" "0,1"
|
|
bitfld.long 0x00 20. "MBIM20,MBIM20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "MBIM19,MBIM19" "0,1"
|
|
bitfld.long 0x00 18. "MBIM18,MBIM18" "0,1"
|
|
bitfld.long 0x00 17. "MBIM17,MBIM17" "0,1"
|
|
bitfld.long 0x00 16. "MBIM16,MBIM16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "MBIM15,MBIM15" "0,1"
|
|
bitfld.long 0x00 14. "MBIM14,MBIM14" "0,1"
|
|
bitfld.long 0x00 13. "MBIM13,MBIM13" "0,1"
|
|
bitfld.long 0x00 12. "MBIM12,MBIM12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "MBIM11,MBIM11" "0,1"
|
|
bitfld.long 0x00 10. "MBIM10,MBIM10" "0,1"
|
|
bitfld.long 0x00 9. "MBIM9,MBIM9" "0,1"
|
|
bitfld.long 0x00 8. "MBIM8,MBIM8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "MBIM7,MBIM7" "0,1"
|
|
bitfld.long 0x00 6. "MBIM6,MBIM6" "0,1"
|
|
bitfld.long 0x00 5. "MBIM5,MBIM5" "0,1"
|
|
bitfld.long 0x00 4. "MBIM4,MBIM4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MBIM3,MBIM3" "0,1"
|
|
bitfld.long 0x00 2. "MBIM2,MBIM2" "0,1"
|
|
bitfld.long 0x00 1. "MBIM1,MBIM1" "0,1"
|
|
bitfld.long 0x00 0. "MBIM0,MBIM0" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CDR,CAN Change Data Request"
|
|
bitfld.long 0x00 30. "CDR30,CDR30" "0,1"
|
|
bitfld.long 0x00 29. "CDR29,CDR29" "0,1"
|
|
bitfld.long 0x00 28. "CDR28,CDR28" "0,1"
|
|
bitfld.long 0x00 27. "CDR27,CDR27" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "CDR26,CDR26" "0,1"
|
|
bitfld.long 0x00 25. "CDR25,CDR25" "0,1"
|
|
bitfld.long 0x00 24. "CDR24,CDR24" "0,1"
|
|
bitfld.long 0x00 23. "CDR23,CDR23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "CDR22,CDR22" "0,1"
|
|
bitfld.long 0x00 21. "CDR21,CDR21" "0,1"
|
|
bitfld.long 0x00 20. "CDR20,CDR20" "0,1"
|
|
bitfld.long 0x00 19. "CDR19,CDR19" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CDR18,CDR18" "0,1"
|
|
bitfld.long 0x00 17. "CDR17,CDR17" "0,1"
|
|
bitfld.long 0x00 16. "CDR16,CDR16" "0,1"
|
|
bitfld.long 0x00 15. "CDR15,CDR15" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CDR14,CDR14" "0,1"
|
|
bitfld.long 0x00 13. "CDR13,CDR13" "0,1"
|
|
bitfld.long 0x00 12. "CDR12,CDR12" "0,1"
|
|
bitfld.long 0x00 11. "CDR11,CDR11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CDR10,CDR10" "0,1"
|
|
bitfld.long 0x00 9. "CDR9,CDR9" "0,1"
|
|
bitfld.long 0x00 8. "CDR8,CDR8" "0,1"
|
|
bitfld.long 0x00 7. "CDR7,CDR7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CDR6,CDR6" "0,1"
|
|
bitfld.long 0x00 5. "CDR5,CDR5" "0,1"
|
|
bitfld.long 0x00 4. "CDR4,CDR4" "0,1"
|
|
bitfld.long 0x00 3. "CDR3,CDR3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CDR2,CDR2" "0,1"
|
|
bitfld.long 0x00 1. "CDR1,CDR1" "0,1"
|
|
bitfld.long 0x00 0. "CDR0,CDR0" "0,1"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "RFP,CAN Remote Frame Pending Register"
|
|
bitfld.long 0x00 31. "RFP31,RFP31" "0,1"
|
|
bitfld.long 0x00 30. "RFP30,RFP30" "0,1"
|
|
bitfld.long 0x00 29. "RFP29,RFP29" "0,1"
|
|
bitfld.long 0x00 28. "RFP28,RFP28" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "RFP27,RFP27" "0,1"
|
|
bitfld.long 0x00 26. "RFP26,RFP26" "0,1"
|
|
bitfld.long 0x00 25. "RFP25,RFP25" "0,1"
|
|
bitfld.long 0x00 24. "RFP24,RFP24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RFP23,RFP23" "0,1"
|
|
bitfld.long 0x00 22. "RFP22,RFP22" "0,1"
|
|
bitfld.long 0x00 21. "RFP21,RFP21" "0,1"
|
|
bitfld.long 0x00 20. "RFP20,RFP20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "RFP19,RFP19" "0,1"
|
|
bitfld.long 0x00 18. "RFP18,RFP18" "0,1"
|
|
bitfld.long 0x00 17. "RFP17,RFP17" "0,1"
|
|
bitfld.long 0x00 16. "RFP16,RFP16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "RFP15,RFP15" "0,1"
|
|
bitfld.long 0x00 14. "RFP14,RFP14" "0,1"
|
|
bitfld.long 0x00 13. "RFP13,RFP13" "0,1"
|
|
bitfld.long 0x00 12. "RFP12,RFP12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RFP11,RFP11" "0,1"
|
|
bitfld.long 0x00 10. "RFP10,RFP10" "0,1"
|
|
bitfld.long 0x00 9. "RFP9,RFP9" "0,1"
|
|
bitfld.long 0x00 8. "RFP8,RFP8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RFP7,RFP7" "0,1"
|
|
bitfld.long 0x00 6. "RFP6,RFP6" "0,1"
|
|
bitfld.long 0x00 5. "RFP5,RFP5" "0,1"
|
|
bitfld.long 0x00 4. "RFP4,RFP4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RFP3,RFP3" "0,1"
|
|
bitfld.long 0x00 2. "RFP2,RFP2" "0,1"
|
|
bitfld.long 0x00 1. "RFP1,RFP1" "0,1"
|
|
bitfld.long 0x00 0. "RFP0,RFP0" "0,1"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CEC,CAN Error Counter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TEC,TEC"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REC,REC"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TSP,CAN Time Stamp Counter Prescaler Register"
|
|
bitfld.long 0x00 0.--3. "TSP,TSP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "TSC,CAN Time Stamp Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TSC,TSC"
|
|
tree.end
|
|
tree "RPAR (RAM Parity (RAMP))"
|
|
repeat 2. (list 0. 1.) (list ad:0x40043000 ad:0x400A3000)
|
|
tree "RPAR$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,RAM Parity control register"
|
|
bitfld.long 0x00 1. "RPARF,RPARF" "0,1"
|
|
bitfld.long 0x00 0. "RPAREN,RPAREN" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ST,RAM Parity status register"
|
|
bitfld.long 0x00 1. "RPARFG1,RPARFG1" "0,1"
|
|
bitfld.long 0x00 0. "RPARFG0,RPARFG0" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CLR,RAM Parity status clear register"
|
|
bitfld.long 0x00 1. "RPARCLR1,RPARCLR1" "0,1"
|
|
bitfld.long 0x00 0. "RPARCLR0,RPARCLR0" "0,1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "EAD0,RAM Parity Error address register 0"
|
|
hexmask.long 0x00 0.--31. 1. "RPAREADD0,RPAREADD0"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "EAD1,RAM Parity Error address register 1"
|
|
hexmask.long 0x00 0.--31. 1. "RPAREADD1,RPAREADD1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "DNFC (Digital Noise Filter (DNF))"
|
|
base ad:0x400A0800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CKCR,DNF clock Control register"
|
|
bitfld.long 0x00 0.--2. "NFCKS,NFCKS" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ENCR,DNF Enable register"
|
|
bitfld.long 0x00 15. "NFEN15,NFEN15" "0,1"
|
|
bitfld.long 0x00 14. "NFEN14,NFEN14" "0,1"
|
|
bitfld.long 0x00 13. "NFEN13,NFEN13" "0,1"
|
|
bitfld.long 0x00 12. "NFEN12,NFEN12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "NFEN11,NFEN11" "0,1"
|
|
bitfld.long 0x00 10. "NFEN10,NFEN10" "0,1"
|
|
bitfld.long 0x00 9. "NFEN9,NFEN9" "0,1"
|
|
bitfld.long 0x00 8. "NFEN8,NFEN8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "NFEN7,NFEN7" "0,1"
|
|
bitfld.long 0x00 6. "NFEN6,NFEN6" "0,1"
|
|
bitfld.long 0x00 5. "NFEN5,NFEN5" "0,1"
|
|
bitfld.long 0x00 4. "NFEN4,NFEN4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "NFEN3,NFEN3" "0,1"
|
|
bitfld.long 0x00 2. "NFEN2,NFEN2" "0,1"
|
|
bitfld.long 0x00 1. "NFEN1,NFEN1" "0,1"
|
|
bitfld.long 0x00 0. "NFEN0,NFEN0" "0,1"
|
|
tree.end
|
|
tree "ADA (12-bit Analog to Digital Converter(ADC))"
|
|
base ad:0x400BA000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,AD Control Register 0"
|
|
bitfld.long 0x00 7. "ADEN,ADEN" "0,1"
|
|
bitfld.long 0x00 1. "SGL,SGL" "0,1"
|
|
bitfld.long 0x00 0. "CNT,CNT" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,AD Control Register 1"
|
|
bitfld.long 0x00 6. "CNTDMEN,CNTDMEN" "0,1"
|
|
bitfld.long 0x00 5. "SGLDMEN,SGLDMEN" "0,1"
|
|
bitfld.long 0x00 4. "TRGDMEN,TRGDMEN" "0,1"
|
|
bitfld.long 0x00 0. "TRGEN,TRGEN" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ST,AD Status Register"
|
|
bitfld.long 0x00 7. "ADBF,ADBF" "0,1"
|
|
bitfld.long 0x00 3. "CNTF,CNTF" "0,1"
|
|
bitfld.long 0x00 2. "SNGF,SNGF" "0,1"
|
|
bitfld.long 0x00 1. "TRGF,TRGF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMDF,PMDF" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,AD Conversion Clock Setting Register"
|
|
bitfld.long 0x00 3.--6. "EXAZ,EXAZ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "VADCLK,VADCLK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MOD0,AD Mode Control Register 0"
|
|
bitfld.long 0x00 1. "RCUT,RCUT" "0,1"
|
|
bitfld.long 0x00 0. "DACON,DACON" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MOD1,AD Mode Control Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MOD1,MOD1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MOD2,AD Mode Control Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "MOD2,MOD2"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPEN,AD Monitor function interrupt permission register"
|
|
bitfld.long 0x00 1. "CMP1EN,CMP1EN" "0,1"
|
|
bitfld.long 0x00 0. "CMP0EN,CMP0EN" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CMPCR0,AD Monitor function Setting Register 0"
|
|
bitfld.long 0x00 8.--11. "CMPCNT0,CMPCNT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "CMPCND0,CMPCND0" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG0,ADBIG0" "0,1"
|
|
bitfld.long 0x00 0.--4. "REGS0,REGS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CMPCR1,AD Monitor function Setting Register 1"
|
|
bitfld.long 0x00 8.--11. "CMPCNT1,CMPCNT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "CMPCND1,CMPCND1" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG1,ADBIG1" "0,1"
|
|
bitfld.long 0x00 0.--4. "REGS1,REGS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CMP0,AD Conversion Result Comparison Register 0"
|
|
hexmask.long.word 0x00 4.--15. 1. "AD0CMP0,AD0CMP0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CMP1,AD Conversion Result Comparison Register 1"
|
|
hexmask.long.word 0x00 4.--15. 1. "AD0CMP1,AD0CMP1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PSEL0,AD PMD Trigger Program Number Select Register 0"
|
|
bitfld.long 0x00 7. "PENS0,PENS0" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS0,PMDS0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PSEL1,AD PMD Trigger Program Number Select Register 1"
|
|
bitfld.long 0x00 7. "PENS1,PENS1" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS1,PMDS1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PSEL2,AD PMD Trigger Program Number Select Register 2"
|
|
bitfld.long 0x00 7. "PENS2,PENS2" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS2,PMDS2" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PSEL3,AD PMD Trigger Program Number Select Register 3"
|
|
bitfld.long 0x00 7. "PENS3,PENS3" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS3,PMDS3" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PSEL4,AD PMD Trigger Program Number Select Register 4"
|
|
bitfld.long 0x00 7. "PENS4,PENS4" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS4,PMDS4" "0,1,2,3,4,5,6,7"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PSEL5,AD PMD Trigger Program Number Select Register 5"
|
|
bitfld.long 0x00 7. "PENS5,PENS5" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS5,PMDS5" "0,1,2,3,4,5,6,7"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PSEL6,AD PMD Trigger Program Number Select Register 6"
|
|
bitfld.long 0x00 7. "PENS6,PENS6" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS6,PMDS6" "0,1,2,3,4,5,6,7"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PSEL7,AD PMD Trigger Program Number Select Register 7"
|
|
bitfld.long 0x00 7. "PENS7,PENS7" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS7,PMDS7" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PSEL8,AD PMD Trigger Program Number Select Register 8"
|
|
bitfld.long 0x00 7. "PENS8,PENS8" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS8,PMDS8" "0,1,2,3,4,5,6,7"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PSEL9,AD PMD Trigger Program Number Select Register 9"
|
|
bitfld.long 0x00 7. "PENS9,PENS9" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS9,PMDS9" "0,1,2,3,4,5,6,7"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PSEL10,AD PMD Trigger Program Number Select Register 10"
|
|
bitfld.long 0x00 7. "PENS10,PENS10" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS10,PMDS10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PSEL11,AD PMD Trigger Program Number Select Register 11"
|
|
bitfld.long 0x00 7. "PENS11,PENS11" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS11,PMDS11" "0,1,2,3,4,5,6,7"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PINTS0,AD PMD Trigger Interrupt Select Register 0"
|
|
bitfld.long 0x00 0.--1. "INTSEL0,INTSEL0" "0,1,2,3"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PINTS1,AD PMD Trigger Interrupt Select Register 1"
|
|
bitfld.long 0x00 0.--1. "INTSEL1,INTSEL1" "0,1,2,3"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PINTS2,AD PMD Trigger Interrupt Select Register 2"
|
|
bitfld.long 0x00 0.--1. "INTSEL2,INTSEL2" "0,1,2,3"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PINTS3,AD PMD Trigger Interrupt Select Register 3"
|
|
bitfld.long 0x00 0.--1. "INTSEL3,INTSEL3" "0,1,2,3"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PINTS4,AD PMD Trigger Interrupt Select Register 4"
|
|
bitfld.long 0x00 0.--1. "INTSEL4,INTSEL4" "0,1,2,3"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PINTS5,AD PMD Trigger Interrupt Select Register 5"
|
|
bitfld.long 0x00 0.--1. "INTSEL5,INTSEL5" "0,1,2,3"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PINTS6,AD PMD Trigger Interrupt Select Register 6"
|
|
bitfld.long 0x00 0.--1. "INTSEL6,INTSEL6" "0,1,2,3"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PINTS7,AD PMD Trigger Interrupt Select Register 7"
|
|
bitfld.long 0x00 0.--1. "INTSEL7,INTSEL7" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PREGS,AD PMD Trigger Conversion Result Storage Select Register 1"
|
|
bitfld.long 0x00 28.--30. "REGSEL7,REGSEL7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "REGSEL6,REGSEL6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. "REGSEL5,REGSEL5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "REGSEL4,REGSEL4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "REGSEL3,REGSEL3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "REGSEL2,REGSEL2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "REGSEL1,REGSEL1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "REGSEL0,REGSEL0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PSET0,AD PMD Trigger Program Register 0"
|
|
bitfld.long 0x00 31. "ENSP03,ENSP03" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS03,UVWIS03" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP03,AINSP03" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP02,ENSP02" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS02,UVWIS02" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP02,AINSP02" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP01,ENSP01" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS01,UVWIS01" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP01,AINSP01" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP00,ENSP00" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS00,UVWIS00" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP00,AINSP00" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "PSET1,AD PMD Trigger Program Register 1"
|
|
bitfld.long 0x00 31. "ENSP13,ENSP13" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS13,UVWIS13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP13,AINSP13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP12,ENSP12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS12,UVWIS12" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP12,AINSP12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP11,ENSP11" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS11,UVWIS11" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP11,AINSP11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP10,ENSP10" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS10,UVWIS10" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP10,AINSP10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PSET2,AD PMD Trigger Program Register 2"
|
|
bitfld.long 0x00 31. "ENSP23,ENSP23" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS23,UVWIS23" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP23,AINSP23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP22,ENSP22" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS22,UVWIS22" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP22,AINSP22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP21,ENSP21" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS21,UVWIS21" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP21,AINSP21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP20,ENSP20" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS20,UVWIS20" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP20,AINSP20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "PSET3,AD PMD Trigger Program Register 3"
|
|
bitfld.long 0x00 31. "ENSP33,ENSP33" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS33,UVWIS33" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP33,AINSP33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP32,ENSP32" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS32,UVWIS32" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP32,AINSP32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP31,ENSP31" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS31,UVWIS31" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP31,AINSP31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP30,ENSP30" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS30,UVWIS30" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP30,AINSP30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PSET4,AD PMD Trigger Program Register 4"
|
|
bitfld.long 0x00 31. "ENSP43,ENSP43" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS43,UVWIS43" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP43,AINSP43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP42,ENSP42" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS42,UVWIS42" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP42,AINSP42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP41,ENSP41" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS41,UVWIS41" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP41,AINSP41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP40,ENSP40" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS40,UVWIS40" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP40,AINSP40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "PSET5,AD PMD Trigger Program Register 5"
|
|
bitfld.long 0x00 31. "ENSP53,ENSP53" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS53,UVWIS53" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP53,AINSP53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP52,ENSP52" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS52,UVWIS52" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP52,AINSP52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP51,ENSP51" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS51,UVWIS51" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP51,AINSP51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP50,ENSP50" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS50,UVWIS50" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP50,AINSP50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xB8++0x03
|
|
line.long 0x00 "PSET6,AD PMD Trigger Program Register 6"
|
|
bitfld.long 0x00 31. "ENSP63,ENSP63" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS63,UVWIS63" "0,1,2,3"
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|
bitfld.long 0x00 24.--28. "AINSP63,AINSP63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 23. "ENSP62,ENSP62" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS62,UVWIS62" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP62,AINSP62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 15. "ENSP61,ENSP61" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS61,UVWIS61" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP61,AINSP61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 7. "ENSP60,ENSP60" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS60,UVWIS60" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP60,AINSP60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xBC++0x03
|
|
line.long 0x00 "PSET7,AD PMD Trigger Program Register 7"
|
|
bitfld.long 0x00 31. "ENSP73,ENSP73" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS73,UVWIS73" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP73,AINSP73" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 23. "ENSP72,ENSP72" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS72,UVWIS72" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP72,AINSP72" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP71,ENSP71" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS71,UVWIS71" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP71,AINSP71" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 7. "ENSP70,ENSP70" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS70,UVWIS70" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP70,AINSP70" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xC0++0x03
|
|
line.long 0x00 "TSET0,AD General purpose Trigger Program Register 0"
|
|
bitfld.long 0x00 7. "ENINT0,ENINT0" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS0,TRGS0" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST0,AINST0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xC4++0x03
|
|
line.long 0x00 "TSET1,AD General purpose Trigger Program Register 1"
|
|
bitfld.long 0x00 7. "ENINT1,ENINT1" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS1,TRGS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST1,AINST1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TSET2,AD General purpose Trigger Program Register 2"
|
|
bitfld.long 0x00 7. "ENINT2,ENINT2" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS2,TRGS2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST2,AINST2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TSET3,AD General purpose Trigger Program Register 3"
|
|
bitfld.long 0x00 7. "ENINT3,ENINT3" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS3,TRGS3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST3,AINST3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TSET4,AD General purpose Trigger Program Register 4"
|
|
bitfld.long 0x00 7. "ENINT4,ENINT4" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS4,TRGS4" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST4,AINST4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xD4++0x03
|
|
line.long 0x00 "TSET5,AD General purpose Trigger Program Register 5"
|
|
bitfld.long 0x00 7. "ENINT5,ENINT5" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS5,TRGS5" "0,1,2,3"
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|
bitfld.long 0x00 0.--4. "AINST5,AINST5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xD8++0x03
|
|
line.long 0x00 "TSET6,AD General purpose Trigger Program Register 6"
|
|
bitfld.long 0x00 7. "ENINT6,ENINT6" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS6,TRGS6" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST6,AINST6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xDC++0x03
|
|
line.long 0x00 "TSET7,AD General purpose Trigger Program Register 7"
|
|
bitfld.long 0x00 7. "ENINT7,ENINT7" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS7,TRGS7" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST7,AINST7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xE0++0x03
|
|
line.long 0x00 "TSET8,AD General purpose Trigger Program Register 8"
|
|
bitfld.long 0x00 7. "ENINT8,ENINT8" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS8,TRGS8" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST8,AINST8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xE4++0x03
|
|
line.long 0x00 "TSET9,AD General purpose Trigger Program Register 9"
|
|
bitfld.long 0x00 7. "ENINT9,ENINT9" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS9,TRGS9" "0,1,2,3"
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|
bitfld.long 0x00 0.--4. "AINST9,AINST9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xE8++0x03
|
|
line.long 0x00 "TSET10,AD General purpose Trigger Program Register 10"
|
|
bitfld.long 0x00 7. "ENINT10,ENINT10" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS10,TRGS10" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST10,AINST10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TSET11,AD General purpose Trigger Program Register 11"
|
|
bitfld.long 0x00 7. "ENINT11,ENINT11" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS11,TRGS11" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST11,AINST11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TSET12,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 7. "ENINT12,ENINT12" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS12,TRGS12" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST12,AINST12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TSET13,AD General purpose Trigger Program Register 13"
|
|
bitfld.long 0x00 7. "ENINT13,ENINT13" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS13,TRGS13" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST13,AINST13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TSET14,AD General purpose Trigger Program Register 14"
|
|
bitfld.long 0x00 7. "ENINT14,ENINT14" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS14,TRGS14" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST14,AINST14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TSET15,AD General purpose Trigger Program Register 15"
|
|
bitfld.long 0x00 7. "ENINT15,ENINT15" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS15,TRGS15" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST15,AINST15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TSET16,AD General purpose Trigger Program Register 16"
|
|
bitfld.long 0x00 7. "ENINT16,ENINT16" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS16,TRGS16" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST16,AINST16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TSET17,AD General purpose Trigger Program Register 17"
|
|
bitfld.long 0x00 7. "ENINT17,ENINT17" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS17,TRGS17" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST17,AINST17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TSET18,AD General purpose Trigger Program Register 18"
|
|
bitfld.long 0x00 7. "ENINT18,ENINT18" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS18,TRGS18" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST18,AINST18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TSET19,AD General purpose Trigger Program Register 19"
|
|
bitfld.long 0x00 7. "ENINT19,ENINT19" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS19,TRGS19" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST19,AINST19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TSET20,AD General purpose Trigger Program Register 20"
|
|
bitfld.long 0x00 7. "ENINT20,ENINT20" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS20,TRGS20" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST20,AINST20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TSET21,AD General purpose Trigger Program Register 21"
|
|
bitfld.long 0x00 7. "ENINT21,ENINT21" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS21,TRGS21" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST21,AINST21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TSET22,AD General purpose Trigger Program Register 22"
|
|
bitfld.long 0x00 7. "ENINT22,ENINT22" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS22,TRGS22" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST22,AINST22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TSET23,AD General purpose Trigger Program Register 23"
|
|
bitfld.long 0x00 7. "ENINT23,ENINT23" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS23,TRGS23" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST23,AINST23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "REG0,AD Conversion Result Register 0"
|
|
bitfld.long 0x00 29. "ADOVRF_M0,ADOVRF_M0" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M0,ADRF_M0" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M0,ADR_M0"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR0,ADR0"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF0,ADOVRF0" "0,1"
|
|
bitfld.long 0x00 0. "ADRF0,ADRF0" "0,1"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "REG1,AD Conversion Result Register 1"
|
|
bitfld.long 0x00 29. "ADOVRF_M1,ADOVRF_M1" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M1,ADRF_M1" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M1,ADR_M1"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR1,ADR1"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF1,ADOVRF1" "0,1"
|
|
bitfld.long 0x00 0. "ADRF1,ADRF1" "0,1"
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "REG2,AD Conversion Result Register 2"
|
|
bitfld.long 0x00 29. "ADOVRF_M2,ADOVRF_M2" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M2,ADRF_M2" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M2,ADR_M2"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR2,ADR2"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF2,ADOVRF2" "0,1"
|
|
bitfld.long 0x00 0. "ADRF2,ADRF2" "0,1"
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "REG3,AD Conversion Result Register 3"
|
|
bitfld.long 0x00 29. "ADOVRF_M3,ADOVRF_M3" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M3,ADRF_M3" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M3,ADR_M3"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR3,ADR3"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF3,ADOVRF3" "0,1"
|
|
bitfld.long 0x00 0. "ADRF3,ADRF3" "0,1"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "REG4,AD Conversion Result Register 4"
|
|
bitfld.long 0x00 29. "ADOVRF_M4,ADOVRF_M4" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M4,ADRF_M4" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M4,ADR_M4"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR4,ADR4"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF4,ADOVRF4" "0,1"
|
|
bitfld.long 0x00 0. "ADRF4,ADRF4" "0,1"
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "REG5,AD Conversion Result Register 5"
|
|
bitfld.long 0x00 29. "ADOVRF_M5,ADOVRF_M5" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M5,ADRF_M5" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M5,ADR_M5"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR5,ADR5"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF5,ADOVRF5" "0,1"
|
|
bitfld.long 0x00 0. "ADRF5,ADRF5" "0,1"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "REG6,AD Conversion Result Register 6"
|
|
bitfld.long 0x00 29. "ADOVRF_M6,ADOVRF_M6" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M6,ADRF_M6" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M6,ADR_M6"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR6,ADR6"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF6,ADOVRF6" "0,1"
|
|
bitfld.long 0x00 0. "ADRF6,ADRF6" "0,1"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "REG7,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVRF_M7,ADOVRF_M7" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M7,ADRF_M7" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M7,ADR_M7"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR7,ADR7"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF7,ADOVRF7" "0,1"
|
|
bitfld.long 0x00 0. "ADRF7,ADRF7" "0,1"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "REG8,AD Conversion Result Register 8"
|
|
bitfld.long 0x00 29. "ADOVRF_M8,ADOVRF_M8" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M8,ADRF_M8" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M8,ADR_M8"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR8,ADR8"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF8,ADOVRF8" "0,1"
|
|
bitfld.long 0x00 0. "ADRF8,ADRF8" "0,1"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "REG9,AD Conversion Result Register 9"
|
|
bitfld.long 0x00 29. "ADOVRF_M9,ADOVRF_M9" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M9,ADRF_M9" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M9,ADR_M9"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR9,ADR9"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF9,ADOVRF9" "0,1"
|
|
bitfld.long 0x00 0. "ADRF9,ADRF9" "0,1"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "REG10,AD Conversion Result Register 10"
|
|
bitfld.long 0x00 29. "ADOVRF_M10,ADOVRF_M10" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M10,ADRF_M10" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M10,ADR_M10"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR10,ADR10"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF10,ADOVRF10" "0,1"
|
|
bitfld.long 0x00 0. "ADRF10,ADRF10" "0,1"
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "REG11,AD Conversion Result Register 11"
|
|
bitfld.long 0x00 29. "ADOVRF_M11,ADOVRF_M11" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M11,ADRF_M11" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M11,ADR_M11"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR11,ADR11"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF11,ADOVRF11" "0,1"
|
|
bitfld.long 0x00 0. "ADRF11,ADRF11" "0,1"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "REG12,AD Conversion Result Register 12"
|
|
bitfld.long 0x00 29. "ADOVRF_M12,ADOVRF_M12" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M12,ADRF_M12" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M12,ADR_M12"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR12,ADR12"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF12,ADOVRF12" "0,1"
|
|
bitfld.long 0x00 0. "ADRF12,ADRF12" "0,1"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "REG13,AD Conversion Result Register 13"
|
|
bitfld.long 0x00 29. "ADOVRF_M13,ADOVRF_M13" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M13,ADRF_M13" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M13,ADR_M13"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR13,ADR13"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF13,ADOVRF13" "0,1"
|
|
bitfld.long 0x00 0. "ADRF13,ADRF13" "0,1"
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "REG14,AD Conversion Result Register 14"
|
|
bitfld.long 0x00 29. "ADOVRF_M14,ADOVRF_M14" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M14,ADRF_M14" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M14,ADR_M14"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR14,ADR14"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF14,ADOVRF14" "0,1"
|
|
bitfld.long 0x00 0. "ADRF14,ADRF14" "0,1"
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "REG15,AD Conversion Result Register 15"
|
|
bitfld.long 0x00 29. "ADOVRF_M15,ADOVRF_M15" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M15,ADRF_M15" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M15,ADR_M15"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR15,ADR15"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF15,ADOVRF15" "0,1"
|
|
bitfld.long 0x00 0. "ADRF15,ADRF15" "0,1"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "REG16,AD Conversion Result Register 16"
|
|
bitfld.long 0x00 29. "ADOVRF_M16,ADOVRF_M16" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M16,ADRF_M16" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M16,ADR_M16"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR16,ADR16"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF16,ADOVRF16" "0,1"
|
|
bitfld.long 0x00 0. "ADRF16,ADRF16" "0,1"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "REG17,AD Conversion Result Register 17"
|
|
bitfld.long 0x00 29. "ADOVRF_M17,ADOVRF_M17" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M17,ADRF_M17" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M17,ADR_M17"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR17,ADR17"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF17,ADOVRF17" "0,1"
|
|
bitfld.long 0x00 0. "ADRF17,ADRF17" "0,1"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "REG18,AD Conversion Result Register 18"
|
|
bitfld.long 0x00 29. "ADOVRF_M18,ADOVRF_M18" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M18,ADRF_M18" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M18,ADR_M18"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR18,ADR18"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF18,ADOVRF18" "0,1"
|
|
bitfld.long 0x00 0. "ADRF18,ADRF18" "0,1"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "REG19,AD Conversion Result Register 19"
|
|
bitfld.long 0x00 29. "ADOVRF_M19,ADOVRF_M19" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M19,ADRF_M19" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M19,ADR_M19"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR19,ADR19"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF19,ADOVRF19" "0,1"
|
|
bitfld.long 0x00 0. "ADRF19,ADRF19" "0,1"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "REG20,AD Conversion Result Register 20"
|
|
bitfld.long 0x00 29. "ADOVRF_M20,ADOVRF_M20" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M20,ADRF_M20" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M20,ADR_M20"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR20,ADR20"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF20,ADOVRF20" "0,1"
|
|
bitfld.long 0x00 0. "ADRF20,ADRF20" "0,1"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "REG21,AD Conversion Result Register 21"
|
|
bitfld.long 0x00 29. "ADOVRF_M21,ADOVRF_M21" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M21,ADRF_M21" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M21,ADR_M21"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR21,ADR21"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF21,ADOVRF21" "0,1"
|
|
bitfld.long 0x00 0. "ADRF21,ADRF21" "0,1"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "REG22,AD Conversion Result Register 22"
|
|
bitfld.long 0x00 29. "ADOVRF_M22,ADOVRF_M22" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M22,ADRF_M22" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M22,ADR_M22"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR22,ADR22"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF22,ADOVRF22" "0,1"
|
|
bitfld.long 0x00 0. "ADRF22,ADRF22" "0,1"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "REG23,AD Conversion Result Register 23"
|
|
bitfld.long 0x00 29. "ADOVRF_M23,ADOVRF_M23" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M23,ADRF_M23" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M23,ADR_M23"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR23,ADR23"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF23,ADOVRF23" "0,1"
|
|
bitfld.long 0x00 0. "ADRF23,ADRF23" "0,1"
|
|
tree.end
|
|
tree "ADB (12-bit Analog to Digital Converter(ADC))"
|
|
base ad:0x400BA400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,AD Control Register 0"
|
|
bitfld.long 0x00 7. "ADEN,ADEN" "0,1"
|
|
bitfld.long 0x00 1. "SGL,SGL" "0,1"
|
|
bitfld.long 0x00 0. "CNT,CNT" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,AD Control Register 1"
|
|
bitfld.long 0x00 6. "CNTDMEN,CNTDMEN" "0,1"
|
|
bitfld.long 0x00 5. "SGLDMEN,SGLDMEN" "0,1"
|
|
bitfld.long 0x00 4. "TRGDMEN,TRGDMEN" "0,1"
|
|
bitfld.long 0x00 0. "TRGEN,TRGEN" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ST,AD Status Register"
|
|
bitfld.long 0x00 7. "ADBF,ADBF" "0,1"
|
|
bitfld.long 0x00 3. "CNTF,CNTF" "0,1"
|
|
bitfld.long 0x00 2. "SNGF,SNGF" "0,1"
|
|
bitfld.long 0x00 1. "TRGF,TRGF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMDF,PMDF" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,AD Conversion Clock Setting Register"
|
|
bitfld.long 0x00 3.--6. "EXAZ,EXAZ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "VADCLK,VADCLK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MOD0,AD Mode Control Register 0"
|
|
bitfld.long 0x00 1. "RCUT,RCUT" "0,1"
|
|
bitfld.long 0x00 0. "DACON,DACON" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MOD1,AD Mode Control Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MOD1,MOD1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MOD2,AD Mode Control Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "MOD2,MOD2"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPEN,AD Monitor function interrupt permission register"
|
|
bitfld.long 0x00 1. "CMP1EN,CMP1EN" "0,1"
|
|
bitfld.long 0x00 0. "CMP0EN,CMP0EN" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CMPCR0,AD Monitor function Setting Register 0"
|
|
bitfld.long 0x00 8.--11. "CMPCNT0,CMPCNT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "CMPCND0,CMPCND0" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG0,ADBIG0" "0,1"
|
|
bitfld.long 0x00 0.--4. "REGS0,REGS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CMPCR1,AD Monitor function Setting Register 1"
|
|
bitfld.long 0x00 8.--11. "CMPCNT1,CMPCNT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "CMPCND1,CMPCND1" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG1,ADBIG1" "0,1"
|
|
bitfld.long 0x00 0.--4. "REGS1,REGS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CMP0,AD Conversion Result Comparison Register 0"
|
|
hexmask.long.word 0x00 4.--15. 1. "AD0CMP0,AD0CMP0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CMP1,AD Conversion Result Comparison Register 1"
|
|
hexmask.long.word 0x00 4.--15. 1. "AD0CMP1,AD0CMP1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PSEL0,AD PMD Trigger Program Number Select Register 0"
|
|
bitfld.long 0x00 7. "PENS0,PENS0" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS0,PMDS0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PSEL1,AD PMD Trigger Program Number Select Register 1"
|
|
bitfld.long 0x00 7. "PENS1,PENS1" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS1,PMDS1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PSEL2,AD PMD Trigger Program Number Select Register 2"
|
|
bitfld.long 0x00 7. "PENS2,PENS2" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS2,PMDS2" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PSEL3,AD PMD Trigger Program Number Select Register 3"
|
|
bitfld.long 0x00 7. "PENS3,PENS3" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS3,PMDS3" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PSEL4,AD PMD Trigger Program Number Select Register 4"
|
|
bitfld.long 0x00 7. "PENS4,PENS4" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS4,PMDS4" "0,1,2,3,4,5,6,7"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PSEL5,AD PMD Trigger Program Number Select Register 5"
|
|
bitfld.long 0x00 7. "PENS5,PENS5" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS5,PMDS5" "0,1,2,3,4,5,6,7"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PSEL6,AD PMD Trigger Program Number Select Register 6"
|
|
bitfld.long 0x00 7. "PENS6,PENS6" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS6,PMDS6" "0,1,2,3,4,5,6,7"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PSEL7,AD PMD Trigger Program Number Select Register 7"
|
|
bitfld.long 0x00 7. "PENS7,PENS7" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS7,PMDS7" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PSEL8,AD PMD Trigger Program Number Select Register 8"
|
|
bitfld.long 0x00 7. "PENS8,PENS8" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS8,PMDS8" "0,1,2,3,4,5,6,7"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PSEL9,AD PMD Trigger Program Number Select Register 9"
|
|
bitfld.long 0x00 7. "PENS9,PENS9" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS9,PMDS9" "0,1,2,3,4,5,6,7"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PSEL10,AD PMD Trigger Program Number Select Register 10"
|
|
bitfld.long 0x00 7. "PENS10,PENS10" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS10,PMDS10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PSEL11,AD PMD Trigger Program Number Select Register 11"
|
|
bitfld.long 0x00 7. "PENS11,PENS11" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS11,PMDS11" "0,1,2,3,4,5,6,7"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PINTS0,AD PMD Trigger Interrupt Select Register 0"
|
|
bitfld.long 0x00 0.--1. "INTSEL0,INTSEL0" "0,1,2,3"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PINTS1,AD PMD Trigger Interrupt Select Register 1"
|
|
bitfld.long 0x00 0.--1. "INTSEL1,INTSEL1" "0,1,2,3"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PINTS2,AD PMD Trigger Interrupt Select Register 2"
|
|
bitfld.long 0x00 0.--1. "INTSEL2,INTSEL2" "0,1,2,3"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PINTS3,AD PMD Trigger Interrupt Select Register 3"
|
|
bitfld.long 0x00 0.--1. "INTSEL3,INTSEL3" "0,1,2,3"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PINTS4,AD PMD Trigger Interrupt Select Register 4"
|
|
bitfld.long 0x00 0.--1. "INTSEL4,INTSEL4" "0,1,2,3"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PINTS5,AD PMD Trigger Interrupt Select Register 5"
|
|
bitfld.long 0x00 0.--1. "INTSEL5,INTSEL5" "0,1,2,3"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PINTS6,AD PMD Trigger Interrupt Select Register 6"
|
|
bitfld.long 0x00 0.--1. "INTSEL6,INTSEL6" "0,1,2,3"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PINTS7,AD PMD Trigger Interrupt Select Register 7"
|
|
bitfld.long 0x00 0.--1. "INTSEL7,INTSEL7" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PREGS,AD PMD Trigger Conversion Result Storage Select Register 1"
|
|
bitfld.long 0x00 28.--30. "REGSEL7,REGSEL7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "REGSEL6,REGSEL6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. "REGSEL5,REGSEL5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "REGSEL4,REGSEL4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "REGSEL3,REGSEL3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "REGSEL2,REGSEL2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "REGSEL1,REGSEL1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "REGSEL0,REGSEL0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PSET0,AD PMD Trigger Program Register 0"
|
|
bitfld.long 0x00 31. "ENSP03,ENSP03" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS03,UVWIS03" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP03,AINSP03" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP02,ENSP02" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS02,UVWIS02" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP02,AINSP02" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP01,ENSP01" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS01,UVWIS01" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP01,AINSP01" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP00,ENSP00" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS00,UVWIS00" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP00,AINSP00" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "PSET1,AD PMD Trigger Program Register 1"
|
|
bitfld.long 0x00 31. "ENSP13,ENSP13" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS13,UVWIS13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP13,AINSP13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP12,ENSP12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS12,UVWIS12" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP12,AINSP12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP11,ENSP11" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS11,UVWIS11" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP11,AINSP11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP10,ENSP10" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS10,UVWIS10" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP10,AINSP10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PSET2,AD PMD Trigger Program Register 2"
|
|
bitfld.long 0x00 31. "ENSP23,ENSP23" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS23,UVWIS23" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP23,AINSP23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP22,ENSP22" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS22,UVWIS22" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP22,AINSP22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP21,ENSP21" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS21,UVWIS21" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP21,AINSP21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP20,ENSP20" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS20,UVWIS20" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP20,AINSP20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "PSET3,AD PMD Trigger Program Register 3"
|
|
bitfld.long 0x00 31. "ENSP33,ENSP33" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS33,UVWIS33" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP33,AINSP33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP32,ENSP32" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS32,UVWIS32" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP32,AINSP32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP31,ENSP31" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS31,UVWIS31" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP31,AINSP31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP30,ENSP30" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS30,UVWIS30" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP30,AINSP30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PSET4,AD PMD Trigger Program Register 4"
|
|
bitfld.long 0x00 31. "ENSP43,ENSP43" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS43,UVWIS43" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP43,AINSP43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP42,ENSP42" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS42,UVWIS42" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP42,AINSP42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP41,ENSP41" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS41,UVWIS41" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP41,AINSP41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP40,ENSP40" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS40,UVWIS40" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP40,AINSP40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "PSET5,AD PMD Trigger Program Register 5"
|
|
bitfld.long 0x00 31. "ENSP53,ENSP53" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS53,UVWIS53" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP53,AINSP53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP52,ENSP52" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS52,UVWIS52" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP52,AINSP52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP51,ENSP51" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS51,UVWIS51" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP51,AINSP51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP50,ENSP50" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS50,UVWIS50" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP50,AINSP50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PSET6,AD PMD Trigger Program Register 6"
|
|
bitfld.long 0x00 31. "ENSP63,ENSP63" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS63,UVWIS63" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP63,AINSP63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP62,ENSP62" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS62,UVWIS62" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP62,AINSP62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP61,ENSP61" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS61,UVWIS61" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP61,AINSP61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP60,ENSP60" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS60,UVWIS60" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP60,AINSP60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "PSET7,AD PMD Trigger Program Register 7"
|
|
bitfld.long 0x00 31. "ENSP73,ENSP73" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS73,UVWIS73" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP73,AINSP73" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP72,ENSP72" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS72,UVWIS72" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP72,AINSP72" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP71,ENSP71" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS71,UVWIS71" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP71,AINSP71" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP70,ENSP70" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS70,UVWIS70" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP70,AINSP70" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TSET0,AD General purpose Trigger Program Register 0"
|
|
bitfld.long 0x00 7. "ENINT0,ENINT0" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS0,TRGS0" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST0,AINST0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TSET1,AD General purpose Trigger Program Register 1"
|
|
bitfld.long 0x00 7. "ENINT1,ENINT1" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS1,TRGS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST1,AINST1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TSET2,AD General purpose Trigger Program Register 2"
|
|
bitfld.long 0x00 7. "ENINT2,ENINT2" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS2,TRGS2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST2,AINST2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TSET3,AD General purpose Trigger Program Register 3"
|
|
bitfld.long 0x00 7. "ENINT3,ENINT3" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS3,TRGS3" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST3,AINST3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TSET4,AD General purpose Trigger Program Register 4"
|
|
bitfld.long 0x00 7. "ENINT4,ENINT4" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS4,TRGS4" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST4,AINST4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TSET5,AD General purpose Trigger Program Register 5"
|
|
bitfld.long 0x00 7. "ENINT5,ENINT5" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS5,TRGS5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST5,AINST5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TSET6,AD General purpose Trigger Program Register 6"
|
|
bitfld.long 0x00 7. "ENINT6,ENINT6" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS6,TRGS6" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST6,AINST6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TSET7,AD General purpose Trigger Program Register 7"
|
|
bitfld.long 0x00 7. "ENINT7,ENINT7" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS7,TRGS7" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST7,AINST7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TSET8,AD General purpose Trigger Program Register 8"
|
|
bitfld.long 0x00 7. "ENINT8,ENINT8" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS8,TRGS8" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST8,AINST8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TSET9,AD General purpose Trigger Program Register 9"
|
|
bitfld.long 0x00 7. "ENINT9,ENINT9" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS9,TRGS9" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST9,AINST9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TSET10,AD General purpose Trigger Program Register 10"
|
|
bitfld.long 0x00 7. "ENINT10,ENINT10" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS10,TRGS10" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST10,AINST10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TSET11,AD General purpose Trigger Program Register 11"
|
|
bitfld.long 0x00 7. "ENINT11,ENINT11" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS11,TRGS11" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST11,AINST11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TSET12,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 7. "ENINT12,ENINT12" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS12,TRGS12" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST12,AINST12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TSET13,AD General purpose Trigger Program Register 13"
|
|
bitfld.long 0x00 7. "ENINT13,ENINT13" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS13,TRGS13" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST13,AINST13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TSET14,AD General purpose Trigger Program Register 14"
|
|
bitfld.long 0x00 7. "ENINT14,ENINT14" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS14,TRGS14" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST14,AINST14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TSET15,AD General purpose Trigger Program Register 15"
|
|
bitfld.long 0x00 7. "ENINT15,ENINT15" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS15,TRGS15" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST15,AINST15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TSET16,AD General purpose Trigger Program Register 16"
|
|
bitfld.long 0x00 7. "ENINT16,ENINT16" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS16,TRGS16" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST16,AINST16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TSET17,AD General purpose Trigger Program Register 17"
|
|
bitfld.long 0x00 7. "ENINT17,ENINT17" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS17,TRGS17" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST17,AINST17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TSET18,AD General purpose Trigger Program Register 18"
|
|
bitfld.long 0x00 7. "ENINT18,ENINT18" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS18,TRGS18" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST18,AINST18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TSET19,AD General purpose Trigger Program Register 19"
|
|
bitfld.long 0x00 7. "ENINT19,ENINT19" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS19,TRGS19" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST19,AINST19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TSET20,AD General purpose Trigger Program Register 20"
|
|
bitfld.long 0x00 7. "ENINT20,ENINT20" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS20,TRGS20" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST20,AINST20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TSET21,AD General purpose Trigger Program Register 21"
|
|
bitfld.long 0x00 7. "ENINT21,ENINT21" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS21,TRGS21" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST21,AINST21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TSET22,AD General purpose Trigger Program Register 22"
|
|
bitfld.long 0x00 7. "ENINT22,ENINT22" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS22,TRGS22" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST22,AINST22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TSET23,AD General purpose Trigger Program Register 23"
|
|
bitfld.long 0x00 7. "ENINT23,ENINT23" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS23,TRGS23" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST23,AINST23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "REG0,AD Conversion Result Register 0"
|
|
bitfld.long 0x00 29. "ADOVRF_M0,ADOVRF_M0" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M0,ADRF_M0" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M0,ADR_M0"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR0,ADR0"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF0,ADOVRF0" "0,1"
|
|
bitfld.long 0x00 0. "ADRF0,ADRF0" "0,1"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "REG1,AD Conversion Result Register 1"
|
|
bitfld.long 0x00 29. "ADOVRF_M1,ADOVRF_M1" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M1,ADRF_M1" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M1,ADR_M1"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR1,ADR1"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF1,ADOVRF1" "0,1"
|
|
bitfld.long 0x00 0. "ADRF1,ADRF1" "0,1"
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "REG2,AD Conversion Result Register 2"
|
|
bitfld.long 0x00 29. "ADOVRF_M2,ADOVRF_M2" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M2,ADRF_M2" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M2,ADR_M2"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR2,ADR2"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF2,ADOVRF2" "0,1"
|
|
bitfld.long 0x00 0. "ADRF2,ADRF2" "0,1"
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "REG3,AD Conversion Result Register 3"
|
|
bitfld.long 0x00 29. "ADOVRF_M3,ADOVRF_M3" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M3,ADRF_M3" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M3,ADR_M3"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR3,ADR3"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF3,ADOVRF3" "0,1"
|
|
bitfld.long 0x00 0. "ADRF3,ADRF3" "0,1"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "REG4,AD Conversion Result Register 4"
|
|
bitfld.long 0x00 29. "ADOVRF_M4,ADOVRF_M4" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M4,ADRF_M4" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M4,ADR_M4"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR4,ADR4"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF4,ADOVRF4" "0,1"
|
|
bitfld.long 0x00 0. "ADRF4,ADRF4" "0,1"
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "REG5,AD Conversion Result Register 5"
|
|
bitfld.long 0x00 29. "ADOVRF_M5,ADOVRF_M5" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M5,ADRF_M5" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M5,ADR_M5"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR5,ADR5"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF5,ADOVRF5" "0,1"
|
|
bitfld.long 0x00 0. "ADRF5,ADRF5" "0,1"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "REG6,AD Conversion Result Register 6"
|
|
bitfld.long 0x00 29. "ADOVRF_M6,ADOVRF_M6" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M6,ADRF_M6" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M6,ADR_M6"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR6,ADR6"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF6,ADOVRF6" "0,1"
|
|
bitfld.long 0x00 0. "ADRF6,ADRF6" "0,1"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "REG7,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVRF_M7,ADOVRF_M7" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M7,ADRF_M7" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M7,ADR_M7"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR7,ADR7"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF7,ADOVRF7" "0,1"
|
|
bitfld.long 0x00 0. "ADRF7,ADRF7" "0,1"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "REG8,AD Conversion Result Register 8"
|
|
bitfld.long 0x00 29. "ADOVRF_M8,ADOVRF_M8" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M8,ADRF_M8" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M8,ADR_M8"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR8,ADR8"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF8,ADOVRF8" "0,1"
|
|
bitfld.long 0x00 0. "ADRF8,ADRF8" "0,1"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "REG9,AD Conversion Result Register 9"
|
|
bitfld.long 0x00 29. "ADOVRF_M9,ADOVRF_M9" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M9,ADRF_M9" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M9,ADR_M9"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR9,ADR9"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF9,ADOVRF9" "0,1"
|
|
bitfld.long 0x00 0. "ADRF9,ADRF9" "0,1"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "REG10,AD Conversion Result Register 10"
|
|
bitfld.long 0x00 29. "ADOVRF_M10,ADOVRF_M10" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M10,ADRF_M10" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M10,ADR_M10"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR10,ADR10"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF10,ADOVRF10" "0,1"
|
|
bitfld.long 0x00 0. "ADRF10,ADRF10" "0,1"
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "REG11,AD Conversion Result Register 11"
|
|
bitfld.long 0x00 29. "ADOVRF_M11,ADOVRF_M11" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M11,ADRF_M11" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M11,ADR_M11"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR11,ADR11"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF11,ADOVRF11" "0,1"
|
|
bitfld.long 0x00 0. "ADRF11,ADRF11" "0,1"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "REG12,AD Conversion Result Register 12"
|
|
bitfld.long 0x00 29. "ADOVRF_M12,ADOVRF_M12" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M12,ADRF_M12" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M12,ADR_M12"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR12,ADR12"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF12,ADOVRF12" "0,1"
|
|
bitfld.long 0x00 0. "ADRF12,ADRF12" "0,1"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "REG13,AD Conversion Result Register 13"
|
|
bitfld.long 0x00 29. "ADOVRF_M13,ADOVRF_M13" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M13,ADRF_M13" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M13,ADR_M13"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR13,ADR13"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF13,ADOVRF13" "0,1"
|
|
bitfld.long 0x00 0. "ADRF13,ADRF13" "0,1"
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "REG14,AD Conversion Result Register 14"
|
|
bitfld.long 0x00 29. "ADOVRF_M14,ADOVRF_M14" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M14,ADRF_M14" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M14,ADR_M14"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR14,ADR14"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF14,ADOVRF14" "0,1"
|
|
bitfld.long 0x00 0. "ADRF14,ADRF14" "0,1"
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "REG15,AD Conversion Result Register 15"
|
|
bitfld.long 0x00 29. "ADOVRF_M15,ADOVRF_M15" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M15,ADRF_M15" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M15,ADR_M15"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR15,ADR15"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF15,ADOVRF15" "0,1"
|
|
bitfld.long 0x00 0. "ADRF15,ADRF15" "0,1"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "REG16,AD Conversion Result Register 16"
|
|
bitfld.long 0x00 29. "ADOVRF_M16,ADOVRF_M16" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M16,ADRF_M16" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M16,ADR_M16"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR16,ADR16"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF16,ADOVRF16" "0,1"
|
|
bitfld.long 0x00 0. "ADRF16,ADRF16" "0,1"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "REG17,AD Conversion Result Register 17"
|
|
bitfld.long 0x00 29. "ADOVRF_M17,ADOVRF_M17" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M17,ADRF_M17" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M17,ADR_M17"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR17,ADR17"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF17,ADOVRF17" "0,1"
|
|
bitfld.long 0x00 0. "ADRF17,ADRF17" "0,1"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "REG18,AD Conversion Result Register 18"
|
|
bitfld.long 0x00 29. "ADOVRF_M18,ADOVRF_M18" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M18,ADRF_M18" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M18,ADR_M18"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR18,ADR18"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF18,ADOVRF18" "0,1"
|
|
bitfld.long 0x00 0. "ADRF18,ADRF18" "0,1"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "REG19,AD Conversion Result Register 19"
|
|
bitfld.long 0x00 29. "ADOVRF_M19,ADOVRF_M19" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M19,ADRF_M19" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M19,ADR_M19"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR19,ADR19"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF19,ADOVRF19" "0,1"
|
|
bitfld.long 0x00 0. "ADRF19,ADRF19" "0,1"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "REG20,AD Conversion Result Register 20"
|
|
bitfld.long 0x00 29. "ADOVRF_M20,ADOVRF_M20" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M20,ADRF_M20" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M20,ADR_M20"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR20,ADR20"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF20,ADOVRF20" "0,1"
|
|
bitfld.long 0x00 0. "ADRF20,ADRF20" "0,1"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "REG21,AD Conversion Result Register 21"
|
|
bitfld.long 0x00 29. "ADOVRF_M21,ADOVRF_M21" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M21,ADRF_M21" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M21,ADR_M21"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR21,ADR21"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF21,ADOVRF21" "0,1"
|
|
bitfld.long 0x00 0. "ADRF21,ADRF21" "0,1"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "REG22,AD Conversion Result Register 22"
|
|
bitfld.long 0x00 29. "ADOVRF_M22,ADOVRF_M22" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M22,ADRF_M22" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M22,ADR_M22"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR22,ADR22"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF22,ADOVRF22" "0,1"
|
|
bitfld.long 0x00 0. "ADRF22,ADRF22" "0,1"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "REG23,AD Conversion Result Register 23"
|
|
bitfld.long 0x00 29. "ADOVRF_M23,ADOVRF_M23" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M23,ADRF_M23" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M23,ADR_M23"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR23,ADR23"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF23,ADOVRF23" "0,1"
|
|
bitfld.long 0x00 0. "ADRF23,ADRF23" "0,1"
|
|
tree.end
|
|
tree "ADC (12-bit Analog to Digital Converter(ADC))"
|
|
base ad:0x400BA800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,AD Control Register 0"
|
|
bitfld.long 0x00 7. "ADEN,ADEN" "0,1"
|
|
bitfld.long 0x00 1. "SGL,SGL" "0,1"
|
|
bitfld.long 0x00 0. "CNT,CNT" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1,AD Control Register 1"
|
|
bitfld.long 0x00 6. "CNTDMEN,CNTDMEN" "0,1"
|
|
bitfld.long 0x00 5. "SGLDMEN,SGLDMEN" "0,1"
|
|
bitfld.long 0x00 4. "TRGDMEN,TRGDMEN" "0,1"
|
|
bitfld.long 0x00 0. "TRGEN,TRGEN" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ST,AD Status Register"
|
|
bitfld.long 0x00 7. "ADBF,ADBF" "0,1"
|
|
bitfld.long 0x00 3. "CNTF,CNTF" "0,1"
|
|
bitfld.long 0x00 2. "SNGF,SNGF" "0,1"
|
|
bitfld.long 0x00 1. "TRGF,TRGF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PMDF,PMDF" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK,AD Conversion Clock Setting Register"
|
|
bitfld.long 0x00 3.--6. "EXAZ,EXAZ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. "VADCLK,VADCLK" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MOD0,AD Mode Control Register 0"
|
|
bitfld.long 0x00 1. "RCUT,RCUT" "0,1"
|
|
bitfld.long 0x00 0. "DACON,DACON" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MOD1,AD Mode Control Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MOD1,MOD1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MOD2,AD Mode Control Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "MOD2,MOD2"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPEN,AD Monitor function interrupt permission register"
|
|
bitfld.long 0x00 1. "CMP1EN,CMP1EN" "0,1"
|
|
bitfld.long 0x00 0. "CMP0EN,CMP0EN" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CMPCR0,AD Monitor function Setting Register 0"
|
|
bitfld.long 0x00 8.--11. "CMPCNT0,CMPCNT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "CMPCND0,CMPCND0" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG0,ADBIG0" "0,1"
|
|
bitfld.long 0x00 0.--4. "REGS0,REGS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CMPCR1,AD Monitor function Setting Register 1"
|
|
bitfld.long 0x00 8.--11. "CMPCNT1,CMPCNT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "CMPCND1,CMPCND1" "0,1"
|
|
bitfld.long 0x00 5. "ADBIG1,ADBIG1" "0,1"
|
|
bitfld.long 0x00 0.--4. "REGS1,REGS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CMP0,AD Conversion Result Comparison Register 0"
|
|
hexmask.long.word 0x00 4.--15. 1. "AD0CMP0,AD0CMP0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CMP1,AD Conversion Result Comparison Register 1"
|
|
hexmask.long.word 0x00 4.--15. 1. "AD0CMP1,AD0CMP1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PSEL0,AD PMD Trigger Program Number Select Register 0"
|
|
bitfld.long 0x00 7. "PENS0,PENS0" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS0,PMDS0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PSEL1,AD PMD Trigger Program Number Select Register 1"
|
|
bitfld.long 0x00 7. "PENS1,PENS1" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS1,PMDS1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PSEL2,AD PMD Trigger Program Number Select Register 2"
|
|
bitfld.long 0x00 7. "PENS2,PENS2" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS2,PMDS2" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PSEL3,AD PMD Trigger Program Number Select Register 3"
|
|
bitfld.long 0x00 7. "PENS3,PENS3" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS3,PMDS3" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PSEL4,AD PMD Trigger Program Number Select Register 4"
|
|
bitfld.long 0x00 7. "PENS4,PENS4" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS4,PMDS4" "0,1,2,3,4,5,6,7"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PSEL5,AD PMD Trigger Program Number Select Register 5"
|
|
bitfld.long 0x00 7. "PENS5,PENS5" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS5,PMDS5" "0,1,2,3,4,5,6,7"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PSEL6,AD PMD Trigger Program Number Select Register 6"
|
|
bitfld.long 0x00 7. "PENS6,PENS6" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS6,PMDS6" "0,1,2,3,4,5,6,7"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PSEL7,AD PMD Trigger Program Number Select Register 7"
|
|
bitfld.long 0x00 7. "PENS7,PENS7" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS7,PMDS7" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PSEL8,AD PMD Trigger Program Number Select Register 8"
|
|
bitfld.long 0x00 7. "PENS8,PENS8" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS8,PMDS8" "0,1,2,3,4,5,6,7"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PSEL9,AD PMD Trigger Program Number Select Register 9"
|
|
bitfld.long 0x00 7. "PENS9,PENS9" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS9,PMDS9" "0,1,2,3,4,5,6,7"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PSEL10,AD PMD Trigger Program Number Select Register 10"
|
|
bitfld.long 0x00 7. "PENS10,PENS10" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS10,PMDS10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PSEL11,AD PMD Trigger Program Number Select Register 11"
|
|
bitfld.long 0x00 7. "PENS11,PENS11" "0,1"
|
|
bitfld.long 0x00 0.--2. "PMDS11,PMDS11" "0,1,2,3,4,5,6,7"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PINTS0,AD PMD Trigger Interrupt Select Register 0"
|
|
bitfld.long 0x00 0.--1. "INTSEL0,INTSEL0" "0,1,2,3"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PINTS1,AD PMD Trigger Interrupt Select Register 1"
|
|
bitfld.long 0x00 0.--1. "INTSEL1,INTSEL1" "0,1,2,3"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PINTS2,AD PMD Trigger Interrupt Select Register 2"
|
|
bitfld.long 0x00 0.--1. "INTSEL2,INTSEL2" "0,1,2,3"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PINTS3,AD PMD Trigger Interrupt Select Register 3"
|
|
bitfld.long 0x00 0.--1. "INTSEL3,INTSEL3" "0,1,2,3"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PINTS4,AD PMD Trigger Interrupt Select Register 4"
|
|
bitfld.long 0x00 0.--1. "INTSEL4,INTSEL4" "0,1,2,3"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PINTS5,AD PMD Trigger Interrupt Select Register 5"
|
|
bitfld.long 0x00 0.--1. "INTSEL5,INTSEL5" "0,1,2,3"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PINTS6,AD PMD Trigger Interrupt Select Register 6"
|
|
bitfld.long 0x00 0.--1. "INTSEL6,INTSEL6" "0,1,2,3"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PINTS7,AD PMD Trigger Interrupt Select Register 7"
|
|
bitfld.long 0x00 0.--1. "INTSEL7,INTSEL7" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PREGS,AD PMD Trigger Conversion Result Storage Select Register 1"
|
|
bitfld.long 0x00 28.--30. "REGSEL7,REGSEL7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "REGSEL6,REGSEL6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. "REGSEL5,REGSEL5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "REGSEL4,REGSEL4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "REGSEL3,REGSEL3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "REGSEL2,REGSEL2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "REGSEL1,REGSEL1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "REGSEL0,REGSEL0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PSET0,AD PMD Trigger Program Register 0"
|
|
bitfld.long 0x00 31. "ENSP03,ENSP03" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS03,UVWIS03" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP03,AINSP03" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "ENSP02,ENSP02" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS02,UVWIS02" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP02,AINSP02" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "ENSP01,ENSP01" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS01,UVWIS01" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP01,AINSP01" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. "ENSP00,ENSP00" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS00,UVWIS00" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP00,AINSP00" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "PSET1,AD PMD Trigger Program Register 1"
|
|
bitfld.long 0x00 31. "ENSP13,ENSP13" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS13,UVWIS13" "0,1,2,3"
|
|
bitfld.long 0x00 24.--28. "AINSP13,AINSP13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 23. "ENSP12,ENSP12" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS12,UVWIS12" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AINSP12,AINSP12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 15. "ENSP11,ENSP11" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS11,UVWIS11" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP11,AINSP11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 7. "ENSP10,ENSP10" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS10,UVWIS10" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINSP10,AINSP10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xA8++0x03
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|
line.long 0x00 "PSET2,AD PMD Trigger Program Register 2"
|
|
bitfld.long 0x00 31. "ENSP23,ENSP23" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS23,UVWIS23" "0,1,2,3"
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|
bitfld.long 0x00 24.--28. "AINSP23,AINSP23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 23. "ENSP22,ENSP22" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS22,UVWIS22" "0,1,2,3"
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|
bitfld.long 0x00 16.--20. "AINSP22,AINSP22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 15. "ENSP21,ENSP21" "0,1"
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|
bitfld.long 0x00 13.--14. "UVWIS21,UVWIS21" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP21,AINSP21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 7. "ENSP20,ENSP20" "0,1"
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|
bitfld.long 0x00 5.--6. "UVWIS20,UVWIS20" "0,1,2,3"
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|
bitfld.long 0x00 0.--4. "AINSP20,AINSP20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xAC++0x03
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|
line.long 0x00 "PSET3,AD PMD Trigger Program Register 3"
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|
bitfld.long 0x00 31. "ENSP33,ENSP33" "0,1"
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|
bitfld.long 0x00 29.--30. "UVWIS33,UVWIS33" "0,1,2,3"
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|
bitfld.long 0x00 24.--28. "AINSP33,AINSP33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 23. "ENSP32,ENSP32" "0,1"
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|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS32,UVWIS32" "0,1,2,3"
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|
bitfld.long 0x00 16.--20. "AINSP32,AINSP32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 15. "ENSP31,ENSP31" "0,1"
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|
bitfld.long 0x00 13.--14. "UVWIS31,UVWIS31" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP31,AINSP31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 7. "ENSP30,ENSP30" "0,1"
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|
bitfld.long 0x00 5.--6. "UVWIS30,UVWIS30" "0,1,2,3"
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|
bitfld.long 0x00 0.--4. "AINSP30,AINSP30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xB0++0x03
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line.long 0x00 "PSET4,AD PMD Trigger Program Register 4"
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bitfld.long 0x00 31. "ENSP43,ENSP43" "0,1"
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|
bitfld.long 0x00 29.--30. "UVWIS43,UVWIS43" "0,1,2,3"
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|
bitfld.long 0x00 24.--28. "AINSP43,AINSP43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 23. "ENSP42,ENSP42" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS42,UVWIS42" "0,1,2,3"
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|
bitfld.long 0x00 16.--20. "AINSP42,AINSP42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 15. "ENSP41,ENSP41" "0,1"
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|
bitfld.long 0x00 13.--14. "UVWIS41,UVWIS41" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP41,AINSP41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 7. "ENSP40,ENSP40" "0,1"
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|
bitfld.long 0x00 5.--6. "UVWIS40,UVWIS40" "0,1,2,3"
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|
bitfld.long 0x00 0.--4. "AINSP40,AINSP40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xB4++0x03
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line.long 0x00 "PSET5,AD PMD Trigger Program Register 5"
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bitfld.long 0x00 31. "ENSP53,ENSP53" "0,1"
|
|
bitfld.long 0x00 29.--30. "UVWIS53,UVWIS53" "0,1,2,3"
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|
bitfld.long 0x00 24.--28. "AINSP53,AINSP53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 23. "ENSP52,ENSP52" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS52,UVWIS52" "0,1,2,3"
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|
bitfld.long 0x00 16.--20. "AINSP52,AINSP52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 15. "ENSP51,ENSP51" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS51,UVWIS51" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP51,AINSP51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 7. "ENSP50,ENSP50" "0,1"
|
|
bitfld.long 0x00 5.--6. "UVWIS50,UVWIS50" "0,1,2,3"
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|
bitfld.long 0x00 0.--4. "AINSP50,AINSP50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xB8++0x03
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line.long 0x00 "PSET6,AD PMD Trigger Program Register 6"
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bitfld.long 0x00 31. "ENSP63,ENSP63" "0,1"
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|
bitfld.long 0x00 29.--30. "UVWIS63,UVWIS63" "0,1,2,3"
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|
bitfld.long 0x00 24.--28. "AINSP63,AINSP63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 23. "ENSP62,ENSP62" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS62,UVWIS62" "0,1,2,3"
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|
bitfld.long 0x00 16.--20. "AINSP62,AINSP62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 15. "ENSP61,ENSP61" "0,1"
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|
bitfld.long 0x00 13.--14. "UVWIS61,UVWIS61" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP61,AINSP61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "ENSP60,ENSP60" "0,1"
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|
bitfld.long 0x00 5.--6. "UVWIS60,UVWIS60" "0,1,2,3"
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|
bitfld.long 0x00 0.--4. "AINSP60,AINSP60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xBC++0x03
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line.long 0x00 "PSET7,AD PMD Trigger Program Register 7"
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|
bitfld.long 0x00 31. "ENSP73,ENSP73" "0,1"
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|
bitfld.long 0x00 29.--30. "UVWIS73,UVWIS73" "0,1,2,3"
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|
bitfld.long 0x00 24.--28. "AINSP73,AINSP73" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 23. "ENSP72,ENSP72" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "UVWIS72,UVWIS72" "0,1,2,3"
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|
bitfld.long 0x00 16.--20. "AINSP72,AINSP72" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 15. "ENSP71,ENSP71" "0,1"
|
|
bitfld.long 0x00 13.--14. "UVWIS71,UVWIS71" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AINSP71,AINSP71" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "ENSP70,ENSP70" "0,1"
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|
bitfld.long 0x00 5.--6. "UVWIS70,UVWIS70" "0,1,2,3"
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|
bitfld.long 0x00 0.--4. "AINSP70,AINSP70" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xC0++0x03
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line.long 0x00 "TSET0,AD General purpose Trigger Program Register 0"
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bitfld.long 0x00 7. "ENINT0,ENINT0" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS0,TRGS0" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST0,AINST0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xC4++0x03
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line.long 0x00 "TSET1,AD General purpose Trigger Program Register 1"
|
|
bitfld.long 0x00 7. "ENINT1,ENINT1" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS1,TRGS1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST1,AINST1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0xC8++0x03
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|
line.long 0x00 "TSET2,AD General purpose Trigger Program Register 2"
|
|
bitfld.long 0x00 7. "ENINT2,ENINT2" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS2,TRGS2" "0,1,2,3"
|
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bitfld.long 0x00 0.--4. "AINST2,AINST2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xCC++0x03
|
|
line.long 0x00 "TSET3,AD General purpose Trigger Program Register 3"
|
|
bitfld.long 0x00 7. "ENINT3,ENINT3" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS3,TRGS3" "0,1,2,3"
|
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bitfld.long 0x00 0.--4. "AINST3,AINST3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xD0++0x03
|
|
line.long 0x00 "TSET4,AD General purpose Trigger Program Register 4"
|
|
bitfld.long 0x00 7. "ENINT4,ENINT4" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS4,TRGS4" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST4,AINST4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xD4++0x03
|
|
line.long 0x00 "TSET5,AD General purpose Trigger Program Register 5"
|
|
bitfld.long 0x00 7. "ENINT5,ENINT5" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS5,TRGS5" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST5,AINST5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0xD8++0x03
|
|
line.long 0x00 "TSET6,AD General purpose Trigger Program Register 6"
|
|
bitfld.long 0x00 7. "ENINT6,ENINT6" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS6,TRGS6" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST6,AINST6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TSET7,AD General purpose Trigger Program Register 7"
|
|
bitfld.long 0x00 7. "ENINT7,ENINT7" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS7,TRGS7" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST7,AINST7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TSET8,AD General purpose Trigger Program Register 8"
|
|
bitfld.long 0x00 7. "ENINT8,ENINT8" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS8,TRGS8" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST8,AINST8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TSET9,AD General purpose Trigger Program Register 9"
|
|
bitfld.long 0x00 7. "ENINT9,ENINT9" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS9,TRGS9" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST9,AINST9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TSET10,AD General purpose Trigger Program Register 10"
|
|
bitfld.long 0x00 7. "ENINT10,ENINT10" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS10,TRGS10" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST10,AINST10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TSET11,AD General purpose Trigger Program Register 11"
|
|
bitfld.long 0x00 7. "ENINT11,ENINT11" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS11,TRGS11" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST11,AINST11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TSET12,AD General purpose Trigger Program Register 12"
|
|
bitfld.long 0x00 7. "ENINT12,ENINT12" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS12,TRGS12" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST12,AINST12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TSET13,AD General purpose Trigger Program Register 13"
|
|
bitfld.long 0x00 7. "ENINT13,ENINT13" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS13,TRGS13" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST13,AINST13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TSET14,AD General purpose Trigger Program Register 14"
|
|
bitfld.long 0x00 7. "ENINT14,ENINT14" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS14,TRGS14" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST14,AINST14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TSET15,AD General purpose Trigger Program Register 15"
|
|
bitfld.long 0x00 7. "ENINT15,ENINT15" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS15,TRGS15" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST15,AINST15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TSET16,AD General purpose Trigger Program Register 16"
|
|
bitfld.long 0x00 7. "ENINT16,ENINT16" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS16,TRGS16" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST16,AINST16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TSET17,AD General purpose Trigger Program Register 17"
|
|
bitfld.long 0x00 7. "ENINT17,ENINT17" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS17,TRGS17" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST17,AINST17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TSET18,AD General purpose Trigger Program Register 18"
|
|
bitfld.long 0x00 7. "ENINT18,ENINT18" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS18,TRGS18" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST18,AINST18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TSET19,AD General purpose Trigger Program Register 19"
|
|
bitfld.long 0x00 7. "ENINT19,ENINT19" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS19,TRGS19" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST19,AINST19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TSET20,AD General purpose Trigger Program Register 20"
|
|
bitfld.long 0x00 7. "ENINT20,ENINT20" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS20,TRGS20" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST20,AINST20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TSET21,AD General purpose Trigger Program Register 21"
|
|
bitfld.long 0x00 7. "ENINT21,ENINT21" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS21,TRGS21" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST21,AINST21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TSET22,AD General purpose Trigger Program Register 22"
|
|
bitfld.long 0x00 7. "ENINT22,ENINT22" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS22,TRGS22" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST22,AINST22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TSET23,AD General purpose Trigger Program Register 23"
|
|
bitfld.long 0x00 7. "ENINT23,ENINT23" "0,1"
|
|
bitfld.long 0x00 5.--6. "TRGS23,TRGS23" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "AINST23,AINST23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "REG0,AD Conversion Result Register 0"
|
|
bitfld.long 0x00 29. "ADOVRF_M0,ADOVRF_M0" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M0,ADRF_M0" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M0,ADR_M0"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR0,ADR0"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF0,ADOVRF0" "0,1"
|
|
bitfld.long 0x00 0. "ADRF0,ADRF0" "0,1"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "REG1,AD Conversion Result Register 1"
|
|
bitfld.long 0x00 29. "ADOVRF_M1,ADOVRF_M1" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M1,ADRF_M1" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M1,ADR_M1"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR1,ADR1"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF1,ADOVRF1" "0,1"
|
|
bitfld.long 0x00 0. "ADRF1,ADRF1" "0,1"
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "REG2,AD Conversion Result Register 2"
|
|
bitfld.long 0x00 29. "ADOVRF_M2,ADOVRF_M2" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M2,ADRF_M2" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M2,ADR_M2"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR2,ADR2"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF2,ADOVRF2" "0,1"
|
|
bitfld.long 0x00 0. "ADRF2,ADRF2" "0,1"
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "REG3,AD Conversion Result Register 3"
|
|
bitfld.long 0x00 29. "ADOVRF_M3,ADOVRF_M3" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M3,ADRF_M3" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M3,ADR_M3"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR3,ADR3"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF3,ADOVRF3" "0,1"
|
|
bitfld.long 0x00 0. "ADRF3,ADRF3" "0,1"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "REG4,AD Conversion Result Register 4"
|
|
bitfld.long 0x00 29. "ADOVRF_M4,ADOVRF_M4" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M4,ADRF_M4" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M4,ADR_M4"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR4,ADR4"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF4,ADOVRF4" "0,1"
|
|
bitfld.long 0x00 0. "ADRF4,ADRF4" "0,1"
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "REG5,AD Conversion Result Register 5"
|
|
bitfld.long 0x00 29. "ADOVRF_M5,ADOVRF_M5" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M5,ADRF_M5" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M5,ADR_M5"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR5,ADR5"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF5,ADOVRF5" "0,1"
|
|
bitfld.long 0x00 0. "ADRF5,ADRF5" "0,1"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "REG6,AD Conversion Result Register 6"
|
|
bitfld.long 0x00 29. "ADOVRF_M6,ADOVRF_M6" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M6,ADRF_M6" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M6,ADR_M6"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR6,ADR6"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF6,ADOVRF6" "0,1"
|
|
bitfld.long 0x00 0. "ADRF6,ADRF6" "0,1"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "REG7,AD Conversion Result Register 7"
|
|
bitfld.long 0x00 29. "ADOVRF_M7,ADOVRF_M7" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M7,ADRF_M7" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M7,ADR_M7"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR7,ADR7"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF7,ADOVRF7" "0,1"
|
|
bitfld.long 0x00 0. "ADRF7,ADRF7" "0,1"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "REG8,AD Conversion Result Register 8"
|
|
bitfld.long 0x00 29. "ADOVRF_M8,ADOVRF_M8" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M8,ADRF_M8" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M8,ADR_M8"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR8,ADR8"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF8,ADOVRF8" "0,1"
|
|
bitfld.long 0x00 0. "ADRF8,ADRF8" "0,1"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "REG9,AD Conversion Result Register 9"
|
|
bitfld.long 0x00 29. "ADOVRF_M9,ADOVRF_M9" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M9,ADRF_M9" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M9,ADR_M9"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR9,ADR9"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF9,ADOVRF9" "0,1"
|
|
bitfld.long 0x00 0. "ADRF9,ADRF9" "0,1"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "REG10,AD Conversion Result Register 10"
|
|
bitfld.long 0x00 29. "ADOVRF_M10,ADOVRF_M10" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M10,ADRF_M10" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M10,ADR_M10"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR10,ADR10"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF10,ADOVRF10" "0,1"
|
|
bitfld.long 0x00 0. "ADRF10,ADRF10" "0,1"
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "REG11,AD Conversion Result Register 11"
|
|
bitfld.long 0x00 29. "ADOVRF_M11,ADOVRF_M11" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M11,ADRF_M11" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M11,ADR_M11"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR11,ADR11"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF11,ADOVRF11" "0,1"
|
|
bitfld.long 0x00 0. "ADRF11,ADRF11" "0,1"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "REG12,AD Conversion Result Register 12"
|
|
bitfld.long 0x00 29. "ADOVRF_M12,ADOVRF_M12" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M12,ADRF_M12" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M12,ADR_M12"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR12,ADR12"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF12,ADOVRF12" "0,1"
|
|
bitfld.long 0x00 0. "ADRF12,ADRF12" "0,1"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "REG13,AD Conversion Result Register 13"
|
|
bitfld.long 0x00 29. "ADOVRF_M13,ADOVRF_M13" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M13,ADRF_M13" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M13,ADR_M13"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR13,ADR13"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF13,ADOVRF13" "0,1"
|
|
bitfld.long 0x00 0. "ADRF13,ADRF13" "0,1"
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "REG14,AD Conversion Result Register 14"
|
|
bitfld.long 0x00 29. "ADOVRF_M14,ADOVRF_M14" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M14,ADRF_M14" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M14,ADR_M14"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR14,ADR14"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF14,ADOVRF14" "0,1"
|
|
bitfld.long 0x00 0. "ADRF14,ADRF14" "0,1"
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "REG15,AD Conversion Result Register 15"
|
|
bitfld.long 0x00 29. "ADOVRF_M15,ADOVRF_M15" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M15,ADRF_M15" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M15,ADR_M15"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR15,ADR15"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF15,ADOVRF15" "0,1"
|
|
bitfld.long 0x00 0. "ADRF15,ADRF15" "0,1"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "REG16,AD Conversion Result Register 16"
|
|
bitfld.long 0x00 29. "ADOVRF_M16,ADOVRF_M16" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M16,ADRF_M16" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M16,ADR_M16"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR16,ADR16"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF16,ADOVRF16" "0,1"
|
|
bitfld.long 0x00 0. "ADRF16,ADRF16" "0,1"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "REG17,AD Conversion Result Register 17"
|
|
bitfld.long 0x00 29. "ADOVRF_M17,ADOVRF_M17" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M17,ADRF_M17" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M17,ADR_M17"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR17,ADR17"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF17,ADOVRF17" "0,1"
|
|
bitfld.long 0x00 0. "ADRF17,ADRF17" "0,1"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "REG18,AD Conversion Result Register 18"
|
|
bitfld.long 0x00 29. "ADOVRF_M18,ADOVRF_M18" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M18,ADRF_M18" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M18,ADR_M18"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR18,ADR18"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF18,ADOVRF18" "0,1"
|
|
bitfld.long 0x00 0. "ADRF18,ADRF18" "0,1"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "REG19,AD Conversion Result Register 19"
|
|
bitfld.long 0x00 29. "ADOVRF_M19,ADOVRF_M19" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M19,ADRF_M19" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M19,ADR_M19"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR19,ADR19"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF19,ADOVRF19" "0,1"
|
|
bitfld.long 0x00 0. "ADRF19,ADRF19" "0,1"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "REG20,AD Conversion Result Register 20"
|
|
bitfld.long 0x00 29. "ADOVRF_M20,ADOVRF_M20" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M20,ADRF_M20" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M20,ADR_M20"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR20,ADR20"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF20,ADOVRF20" "0,1"
|
|
bitfld.long 0x00 0. "ADRF20,ADRF20" "0,1"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "REG21,AD Conversion Result Register 21"
|
|
bitfld.long 0x00 29. "ADOVRF_M21,ADOVRF_M21" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M21,ADRF_M21" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M21,ADR_M21"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR21,ADR21"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF21,ADOVRF21" "0,1"
|
|
bitfld.long 0x00 0. "ADRF21,ADRF21" "0,1"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "REG22,AD Conversion Result Register 22"
|
|
bitfld.long 0x00 29. "ADOVRF_M22,ADOVRF_M22" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M22,ADRF_M22" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M22,ADR_M22"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR22,ADR22"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF22,ADOVRF22" "0,1"
|
|
bitfld.long 0x00 0. "ADRF22,ADRF22" "0,1"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "REG23,AD Conversion Result Register 23"
|
|
bitfld.long 0x00 29. "ADOVRF_M23,ADOVRF_M23" "0,1"
|
|
bitfld.long 0x00 28. "ADRF_M23,ADRF_M23" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "ADR_M23,ADR_M23"
|
|
hexmask.long.word 0x00 4.--15. 1. "ADR23,ADR23"
|
|
newline
|
|
bitfld.long 0x00 1. "ADOVRF23,ADOVRF23" "0,1"
|
|
bitfld.long 0x00 0. "ADRF23,ADRF23" "0,1"
|
|
tree.end
|
|
tree "PMD2 (Advanced Progammable Motor Control Circuit (A-PMD))"
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base ad:0x400E9800
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group.long 0x00++0x03
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line.long 0x00 "MDEN,PMD Enable Register"
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bitfld.long 0x00 0. "PWMEN,PWMEN" "0,1"
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group.long 0x04++0x03
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line.long 0x00 "PORTMD,PMD Port Output Mode Register"
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bitfld.long 0x00 0.--1. "PORTMD,PORTMD" "0,1,2,3"
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sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
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group.long 0x08++0x03
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line.long 0x00 "MDCR,PMD Control Register"
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bitfld.long 0x00 14.--15. "WPWMES,WPWMES" "0,1,2,3"
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bitfld.long 0x00 12.--13. "VPWMES,VPWMES" "0,1,2,3"
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bitfld.long 0x00 10.--11. "UPWMES,UPWMES" "0,1,2,3"
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bitfld.long 0x00 8.--9. "DSYNCS,DSYNCS" "0,1,2,3"
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newline
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bitfld.long 0x00 7. "DTCREN,DTCREN" "0,1"
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bitfld.long 0x00 6. "PWMCK,PWMCK" "0,1"
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bitfld.long 0x00 5. "SYNTMD,SYNTMD" "0,1"
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bitfld.long 0x00 4. "DTYMD,DTYMD" "0,1"
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newline
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bitfld.long 0x00 3. "PINT,PINT" "0,1"
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bitfld.long 0x00 1.--2. "INTPRD,INTPRD" "0,1,2,3"
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bitfld.long 0x00 0. "PWMMD,PWMMD" "0,1"
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endif
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sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
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group.long 0x08++0x03
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line.long 0x00 "MDCR,PMD Control Register"
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bitfld.long 0x00 14.--15. "WPWMMD,WPWMMD" "0,1,2,3"
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bitfld.long 0x00 12.--13. "VPWMMD,VPWMMD" "0,1,2,3"
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bitfld.long 0x00 10.--11. "UPWMMD,UPWMMD" "0,1,2,3"
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bitfld.long 0x00 8.--9. "DSYNCS,DSYNCS" "0,1,2,3"
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newline
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bitfld.long 0x00 7. "DTCREN,DTCREN" "0,1"
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bitfld.long 0x00 6. "DCMEN,DCMEN" "0,1"
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bitfld.long 0x00 5. "SYNTMD,SYNTMD" "0,1"
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bitfld.long 0x00 4. "DTYMD,DTYMD" "0,1"
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newline
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bitfld.long 0x00 3. "PINT,PINT" "0,1"
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bitfld.long 0x00 1.--2. "INTPRD,INTPRD" "0,1,2,3"
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endif
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sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
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rgroup.long 0x0C++0x03
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line.long 0x00 "CNTSTA,PMD PWM Counter Status Register"
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bitfld.long 0x00 0. "UPDWN,UPDWN" "0,1"
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endif
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sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
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rgroup.long 0x0C++0x03
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line.long 0x00 "CARSTA,PWM Carrier Status Register"
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bitfld.long 0x00 2. "PWMWST,PWMWST" "0,1"
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bitfld.long 0x00 1. "PWMVST,PWMVST" "0,1"
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bitfld.long 0x00 0. "PWMUST,PWMUST" "0,1"
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endif
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sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
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rgroup.long 0x10++0x03
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line.long 0x00 "MDCNT,PMD PWM Counter Register"
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hexmask.long.word 0x00 0.--15. 1. "MDCNT,MDCNT"
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endif
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sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
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rgroup.long 0x10++0x03
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line.long 0x00 "BCARI,PWM Basic Carrier Register"
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hexmask.long.word 0x00 0.--14. 1. "BCARI,BCARI"
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endif
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sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
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group.long 0x14++0x03
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line.long 0x00 "MDPRD,PMD PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "MDPRD,MDPRD"
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endif
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sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
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group.long 0x14++0x03
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line.long 0x00 "RATE,PWM Frequency Register"
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hexmask.long.word 0x00 0.--14. 1. "RATE,RATE"
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endif
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group.long 0x18++0x03
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line.long 0x00 "CMPU,PMD PWM Compare U Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPU,CMPU"
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group.long 0x1C++0x03
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line.long 0x00 "CMPV,PMD PWM Compare V Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPV,CMPV"
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group.long 0x20++0x03
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line.long 0x00 "CMPW,PMD PWM Compare W Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPW,CMPW"
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sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
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group.long 0x24++0x03
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line.long 0x00 "MODESEL,PMD Mode Select Register"
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bitfld.long 0x00 7. "DCMPEN,DCMPEN" "0,1"
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bitfld.long 0x00 3. "MDSEL3,MDSEL3" "0,1"
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bitfld.long 0x00 2. "MDSEL2,MDSEL2" "0,1"
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bitfld.long 0x00 1. "MDSEL1,MDSEL1" "0,1"
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newline
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bitfld.long 0x00 0. "MDSEL0,MDSEL0" "0,1"
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endif
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sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
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group.long 0x24++0x03
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line.long 0x00 "MODESEL,PMD Mode Selection Register"
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bitfld.long 0x00 7. "DCMPEN,DCMPEN" "0,1"
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bitfld.long 0x00 3. "MDSEL3,MDSEL3" "0,1"
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bitfld.long 0x00 2. "MDSEL2,MDSEL2" "0,1"
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bitfld.long 0x00 1. "MDSEL1,MDSEL1" "0,1"
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newline
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bitfld.long 0x00 0. "MDSEL0,MDSEL0" "0,1"
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endif
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group.long 0x28++0x03
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line.long 0x00 "MDOUT,PMD Conduction Control Register"
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bitfld.long 0x00 10. "WPWM,WPWM" "0,1"
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bitfld.long 0x00 9. "VPWM,VPWM" "0,1"
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bitfld.long 0x00 8. "UPWM,UPWM" "0,1"
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bitfld.long 0x00 4.--5. "WOC,WOC" "0,1,2,3"
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newline
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bitfld.long 0x00 2.--3. "VOC,VOC" "0,1,2,3"
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bitfld.long 0x00 0.--1. "UOC,UOC" "0,1,2,3"
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group.long 0x2C++0x03
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line.long 0x00 "MDPOT,PMD Output Setting Register"
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bitfld.long 0x00 8.--9. "SYNCS,SYNCS" "0,1,2,3"
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bitfld.long 0x00 3. "POLH,POLH" "0,1"
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bitfld.long 0x00 2. "POLL,POLL" "0,1"
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bitfld.long 0x00 0.--1. "PSYNCS,PSYNCS" "0,1,2,3"
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wgroup.long 0x30++0x03
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line.long 0x00 "EMGREL,PMD EMG Release Register"
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hexmask.long.byte 0x00 0.--7. 1. "EMGREL,EMGREL"
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sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
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group.long 0x34++0x03
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line.long 0x00 "EMGCR,PMD EMG Control Register"
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bitfld.long 0x00 8.--11. "EMGCNT,EMGCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 5. "INHEN,INHEN" "0,1"
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bitfld.long 0x00 3.--4. "EMGMD,EMGMD" "0,1,2,3"
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bitfld.long 0x00 1. "EMGRS,EMGRS" "0,1"
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newline
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bitfld.long 0x00 0. "EMGEN,EMGEN" "0,1"
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endif
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sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
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group.long 0x34++0x03
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line.long 0x00 "EMGCR,PMD EMG Control Register"
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bitfld.long 0x00 15. "CPCIEN,CPCIEN" "0,1"
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bitfld.long 0x00 14. "CPBIEN,CPBIEN" "0,1"
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bitfld.long 0x00 13. "CPAIEN,CPAIEN" "0,1"
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bitfld.long 0x00 8.--12. "EMGCNT,EMGCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 7. "EMGPOL,EMGPOL" "0,1"
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bitfld.long 0x00 5. "INHEN,INHEN" "0,1"
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bitfld.long 0x00 3.--4. "EMGMD,EMGMD" "0,1,2,3"
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bitfld.long 0x00 2. "EMGISEL,EMGISEL" "0,1"
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newline
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bitfld.long 0x00 1. "EMGRS,EMGRS" "0,1"
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bitfld.long 0x00 0. "EMGEN,EMGEN" "0,1"
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endif
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rgroup.long 0x38++0x03
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line.long 0x00 "EMGSTA,PMD EMG Status Register"
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bitfld.long 0x00 1. "EMGI,EMGI" "0,1"
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bitfld.long 0x00 0. "EMGST,EMGST" "0,1"
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sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
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group.long 0x3C++0x03
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line.long 0x00 "OVVCR,PMD OVV Control Register"
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bitfld.long 0x00 15. "OVVRSMD,OVVRSMD" "0,1"
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bitfld.long 0x00 8.--12. "OVVCNT,OVVCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 7. "OVVIPOL,OVVIPOL" "0,1"
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bitfld.long 0x00 6. "ADIN1EN,ADIN1EN" "0,1"
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newline
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bitfld.long 0x00 5. "ADIN0EN,ADIN0EN" "0,1"
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bitfld.long 0x00 3.--4. "OVVMD,OVVMD" "0,1,2,3"
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bitfld.long 0x00 2. "OVVISEL,OVVISEL" "0,1"
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bitfld.long 0x00 1. "OVVRS,OVVRS" "0,1"
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newline
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bitfld.long 0x00 0. "OVVEN,OVVEN" "0,1"
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endif
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sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
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group.long 0x3C++0x03
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line.long 0x00 "OVVCR,PMD OVV Control Register"
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bitfld.long 0x00 8.--11. "OVVCNT,OVVCNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6. "ADIN1EN,ADIN1EN" "0,1"
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bitfld.long 0x00 5. "ADIN0EN,ADIN0EN" "0,1"
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bitfld.long 0x00 3.--4. "OVVMD,OVVMD" "0,1,2,3"
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newline
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bitfld.long 0x00 2. "OVVISEL,OVVISEL" "0,1"
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bitfld.long 0x00 1. "OVVRS,OVVRS" "0,1"
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bitfld.long 0x00 0. "OVVEN,OVVEN" "0,1"
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endif
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rgroup.long 0x40++0x03
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line.long 0x00 "OVVSTA,PMD OVV Status Register"
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bitfld.long 0x00 1. "OVVI,OVVI" "0,1"
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bitfld.long 0x00 0. "OVVST,OVVST" "0,1"
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sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
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group.long 0x44++0x03
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line.long 0x00 "DTR,PMD Dead Time Register"
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hexmask.long.byte 0x00 0.--7. 1. "DTR,DTR"
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endif
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sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
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group.long 0x44++0x03
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line.long 0x00 "DTR,PMD Dead Time Register"
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hexmask.long.word 0x00 0.--9. 1. "DTR,DTR"
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group.long 0x48++0x03
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line.long 0x00 "TRGCMP0,PMD Trigger Compare Register 0"
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hexmask.long.word 0x00 0.--14. 1. "TRGCMP0,TRGCMP0"
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endif
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sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
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group.long 0x48++0x03
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line.long 0x00 "TRGCMP0,PMD Trigger Compare Register 0"
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hexmask.long.word 0x00 0.--15. 1. "TRGCMP0,TRGCMP0"
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group.long 0x4C++0x03
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line.long 0x00 "TRGCMP1,PMD Trigger Compare Register 1"
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hexmask.long.word 0x00 0.--15. 1. "TRGCMP1,TRGCMP1"
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endif
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sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
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group.long 0x4C++0x03
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line.long 0x00 "TRGCMP1,PMD Trigger Compare Register 1"
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hexmask.long.word 0x00 0.--14. 1. "TRGCMP1,TRGCMP1"
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endif
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sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
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group.long 0x50++0x03
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line.long 0x00 "TRGCMP2,PMD Trigger Compare Register 2"
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hexmask.long.word 0x00 0.--15. 1. "TRGCMP2,TRGCMP2"
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endif
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sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
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group.long 0x50++0x03
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line.long 0x00 "TRGCMP2,PMD Trigger Compare Register 2"
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hexmask.long.word 0x00 0.--14. 1. "TRGCMP2,TRGCMP2"
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endif
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sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
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group.long 0x54++0x03
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line.long 0x00 "TRGCMP3,PMD Trigger Compare Register 3"
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hexmask.long.word 0x00 0.--15. 1. "TRGCMP3,TRGCMP3"
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endif
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sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
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group.long 0x54++0x03
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line.long 0x00 "TRGCMP3,PMD Trigger Compare Register 3"
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hexmask.long.word 0x00 0.--14. 1. "TRGCMP3,TRGCMP3"
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group.long 0x58++0x03
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line.long 0x00 "TRGCR,PMD Trigger Control Register"
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bitfld.long 0x00 16. "CARSEL,CARSEL" "0,1"
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bitfld.long 0x00 15. "TRG3BE,TRG3BE" "0,1"
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bitfld.long 0x00 12.--14. "TRG3MD,TRG3MD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 11. "TRG2BE,TRG2BE" "0,1"
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newline
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bitfld.long 0x00 8.--10. "TRG2MD,TRG2MD" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 7. "TRG1BE,TRG1BE" "0,1"
|
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bitfld.long 0x00 4.--6. "TRG1MD,TRG1MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "TRG0BE,TRG0BE" "0,1"
|
|
newline
|
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bitfld.long 0x00 0.--2. "TRG0MD,TRG0MD" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("TMPM4L2*")||cpuis("TMPM4L2*")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TRGCR,PMD Trigger Control Register"
|
|
bitfld.long 0x00 15. "TRG3BE,TRG3BE" "0,1"
|
|
bitfld.long 0x00 12.--14. "TRG3MD,TRG3MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "TRG2BE,TRG2BE" "0,1"
|
|
bitfld.long 0x00 8.--10. "TRG2MD,TRG2MD" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. "TRG1BE,TRG1BE" "0,1"
|
|
bitfld.long 0x00 4.--6. "TRG1MD,TRG1MD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "TRG0BE,TRG0BE" "0,1"
|
|
bitfld.long 0x00 0.--2. "TRG0MD,TRG0MD" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRGMD,PMD Trigger Output Mode Setting Register"
|
|
bitfld.long 0x00 1. "TRGOUT,TRGOUT" "0,1"
|
|
bitfld.long 0x00 0. "EMGTGE,EMGTGE" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRGSEL,PMD Trigger Output Select Register"
|
|
bitfld.long 0x00 0.--2. "TRGSEL,TRGSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRGSYNCR,PMD Trigger Update Timing Setting Register"
|
|
bitfld.long 0x00 0.--1. "TSYNCS,TSYNCS" "0,1,2,3"
|
|
sif cpuis("TMPM4G7*")||cpuis("TMPM4G7*")||cpuis("TMPM4G8*")||cpuis("TMPM4G9*")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "VPWMPH,Phase difference setting of the V-phase PWM"
|
|
hexmask.long.word 0x00 0.--14. 1. "VPWMPH,VPWMPH"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "WPWMPH,Phase difference setting of the W-phase PWM"
|
|
hexmask.long.word 0x00 0.--14. 1. "WPWMPH,WPWMPH"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MBUFCR,Update timing of the triple buffer"
|
|
bitfld.long 0x00 0.--2. "BUFCTR,BUFCTR" "0,1,2,3,4,5,6,7"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "SYNCCR,Synchronization control between the PMD channel"
|
|
bitfld.long 0x00 6.--7. "OVVSMD,OVVSMD" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "EMGSMD,EMGSMD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "PWMSMD,PWMSMD" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DBGOUTCR,Debug output control"
|
|
bitfld.long 0x00 31. "INIFF,INIFF" "0,1"
|
|
bitfld.long 0x00 21. "TRG5EN,TRG5EN" "0,1"
|
|
bitfld.long 0x00 20. "TRG4EN,TRG4EN" "0,1"
|
|
bitfld.long 0x00 19. "TRG3EN,TRG3EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TRG2EN,TRG2EN" "0,1"
|
|
bitfld.long 0x00 17. "TRG1EN,TRG1EN" "0,1"
|
|
bitfld.long 0x00 16. "TRG0EN,TRG0EN" "0,1"
|
|
bitfld.long 0x00 12. "IENCEN,IENCEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IVEEN,IVEEN" "0,1"
|
|
bitfld.long 0x00 10. "IOVVEN,IOVVEN" "0,1"
|
|
bitfld.long 0x00 9. "IADGEN,IADGEN" "0,1"
|
|
bitfld.long 0x00 8. "IADFEN,IADFEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IADEEN,IADEEN" "0,1"
|
|
bitfld.long 0x00 6. "IADDEN,IADDEN" "0,1"
|
|
bitfld.long 0x00 5. "IADCEN,IADCEN" "0,1"
|
|
bitfld.long 0x00 4. "IADBEN,IADBEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IADAEN,IADAEN" "0,1"
|
|
bitfld.long 0x00 1.--2. "DBGMD,DBGMD" "0,1,2,3"
|
|
bitfld.long 0x00 0. "DBGEN,DBGEN" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4M*")||cpuis("TMPM4KN*")||cpuis("TMPM4KP*")||cpuis("TMPM4KQ*")
|
|
tree "EN (Advanced Encoder Input (A-ENC32))"
|
|
repeat 3. (list 0. 1. 2.) (list ad:0x400EA000 ad:0x400EA400 ad:0x400EA800)
|
|
tree "EN$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TNCR,ENC Control Register"
|
|
bitfld.long 0x00 28. "CMPSEL,CMPSEL" "0,1"
|
|
bitfld.long 0x00 26.--27. "UDMD,UDMD" "0,1,2,3"
|
|
bitfld.long 0x00 25. "TOVMD,TOVMD" "0,1"
|
|
bitfld.long 0x00 24. "MCMPMD,MCMPMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "DECMD,DECMD" "0,1,2,3"
|
|
bitfld.long 0x00 21. "SDTEN,SDTEN" "0,1"
|
|
bitfld.long 0x00 17.--19. "MODE,MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. "P3EN,P3EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "TRGCAPMD,TRGCAPMD" "0,1"
|
|
bitfld.long 0x00 11. "SFTCAP,SFTCAP" "0,1"
|
|
bitfld.long 0x00 10. "ENCLR,ENCLR" "0,1"
|
|
bitfld.long 0x00 8.--9. "ZESEL,ZESEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "ZEN,ZEN" "0,1"
|
|
bitfld.long 0x00 6. "ENRUN,ENRUN" "0,1"
|
|
bitfld.long 0x00 5. "ZEACT,ZEACT" "0,1"
|
|
bitfld.long 0x00 0.--2. "ENDEV,ENDEV" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RELOAD,ENC Reload Compare Register"
|
|
hexmask.long 0x00 0.--31. 1. "RELOAD,RELOAD"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "INT,ENC INT Compare Register"
|
|
hexmask.long 0x00 0.--31. 1. "INT,INT"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CNT,ENC Counter_Capture Register"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,CNT"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCMP,ENC MCMP Compare Register"
|
|
hexmask.long 0x00 0.--31. 1. "MCMP,MCMP"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RATE,ENC Phase Count Rate Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RATE,RATE"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "STS,ENC Status Register"
|
|
bitfld.long 0x00 14. "REVERR,REVERR" "0,1"
|
|
bitfld.long 0x00 13. "UD,UD" "0,1"
|
|
bitfld.long 0x00 12. "ZDET,ZDET" "0,1"
|
|
bitfld.long 0x00 2. "SKPDT,SKPDT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PDERR,PDERR" "0,1"
|
|
bitfld.long 0x00 0. "INERR,INERR" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "INPCR,ENC Input Process Cntrol Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. "NCT,NCT"
|
|
bitfld.long 0x00 7. "PDSTP,PDSTP" "0,1"
|
|
bitfld.long 0x00 6. "PDSTT,PDSTT" "0,1"
|
|
bitfld.long 0x00 2. "SYNCNCZEN,SYNCNCZEN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SYNCSPLMD,SYNCSPLMD" "0,1"
|
|
bitfld.long 0x00 0. "SYNCSPLEN,SYNCSPLEN" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SMPDLY,ENC Sample Delay Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SMPDLY,SMPDLY"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INPMON,ENC Input Moniter Register"
|
|
bitfld.long 0x00 6. "DETMONZ,DETMONZ" "0,1"
|
|
bitfld.long 0x00 5. "DETMONB,DETMONB" "0,1"
|
|
bitfld.long 0x00 4. "DETMONA,DETMONA" "0,1"
|
|
bitfld.long 0x00 2. "SPLMONZ,SPLMONZ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SPLMONB,SPLMONB" "0,1"
|
|
bitfld.long 0x00 0. "SPLMONA,SPLMONA" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CLKCR,ENC Sample Clock Control Register"
|
|
bitfld.long 0x00 0.--1. "SPLCKS,SPLCKS" "0,1,2,3"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTCR,ENC Interrupt Control Register"
|
|
bitfld.long 0x00 5. "MCMPIE,MCMPIE" "0,1"
|
|
bitfld.long 0x00 4. "RLDIE,RLDIE" "0,1"
|
|
bitfld.long 0x00 3. "CMPIE,CMPIE" "0,1"
|
|
bitfld.long 0x00 2. "ERRIE,ERRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CAPIE,CAPIE" "0,1"
|
|
bitfld.long 0x00 0. "TPLSIE,TPLSIE" "0,1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INTF,ENC Interrupt Event Flag Register"
|
|
bitfld.long 0x00 5. "MCMPF,MCMPF" "0,1"
|
|
bitfld.long 0x00 4. "RLDCPF,RLDCPF" "0,1"
|
|
bitfld.long 0x00 3. "INTCPF,INTCPF" "0,1"
|
|
bitfld.long 0x00 2. "ERRF,ERRF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CAPF,CAPF" "0,1"
|
|
bitfld.long 0x00 0. "TPLSF,TPLSF" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMPM4L1*")||cpuis("TMPM4L2*")
|
|
tree "GP (General Purpose Register)"
|
|
base ad:0x4003FF00
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "REG0,General Purpose Register 0"
|
|
bitfld.byte 0x00 1. "TSNC1SEL,TSNC1SEL" "0,1"
|
|
bitfld.byte 0x00 0. "TSNC0SEL,TSNC0SEL" "0,1"
|
|
tree.end
|
|
endif
|
|
autoindent.off
|
|
newline
|