35569 lines
1.8 MiB
35569 lines
1.8 MiB
; --------------------------------------------------------------------------------
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; @Title: STM32L5 On-Chip Peripherals
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; @Props: Released
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; @Author: BGI, RSA, DAB, NEJ
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; @Changelog: 2019-04-24 BGI
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; 2022-01-28 DAB
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; 2022-10-07 NEJ
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; @Manufacturer: STM - ST Microelectronics N.V.
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; @Doc: SVD Generated (SVD2PER 1.8.5), based on: STM32L552.svd (Ver. 1.5),
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; STM32L562.svd (Ver. 1.5)
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; @Core: Cortex-M33F
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; @Chip: STM32L552CC, STM32L552CE, STM32L552ME, STM32L552QC, STM32L552QE,
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; STM32L552RC, STM32L552RE, STM32L552VC, STM32L552VE, STM32L552ZC,
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; STM32L552ZE, STM32L562CE, STM32L562ME, STM32L562QE, STM32L562RE,
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; STM32L562VE, STM32L562ZE
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perstm32l5.per 15290 2022-10-07 10:33:39Z kwisniewski $
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tree.close "Core Registers (Cortex-M33F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
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bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
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bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
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textline " "
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bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes"
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group.long 0x0C++0x0F
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line.long 0x00 "CPPWR,Coprocessor Power Control Register"
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bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only"
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textline " "
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bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
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textline " "
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bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only"
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textline " "
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bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
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textline " "
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bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only"
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textline " "
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bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
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line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x0C "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Reserved,Reserved,Patch 2,?..."
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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textline " "
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bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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textline " "
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
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textline " "
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bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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line.long 0x14 "SHPR1,System Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
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bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
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bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
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bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active"
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textline " "
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bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
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bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "UFSR,Usage Fault Status Register"
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eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error"
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textline " "
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eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
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textline " "
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eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x03
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line.long 0x00 "HFSR,HardFault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
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if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
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group.long 0xD8C++0x03
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line.long 0x00 "NSACR,Non-Secure Access Control Register"
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bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
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bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
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bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
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bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
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bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
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bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
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bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
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else
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hgroup.long 0xD8C++0x03
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hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
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endif
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Triggered Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x03
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
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bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
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textline " "
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
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bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
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bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
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textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
|
|
rgroup.long 0xD7C++0x03
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
|
|
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0xD7C++0x03
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
|
|
endif
|
|
rgroup.long 0xD80++0x03
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
|
|
bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
|
|
group.long 0xD84++0x03
|
|
line.long 0x00 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
|
|
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
|
|
wgroup.long 0xF50++0x03
|
|
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
|
|
wgroup.long 0xF58++0x23
|
|
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
|
|
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
|
|
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
|
|
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
|
|
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
|
|
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
|
|
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
|
|
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
|
|
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
width 10.
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
|
|
rgroup.long 0xD4C++0x03
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
|
|
rgroup.long 0xD54++0x03
|
|
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD5C++0x03
|
|
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
|
|
bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x03
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
rgroup.long 0xD64++0x03
|
|
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
|
|
rgroup.long 0xD68++0x03
|
|
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
|
|
bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
|
|
rgroup.long 0xD6C++0x03
|
|
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
|
|
rgroup.long 0xD70++0x03
|
|
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
|
|
bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
|
|
bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 11.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DPIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DPIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DPIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DPIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DCIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DCIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DCIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit (SAU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree.close "SAU regions"
|
|
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x03 "Region 0"
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x03 "Region 1"
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x03 "Region 2"
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x03 "Region 3"
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x03 "Region 4"
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x03 "Region 5"
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x03 "Region 6"
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x03 "Region 7"
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
tree.end
|
|
group.long 0xDE4++0x03
|
|
line.long 0x00 "SFSR,Secure Fault Status Register"
|
|
bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred"
|
|
group.long 0xDE8++0x03
|
|
line.long 0x00 "SFAR,Secure Fault Address Register"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
|
|
width 24.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x120++0x03
|
|
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x124++0x03
|
|
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x134++0x03
|
|
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x138++0x03
|
|
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x13C++0x03
|
|
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
width 24.
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x224++0x03
|
|
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x228++0x03
|
|
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x22C++0x03
|
|
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x234++0x03
|
|
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x238++0x03
|
|
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x23C++0x03
|
|
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
width 11.
|
|
tree "Interrupt Active Bit Registers"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
rgroup.long 0x320++0x03
|
|
line.long 0x00 "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
rgroup.long 0x324++0x03
|
|
line.long 0x00 "ACTIVE9,Active Bit Register 9"
|
|
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x324++0x03
|
|
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
rgroup.long 0x328++0x03
|
|
line.long 0x00 "ACTIVE10,Active Bit Register 10"
|
|
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x328++0x03
|
|
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
rgroup.long 0x32C++0x03
|
|
line.long 0x00 "ACTIVE11,Active Bit Register 11"
|
|
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x32C++0x03
|
|
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
rgroup.long 0x330++0x03
|
|
line.long 0x00 "ACTIVE12,Active Bit Register 12"
|
|
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
rgroup.long 0x334++0x03
|
|
line.long 0x00 "ACTIVE13,Active Bit Register 13"
|
|
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x334++0x03
|
|
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
rgroup.long 0x338++0x03
|
|
line.long 0x00 "ACTIVE14,Active Bit Register 14"
|
|
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x338++0x03
|
|
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
|
|
rgroup.long 0x33C++0x03
|
|
line.long 0x00 "ACTIVE15,Active Bit Register 15"
|
|
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x33C++0x03
|
|
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
|
|
endif
|
|
tree.end
|
|
width 13.
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
|
|
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
|
|
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A4++0x03
|
|
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
|
|
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A8++0x03
|
|
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
|
|
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3AC++0x03
|
|
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
|
|
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
|
|
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B4++0x03
|
|
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
|
|
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B8++0x03
|
|
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
|
|
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3BC++0x03
|
|
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x1F
|
|
line.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0xC "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x1C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
else
|
|
hgroup.long 0x420++0x1F
|
|
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hide.long 0xC "IPR11,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x1F
|
|
line.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0xC "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x1C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
else
|
|
hgroup.long 0x440++0x1F
|
|
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hide.long 0xC "IPR19,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x1F
|
|
line.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0xC "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x1C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
else
|
|
hgroup.long 0x460++0x1F
|
|
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hide.long 0xC "IPR27,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x1F
|
|
line.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0xC "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x1C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
else
|
|
hgroup.long 0x480++0x1F
|
|
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hide.long 0xC "IPR35,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x1F
|
|
line.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0x1C "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
else
|
|
hgroup.long 0x4A0++0x1F
|
|
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xC "IPR43,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x1F
|
|
line.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0x1C "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
else
|
|
hgroup.long 0x4C0++0x1F
|
|
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xC "IPR51,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x1F
|
|
line.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
line.long 0x10 "IPR60,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority"
|
|
line.long 0x14 "IPR61,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority"
|
|
line.long 0x18 "IPR62,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority"
|
|
line.long 0x1C "IPR63,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority"
|
|
else
|
|
hgroup.long 0x4E0++0x1F
|
|
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xC "IPR59,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR60,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR61,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR62,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR63,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x500++0x1F
|
|
line.long 0x0 "IPR64,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority"
|
|
line.long 0x4 "IPR65,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority"
|
|
line.long 0x8 "IPR66,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority"
|
|
line.long 0xC "IPR67,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority"
|
|
line.long 0x10 "IPR68,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority"
|
|
line.long 0x14 "IPR69,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority"
|
|
line.long 0x18 "IPR70,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority"
|
|
line.long 0x1C "IPR71,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority"
|
|
else
|
|
hgroup.long 0x500++0x1F
|
|
hide.long 0x0 "IPR64,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR65,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR66,Interrupt Priority Register"
|
|
hide.long 0xC "IPR67,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR68,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR69,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR70,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR71,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x520++0x1F
|
|
line.long 0x0 "IPR72,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority"
|
|
line.long 0x4 "IPR73,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority"
|
|
line.long 0x8 "IPR74,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority"
|
|
line.long 0xC "IPR75,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority"
|
|
line.long 0x10 "IPR76,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority"
|
|
line.long 0x14 "IPR77,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority"
|
|
line.long 0x18 "IPR78,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority"
|
|
line.long 0x1C "IPR79,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority"
|
|
else
|
|
hgroup.long 0x520++0x1F
|
|
hide.long 0x0 "IPR72,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR73,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR74,Interrupt Priority Register"
|
|
hide.long 0xC "IPR75,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR76,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR77,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR78,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR79,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x540++0x1F
|
|
line.long 0x0 "IPR80,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority"
|
|
line.long 0x4 "IPR81,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority"
|
|
line.long 0x8 "IPR82,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority"
|
|
line.long 0xC "IPR83,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority"
|
|
line.long 0x10 "IPR84,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority"
|
|
line.long 0x14 "IPR85,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority"
|
|
line.long 0x18 "IPR86,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority"
|
|
line.long 0x1C "IPR87,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority"
|
|
else
|
|
hgroup.long 0x540++0x1F
|
|
hide.long 0x0 "IPR80,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR81,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR82,Interrupt Priority Register"
|
|
hide.long 0xC "IPR83,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR84,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR85,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR86,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR87,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x560++0x1F
|
|
line.long 0x0 "IPR88,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority"
|
|
line.long 0x4 "IPR89,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority"
|
|
line.long 0x8 "IPR90,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority"
|
|
line.long 0xC "IPR91,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority"
|
|
line.long 0x10 "IPR92,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority"
|
|
line.long 0x14 "IPR93,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority"
|
|
line.long 0x18 "IPR94,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority"
|
|
line.long 0x1C "IPR95,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority"
|
|
else
|
|
hgroup.long 0x560++0x1F
|
|
hide.long 0x0 "IPR88,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR89,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR90,Interrupt Priority Register"
|
|
hide.long 0xC "IPR91,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR92,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR93,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR94,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR95,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x580++0x1F
|
|
line.long 0x0 "IPR96,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority"
|
|
line.long 0x4 "IPR97,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority"
|
|
line.long 0x8 "IPR98,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority"
|
|
line.long 0xC "IPR99,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority"
|
|
line.long 0x10 "IPR100,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority"
|
|
line.long 0x14 "IPR101,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority"
|
|
line.long 0x18 "IPR102,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority"
|
|
line.long 0x1C "IPR103,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority"
|
|
else
|
|
hgroup.long 0x580++0x1F
|
|
hide.long 0x0 "IPR96,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR97,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR98,Interrupt Priority Register"
|
|
hide.long 0xC "IPR99,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR100,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR101,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR102,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR103,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x5A0++0x1F
|
|
line.long 0x0 "IPR104,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority"
|
|
line.long 0x4 "IPR105,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority"
|
|
line.long 0x8 "IPR106,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority"
|
|
line.long 0xC "IPR107,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority"
|
|
line.long 0x10 "IPR108,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority"
|
|
line.long 0x14 "IPR109,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority"
|
|
line.long 0x18 "IPR110,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority"
|
|
line.long 0x1C "IPR111,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority"
|
|
else
|
|
hgroup.long 0x5A0++0x1F
|
|
hide.long 0x0 "IPR104,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR105,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR106,Interrupt Priority Register"
|
|
hide.long 0xC "IPR107,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR108,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR109,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR110,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR111,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x5C0++0x1F
|
|
line.long 0x0 "IPR112,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority"
|
|
line.long 0x4 "IPR113,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority"
|
|
line.long 0x8 "IPR114,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority"
|
|
line.long 0xC "IPR115,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority"
|
|
line.long 0x10 "IPR116,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority"
|
|
line.long 0x14 "IPR117,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority"
|
|
line.long 0x18 "IPR118,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority"
|
|
line.long 0x1C "IPR119,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority"
|
|
else
|
|
hgroup.long 0x5C0++0x1F
|
|
hide.long 0x0 "IPR112,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR113,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR114,Interrupt Priority Register"
|
|
hide.long 0xC "IPR115,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR116,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR117,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR118,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR119,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif (CORENAME()=="CORTEXM33F")
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
|
|
newline
|
|
bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
|
|
bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
|
|
newline
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
|
|
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 13.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
|
|
hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
tree "CoreSight Identification Registers"
|
|
width 12.
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "FP_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
tree "CoreSight Identification Registers"
|
|
width 13.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DWT_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
repeat 2. (list 1. 2.) (list ad:0x42028000 ad:0x42028100)
|
|
tree "ADC$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ISR,interrupt and status register"
|
|
bitfld.long 0x00 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x00 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x00 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x00 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x00 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x00 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x00 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x00 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x00 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x00 0. "ADRDY,ADRDY" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER,interrupt enable register"
|
|
bitfld.long 0x00 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x00 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x00 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x00 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x00 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x00 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x00 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x00 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x00 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x00 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,control register"
|
|
bitfld.long 0x00 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x00 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x00 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x00 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x00 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x00 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x00 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x00 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x00 0. "ADEN,ADEN" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CFGR,configuration register"
|
|
bitfld.long 0x00 31. "JQDIS,JQDIS" "0,1"
|
|
bitfld.long 0x00 26.--30. "AWDCH1CH,AWDCH1CH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0x00 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0x00 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0x00 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0x00 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0x00 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0x00 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0x00 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0x00 12. "OVRMOD,OVRMOD" "0,1"
|
|
bitfld.long 0x00 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--9. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0x00 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0x00 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0x00 0. "DMAEN,DMAEN" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CFGR2,configuration register"
|
|
bitfld.long 0x00 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x00 9. "TOVS,EXTSEL" "0,1"
|
|
bitfld.long 0x00 5.--8. "OVSS,ALIGN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x00 0. "ROVSE,DMAEN" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SMPR1,sample time register 1"
|
|
bitfld.long 0x00 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SMPR2,sample time register 2"
|
|
bitfld.long 0x00 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. "HT1,HT1"
|
|
hexmask.long.word 0x00 0.--11. 1. "LT1,LT1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LT2,LT2"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SQR1,regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. "SQ4,SQ4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18.--22. "SQ3,SQ3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--16. "SQ2,SQ2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--10. "SQ1,SQ1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. "L,L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SQR2,regular sequence register 2"
|
|
bitfld.long 0x00 24.--28. "SQ9,SQ9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18.--22. "SQ8,SQ8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--16. "SQ7,SQ7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--10. "SQ6,SQ6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "SQ5,SQ5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SQR3,regular sequence register 3"
|
|
bitfld.long 0x00 24.--28. "SQ14,SQ14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18.--22. "SQ13,SQ13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--16. "SQ12,SQ12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--10. "SQ11,SQ11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "SQ10,SQ10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SQR4,regular sequence register 4"
|
|
bitfld.long 0x00 6.--10. "SQ16,SQ16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "SQ15,SQ15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "DR,regular Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDATA,regularDATA"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "JSQR,injected sequence register"
|
|
bitfld.long 0x00 26.--30. "JSQ4,JSQ4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20.--24. "JSQ3,JSQ3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14.--18. "JSQ2,JSQ2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. "JSQ1,JSQ1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
bitfld.long 0x00 2.--5. "JEXTSEL,JEXTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OFR1,offset register 1"
|
|
bitfld.long 0x00 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
bitfld.long 0x00 26.--30. "OFFSET1_CH,OFFSET1_CH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFFSET1,OFFSET1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "OFR2,offset register 2"
|
|
bitfld.long 0x00 31. "OFFSET2_EN,OFFSET2_EN" "0,1"
|
|
bitfld.long 0x00 26.--30. "OFFSET2_CH,OFFSET2_CH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFFSET2,OFFSET2"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "OFR3,offset register 3"
|
|
bitfld.long 0x00 31. "OFFSET3_EN,OFFSET3_EN" "0,1"
|
|
bitfld.long 0x00 26.--30. "OFFSET3_CH,OFFSET3_CH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFFSET3,OFFSET3"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "OFR4,offset register 4"
|
|
bitfld.long 0x00 31. "OFFSET4_EN,OFFSET4_EN" "0,1"
|
|
bitfld.long 0x00 26.--30. "OFFSET4_CH,OFFSET4_CH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFFSET4,OFFSET4"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "JDATA,JDATA1"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "JDATA,JDATA2"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "JDATA,JDATA3"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "JDR4,injected data register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "JDATA,JDATA4"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. "AWD2CH,AWD2CH"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DIFSEL,Differential Mode Selection Register 2"
|
|
rbitfld.long 0x00 16.--18. "DIFSEL_16_18,Differential mode for channels 18 to 16" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 1.--15. 1. "DIFSEL_1_15,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x00 0. "DIFSEL_0,Differential mode for channel 0" "0,1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x00 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
tree.end
|
|
repeat.end
|
|
tree "ADC_COMMON"
|
|
base ad:0x42028300
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CSR,ADC Common status register"
|
|
bitfld.long 0x00 26. "JQOVF_SLV,JQOVF_SLV" "0,1"
|
|
bitfld.long 0x00 25. "AWD3_SLV,AWD3_SLV" "0,1"
|
|
bitfld.long 0x00 24. "AWD2_SLV,AWD2_SLV" "0,1"
|
|
bitfld.long 0x00 23. "AWD1_SLV,AWD1_SLV" "0,1"
|
|
bitfld.long 0x00 22. "JEOS_SLV,JEOS_SLV" "0,1"
|
|
bitfld.long 0x00 21. "JEOC_SLV,JEOC_SLV" "0,1"
|
|
bitfld.long 0x00 20. "OVR_SLV,OVR_SLV" "0,1"
|
|
bitfld.long 0x00 19. "EOS_SLV,EOS_SLV" "0,1"
|
|
bitfld.long 0x00 18. "EOC_SLV,EOC_SLV" "0,1"
|
|
bitfld.long 0x00 17. "EOSMP_SLV,EOSMP_SLV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ADRDY_SLV,ADRDY_SLV" "0,1"
|
|
bitfld.long 0x00 10. "JQOVF_MST,JQOVF_MST" "0,1"
|
|
bitfld.long 0x00 9. "AWD3_MST,AWD3_MST" "0,1"
|
|
bitfld.long 0x00 8. "AWD2_MST,AWD2_MST" "0,1"
|
|
bitfld.long 0x00 7. "AWD1_MST,AWD1_MST" "0,1"
|
|
bitfld.long 0x00 6. "JEOS_MST,JEOS_MST" "0,1"
|
|
bitfld.long 0x00 5. "JEOC_MST,JEOC_MST" "0,1"
|
|
bitfld.long 0x00 4. "OVR_MST,OVR_MST" "0,1"
|
|
bitfld.long 0x00 3. "EOS_MST,EOS_MST" "0,1"
|
|
bitfld.long 0x00 2. "EOC_MST,EOC_MST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EOSMP_MST,EOSMP_MST" "0,1"
|
|
bitfld.long 0x00 0. "ADDRDY_MST,ADDRDY_MST" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CCR,ADC common control register"
|
|
bitfld.long 0x00 24. "CH18SEL,CH18SEL" "0,1"
|
|
bitfld.long 0x00 23. "CH17SEL,CH17SEL" "0,1"
|
|
bitfld.long 0x00 22. "VREFEN,VREFINT enable" "0,1"
|
|
bitfld.long 0x00 18.--21. "PRESC,ADC prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. "CKMODE,ADC clock mode" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MDMA,MDMA" "0,1,2,3"
|
|
bitfld.long 0x00 13. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0x00 8.--10. "DELAY,DELAY" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "DUAL,DUAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CDR,Common regular data register for dual mode"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDATA_SLV,RDATA_SLV"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDATA_MST,RDATA_MST"
|
|
tree.end
|
|
repeat 2. (list 1. 2.) (list ad:0x52028000 ad:0x52028100)
|
|
tree "SEC_ADC$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ISR,interrupt and status register"
|
|
bitfld.long 0x00 10. "JQOVF,JQOVF" "0,1"
|
|
bitfld.long 0x00 9. "AWD3,AWD3" "0,1"
|
|
bitfld.long 0x00 8. "AWD2,AWD2" "0,1"
|
|
bitfld.long 0x00 7. "AWD1,AWD1" "0,1"
|
|
bitfld.long 0x00 6. "JEOS,JEOS" "0,1"
|
|
bitfld.long 0x00 5. "JEOC,JEOC" "0,1"
|
|
bitfld.long 0x00 4. "OVR,OVR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EOS,EOS" "0,1"
|
|
bitfld.long 0x00 2. "EOC,EOC" "0,1"
|
|
bitfld.long 0x00 1. "EOSMP,EOSMP" "0,1"
|
|
bitfld.long 0x00 0. "ADRDY,ADRDY" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER,interrupt enable register"
|
|
bitfld.long 0x00 10. "JQOVFIE,JQOVFIE" "0,1"
|
|
bitfld.long 0x00 9. "AWD3IE,AWD3IE" "0,1"
|
|
bitfld.long 0x00 8. "AWD2IE,AWD2IE" "0,1"
|
|
bitfld.long 0x00 7. "AWD1IE,AWD1IE" "0,1"
|
|
bitfld.long 0x00 6. "JEOSIE,JEOSIE" "0,1"
|
|
bitfld.long 0x00 5. "JEOCIE,JEOCIE" "0,1"
|
|
bitfld.long 0x00 4. "OVRIE,OVRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EOSIE,EOSIE" "0,1"
|
|
bitfld.long 0x00 2. "EOCIE,EOCIE" "0,1"
|
|
bitfld.long 0x00 1. "EOSMPIE,EOSMPIE" "0,1"
|
|
bitfld.long 0x00 0. "ADRDYIE,ADRDYIE" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,control register"
|
|
bitfld.long 0x00 31. "ADCAL,ADCAL" "0,1"
|
|
bitfld.long 0x00 30. "ADCALDIF,ADCALDIF" "0,1"
|
|
bitfld.long 0x00 29. "DEEPPWD,DEEPPWD" "0,1"
|
|
bitfld.long 0x00 28. "ADVREGEN,ADVREGEN" "0,1"
|
|
bitfld.long 0x00 5. "JADSTP,JADSTP" "0,1"
|
|
bitfld.long 0x00 4. "ADSTP,ADSTP" "0,1"
|
|
bitfld.long 0x00 3. "JADSTART,JADSTART" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ADSTART,ADSTART" "0,1"
|
|
bitfld.long 0x00 1. "ADDIS,ADDIS" "0,1"
|
|
bitfld.long 0x00 0. "ADEN,ADEN" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CFGR,configuration register"
|
|
bitfld.long 0x00 31. "JQDIS,JQDIS" "0,1"
|
|
bitfld.long 0x00 26.--30. "AWDCH1CH,AWDCH1CH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 25. "JAUTO,JAUTO" "0,1"
|
|
bitfld.long 0x00 24. "JAWD1EN,JAWD1EN" "0,1"
|
|
bitfld.long 0x00 23. "AWD1EN,AWD1EN" "0,1"
|
|
bitfld.long 0x00 22. "AWD1SGL,AWD1SGL" "0,1"
|
|
bitfld.long 0x00 21. "JQM,JQM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "JDISCEN,JDISCEN" "0,1"
|
|
bitfld.long 0x00 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. "DISCEN,DISCEN" "0,1"
|
|
bitfld.long 0x00 14. "AUTDLY,AUTDLY" "0,1"
|
|
bitfld.long 0x00 13. "CONT,CONT" "0,1"
|
|
bitfld.long 0x00 12. "OVRMOD,OVRMOD" "0,1"
|
|
bitfld.long 0x00 10.--11. "EXTEN,EXTEN" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--9. "EXTSEL,EXTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. "ALIGN,ALIGN" "0,1"
|
|
bitfld.long 0x00 3.--4. "RES,RES" "0,1,2,3"
|
|
bitfld.long 0x00 1. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0x00 0. "DMAEN,DMAEN" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CFGR2,configuration register"
|
|
bitfld.long 0x00 10. "ROVSM,EXTEN" "0,1"
|
|
bitfld.long 0x00 9. "TOVS,EXTSEL" "0,1"
|
|
bitfld.long 0x00 5.--8. "OVSS,ALIGN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--4. "OVSR,RES" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "JOVSE,DMACFG" "0,1"
|
|
bitfld.long 0x00 0. "ROVSE,DMAEN" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SMPR1,sample time register 1"
|
|
bitfld.long 0x00 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SMPR2,sample time register 2"
|
|
bitfld.long 0x00 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TR1,watchdog threshold register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. "HT1,HT1"
|
|
hexmask.long.word 0x00 0.--11. 1. "LT1,LT1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TR2,watchdog threshold register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HT2,HT2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LT2,LT2"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TR3,watchdog threshold register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HT3,HT3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LT3,LT3"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SQR1,regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. "SQ4,SQ4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18.--22. "SQ3,SQ3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--16. "SQ2,SQ2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--10. "SQ1,SQ1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. "L,L" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SQR2,regular sequence register 2"
|
|
bitfld.long 0x00 24.--28. "SQ9,SQ9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18.--22. "SQ8,SQ8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--16. "SQ7,SQ7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--10. "SQ6,SQ6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "SQ5,SQ5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SQR3,regular sequence register 3"
|
|
bitfld.long 0x00 24.--28. "SQ14,SQ14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18.--22. "SQ13,SQ13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--16. "SQ12,SQ12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--10. "SQ11,SQ11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "SQ10,SQ10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SQR4,regular sequence register 4"
|
|
bitfld.long 0x00 6.--10. "SQ16,SQ16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "SQ15,SQ15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "DR,regular Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDATA,regularDATA"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "JSQR,injected sequence register"
|
|
bitfld.long 0x00 26.--30. "JSQ4,JSQ4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20.--24. "JSQ3,JSQ3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14.--18. "JSQ2,JSQ2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. "JSQ1,JSQ1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. "JEXTEN,JEXTEN" "0,1,2,3"
|
|
bitfld.long 0x00 2.--5. "JEXTSEL,JEXTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "JL,JL" "0,1,2,3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OFR1,offset register 1"
|
|
bitfld.long 0x00 31. "OFFSET1_EN,OFFSET1_EN" "0,1"
|
|
bitfld.long 0x00 26.--30. "OFFSET1_CH,OFFSET1_CH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFFSET1,OFFSET1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "OFR2,offset register 2"
|
|
bitfld.long 0x00 31. "OFFSET2_EN,OFFSET2_EN" "0,1"
|
|
bitfld.long 0x00 26.--30. "OFFSET2_CH,OFFSET2_CH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFFSET2,OFFSET2"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "OFR3,offset register 3"
|
|
bitfld.long 0x00 31. "OFFSET3_EN,OFFSET3_EN" "0,1"
|
|
bitfld.long 0x00 26.--30. "OFFSET3_CH,OFFSET3_CH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFFSET3,OFFSET3"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "OFR4,offset register 4"
|
|
bitfld.long 0x00 31. "OFFSET4_EN,OFFSET4_EN" "0,1"
|
|
bitfld.long 0x00 26.--30. "OFFSET4_CH,OFFSET4_CH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--11. 1. "OFFSET4,OFFSET4"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "JDR1,injected data register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "JDATA,JDATA1"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "JDR2,injected data register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "JDATA,JDATA2"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "JDR3,injected data register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "JDATA,JDATA3"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "JDR4,injected data register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "JDATA,JDATA4"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "AWD2CR,Analog Watchdog 2 Configuration Register"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. "AWD2CH,AWD2CH"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "AWD3CR,Analog Watchdog 3 Configuration Register"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. "AWD3CH,AWD3CH"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DIFSEL,Differential Mode Selection Register 2"
|
|
rbitfld.long 0x00 16.--18. "DIFSEL_16_18,Differential mode for channels 18 to 16" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 1.--15. 1. "DIFSEL_1_15,Differential mode for channels 15 to 1"
|
|
rbitfld.long 0x00 0. "DIFSEL_0,Differential mode for channel 0" "0,1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CALFACT,Calibration Factors"
|
|
hexmask.long.byte 0x00 16.--22. 1. "CALFACT_D,CALFACT_D"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CALFACT_S,CALFACT_S"
|
|
tree.end
|
|
repeat.end
|
|
tree "SEC_ADC_COMMON"
|
|
base ad:0x52028300
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CSR,ADC Common status register"
|
|
bitfld.long 0x00 26. "JQOVF_SLV,JQOVF_SLV" "0,1"
|
|
bitfld.long 0x00 25. "AWD3_SLV,AWD3_SLV" "0,1"
|
|
bitfld.long 0x00 24. "AWD2_SLV,AWD2_SLV" "0,1"
|
|
bitfld.long 0x00 23. "AWD1_SLV,AWD1_SLV" "0,1"
|
|
bitfld.long 0x00 22. "JEOS_SLV,JEOS_SLV" "0,1"
|
|
bitfld.long 0x00 21. "JEOC_SLV,JEOC_SLV" "0,1"
|
|
bitfld.long 0x00 20. "OVR_SLV,OVR_SLV" "0,1"
|
|
bitfld.long 0x00 19. "EOS_SLV,EOS_SLV" "0,1"
|
|
bitfld.long 0x00 18. "EOC_SLV,EOC_SLV" "0,1"
|
|
bitfld.long 0x00 17. "EOSMP_SLV,EOSMP_SLV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ADRDY_SLV,ADRDY_SLV" "0,1"
|
|
bitfld.long 0x00 10. "JQOVF_MST,JQOVF_MST" "0,1"
|
|
bitfld.long 0x00 9. "AWD3_MST,AWD3_MST" "0,1"
|
|
bitfld.long 0x00 8. "AWD2_MST,AWD2_MST" "0,1"
|
|
bitfld.long 0x00 7. "AWD1_MST,AWD1_MST" "0,1"
|
|
bitfld.long 0x00 6. "JEOS_MST,JEOS_MST" "0,1"
|
|
bitfld.long 0x00 5. "JEOC_MST,JEOC_MST" "0,1"
|
|
bitfld.long 0x00 4. "OVR_MST,OVR_MST" "0,1"
|
|
bitfld.long 0x00 3. "EOS_MST,EOS_MST" "0,1"
|
|
bitfld.long 0x00 2. "EOC_MST,EOC_MST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EOSMP_MST,EOSMP_MST" "0,1"
|
|
bitfld.long 0x00 0. "ADDRDY_MST,ADDRDY_MST" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CCR,ADC common control register"
|
|
bitfld.long 0x00 24. "CH18SEL,CH18SEL" "0,1"
|
|
bitfld.long 0x00 23. "CH17SEL,CH17SEL" "0,1"
|
|
bitfld.long 0x00 22. "VREFEN,VREFINT enable" "0,1"
|
|
bitfld.long 0x00 18.--21. "PRESC,ADC prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. "CKMODE,ADC clock mode" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MDMA,MDMA" "0,1,2,3"
|
|
bitfld.long 0x00 13. "DMACFG,DMACFG" "0,1"
|
|
bitfld.long 0x00 8.--10. "DELAY,DELAY" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "DUAL,DUAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CDR,Common regular data register for dual mode"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDATA_SLV,RDATA_SLV"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDATA_MST,RDATA_MST"
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("STM32L562*")
|
|
tree "AES (Advanced encryption standard hardware accelerator 1)"
|
|
tree "AES"
|
|
base ad:0x420C0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,control register"
|
|
bitfld.long 0x00 20.--23. "NPBLB,Number of padding bytes in last block of payload" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18. "KEYSIZE,Key size selection" "0,1"
|
|
bitfld.long 0x00 16. "CHMOD2,AES chaining mode Bit2" "0,1"
|
|
bitfld.long 0x00 13.--14. "GCMPH,Used only for GCM CCM and GMAC algorithms and has no effect when other algorithms are selected" "0,1,2,3"
|
|
bitfld.long 0x00 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1"
|
|
bitfld.long 0x00 11. "DMAINEN,Enable DMA management of data input phase" "0,1"
|
|
bitfld.long 0x00 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x00 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
bitfld.long 0x00 8. "ERRC,Error clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CCFC,Computation Complete Flag Clear" "0,1"
|
|
bitfld.long 0x00 5.--6. "CHMOD,AES chaining mode selection Bit1 Bit0" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3"
|
|
bitfld.long 0x00 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 3. "BUSY,Busy flag" "0,1"
|
|
bitfld.long 0x00 2. "WRERR,Write error flag" "0,1"
|
|
bitfld.long 0x00 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x00 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DINR,data input register"
|
|
hexmask.long 0x00 0.--31. 1. "DIN,Data Input Register"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DOUTR,data output register"
|
|
hexmask.long 0x00 0.--31. 1. "DOUT,Data output register"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "KEYR0,key register 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits[31:0]"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "KEYR1,key register 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [63:32])"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "KEYR2,key register 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [95:64])"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "KEYR3,key register 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [127:96])"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IVR0,initialization vector register 0"
|
|
hexmask.long 0x00 0.--31. 1. "IVI,initialization vector register (LSB IVR [31:0])"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IVR1,initialization vector register 1"
|
|
hexmask.long 0x00 0.--31. 1. "IVI,Initialization Vector Register (IVR [63:32])"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IVR2,initialization vector register 2"
|
|
hexmask.long 0x00 0.--31. 1. "IVI,Initialization Vector Register (IVR [95:64])"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IVR3,initialization vector register 3"
|
|
hexmask.long 0x00 0.--31. 1. "IVI,Initialization Vector Register (MSB IVR [127:96])"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "KEYR4,key register 4"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [159:128])"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "KEYR5,key register 5"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [191:160])"
|
|
wgroup.long 0x38++0x03
|
|
line.long 0x00 "KEYR6,key register 6"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [223:192])"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "KEYR7,key register 7"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [255:224])"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SUSP0R,AES suspend register 0"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP0R,AES suspend register 0"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SUSP1R,AES suspend register 1"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP1R,AES suspend register 1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SUSP2R,AES suspend register 2"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP2R,AES suspend register 2"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SUSP3R,AES suspend register 3"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP3R,AES suspend register 3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SUSP4R,AES suspend register 4"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP4R,AES suspend register 4"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SUSP5R,AES suspend register 5"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP5R,AES suspend register 5"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SUSP6R,AES suspend register 6"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP6R,AES suspend register 6"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SUSP7R,AES suspend register 7"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP7R,AES suspend register 7"
|
|
tree.end
|
|
tree "SEC_AES"
|
|
base ad:0x520C0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,control register"
|
|
bitfld.long 0x00 20.--23. "NPBLB,Number of padding bytes in last block of payload" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18. "KEYSIZE,Key size selection" "0,1"
|
|
bitfld.long 0x00 16. "CHMOD2,AES chaining mode Bit2" "0,1"
|
|
bitfld.long 0x00 13.--14. "GCMPH,Used only for GCM CCM and GMAC algorithms and has no effect when other algorithms are selected" "0,1,2,3"
|
|
bitfld.long 0x00 12. "DMAOUTEN,Enable DMA management of data output phase" "0,1"
|
|
bitfld.long 0x00 11. "DMAINEN,Enable DMA management of data input phase" "0,1"
|
|
bitfld.long 0x00 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x00 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
bitfld.long 0x00 8. "ERRC,Error clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CCFC,Computation Complete Flag Clear" "0,1"
|
|
bitfld.long 0x00 5.--6. "CHMOD,AES chaining mode selection Bit1 Bit0" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. "DATATYPE,Data type selection (for data in and data out to/from the cryptographic block)" "0,1,2,3"
|
|
bitfld.long 0x00 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 3. "BUSY,Busy flag" "0,1"
|
|
bitfld.long 0x00 2. "WRERR,Write error flag" "0,1"
|
|
bitfld.long 0x00 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x00 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DINR,data input register"
|
|
hexmask.long 0x00 0.--31. 1. "DIN,Data Input Register"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DOUTR,data output register"
|
|
hexmask.long 0x00 0.--31. 1. "DOUT,Data output register"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "KEYR0,key register 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits[31:0]"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "KEYR1,key register 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [63:32])"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "KEYR2,key register 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [95:64])"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "KEYR3,key register 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [127:96])"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IVR0,initialization vector register 0"
|
|
hexmask.long 0x00 0.--31. 1. "IVI,initialization vector register (LSB IVR [31:0])"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IVR1,initialization vector register 1"
|
|
hexmask.long 0x00 0.--31. 1. "IVI,Initialization Vector Register (IVR [63:32])"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IVR2,initialization vector register 2"
|
|
hexmask.long 0x00 0.--31. 1. "IVI,Initialization Vector Register (IVR [95:64])"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IVR3,initialization vector register 3"
|
|
hexmask.long 0x00 0.--31. 1. "IVI,Initialization Vector Register (MSB IVR [127:96])"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "KEYR4,key register 4"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [159:128])"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "KEYR5,key register 5"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [191:160])"
|
|
wgroup.long 0x38++0x03
|
|
line.long 0x00 "KEYR6,key register 6"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [223:192])"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "KEYR7,key register 7"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Cryptographic key bits [255:224])"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SUSP0R,AES suspend register 0"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP0R,AES suspend register 0"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SUSP1R,AES suspend register 1"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP1R,AES suspend register 1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SUSP2R,AES suspend register 2"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP2R,AES suspend register 2"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SUSP3R,AES suspend register 3"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP3R,AES suspend register 3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SUSP4R,AES suspend register 4"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP4R,AES suspend register 4"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SUSP5R,AES suspend register 5"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP5R,AES suspend register 5"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SUSP6R,AES suspend register 6"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP6R,AES suspend register 6"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SUSP7R,AES suspend register 7"
|
|
hexmask.long 0x00 0.--31. 1. "AES_SUSP7R,AES suspend register 7"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "COMP (Comparator)"
|
|
tree "COMP"
|
|
base ad:0x40010200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMP1_CSR,Comparator 1 control and status register"
|
|
bitfld.long 0x00 31. "COMP1_LOCK,COMP1_CSR register lock bit" "0,1"
|
|
rbitfld.long 0x00 30. "COMP1_VALUE,Comparator 1 output status bit" "0,1"
|
|
bitfld.long 0x00 23. "COMP1_SCALEN,Voltage scaler enable bit" "0,1"
|
|
bitfld.long 0x00 22. "COMP1_BRGEN,Scaler bridge enable" "0,1"
|
|
bitfld.long 0x00 18.--20. "COMP1_BLANKING,Comparator 1 blanking source selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. "COMP1_HYST,Comparator 1 hysteresis selection bits" "0,1,2,3"
|
|
bitfld.long 0x00 15. "COMP1_POLARITY,Comparator 1 polarity selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "COMP1_INPSEL,Comparator1 input plus selection bit" "0,1"
|
|
bitfld.long 0x00 4.--6. "COMP1_INMSEL,Comparator 1 Input Minus connection configuration bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--3. "COMP1_PWRMODE,Power Mode of the comparator 1" "0,1,2,3"
|
|
bitfld.long 0x00 0. "COMP1_EN,Comparator 1 enable bit" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "COMP2_CSR,Comparator 2 control and status register"
|
|
bitfld.long 0x00 31. "COMP2_LOCK,COMP2_CSR register lock bit" "0,1"
|
|
rbitfld.long 0x00 30. "COMP2_VALUE,Comparator 2 output status bit" "0,1"
|
|
bitfld.long 0x00 23. "COMP2_SCALEN,Voltage scaler enable bit" "0,1"
|
|
bitfld.long 0x00 22. "COMP2_BRGEN,Scaler bridge enable" "0,1"
|
|
bitfld.long 0x00 18.--20. "COMP2_BLANKING,Comparator 2 blanking source selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. "COMP2_HYST,Comparator 2 hysteresis selection bits" "0,1,2,3"
|
|
bitfld.long 0x00 15. "COMP2_POLARITY,Comparator 2 polarity selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "COMP2_WINMODE,Windows mode selection bit" "0,1"
|
|
bitfld.long 0x00 7. "COMP2_INPSEL,Comparator 2 Input Plus connection configuration bit" "0,1"
|
|
bitfld.long 0x00 4.--6. "COMP2_INMSEL,Comparator 2 Input Minus connection configuration bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--3. "COMP2_PWRMODE,Power Mode of the comparator 2" "0,1,2,3"
|
|
bitfld.long 0x00 0. "COMP2_EN,Comparator 2 enable bit" "0,1"
|
|
tree.end
|
|
tree "SEC_COMP"
|
|
base ad:0x50010200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMP1_CSR,Comparator 1 control and status register"
|
|
bitfld.long 0x00 31. "COMP1_LOCK,COMP1_CSR register lock bit" "0,1"
|
|
rbitfld.long 0x00 30. "COMP1_VALUE,Comparator 1 output status bit" "0,1"
|
|
bitfld.long 0x00 23. "COMP1_SCALEN,Voltage scaler enable bit" "0,1"
|
|
bitfld.long 0x00 22. "COMP1_BRGEN,Scaler bridge enable" "0,1"
|
|
bitfld.long 0x00 18.--20. "COMP1_BLANKING,Comparator 1 blanking source selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. "COMP1_HYST,Comparator 1 hysteresis selection bits" "0,1,2,3"
|
|
bitfld.long 0x00 15. "COMP1_POLARITY,Comparator 1 polarity selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "COMP1_INPSEL,Comparator1 input plus selection bit" "0,1"
|
|
bitfld.long 0x00 4.--6. "COMP1_INMSEL,Comparator 1 Input Minus connection configuration bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--3. "COMP1_PWRMODE,Power Mode of the comparator 1" "0,1,2,3"
|
|
bitfld.long 0x00 0. "COMP1_EN,Comparator 1 enable bit" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "COMP2_CSR,Comparator 2 control and status register"
|
|
bitfld.long 0x00 31. "COMP2_LOCK,COMP2_CSR register lock bit" "0,1"
|
|
rbitfld.long 0x00 30. "COMP2_VALUE,Comparator 2 output status bit" "0,1"
|
|
bitfld.long 0x00 23. "COMP2_SCALEN,Voltage scaler enable bit" "0,1"
|
|
bitfld.long 0x00 22. "COMP2_BRGEN,Scaler bridge enable" "0,1"
|
|
bitfld.long 0x00 18.--20. "COMP2_BLANKING,Comparator 2 blanking source selection bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. "COMP2_HYST,Comparator 2 hysteresis selection bits" "0,1,2,3"
|
|
bitfld.long 0x00 15. "COMP2_POLARITY,Comparator 2 polarity selection bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "COMP2_WINMODE,Windows mode selection bit" "0,1"
|
|
bitfld.long 0x00 7. "COMP2_INPSEL,Comparator 2 Input Plus connection configuration bit" "0,1"
|
|
bitfld.long 0x00 4.--6. "COMP2_INMSEL,Comparator 2 Input Minus connection configuration bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--3. "COMP2_PWRMODE,Power Mode of the comparator 2" "0,1,2,3"
|
|
bitfld.long 0x00 0. "COMP2_EN,Comparator 2 enable bit" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "CRC (Cyclic redundancy check calculation unit)"
|
|
tree "CRC"
|
|
base ad:0x40023000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Data register"
|
|
hexmask.long 0x00 0.--31. 1. "DR,Data register bits"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IDR,Independent data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IDR,General-purpose 8-bit data register bits"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,Control register"
|
|
bitfld.long 0x00 7. "REV_OUT,Reverse output data" "0,1"
|
|
bitfld.long 0x00 5.--6. "REV_IN,Reverse input data" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. "POLYSIZE,Polynomial size" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INIT,Initial CRC value"
|
|
hexmask.long 0x00 0.--31. 1. "CRC_INIT,Programmable initial CRC value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "POL,polynomial"
|
|
hexmask.long 0x00 0.--31. 1. "Polynomialcoefficients,Programmable polynomial"
|
|
tree.end
|
|
tree "SEC_CRC"
|
|
base ad:0x50023000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Data register"
|
|
hexmask.long 0x00 0.--31. 1. "DR,Data register bits"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IDR,Independent data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IDR,General-purpose 8-bit data register bits"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,Control register"
|
|
bitfld.long 0x00 7. "REV_OUT,Reverse output data" "0,1"
|
|
bitfld.long 0x00 5.--6. "REV_IN,Reverse input data" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. "POLYSIZE,Polynomial size" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INIT,Initial CRC value"
|
|
hexmask.long 0x00 0.--31. 1. "CRC_INIT,Programmable initial CRC value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "POL,polynomial"
|
|
hexmask.long 0x00 0.--31. 1. "Polynomialcoefficients,Programmable polynomial"
|
|
tree.end
|
|
tree.end
|
|
tree "CRS (Clock recovery system)"
|
|
tree "CRS"
|
|
base ad:0x40006000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,control register"
|
|
hexmask.long.byte 0x00 8.--14. 1. "TRIM,HSI48 oscillator smooth trimming"
|
|
bitfld.long 0x00 7. "SWSYNC,Generate software SYNC event" "0,1"
|
|
bitfld.long 0x00 6. "AUTOTRIMEN,Automatic trimming enable" "0,1"
|
|
bitfld.long 0x00 5. "CEN,Frequency error counter enable" "0,1"
|
|
bitfld.long 0x00 3. "ESYNCIE,Expected SYNC interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "ERRIE,Synchronization or trimming error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "SYNCWARNIE,SYNC warning interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "SYNCOKIE,SYNC event OK interrupt enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFGR,configuration register"
|
|
bitfld.long 0x00 31. "SYNCPOL,SYNC polarity selection" "0,1"
|
|
bitfld.long 0x00 28.--29. "SYNCSRC,SYNC signal source selection" "0,1,2,3"
|
|
bitfld.long 0x00 24.--26. "SYNCDIV,SYNC divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FELIM,Frequency error limit"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELOAD,Counter reload value"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ISR,interrupt and status register"
|
|
hexmask.long.word 0x00 16.--31. 1. "FECAP,Frequency error capture"
|
|
bitfld.long 0x00 15. "FEDIR,Frequency error direction" "0,1"
|
|
bitfld.long 0x00 10. "TRIMOVF,Trimming overflow or underflow" "0,1"
|
|
bitfld.long 0x00 9. "SYNCMISS,SYNC missed" "0,1"
|
|
bitfld.long 0x00 8. "SYNCERR,SYNC error" "0,1"
|
|
bitfld.long 0x00 3. "ESYNCF,Expected SYNC flag" "0,1"
|
|
bitfld.long 0x00 2. "ERRF,Error flag" "0,1"
|
|
bitfld.long 0x00 1. "SYNCWARNF,SYNC warning flag" "0,1"
|
|
bitfld.long 0x00 0. "SYNCOKF,SYNC event OK flag" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ICR,interrupt flag clear register"
|
|
bitfld.long 0x00 3. "ESYNCC,Expected SYNC clear flag" "0,1"
|
|
bitfld.long 0x00 2. "ERRC,Error clear flag" "0,1"
|
|
bitfld.long 0x00 1. "SYNCWARNC,SYNC warning clear flag" "0,1"
|
|
bitfld.long 0x00 0. "SYNCOKC,SYNC event OK clear flag" "0,1"
|
|
tree.end
|
|
tree "SEC_CRS"
|
|
base ad:0x50006000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,control register"
|
|
hexmask.long.byte 0x00 8.--14. 1. "TRIM,HSI48 oscillator smooth trimming"
|
|
bitfld.long 0x00 7. "SWSYNC,Generate software SYNC event" "0,1"
|
|
bitfld.long 0x00 6. "AUTOTRIMEN,Automatic trimming enable" "0,1"
|
|
bitfld.long 0x00 5. "CEN,Frequency error counter enable" "0,1"
|
|
bitfld.long 0x00 3. "ESYNCIE,Expected SYNC interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "ERRIE,Synchronization or trimming error interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "SYNCWARNIE,SYNC warning interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "SYNCOKIE,SYNC event OK interrupt enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFGR,configuration register"
|
|
bitfld.long 0x00 31. "SYNCPOL,SYNC polarity selection" "0,1"
|
|
bitfld.long 0x00 28.--29. "SYNCSRC,SYNC signal source selection" "0,1,2,3"
|
|
bitfld.long 0x00 24.--26. "SYNCDIV,SYNC divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FELIM,Frequency error limit"
|
|
hexmask.long.word 0x00 0.--15. 1. "RELOAD,Counter reload value"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ISR,interrupt and status register"
|
|
hexmask.long.word 0x00 16.--31. 1. "FECAP,Frequency error capture"
|
|
bitfld.long 0x00 15. "FEDIR,Frequency error direction" "0,1"
|
|
bitfld.long 0x00 10. "TRIMOVF,Trimming overflow or underflow" "0,1"
|
|
bitfld.long 0x00 9. "SYNCMISS,SYNC missed" "0,1"
|
|
bitfld.long 0x00 8. "SYNCERR,SYNC error" "0,1"
|
|
bitfld.long 0x00 3. "ESYNCF,Expected SYNC flag" "0,1"
|
|
bitfld.long 0x00 2. "ERRF,Error flag" "0,1"
|
|
bitfld.long 0x00 1. "SYNCWARNF,SYNC warning flag" "0,1"
|
|
bitfld.long 0x00 0. "SYNCOKF,SYNC event OK flag" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ICR,interrupt flag clear register"
|
|
bitfld.long 0x00 3. "ESYNCC,Expected SYNC clear flag" "0,1"
|
|
bitfld.long 0x00 2. "ERRC,Error clear flag" "0,1"
|
|
bitfld.long 0x00 1. "SYNCWARNC,SYNC warning clear flag" "0,1"
|
|
bitfld.long 0x00 0. "SYNCOKC,SYNC event OK clear flag" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "DAC"
|
|
tree "DAC"
|
|
base ad:0x40007400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC control register"
|
|
bitfld.long 0x00 30. "CEN2,DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled).." "0,1"
|
|
bitfld.long 0x00 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software" "0,1"
|
|
bitfld.long 0x00 28. "DMAEN2,DAC channel2 DMA enable This bit is set and cleared by software" "0,1"
|
|
bitfld.long 0x00 24.--27. "MAMP2,DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. "WAVE2,DAC channel2 noise/triangle wave generation enable These bits are set/reset by software" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TSEL23,TSEL23" "0,1"
|
|
bitfld.long 0x00 20. "TSEL22,TSEL22" "0,1"
|
|
bitfld.long 0x00 19. "TSEL21,TSEL21" "0,1"
|
|
bitfld.long 0x00 18. "TSEL20,TSEL20" "0,1"
|
|
bitfld.long 0x00 17. "TEN2,DAC channel2 trigger enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "EN2,DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2" "0,1"
|
|
bitfld.long 0x00 15. "HFSEL,HFSEL" "0,1"
|
|
bitfld.long 0x00 14. "CEN1,DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled).." "0,1"
|
|
bitfld.long 0x00 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software" "0,1"
|
|
bitfld.long 0x00 12. "DMAEN1,DAC channel1 DMA enable This bit is set and cleared by software" "0,1"
|
|
bitfld.long 0x00 8.--11. "MAMP1,DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "WAVE1,DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software" "0,1,2,3"
|
|
bitfld.long 0x00 5. "TSEL13,TSEL13" "0,1"
|
|
bitfld.long 0x00 4. "TSEL12,TSEL12" "0,1"
|
|
bitfld.long 0x00 3. "TSEL11,TSEL11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TSEL10,TSEL10" "0,1"
|
|
bitfld.long 0x00 1. "TEN1,DAC channel1 trigger enable" "0,1"
|
|
bitfld.long 0x00 0. "EN1,DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC_SWTRGR,DAC software trigger register"
|
|
bitfld.long 0x00 1. "SWTRIG2,DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode" "0,1"
|
|
bitfld.long 0x00 0. "SWTRIG1,DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DAC_DHR12R1,DAC channel1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DAC_DHR12L1,DAC channel1 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x00 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DAC_DHR8R1,DAC channel1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DAC_DHR12R2,DAC channel2 12-bit right aligned data holding register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DAC_DHR12L2,DAC channel2 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x00 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DAC_DHR8R2,DAC channel2 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DAC_DHR12RD,Dual DAC 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2"
|
|
hexmask.long.word 0x00 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DAC_DHR12LD,DUAL DAC 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x00 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2"
|
|
hexmask.long.word 0x00 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DAC_DHR8RD,DUAL DAC 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DAC_DOR1,DAC channel1 data output register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are read-only they contain data output for DAC channel1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DAC_DOR2,DAC channel2 data output register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are read-only they contain data output for DAC channel2"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC_SR,DAC status register"
|
|
rbitfld.long 0x00 31. "BWST2,DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2 It is cleared by hardware when the write operation of DAC_SHSR2 is.." "0,1"
|
|
rbitfld.long 0x00 30. "CAL_FLAG2,DAC Channel 2 calibration offset status This bit is set and cleared by hardware" "0,1"
|
|
bitfld.long 0x00 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)" "0,1"
|
|
rbitfld.long 0x00 15. "BWST1,DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1 It is cleared by hardware when the write operation of DAC_SHSR1 is.." "0,1"
|
|
rbitfld.long 0x00 14. "CAL_FLAG1,DAC Channel 1 calibration offset status This bit is set and cleared by hardware" "0,1"
|
|
bitfld.long 0x00 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DAC_CCR,DAC calibration control register"
|
|
bitfld.long 0x00 16.--20. "OTRIM2,DAC Channel 2 offset trimming value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "OTRIM1,DAC Channel 1 offset trimming value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "DAC_MCR,DAC mode control register"
|
|
bitfld.long 0x00 16.--18. "MODE2,DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "MODE1,DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register)" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DAC_SHSR1,DAC Sample and Hold sample time register 1"
|
|
hexmask.long.word 0x00 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DAC_SHSR2,DAC Sample and Hold sample time register 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DAC_SHHR,DAC Sample and Hold hold time register"
|
|
hexmask.long.word 0x00 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in sample & hold mode)"
|
|
hexmask.long.word 0x00 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DAC_SHRR,DAC Sample and Hold refresh time register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI"
|
|
tree.end
|
|
tree "SEC_DAC"
|
|
base ad:0x50007400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC control register"
|
|
bitfld.long 0x00 30. "CEN2,DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled).." "0,1"
|
|
bitfld.long 0x00 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software" "0,1"
|
|
bitfld.long 0x00 28. "DMAEN2,DAC channel2 DMA enable This bit is set and cleared by software" "0,1"
|
|
bitfld.long 0x00 24.--27. "MAMP2,DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. "WAVE2,DAC channel2 noise/triangle wave generation enable These bits are set/reset by software" "0,1,2,3"
|
|
bitfld.long 0x00 21. "TSEL23,TSEL23" "0,1"
|
|
bitfld.long 0x00 20. "TSEL22,TSEL22" "0,1"
|
|
bitfld.long 0x00 19. "TSEL21,TSEL21" "0,1"
|
|
bitfld.long 0x00 18. "TSEL20,TSEL20" "0,1"
|
|
bitfld.long 0x00 17. "TEN2,DAC channel2 trigger enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "EN2,DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2" "0,1"
|
|
bitfld.long 0x00 15. "HFSEL,HFSEL" "0,1"
|
|
bitfld.long 0x00 14. "CEN1,DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled).." "0,1"
|
|
bitfld.long 0x00 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software" "0,1"
|
|
bitfld.long 0x00 12. "DMAEN1,DAC channel1 DMA enable This bit is set and cleared by software" "0,1"
|
|
bitfld.long 0x00 8.--11. "MAMP1,DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "WAVE1,DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software" "0,1,2,3"
|
|
bitfld.long 0x00 5. "TSEL13,TSEL13" "0,1"
|
|
bitfld.long 0x00 4. "TSEL12,TSEL12" "0,1"
|
|
bitfld.long 0x00 3. "TSEL11,TSEL11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TSEL10,TSEL10" "0,1"
|
|
bitfld.long 0x00 1. "TEN1,DAC channel1 trigger enable" "0,1"
|
|
bitfld.long 0x00 0. "EN1,DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC_SWTRGR,DAC software trigger register"
|
|
bitfld.long 0x00 1. "SWTRIG2,DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode" "0,1"
|
|
bitfld.long 0x00 0. "SWTRIG1,DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DAC_DHR12R1,DAC channel1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DAC_DHR12L1,DAC channel1 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x00 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DAC_DHR8R1,DAC channel1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DAC_DHR12R2,DAC channel2 12-bit right aligned data holding register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DAC_DHR12L2,DAC channel2 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x00 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DAC_DHR8R2,DAC channel2 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DAC_DHR12RD,Dual DAC 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x00 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2"
|
|
hexmask.long.word 0x00 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DAC_DHR12LD,DUAL DAC 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x00 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2"
|
|
hexmask.long.word 0x00 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DAC_DHR8RD,DUAL DAC 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DAC_DOR1,DAC channel1 data output register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are read-only they contain data output for DAC channel1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DAC_DOR2,DAC channel2 data output register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are read-only they contain data output for DAC channel2"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC_SR,DAC status register"
|
|
rbitfld.long 0x00 31. "BWST2,DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2 It is cleared by hardware when the write operation of DAC_SHSR2 is.." "0,1"
|
|
rbitfld.long 0x00 30. "CAL_FLAG2,DAC Channel 2 calibration offset status This bit is set and cleared by hardware" "0,1"
|
|
bitfld.long 0x00 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)" "0,1"
|
|
rbitfld.long 0x00 15. "BWST1,DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1 It is cleared by hardware when the write operation of DAC_SHSR1 is.." "0,1"
|
|
rbitfld.long 0x00 14. "CAL_FLAG1,DAC Channel 1 calibration offset status This bit is set and cleared by hardware" "0,1"
|
|
bitfld.long 0x00 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DAC_CCR,DAC calibration control register"
|
|
bitfld.long 0x00 16.--20. "OTRIM2,DAC Channel 2 offset trimming value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "OTRIM1,DAC Channel 1 offset trimming value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "DAC_MCR,DAC mode control register"
|
|
bitfld.long 0x00 16.--18. "MODE2,DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "MODE1,DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register)" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DAC_SHSR1,DAC Sample and Hold sample time register 1"
|
|
hexmask.long.word 0x00 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DAC_SHSR2,DAC Sample and Hold sample time register 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DAC_SHHR,DAC Sample and Hold hold time register"
|
|
hexmask.long.word 0x00 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in sample & hold mode)"
|
|
hexmask.long.word 0x00 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DAC_SHRR,DAC Sample and Hold refresh time register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI"
|
|
tree.end
|
|
tree.end
|
|
tree "DBGMCU (MCU debug component)"
|
|
base ad:0xE0044000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IDCODE,DBGMCU_IDCODE"
|
|
hexmask.long.word 0x00 16.--31. 1. "REV_ID,Revision identifie"
|
|
hexmask.long.word 0x00 0.--11. 1. "DEV_ID,Device identifier"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR,Debug MCU configuration register"
|
|
bitfld.long 0x00 6.--7. "TRACE_MODE,Trace pin assignment control" "0,1,2,3"
|
|
bitfld.long 0x00 5. "TRACE_EN,trace port and clock enable" "0,1"
|
|
bitfld.long 0x00 4. "TRACE_IOEN,Trace pin assignment control" "0,1"
|
|
bitfld.long 0x00 2. "DBG_STANDBY,Debug Standby mode" "0,1"
|
|
bitfld.long 0x00 1. "DBG_STOP,Debug Stop mode" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "APB1LFZR,Debug MCU APB1 freeze register1"
|
|
bitfld.long 0x00 31. "DBG_LPTIM1_STOP,LPTIM1 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x00 23. "DBG_I2C3_STOP,I2C3 SMBUS timeout counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x00 22. "DBG_I2C2_STOP,I2C2 SMBUS timeout counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x00 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x00 12. "DBG_IWDG_STOP,Independent watchdog counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x00 11. "DBG_WWDG_STOP,Window watchdog counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x00 10. "DBG_RTC_STOP,RTC counter stopped when core is halted" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DBG_TIM7_STOP,TIM7 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x00 4. "DBG_TIM6_STOP,TIM6 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x00 3. "DBG_TIM5_STOP,TIM5 stop in debug" "0,1"
|
|
bitfld.long 0x00 2. "DBG_TIM4_STOP,TIM4 stop in debug" "0,1"
|
|
bitfld.long 0x00 1. "DBG_TIM3_STOP,TIM3 stop in debug" "0,1"
|
|
bitfld.long 0x00 0. "DBG_TIM2_STOP,TIM2 counter stopped when core is halted" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "APB1HFZR,Debug MCU APB1 freeze register 2"
|
|
bitfld.long 0x00 6. "DBG_LPTIM3_STOP,LPTIM3 stop in debug" "0,1"
|
|
bitfld.long 0x00 5. "DBG_LPTIM2_STOP,LPTIM2 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x00 1. "DBG_I2C4_STOP,I2C4 stop in debug" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "APB2FZR,Debug MCU APB2 freeze register"
|
|
bitfld.long 0x00 18. "DBG_TIM17_STOP,DBG_TIM17_STOP" "0,1"
|
|
bitfld.long 0x00 17. "DBG_TIM16_STOP,TIM16 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x00 16. "DBG_TIM15_STOP,TIM15 counter stopped when core is halted" "0,1"
|
|
bitfld.long 0x00 13. "DBG_TIM8_STOP,TIM8 stop in debug" "0,1"
|
|
bitfld.long 0x00 11. "DBG_TIM1_STOP,TIM1 counter stopped when core is halted" "0,1"
|
|
tree.end
|
|
tree "DCB (Debug Control Block)"
|
|
base ad:0xE000EE08
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x00 16. "CDS,Current domain Secure" "0,1"
|
|
tree.end
|
|
tree "DFSDM (Digital filter for sigma delta modulators)"
|
|
tree "DFSDM1"
|
|
base ad:0x40016000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CH0CFGR1,channel configuration y register"
|
|
bitfld.long 0x00 31. "DFSDMEN,DFSDMEN" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,CKOUTSRC" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,CKOUTDIV"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CH0CFGR2,channel configuration y register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CH0AWSCDR,analog watchdog and short-circuit detector register"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CH0WDATR,channel watchdog filter data register"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0DATINR,channel data input register"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CH1CFGR1,CHCFG1R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CH1CFGR2,CHCFG1R2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CH1AWSCDR,AWSCD1R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CH1WDATR,CHWDAT1R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CH1DATINR,CHDATIN1R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH2CFGR1,CHCFG2R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CH2CFGR2,CHCFG2R2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CH2AWSCDR,AWSCD2R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CH2WDATR,CHWDAT2R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH2DATINR,CHDATIN2R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CH3CFGR1,CHCFG3R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CH3CFGR2,CHCFG3R2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CH3AWSCDR,AWSCD3R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CH3WDATR,CHWDAT3R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CH3DATINR,CHDATIN3R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH4CFGR1,CHCFG4R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CH4CFGR2,CHCFG4R2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CH4AWSCDR,AWSCD4R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CH4WDATR,CHWDAT4R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH4DATINR,CHDATIN4R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CH5CFGR1,CHCFG5R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CH5CFGR2,CHCFG5R2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CH5AWSCDR,AWSCD5R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CH5WDATR,CHWDAT5R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CH5DATINR,CHDATIN5R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CH6CFGR1,CHCFG6R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CH6CFGR2,CH6CFGR2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CH6AWSCDR,AWSCD6R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CH6WDATR,CHWDAT6R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CH6DATINR,CHDATIN6R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CH7CFGR1,CHCFG7R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CH7CFGR2,CHCFG7R2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CH7AWSCDR,AWSCD7R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CH7WDATR,CHWDAT7R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CH7DATINR,CHDATIN7R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FLT0CR1,control register 1"
|
|
bitfld.long 0x00 30. "AWFSEL,Analog watchdog fast mode select" "0,1"
|
|
bitfld.long 0x00 29. "FAST,Fast conversion mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
|
|
bitfld.long 0x00 19. "RSYNC,Launch regular conversion synchronously with DFSDM0" "0,1"
|
|
bitfld.long 0x00 18. "RCONT,Continuous mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 17. "RSWSTART,Software start of a conversion on the regular channel" "0,1"
|
|
bitfld.long 0x00 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "JEXTSEL,Trigger signal selection for launching injected conversions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "JSCAN,Scanning conversion mode for injected conversions" "0,1"
|
|
bitfld.long 0x00 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "0,1"
|
|
bitfld.long 0x00 1. "JSWSTART,Start a conversion of the injected group of channels" "0,1"
|
|
bitfld.long 0x00 0. "DFEN,DFSDM enable" "0,1"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "FLT0CR2,control register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AWDCH,Analog watchdog channel selection"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXCH,Extremes detector channel selection"
|
|
bitfld.long 0x00 6. "CKABIE,Clock absence interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "SCDIE,Short-circuit detector interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "AWDIE,Analog watchdog interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "ROVRIE,Regular data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "JOVRIE,Injected data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "REOCIE,Regular end of conversion interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "JEOCIE,Injected end of conversion interrupt enable" "0,1"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "FLT0ISR,interrupt and status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCDF,short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKABF,Clock absence flag"
|
|
bitfld.long 0x00 14. "RCIP,Regular conversion in progress status" "0,1"
|
|
bitfld.long 0x00 13. "JCIP,Injected conversion in progress status" "0,1"
|
|
bitfld.long 0x00 4. "AWDF,Analog watchdog" "0,1"
|
|
bitfld.long 0x00 3. "ROVRF,Regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "JOVRF,Injected conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 1. "REOCF,End of regular conversion flag" "0,1"
|
|
bitfld.long 0x00 0. "JEOCF,End of injected conversion flag" "0,1"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "FLT0ICR,interrupt flag clear register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CLRCKABF,Clear the clock absence flag"
|
|
bitfld.long 0x00 3. "CLRROVRF,Clear the regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0,1"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "FLT0JCHGR,injected channel group selection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "JCHG,Injected channel group selection"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FLT0FCR,filter control register"
|
|
bitfld.long 0x00 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "FLT0JDATAR,data register for injected group"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "JDATA,Injected group conversion data"
|
|
bitfld.long 0x00 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "FLT0RDATAR,data register for the regular channel"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RDATA,Regular channel conversion data"
|
|
bitfld.long 0x00 4. "RPEND,Regular channel pending data" "0,1"
|
|
bitfld.long 0x00 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "FLT0AWHTR,analog watchdog high threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWHT,Analog watchdog high threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWH,Break signal assignment to analog watchdog high threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "FLT0AWLTR,analog watchdog low threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWLT,Analog watchdog low threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWL,Break signal assignment to analog watchdog low threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "FLT0AWSR,analog watchdog status register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "AWHTF,Analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AWLTF,Analog watchdog low threshold flag"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "FLT0AWCFR,analog watchdog clear flag register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "FLT0EXMAX,Extremes detector maximum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMAX,Extremes detector maximum value"
|
|
bitfld.long 0x00 0.--2. "EXMAXCH,Extremes detector maximum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "FLT0EXMIN,Extremes detector minimum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMIN,EXMIN"
|
|
bitfld.long 0x00 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "FLT0CNVTIMR,conversion timer register"
|
|
hexmask.long 0x00 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "FLT1CR1,control register 1"
|
|
bitfld.long 0x00 30. "AWFSEL,Analog watchdog fast mode select" "0,1"
|
|
bitfld.long 0x00 29. "FAST,Fast conversion mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
|
|
bitfld.long 0x00 19. "RSYNC,Launch regular conversion synchronously with DFSDM0" "0,1"
|
|
bitfld.long 0x00 18. "RCONT,Continuous mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 17. "RSWSTART,Software start of a conversion on the regular channel" "0,1"
|
|
bitfld.long 0x00 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "JEXTSEL,Trigger signal selection for launching injected conversions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "JSCAN,Scanning conversion mode for injected conversions" "0,1"
|
|
bitfld.long 0x00 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "0,1"
|
|
bitfld.long 0x00 1. "JSWSTART,Start a conversion of the injected group of channels" "0,1"
|
|
bitfld.long 0x00 0. "DFEN,DFSDM enable" "0,1"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "FLT1CR2,control register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AWDCH,Analog watchdog channel selection"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXCH,Extremes detector channel selection"
|
|
bitfld.long 0x00 6. "CKABIE,Clock absence interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "SCDIE,Short-circuit detector interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "AWDIE,Analog watchdog interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "ROVRIE,Regular data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "JOVRIE,Injected data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "REOCIE,Regular end of conversion interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "JEOCIE,Injected end of conversion interrupt enable" "0,1"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "FLT1ISR,interrupt and status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCDF,short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKABF,Clock absence flag"
|
|
bitfld.long 0x00 14. "RCIP,Regular conversion in progress status" "0,1"
|
|
bitfld.long 0x00 13. "JCIP,Injected conversion in progress status" "0,1"
|
|
bitfld.long 0x00 4. "AWDF,Analog watchdog" "0,1"
|
|
bitfld.long 0x00 3. "ROVRF,Regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "JOVRF,Injected conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 1. "REOCF,End of regular conversion flag" "0,1"
|
|
bitfld.long 0x00 0. "JEOCF,End of injected conversion flag" "0,1"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "FLT1ICR,interrupt flag clear register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CLRCKABF,Clear the clock absence flag"
|
|
bitfld.long 0x00 3. "CLRROVRF,Clear the regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0,1"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "FLT1JCHGR,injected channel group selection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "JCHG,Injected channel group selection"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "FLT1FCR,filter control register"
|
|
bitfld.long 0x00 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "FLT1JDATAR,data register for injected group"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "JDATA,Injected group conversion data"
|
|
bitfld.long 0x00 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "FLT1RDATAR,data register for the regular channel"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RDATA,Regular channel conversion data"
|
|
bitfld.long 0x00 4. "RPEND,Regular channel pending data" "0,1"
|
|
bitfld.long 0x00 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "FLT1AWHTR,analog watchdog high threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWHT,Analog watchdog high threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWH,Break signal assignment to analog watchdog high threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "FLT1AWLTR,analog watchdog low threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWLT,Analog watchdog low threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWL,Break signal assignment to analog watchdog low threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "FLT1AWSR,analog watchdog status register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "AWHTF,Analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AWLTF,Analog watchdog low threshold flag"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "FLT1AWCFR,analog watchdog clear flag register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "FLT1EXMAX,Extremes detector maximum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMAX,Extremes detector maximum value"
|
|
bitfld.long 0x00 0.--2. "EXMAXCH,Extremes detector maximum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "FLT1EXMIN,Extremes detector minimum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMIN,EXMIN"
|
|
bitfld.long 0x00 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "FLT1CNVTIMR,conversion timer register"
|
|
hexmask.long 0x00 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "FLT2CR1,control register 1"
|
|
bitfld.long 0x00 30. "AWFSEL,Analog watchdog fast mode select" "0,1"
|
|
bitfld.long 0x00 29. "FAST,Fast conversion mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
|
|
bitfld.long 0x00 19. "RSYNC,Launch regular conversion synchronously with DFSDM0" "0,1"
|
|
bitfld.long 0x00 18. "RCONT,Continuous mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 17. "RSWSTART,Software start of a conversion on the regular channel" "0,1"
|
|
bitfld.long 0x00 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "JEXTSEL,Trigger signal selection for launching injected conversions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "JSCAN,Scanning conversion mode for injected conversions" "0,1"
|
|
bitfld.long 0x00 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "0,1"
|
|
bitfld.long 0x00 1. "JSWSTART,Start a conversion of the injected group of channels" "0,1"
|
|
bitfld.long 0x00 0. "DFEN,DFSDM enable" "0,1"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "FLT2CR2,control register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AWDCH,Analog watchdog channel selection"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXCH,Extremes detector channel selection"
|
|
bitfld.long 0x00 6. "CKABIE,Clock absence interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "SCDIE,Short-circuit detector interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "AWDIE,Analog watchdog interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "ROVRIE,Regular data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "JOVRIE,Injected data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "REOCIE,Regular end of conversion interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "JEOCIE,Injected end of conversion interrupt enable" "0,1"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "FLT2ISR,interrupt and status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCDF,short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKABF,Clock absence flag"
|
|
bitfld.long 0x00 14. "RCIP,Regular conversion in progress status" "0,1"
|
|
bitfld.long 0x00 13. "JCIP,Injected conversion in progress status" "0,1"
|
|
bitfld.long 0x00 4. "AWDF,Analog watchdog" "0,1"
|
|
bitfld.long 0x00 3. "ROVRF,Regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "JOVRF,Injected conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 1. "REOCF,End of regular conversion flag" "0,1"
|
|
bitfld.long 0x00 0. "JEOCF,End of injected conversion flag" "0,1"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "FLT2ICR,interrupt flag clear register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CLRCKABF,Clear the clock absence flag"
|
|
bitfld.long 0x00 3. "CLRROVRF,Clear the regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0,1"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "FLT2JCHGR,injected channel group selection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "JCHG,Injected channel group selection"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "FLT2FCR,filter control register"
|
|
bitfld.long 0x00 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)"
|
|
rgroup.long 0x218++0x03
|
|
line.long 0x00 "FLT2JDATAR,data register for injected group"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "JDATA,Injected group conversion data"
|
|
bitfld.long 0x00 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "FLT2RDATAR,data register for the regular channel"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RDATA,Regular channel conversion data"
|
|
bitfld.long 0x00 4. "RPEND,Regular channel pending data" "0,1"
|
|
bitfld.long 0x00 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "FLT2AWHTR,analog watchdog high threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWHT,Analog watchdog high threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWH,Break signal assignment to analog watchdog high threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "FLT2AWLTR,analog watchdog low threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWLT,Analog watchdog low threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWL,Break signal assignment to analog watchdog low threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x228++0x03
|
|
line.long 0x00 "FLT2AWSR,analog watchdog status register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "AWHTF,Analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AWLTF,Analog watchdog low threshold flag"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "FLT2AWCFR,analog watchdog clear flag register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag"
|
|
rgroup.long 0x230++0x03
|
|
line.long 0x00 "FLT2EXMAX,Extremes detector maximum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMAX,Extremes detector maximum value"
|
|
bitfld.long 0x00 0.--2. "EXMAXCH,Extremes detector maximum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x234++0x03
|
|
line.long 0x00 "FLT2EXMIN,Extremes detector minimum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMIN,EXMIN"
|
|
bitfld.long 0x00 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x238++0x03
|
|
line.long 0x00 "FLT2CNVTIMR,conversion timer register"
|
|
hexmask.long 0x00 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "FLT3CR1,control register 1"
|
|
bitfld.long 0x00 30. "AWFSEL,Analog watchdog fast mode select" "0,1"
|
|
bitfld.long 0x00 29. "FAST,Fast conversion mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
|
|
bitfld.long 0x00 19. "RSYNC,Launch regular conversion synchronously with DFSDM0" "0,1"
|
|
bitfld.long 0x00 18. "RCONT,Continuous mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 17. "RSWSTART,Software start of a conversion on the regular channel" "0,1"
|
|
bitfld.long 0x00 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "JEXTSEL,Trigger signal selection for launching injected conversions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "JSCAN,Scanning conversion mode for injected conversions" "0,1"
|
|
bitfld.long 0x00 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "0,1"
|
|
bitfld.long 0x00 1. "JSWSTART,Start a conversion of the injected group of channels" "0,1"
|
|
bitfld.long 0x00 0. "DFEN,DFSDM enable" "0,1"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "FLT3CR2,control register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AWDCH,Analog watchdog channel selection"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXCH,Extremes detector channel selection"
|
|
bitfld.long 0x00 6. "CKABIE,Clock absence interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "SCDIE,Short-circuit detector interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "AWDIE,Analog watchdog interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "ROVRIE,Regular data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "JOVRIE,Injected data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "REOCIE,Regular end of conversion interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "JEOCIE,Injected end of conversion interrupt enable" "0,1"
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "FLT3ISR,interrupt and status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCDF,short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKABF,Clock absence flag"
|
|
bitfld.long 0x00 14. "RCIP,Regular conversion in progress status" "0,1"
|
|
bitfld.long 0x00 13. "JCIP,Injected conversion in progress status" "0,1"
|
|
bitfld.long 0x00 4. "AWDF,Analog watchdog" "0,1"
|
|
bitfld.long 0x00 3. "ROVRF,Regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "JOVRF,Injected conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 1. "REOCF,End of regular conversion flag" "0,1"
|
|
bitfld.long 0x00 0. "JEOCF,End of injected conversion flag" "0,1"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "FLT3ICR,interrupt flag clear register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CLRCKABF,Clear the clock absence flag"
|
|
bitfld.long 0x00 3. "CLRROVRF,Clear the regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0,1"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "FLT3JCHGR,injected channel group selection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "JCHG,Injected channel group selection"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "FLT3FCR,filter control register"
|
|
bitfld.long 0x00 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)"
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "FLT3JDATAR,data register for injected group"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "JDATA,Injected group conversion data"
|
|
bitfld.long 0x00 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x29C++0x03
|
|
line.long 0x00 "FLT3RDATAR,data register for the regular channel"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RDATA,Regular channel conversion data"
|
|
bitfld.long 0x00 4. "RPEND,Regular channel pending data" "0,1"
|
|
bitfld.long 0x00 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "FLT3AWHTR,analog watchdog high threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWHT,Analog watchdog high threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWH,Break signal assignment to analog watchdog high threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "FLT3AWLTR,analog watchdog low threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWLT,Analog watchdog low threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWL,Break signal assignment to analog watchdog low threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x2A8++0x03
|
|
line.long 0x00 "FLT3AWSR,analog watchdog status register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "AWHTF,Analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AWLTF,Analog watchdog low threshold flag"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "FLT3AWCFR,analog watchdog clear flag register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag"
|
|
rgroup.long 0x2B0++0x03
|
|
line.long 0x00 "FLT3EXMAX,Extremes detector maximum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMAX,Extremes detector maximum value"
|
|
bitfld.long 0x00 0.--2. "EXMAXCH,Extremes detector maximum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2B4++0x03
|
|
line.long 0x00 "FLT3EXMIN,Extremes detector minimum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMIN,EXMIN"
|
|
bitfld.long 0x00 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2B8++0x03
|
|
line.long 0x00 "FLT3CNVTIMR,conversion timer register"
|
|
hexmask.long 0x00 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH0DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,Pulses to skip for input data skipping function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH1DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,PLSSKP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CH2DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,PLSSKP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CH3DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,PLSSKP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CH4DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,PLSSKP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CH5DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,read-only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CH6DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,PLSSKP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "CH7DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,PLSSKP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree "SEC_DFSDM1"
|
|
base ad:0x50016000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CH0CFGR1,channel configuration y register"
|
|
bitfld.long 0x00 31. "DFSDMEN,DFSDMEN" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,CKOUTSRC" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,CKOUTDIV"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CH0CFGR2,channel configuration y register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CH0AWSCDR,analog watchdog and short-circuit detector register"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CH0WDATR,channel watchdog filter data register"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0DATINR,channel data input register"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CH1CFGR1,CHCFG1R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CH1CFGR2,CHCFG1R2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CH1AWSCDR,AWSCD1R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CH1WDATR,CHWDAT1R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CH1DATINR,CHDATIN1R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH2CFGR1,CHCFG2R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CH2CFGR2,CHCFG2R2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CH2AWSCDR,AWSCD2R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CH2WDATR,CHWDAT2R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH2DATINR,CHDATIN2R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CH3CFGR1,CHCFG3R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CH3CFGR2,CHCFG3R2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CH3AWSCDR,AWSCD3R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CH3WDATR,CHWDAT3R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CH3DATINR,CHDATIN3R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH4CFGR1,CHCFG4R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CH4CFGR2,CHCFG4R2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CH4AWSCDR,AWSCD4R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CH4WDATR,CHWDAT4R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH4DATINR,CHDATIN4R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CH5CFGR1,CHCFG5R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CH5CFGR2,CHCFG5R2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CH5AWSCDR,AWSCD5R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CH5WDATR,CHWDAT5R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CH5DATINR,CHDATIN5R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CH6CFGR1,CHCFG6R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CH6CFGR2,CH6CFGR2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CH6AWSCDR,AWSCD6R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CH6WDATR,CHWDAT6R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CH6DATINR,CHDATIN6R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CH7CFGR1,CHCFG7R1"
|
|
bitfld.long 0x00 31. "DFSDMEN,Global enable for DFSDM interface" "0,1"
|
|
bitfld.long 0x00 30. "CKOUTSRC,Output serial clock source selection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKOUTDIV,Output serial clock divider"
|
|
bitfld.long 0x00 14.--15. "DATPACK,DATPACK" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DATMPX,DATMPX" "0,1,2,3"
|
|
bitfld.long 0x00 8. "CHINSEL,CHINSEL" "0,1"
|
|
bitfld.long 0x00 7. "CHEN,CHEN" "0,1"
|
|
bitfld.long 0x00 6. "CKABEN,CKABEN" "0,1"
|
|
bitfld.long 0x00 5. "SCDEN,SCDEN" "0,1"
|
|
bitfld.long 0x00 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SITP,SITP" "0,1,2,3"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CH7CFGR2,CHCFG7R2"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,OFFSET"
|
|
bitfld.long 0x00 3.--7. "DTRBS,DTRBS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CH7AWSCDR,AWSCD7R"
|
|
bitfld.long 0x00 22.--23. "AWFORD,AWFORD" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "AWFOSR,AWFOSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. "BKSCD,BKSCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCDT,SCDT"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CH7WDATR,CHWDAT7R"
|
|
hexmask.long.word 0x00 0.--15. 1. "WDATA,WDATA"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CH7DATINR,CHDATIN7R"
|
|
hexmask.long.word 0x00 16.--31. 1. "INDAT1,INDAT1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INDAT0,INDAT0"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FLT0CR1,control register 1"
|
|
bitfld.long 0x00 30. "AWFSEL,Analog watchdog fast mode select" "0,1"
|
|
bitfld.long 0x00 29. "FAST,Fast conversion mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
|
|
bitfld.long 0x00 19. "RSYNC,Launch regular conversion synchronously with DFSDM0" "0,1"
|
|
bitfld.long 0x00 18. "RCONT,Continuous mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 17. "RSWSTART,Software start of a conversion on the regular channel" "0,1"
|
|
bitfld.long 0x00 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "JEXTSEL,Trigger signal selection for launching injected conversions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "JSCAN,Scanning conversion mode for injected conversions" "0,1"
|
|
bitfld.long 0x00 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "0,1"
|
|
bitfld.long 0x00 1. "JSWSTART,Start a conversion of the injected group of channels" "0,1"
|
|
bitfld.long 0x00 0. "DFEN,DFSDM enable" "0,1"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "FLT0CR2,control register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AWDCH,Analog watchdog channel selection"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXCH,Extremes detector channel selection"
|
|
bitfld.long 0x00 6. "CKABIE,Clock absence interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "SCDIE,Short-circuit detector interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "AWDIE,Analog watchdog interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "ROVRIE,Regular data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "JOVRIE,Injected data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "REOCIE,Regular end of conversion interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "JEOCIE,Injected end of conversion interrupt enable" "0,1"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "FLT0ISR,interrupt and status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCDF,short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKABF,Clock absence flag"
|
|
bitfld.long 0x00 14. "RCIP,Regular conversion in progress status" "0,1"
|
|
bitfld.long 0x00 13. "JCIP,Injected conversion in progress status" "0,1"
|
|
bitfld.long 0x00 4. "AWDF,Analog watchdog" "0,1"
|
|
bitfld.long 0x00 3. "ROVRF,Regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "JOVRF,Injected conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 1. "REOCF,End of regular conversion flag" "0,1"
|
|
bitfld.long 0x00 0. "JEOCF,End of injected conversion flag" "0,1"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "FLT0ICR,interrupt flag clear register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CLRCKABF,Clear the clock absence flag"
|
|
bitfld.long 0x00 3. "CLRROVRF,Clear the regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0,1"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "FLT0JCHGR,injected channel group selection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "JCHG,Injected channel group selection"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FLT0FCR,filter control register"
|
|
bitfld.long 0x00 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "FLT0JDATAR,data register for injected group"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "JDATA,Injected group conversion data"
|
|
bitfld.long 0x00 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "FLT0RDATAR,data register for the regular channel"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RDATA,Regular channel conversion data"
|
|
bitfld.long 0x00 4. "RPEND,Regular channel pending data" "0,1"
|
|
bitfld.long 0x00 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "FLT0AWHTR,analog watchdog high threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWHT,Analog watchdog high threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWH,Break signal assignment to analog watchdog high threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "FLT0AWLTR,analog watchdog low threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWLT,Analog watchdog low threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWL,Break signal assignment to analog watchdog low threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "FLT0AWSR,analog watchdog status register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "AWHTF,Analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AWLTF,Analog watchdog low threshold flag"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "FLT0AWCFR,analog watchdog clear flag register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "FLT0EXMAX,Extremes detector maximum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMAX,Extremes detector maximum value"
|
|
bitfld.long 0x00 0.--2. "EXMAXCH,Extremes detector maximum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "FLT0EXMIN,Extremes detector minimum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMIN,EXMIN"
|
|
bitfld.long 0x00 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "FLT0CNVTIMR,conversion timer register"
|
|
hexmask.long 0x00 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "FLT1CR1,control register 1"
|
|
bitfld.long 0x00 30. "AWFSEL,Analog watchdog fast mode select" "0,1"
|
|
bitfld.long 0x00 29. "FAST,Fast conversion mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
|
|
bitfld.long 0x00 19. "RSYNC,Launch regular conversion synchronously with DFSDM0" "0,1"
|
|
bitfld.long 0x00 18. "RCONT,Continuous mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 17. "RSWSTART,Software start of a conversion on the regular channel" "0,1"
|
|
bitfld.long 0x00 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "JEXTSEL,Trigger signal selection for launching injected conversions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "JSCAN,Scanning conversion mode for injected conversions" "0,1"
|
|
bitfld.long 0x00 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "0,1"
|
|
bitfld.long 0x00 1. "JSWSTART,Start a conversion of the injected group of channels" "0,1"
|
|
bitfld.long 0x00 0. "DFEN,DFSDM enable" "0,1"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "FLT1CR2,control register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AWDCH,Analog watchdog channel selection"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXCH,Extremes detector channel selection"
|
|
bitfld.long 0x00 6. "CKABIE,Clock absence interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "SCDIE,Short-circuit detector interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "AWDIE,Analog watchdog interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "ROVRIE,Regular data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "JOVRIE,Injected data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "REOCIE,Regular end of conversion interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "JEOCIE,Injected end of conversion interrupt enable" "0,1"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "FLT1ISR,interrupt and status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCDF,short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKABF,Clock absence flag"
|
|
bitfld.long 0x00 14. "RCIP,Regular conversion in progress status" "0,1"
|
|
bitfld.long 0x00 13. "JCIP,Injected conversion in progress status" "0,1"
|
|
bitfld.long 0x00 4. "AWDF,Analog watchdog" "0,1"
|
|
bitfld.long 0x00 3. "ROVRF,Regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "JOVRF,Injected conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 1. "REOCF,End of regular conversion flag" "0,1"
|
|
bitfld.long 0x00 0. "JEOCF,End of injected conversion flag" "0,1"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "FLT1ICR,interrupt flag clear register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CLRCKABF,Clear the clock absence flag"
|
|
bitfld.long 0x00 3. "CLRROVRF,Clear the regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0,1"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "FLT1JCHGR,injected channel group selection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "JCHG,Injected channel group selection"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "FLT1FCR,filter control register"
|
|
bitfld.long 0x00 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "FLT1JDATAR,data register for injected group"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "JDATA,Injected group conversion data"
|
|
bitfld.long 0x00 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "FLT1RDATAR,data register for the regular channel"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RDATA,Regular channel conversion data"
|
|
bitfld.long 0x00 4. "RPEND,Regular channel pending data" "0,1"
|
|
bitfld.long 0x00 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "FLT1AWHTR,analog watchdog high threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWHT,Analog watchdog high threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWH,Break signal assignment to analog watchdog high threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "FLT1AWLTR,analog watchdog low threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWLT,Analog watchdog low threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWL,Break signal assignment to analog watchdog low threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "FLT1AWSR,analog watchdog status register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "AWHTF,Analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AWLTF,Analog watchdog low threshold flag"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "FLT1AWCFR,analog watchdog clear flag register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "FLT1EXMAX,Extremes detector maximum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMAX,Extremes detector maximum value"
|
|
bitfld.long 0x00 0.--2. "EXMAXCH,Extremes detector maximum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "FLT1EXMIN,Extremes detector minimum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMIN,EXMIN"
|
|
bitfld.long 0x00 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "FLT1CNVTIMR,conversion timer register"
|
|
hexmask.long 0x00 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "FLT2CR1,control register 1"
|
|
bitfld.long 0x00 30. "AWFSEL,Analog watchdog fast mode select" "0,1"
|
|
bitfld.long 0x00 29. "FAST,Fast conversion mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
|
|
bitfld.long 0x00 19. "RSYNC,Launch regular conversion synchronously with DFSDM0" "0,1"
|
|
bitfld.long 0x00 18. "RCONT,Continuous mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 17. "RSWSTART,Software start of a conversion on the regular channel" "0,1"
|
|
bitfld.long 0x00 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "JEXTSEL,Trigger signal selection for launching injected conversions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "JSCAN,Scanning conversion mode for injected conversions" "0,1"
|
|
bitfld.long 0x00 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "0,1"
|
|
bitfld.long 0x00 1. "JSWSTART,Start a conversion of the injected group of channels" "0,1"
|
|
bitfld.long 0x00 0. "DFEN,DFSDM enable" "0,1"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "FLT2CR2,control register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AWDCH,Analog watchdog channel selection"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXCH,Extremes detector channel selection"
|
|
bitfld.long 0x00 6. "CKABIE,Clock absence interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "SCDIE,Short-circuit detector interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "AWDIE,Analog watchdog interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "ROVRIE,Regular data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "JOVRIE,Injected data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "REOCIE,Regular end of conversion interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "JEOCIE,Injected end of conversion interrupt enable" "0,1"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "FLT2ISR,interrupt and status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCDF,short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKABF,Clock absence flag"
|
|
bitfld.long 0x00 14. "RCIP,Regular conversion in progress status" "0,1"
|
|
bitfld.long 0x00 13. "JCIP,Injected conversion in progress status" "0,1"
|
|
bitfld.long 0x00 4. "AWDF,Analog watchdog" "0,1"
|
|
bitfld.long 0x00 3. "ROVRF,Regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "JOVRF,Injected conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 1. "REOCF,End of regular conversion flag" "0,1"
|
|
bitfld.long 0x00 0. "JEOCF,End of injected conversion flag" "0,1"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "FLT2ICR,interrupt flag clear register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CLRCKABF,Clear the clock absence flag"
|
|
bitfld.long 0x00 3. "CLRROVRF,Clear the regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0,1"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "FLT2JCHGR,injected channel group selection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "JCHG,Injected channel group selection"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "FLT2FCR,filter control register"
|
|
bitfld.long 0x00 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)"
|
|
rgroup.long 0x218++0x03
|
|
line.long 0x00 "FLT2JDATAR,data register for injected group"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "JDATA,Injected group conversion data"
|
|
bitfld.long 0x00 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "FLT2RDATAR,data register for the regular channel"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RDATA,Regular channel conversion data"
|
|
bitfld.long 0x00 4. "RPEND,Regular channel pending data" "0,1"
|
|
bitfld.long 0x00 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "FLT2AWHTR,analog watchdog high threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWHT,Analog watchdog high threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWH,Break signal assignment to analog watchdog high threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "FLT2AWLTR,analog watchdog low threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWLT,Analog watchdog low threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWL,Break signal assignment to analog watchdog low threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x228++0x03
|
|
line.long 0x00 "FLT2AWSR,analog watchdog status register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "AWHTF,Analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AWLTF,Analog watchdog low threshold flag"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "FLT2AWCFR,analog watchdog clear flag register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag"
|
|
rgroup.long 0x230++0x03
|
|
line.long 0x00 "FLT2EXMAX,Extremes detector maximum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMAX,Extremes detector maximum value"
|
|
bitfld.long 0x00 0.--2. "EXMAXCH,Extremes detector maximum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x234++0x03
|
|
line.long 0x00 "FLT2EXMIN,Extremes detector minimum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMIN,EXMIN"
|
|
bitfld.long 0x00 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x238++0x03
|
|
line.long 0x00 "FLT2CNVTIMR,conversion timer register"
|
|
hexmask.long 0x00 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "FLT3CR1,control register 1"
|
|
bitfld.long 0x00 30. "AWFSEL,Analog watchdog fast mode select" "0,1"
|
|
bitfld.long 0x00 29. "FAST,Fast conversion mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0,1"
|
|
bitfld.long 0x00 19. "RSYNC,Launch regular conversion synchronously with DFSDM0" "0,1"
|
|
bitfld.long 0x00 18. "RCONT,Continuous mode selection for regular conversions" "0,1"
|
|
bitfld.long 0x00 17. "RSWSTART,Software start of a conversion on the regular channel" "0,1"
|
|
bitfld.long 0x00 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0,1,2,3"
|
|
bitfld.long 0x00 8.--10. "JEXTSEL,Trigger signal selection for launching injected conversions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "JSCAN,Scanning conversion mode for injected conversions" "0,1"
|
|
bitfld.long 0x00 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "0,1"
|
|
bitfld.long 0x00 1. "JSWSTART,Start a conversion of the injected group of channels" "0,1"
|
|
bitfld.long 0x00 0. "DFEN,DFSDM enable" "0,1"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "FLT3CR2,control register 2"
|
|
hexmask.long.byte 0x00 16.--23. 1. "AWDCH,Analog watchdog channel selection"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXCH,Extremes detector channel selection"
|
|
bitfld.long 0x00 6. "CKABIE,Clock absence interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "SCDIE,Short-circuit detector interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "AWDIE,Analog watchdog interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "ROVRIE,Regular data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "JOVRIE,Injected data overrun interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "REOCIE,Regular end of conversion interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "JEOCIE,Injected end of conversion interrupt enable" "0,1"
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "FLT3ISR,interrupt and status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCDF,short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKABF,Clock absence flag"
|
|
bitfld.long 0x00 14. "RCIP,Regular conversion in progress status" "0,1"
|
|
bitfld.long 0x00 13. "JCIP,Injected conversion in progress status" "0,1"
|
|
bitfld.long 0x00 4. "AWDF,Analog watchdog" "0,1"
|
|
bitfld.long 0x00 3. "ROVRF,Regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "JOVRF,Injected conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 1. "REOCF,End of regular conversion flag" "0,1"
|
|
bitfld.long 0x00 0. "JEOCF,End of injected conversion flag" "0,1"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "FLT3ICR,interrupt flag clear register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CLRCKABF,Clear the clock absence flag"
|
|
bitfld.long 0x00 3. "CLRROVRF,Clear the regular conversion overrun flag" "0,1"
|
|
bitfld.long 0x00 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0,1"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "FLT3JCHGR,injected channel group selection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "JCHG,Injected channel group selection"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "FLT3FCR,filter control register"
|
|
bitfld.long 0x00 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)"
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "FLT3JDATAR,data register for injected group"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "JDATA,Injected group conversion data"
|
|
bitfld.long 0x00 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x29C++0x03
|
|
line.long 0x00 "FLT3RDATAR,data register for the regular channel"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RDATA,Regular channel conversion data"
|
|
bitfld.long 0x00 4. "RPEND,Regular channel pending data" "0,1"
|
|
bitfld.long 0x00 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "FLT3AWHTR,analog watchdog high threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWHT,Analog watchdog high threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWH,Break signal assignment to analog watchdog high threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "FLT3AWLTR,analog watchdog low threshold register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "AWLT,Analog watchdog low threshold"
|
|
bitfld.long 0x00 0.--3. "BKAWL,Break signal assignment to analog watchdog low threshold event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x2A8++0x03
|
|
line.long 0x00 "FLT3AWSR,analog watchdog status register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "AWHTF,Analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AWLTF,Analog watchdog low threshold flag"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "FLT3AWCFR,analog watchdog clear flag register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag"
|
|
rgroup.long 0x2B0++0x03
|
|
line.long 0x00 "FLT3EXMAX,Extremes detector maximum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMAX,Extremes detector maximum value"
|
|
bitfld.long 0x00 0.--2. "EXMAXCH,Extremes detector maximum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2B4++0x03
|
|
line.long 0x00 "FLT3EXMIN,Extremes detector minimum register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "EXMIN,EXMIN"
|
|
bitfld.long 0x00 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2B8++0x03
|
|
line.long 0x00 "FLT3CNVTIMR,conversion timer register"
|
|
hexmask.long 0x00 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH0DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,Pulses to skip for input data skipping function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH1DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,PLSSKP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CH2DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,PLSSKP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CH3DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,PLSSKP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CH4DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,PLSSKP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CH5DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,read-only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CH6DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,PLSSKP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "CH7DLYR,DFSDM channel y delay register"
|
|
bitfld.long 0x00 0.--5. "PLSSKP,PLSSKP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree.end
|
|
tree "DMA (Direct memory access controller)"
|
|
repeat 2. (list 1. 2.) (list ad:0x40020000 ad:0x40020400)
|
|
tree "DMA$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ISR,interrupt status register"
|
|
bitfld.long 0x00 31. "TEIF8,transfer error (TE) flag for channel 8" "0,1"
|
|
bitfld.long 0x00 30. "HTIF8,half transfer (HT) flag for channel 8" "0,1"
|
|
bitfld.long 0x00 29. "TCIF8,transfer complete (TC) flag for channel 8" "0,1"
|
|
bitfld.long 0x00 28. "GIF8,global interrupt flag for channel 8" "0,1"
|
|
bitfld.long 0x00 27. "TEIF7,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 26. "HTIF7,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 25. "TCIF7,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 24. "GIF7,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 23. "TEIF6,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 22. "HTIF6,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 21. "TCIF6,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "GIF6,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 19. "TEIF5,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 18. "HTIF5,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 17. "TCIF5,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 16. "GIF5,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 15. "TEIF4,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 14. "HTIF4,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 13. "TCIF4,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 12. "GIF4,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 11. "TEIF3,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 10. "HTIF3,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TCIF3,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 8. "GIF3,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 7. "TEIF2,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 6. "HTIF2,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 5. "TCIF2,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 4. "GIF2,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 3. "TEIF1,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 2. "HTIF1,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 1. "TCIF1,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 0. "GIF1,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "IFCR,interrupt flag clear register"
|
|
bitfld.long 0x00 31. "CTEIF8,transfer error flag clear for channel 8" "0,1"
|
|
bitfld.long 0x00 30. "CHTIF8,half transfer flag clear for channel 8" "0,1"
|
|
bitfld.long 0x00 29. "CTCIF8,transfer complete flag clear for channel 8" "0,1"
|
|
bitfld.long 0x00 28. "CGIF8,global interrupt flag clear for channel 8" "0,1"
|
|
bitfld.long 0x00 27. "CTEIF7,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 26. "CHTIF7,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 25. "CTCIF7,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 24. "CGIF7,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 23. "CTEIF6,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 22. "CHTIF6,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 21. "CTCIF6,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "CGIF6,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 19. "CTEIF5,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 18. "CHTIF5,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 17. "CTCIF5,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 16. "CGIF5,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 15. "CTEIF4,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 14. "CHTIF4,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 13. "CTCIF4,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 12. "CGIF4,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 11. "CTEIF3,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 10. "CHTIF3,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CTCIF3,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 8. "CGIF3,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 7. "CTEIF2,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 6. "CHTIF2,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 5. "CTCIF2,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 4. "CGIF2,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 3. "CTEIF1,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 2. "CHTIF1,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 1. "CTCIF1,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 0. "CGIF1,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CCR1,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNDTR1,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CPAR1,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CM0AR1,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CM1AR1,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCR2,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CNDTR2,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CPAR2,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CM0AR2,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CM1AR2,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CCR3,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CNDTR3,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CPAR3,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CM0AR3,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CM1AR3,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CCR4,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CNDTR4,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CPAR4,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CM0AR4,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CM1AR4,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CCR5,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CNDTR5,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CPAR5,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CM0AR5,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CM1AR5,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CCR6,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CNDTR6,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CPAR6,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CM0AR6,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CM1AR6,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CCR7,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CNDTR7,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CPAR7,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CM0AR7,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CM1AR7,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CCR8,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CNDTR8,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CPAR8,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CM0AR8,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CM1AR8,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CSELR,channel selection register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
tree.end
|
|
repeat.end
|
|
repeat 2. (list 1. 2.) (list ad:0x50020000 ad:0x50020400)
|
|
tree "SEC_DMA$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ISR,interrupt status register"
|
|
bitfld.long 0x00 31. "TEIF8,transfer error (TE) flag for channel 8" "0,1"
|
|
bitfld.long 0x00 30. "HTIF8,half transfer (HT) flag for channel 8" "0,1"
|
|
bitfld.long 0x00 29. "TCIF8,transfer complete (TC) flag for channel 8" "0,1"
|
|
bitfld.long 0x00 28. "GIF8,global interrupt flag for channel 8" "0,1"
|
|
bitfld.long 0x00 27. "TEIF7,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 26. "HTIF7,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 25. "TCIF7,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 24. "GIF7,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 23. "TEIF6,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 22. "HTIF6,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 21. "TCIF6,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "GIF6,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 19. "TEIF5,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 18. "HTIF5,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 17. "TCIF5,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 16. "GIF5,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 15. "TEIF4,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 14. "HTIF4,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 13. "TCIF4,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 12. "GIF4,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 11. "TEIF3,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 10. "HTIF3,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TCIF3,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 8. "GIF3,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 7. "TEIF2,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 6. "HTIF2,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 5. "TCIF2,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 4. "GIF2,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 3. "TEIF1,Channel x transfer error flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 2. "HTIF1,Channel x half transfer flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 1. "TCIF1,Channel x transfer complete flag (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 0. "GIF1,Channel x global interrupt flag (x = 1 ..7)" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "IFCR,interrupt flag clear register"
|
|
bitfld.long 0x00 31. "CTEIF8,transfer error flag clear for channel 8" "0,1"
|
|
bitfld.long 0x00 30. "CHTIF8,half transfer flag clear for channel 8" "0,1"
|
|
bitfld.long 0x00 29. "CTCIF8,transfer complete flag clear for channel 8" "0,1"
|
|
bitfld.long 0x00 28. "CGIF8,global interrupt flag clear for channel 8" "0,1"
|
|
bitfld.long 0x00 27. "CTEIF7,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 26. "CHTIF7,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 25. "CTCIF7,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 24. "CGIF7,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 23. "CTEIF6,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 22. "CHTIF6,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 21. "CTCIF6,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "CGIF6,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 19. "CTEIF5,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 18. "CHTIF5,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 17. "CTCIF5,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 16. "CGIF5,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 15. "CTEIF4,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 14. "CHTIF4,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 13. "CTCIF4,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 12. "CGIF4,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 11. "CTEIF3,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 10. "CHTIF3,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CTCIF3,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 8. "CGIF3,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 7. "CTEIF2,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 6. "CHTIF2,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 5. "CTCIF2,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 4. "CGIF2,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 3. "CTEIF1,Channel x transfer error clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 2. "CHTIF1,Channel x half transfer clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 1. "CTCIF1,Channel x transfer complete clear (x = 1 ..7)" "0,1"
|
|
bitfld.long 0x00 0. "CGIF1,Channel x global interrupt clear (x = 1 ..7)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CCR1,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNDTR1,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CPAR1,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CM0AR1,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CM1AR1,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCR2,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CNDTR2,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CPAR2,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CM0AR2,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CM1AR2,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CCR3,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CNDTR3,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CPAR3,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CM0AR3,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CM1AR3,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CCR4,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CNDTR4,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CPAR4,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CM0AR4,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CM1AR4,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CCR5,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CNDTR5,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CPAR5,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CM0AR5,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CM1AR5,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CCR6,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CNDTR6,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CPAR6,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CM0AR6,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CM1AR6,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CCR7,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CNDTR7,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CPAR7,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CM0AR7,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CM1AR7,channel x memory address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CCR8,channel x configuration register"
|
|
bitfld.long 0x00 20. "PRIV,privileged mode" "0,1"
|
|
bitfld.long 0x00 19. "DSEC,security of the DMA transfer to the destination" "0,1"
|
|
bitfld.long 0x00 18. "SSEC,security of the DMA transfer from the source" "0,1"
|
|
bitfld.long 0x00 17. "SECM,secure mode" "0,1"
|
|
bitfld.long 0x00 16. "CT,current target memory of DMA transfer in double-buffer mode" "0,1"
|
|
bitfld.long 0x00 15. "DBM,double-buffer mode" "0,1"
|
|
bitfld.long 0x00 14. "MEM2MEM,Memory to memory mode" "0,1"
|
|
bitfld.long 0x00 12.--13. "PL,Channel priority level" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "MSIZE,Memory size" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PSIZE,Peripheral size" "0,1,2,3"
|
|
bitfld.long 0x00 7. "MINC,Memory increment mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PINC,Peripheral increment mode" "0,1"
|
|
bitfld.long 0x00 5. "CIRC,Circular mode" "0,1"
|
|
bitfld.long 0x00 4. "DIR,Data transfer direction" "0,1"
|
|
bitfld.long 0x00 3. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "HTIE,Half transfer interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EN,Channel enable" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CNDTR8,channel x number of data register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "NDT,Number of data to transfer"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CPAR8,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "PA,Peripheral address"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CM0AR8,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,Memory address"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CM1AR8,channel x peripheral address register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CSELR,channel selection register"
|
|
hexmask.long 0x00 0.--31. 1. "MA,peripheral address"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "DMAMUX (Direct memory access Multiplexer)"
|
|
tree "DMAMUX1"
|
|
base ad:0x40020800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "C0CR,DMA Multiplexer Channel 0 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "C1CR,DMA Multiplexer Channel 1 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "C2CR,DMA Multiplexer Channel 2 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "C3CR,DMA Multiplexer Channel 3 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "C4CR,DMA Multiplexer Channel 4 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "C5CR,DMA Multiplexer Channel 5 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "OIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "C6CR,DMA Multiplexer Channel 6 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "C7CR,DMA Multiplexer Channel 7 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "C8CR,DMA Multiplexer Channel 8 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "C9CR,DMA Multiplexer Channel 9 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "C10CR,DMA Multiplexer Channel 10 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "C11CR,DMA Multiplexer Channel 11 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "C12CR,DMA Multiplexer Channel 12 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "C13CR,DMA Multiplexer Channel 13 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "C14CR,DMA Multiplexer Channel 10 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Number of DMA requests minus 1 to forward" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Synchronization polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event generation enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA request identification"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "C15CR,DMA Multiplexer Channel 10 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Number of DMA requests minus 1 to forward" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Synchronization polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event generation enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA request identification"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CSR,DMA Multiplexer Channel Status register"
|
|
bitfld.long 0x00 15. "SOF15,Synchronization Overrun Flag 13" "0,1"
|
|
bitfld.long 0x00 14. "SOF14,Synchronization Overrun Flag 13" "0,1"
|
|
bitfld.long 0x00 13. "SOF13,Synchronization Overrun Flag 13" "0,1"
|
|
bitfld.long 0x00 12. "SOF12,Synchronization Overrun Flag 12" "0,1"
|
|
bitfld.long 0x00 11. "SOF11,Synchronization Overrun Flag 11" "0,1"
|
|
bitfld.long 0x00 10. "SOF10,Synchronization Overrun Flag 10" "0,1"
|
|
bitfld.long 0x00 9. "SOF9,Synchronization Overrun Flag 9" "0,1"
|
|
bitfld.long 0x00 8. "SOF8,Synchronization Overrun Flag 8" "0,1"
|
|
bitfld.long 0x00 7. "SOF7,Synchronization Overrun Flag 7" "0,1"
|
|
bitfld.long 0x00 6. "SOF6,Synchronization Overrun Flag 6" "0,1"
|
|
bitfld.long 0x00 5. "SOF5,Synchronization Overrun Flag 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SOF4,Synchronization Overrun Flag 4" "0,1"
|
|
bitfld.long 0x00 3. "SOF3,Synchronization Overrun Flag 3" "0,1"
|
|
bitfld.long 0x00 2. "SOF2,Synchronization Overrun Flag 2" "0,1"
|
|
bitfld.long 0x00 1. "SOF1,Synchronization Overrun Flag 1" "0,1"
|
|
bitfld.long 0x00 0. "SOF0,Synchronization Overrun Flag 0" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CCFR,DMA Channel Clear Flag Register"
|
|
bitfld.long 0x00 15. "CSOF15,Synchronization Clear Overrun Flag 13" "0,1"
|
|
bitfld.long 0x00 14. "CSOF14,Synchronization Clear Overrun Flag 13" "0,1"
|
|
bitfld.long 0x00 13. "CSOF13,Synchronization Clear Overrun Flag 13" "0,1"
|
|
bitfld.long 0x00 12. "CSOF12,Synchronization Clear Overrun Flag 12" "0,1"
|
|
bitfld.long 0x00 11. "CSOF11,Synchronization Clear Overrun Flag 11" "0,1"
|
|
bitfld.long 0x00 10. "CSOF10,Synchronization Clear Overrun Flag 10" "0,1"
|
|
bitfld.long 0x00 9. "CSOF9,Synchronization Clear Overrun Flag 9" "0,1"
|
|
bitfld.long 0x00 8. "CSOF8,Synchronization Clear Overrun Flag 8" "0,1"
|
|
bitfld.long 0x00 7. "CSOF7,Synchronization Clear Overrun Flag 7" "0,1"
|
|
bitfld.long 0x00 6. "CSOF6,Synchronization Clear Overrun Flag 6" "0,1"
|
|
bitfld.long 0x00 5. "CSOF5,Synchronization Clear Overrun Flag 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CSOF4,Synchronization Clear Overrun Flag 4" "0,1"
|
|
bitfld.long 0x00 3. "CSOF3,Synchronization Clear Overrun Flag 3" "0,1"
|
|
bitfld.long 0x00 2. "CSOF2,Synchronization Clear Overrun Flag 2" "0,1"
|
|
bitfld.long 0x00 1. "CSOF1,Synchronization Clear Overrun Flag 1" "0,1"
|
|
bitfld.long 0x00 0. "CSOF0,Synchronization Clear Overrun Flag 0" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "RG0CR,DMA Request Generator 0 Control Register"
|
|
bitfld.long 0x00 19.--23. "GNBREQ,Number of Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "GPOL,Generation Polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "GE,Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "OIE,Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0.--4. "SIG_ID,Signal ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "RG1CR,DMA Request Generator 1 Control Register"
|
|
bitfld.long 0x00 19.--23. "GNBREQ,Number of Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "GPOL,Generation Polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "GE,Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "OIE,Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0.--4. "SIG_ID,Signal ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "RG2CR,DMA Request Generator 2 Control Register"
|
|
bitfld.long 0x00 19.--23. "GNBREQ,Number of Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "GPOL,Generation Polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "GE,Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "OIE,Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0.--4. "SIG_ID,Signal ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "RG3CR,DMA Request Generator 3 Control Register"
|
|
bitfld.long 0x00 19.--23. "GNBREQ,Number of Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "GPOL,Generation Polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "GE,Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "OIE,Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0.--4. "SIG_ID,Signal ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "RGSR,DMA Request Generator Status Register"
|
|
bitfld.long 0x00 3. "OF3,Generator Overrun Flag 3" "0,1"
|
|
bitfld.long 0x00 2. "OF2,Generator Overrun Flag 2" "0,1"
|
|
bitfld.long 0x00 1. "OF1,Generator Overrun Flag 1" "0,1"
|
|
bitfld.long 0x00 0. "OF0,Generator Overrun Flag 0" "0,1"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "RGCFR,DMA Request Generator Clear Flag Register"
|
|
bitfld.long 0x00 3. "CSOF3,Generator Clear Overrun Flag 3" "0,1"
|
|
bitfld.long 0x00 2. "CSOF2,Generator Clear Overrun Flag 2" "0,1"
|
|
bitfld.long 0x00 1. "CSOF1,Generator Clear Overrun Flag 1" "0,1"
|
|
bitfld.long 0x00 0. "CSOF0,Generator Clear Overrun Flag 0" "0,1"
|
|
tree.end
|
|
tree "SEC_DMAMUX1"
|
|
base ad:0x50020800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "C0CR,DMA Multiplexer Channel 0 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "C1CR,DMA Multiplexer Channel 1 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "C2CR,DMA Multiplexer Channel 2 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "C3CR,DMA Multiplexer Channel 3 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "C4CR,DMA Multiplexer Channel 4 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "C5CR,DMA Multiplexer Channel 5 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "OIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "C6CR,DMA Multiplexer Channel 6 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "C7CR,DMA Multiplexer Channel 7 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "C8CR,DMA Multiplexer Channel 8 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "C9CR,DMA Multiplexer Channel 9 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "C10CR,DMA Multiplexer Channel 10 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "C11CR,DMA Multiplexer Channel 11 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "C12CR,DMA Multiplexer Channel 12 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "C13CR,DMA Multiplexer Channel 13 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Nb request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Sync polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization Overrun Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA Request ID"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "C14CR,DMA Multiplexer Channel 10 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Number of DMA requests minus 1 to forward" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Synchronization polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event generation enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA request identification"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "C15CR,DMA Multiplexer Channel 10 Control register"
|
|
bitfld.long 0x00 24.--28. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. "NBREQ,Number of DMA requests minus 1 to forward" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "SPOL,Synchronization polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "SE,Synchronization enable" "0,1"
|
|
bitfld.long 0x00 9. "EGE,Event generation enable" "0,1"
|
|
bitfld.long 0x00 8. "SOIE,Synchronization overrun interrupt enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DMAREQ_ID,DMA request identification"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CSR,DMA Multiplexer Channel Status register"
|
|
bitfld.long 0x00 15. "SOF15,Synchronization Overrun Flag 13" "0,1"
|
|
bitfld.long 0x00 14. "SOF14,Synchronization Overrun Flag 13" "0,1"
|
|
bitfld.long 0x00 13. "SOF13,Synchronization Overrun Flag 13" "0,1"
|
|
bitfld.long 0x00 12. "SOF12,Synchronization Overrun Flag 12" "0,1"
|
|
bitfld.long 0x00 11. "SOF11,Synchronization Overrun Flag 11" "0,1"
|
|
bitfld.long 0x00 10. "SOF10,Synchronization Overrun Flag 10" "0,1"
|
|
bitfld.long 0x00 9. "SOF9,Synchronization Overrun Flag 9" "0,1"
|
|
bitfld.long 0x00 8. "SOF8,Synchronization Overrun Flag 8" "0,1"
|
|
bitfld.long 0x00 7. "SOF7,Synchronization Overrun Flag 7" "0,1"
|
|
bitfld.long 0x00 6. "SOF6,Synchronization Overrun Flag 6" "0,1"
|
|
bitfld.long 0x00 5. "SOF5,Synchronization Overrun Flag 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SOF4,Synchronization Overrun Flag 4" "0,1"
|
|
bitfld.long 0x00 3. "SOF3,Synchronization Overrun Flag 3" "0,1"
|
|
bitfld.long 0x00 2. "SOF2,Synchronization Overrun Flag 2" "0,1"
|
|
bitfld.long 0x00 1. "SOF1,Synchronization Overrun Flag 1" "0,1"
|
|
bitfld.long 0x00 0. "SOF0,Synchronization Overrun Flag 0" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CCFR,DMA Channel Clear Flag Register"
|
|
bitfld.long 0x00 15. "CSOF15,Synchronization Clear Overrun Flag 13" "0,1"
|
|
bitfld.long 0x00 14. "CSOF14,Synchronization Clear Overrun Flag 13" "0,1"
|
|
bitfld.long 0x00 13. "CSOF13,Synchronization Clear Overrun Flag 13" "0,1"
|
|
bitfld.long 0x00 12. "CSOF12,Synchronization Clear Overrun Flag 12" "0,1"
|
|
bitfld.long 0x00 11. "CSOF11,Synchronization Clear Overrun Flag 11" "0,1"
|
|
bitfld.long 0x00 10. "CSOF10,Synchronization Clear Overrun Flag 10" "0,1"
|
|
bitfld.long 0x00 9. "CSOF9,Synchronization Clear Overrun Flag 9" "0,1"
|
|
bitfld.long 0x00 8. "CSOF8,Synchronization Clear Overrun Flag 8" "0,1"
|
|
bitfld.long 0x00 7. "CSOF7,Synchronization Clear Overrun Flag 7" "0,1"
|
|
bitfld.long 0x00 6. "CSOF6,Synchronization Clear Overrun Flag 6" "0,1"
|
|
bitfld.long 0x00 5. "CSOF5,Synchronization Clear Overrun Flag 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CSOF4,Synchronization Clear Overrun Flag 4" "0,1"
|
|
bitfld.long 0x00 3. "CSOF3,Synchronization Clear Overrun Flag 3" "0,1"
|
|
bitfld.long 0x00 2. "CSOF2,Synchronization Clear Overrun Flag 2" "0,1"
|
|
bitfld.long 0x00 1. "CSOF1,Synchronization Clear Overrun Flag 1" "0,1"
|
|
bitfld.long 0x00 0. "CSOF0,Synchronization Clear Overrun Flag 0" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "RG0CR,DMA Request Generator 0 Control Register"
|
|
bitfld.long 0x00 19.--23. "GNBREQ,Number of Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "GPOL,Generation Polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "GE,Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "OIE,Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0.--4. "SIG_ID,Signal ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "RG1CR,DMA Request Generator 1 Control Register"
|
|
bitfld.long 0x00 19.--23. "GNBREQ,Number of Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "GPOL,Generation Polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "GE,Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "OIE,Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0.--4. "SIG_ID,Signal ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "RG2CR,DMA Request Generator 2 Control Register"
|
|
bitfld.long 0x00 19.--23. "GNBREQ,Number of Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "GPOL,Generation Polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "GE,Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "OIE,Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0.--4. "SIG_ID,Signal ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "RG3CR,DMA Request Generator 3 Control Register"
|
|
bitfld.long 0x00 19.--23. "GNBREQ,Number of Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17.--18. "GPOL,Generation Polarity" "0,1,2,3"
|
|
bitfld.long 0x00 16. "GE,Generation Enable" "0,1"
|
|
bitfld.long 0x00 8. "OIE,Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0.--4. "SIG_ID,Signal ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "RGSR,DMA Request Generator Status Register"
|
|
bitfld.long 0x00 3. "OF3,Generator Overrun Flag 3" "0,1"
|
|
bitfld.long 0x00 2. "OF2,Generator Overrun Flag 2" "0,1"
|
|
bitfld.long 0x00 1. "OF1,Generator Overrun Flag 1" "0,1"
|
|
bitfld.long 0x00 0. "OF0,Generator Overrun Flag 0" "0,1"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "RGCFR,DMA Request Generator Clear Flag Register"
|
|
bitfld.long 0x00 3. "CSOF3,Generator Clear Overrun Flag 3" "0,1"
|
|
bitfld.long 0x00 2. "CSOF2,Generator Clear Overrun Flag 2" "0,1"
|
|
bitfld.long 0x00 1. "CSOF1,Generator Clear Overrun Flag 1" "0,1"
|
|
bitfld.long 0x00 0. "CSOF0,Generator Clear Overrun Flag 0" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "EXTI (External interrupt/event controller)"
|
|
tree "EXTI"
|
|
base ad:0x4002F400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTSR1,EXTI rising trigger selection register"
|
|
bitfld.long 0x00 22. "RT22,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 21. "RT21,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 16. "RT16,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 15. "RT15,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 14. "RT14,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 13. "RT13,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 12. "RT12,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 11. "RT11,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 10. "RT10,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 9. "RT9,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RT8,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 7. "RT7,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 6. "RT6,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 5. "RT5,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 4. "RT4,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 3. "RT3,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 2. "RT2,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 1. "RT1,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 0. "RT0,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "FTSR1,EXTI falling trigger selection register"
|
|
bitfld.long 0x00 22. "FT22,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 21. "FT21,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 16. "FT16,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 15. "FT15,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 14. "FT14,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 13. "FT13,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 12. "FT12,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 11. "FT11,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 10. "FT10,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 9. "FT9,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "FT8,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 7. "FT7,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 6. "FT6,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 5. "FT5,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 4. "FT4,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 3. "FT3,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 2. "FT2,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 1. "FT1,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 0. "FT0,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SWIER1,EXTI software interrupt event register"
|
|
bitfld.long 0x00 22. "SWI22,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 21. "SWI21,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 16. "SWI16,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 15. "SWI15,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 14. "SWI14,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 13. "SWI13,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 12. "SWI12,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 11. "SWI11,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 10. "SWI10,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 9. "SWI9,Software interrupt on event x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "SWI8,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 7. "SWI7,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 6. "SWI6,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 5. "SWI5,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 4. "SWI4,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 3. "SWI3,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 2. "SWI2,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 1. "SWI1,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 0. "SWI0,Software interrupt on event x" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RPR1,EXTI rising edge pending register"
|
|
bitfld.long 0x00 22. "RPIF22,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 21. "RPIF21,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 16. "RPIF16,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 15. "RPIF15,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 14. "RPIF14,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 13. "RPIF13,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 12. "RPIF12,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 11. "RPIF11,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 10. "RPIF10,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 9. "RPIF9,configurable event inputs x rising edge pending bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RPIF8,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 7. "RPIF7,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 6. "RPIF6,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 5. "RPIF5,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 4. "RPIF4,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 3. "RPIF3,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 2. "RPIF2,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 1. "RPIF1,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 0. "RPIF0,configurable event inputs x rising edge pending bit" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FPR1,EXTI falling edge pending register"
|
|
bitfld.long 0x00 22. "FPIF22,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 21. "FPIF21,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 16. "FPIF16,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 15. "FPIF15,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 14. "FPIF14,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 13. "FPIF13,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 12. "FPIF12,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 11. "FPIF11,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 10. "FPIF10,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 9. "FPIF9,configurable event inputs x falling edge pending bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "FPIF8,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 7. "FPIF7,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 6. "FPIF6,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 5. "FPIF5,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 4. "FPIF4,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 3. "FPIF3,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 2. "FPIF2,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 1. "FPIF1,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 0. "FPIF0,configurable event inputs x falling edge pending bit" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SECCFGR1,EXTI security configuration register"
|
|
bitfld.long 0x00 31. "SEC31,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 30. "SEC30,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 29. "SEC29,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 28. "SEC28,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 27. "SEC27,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 26. "SEC26,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 25. "SEC25,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 24. "SEC24,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 23. "SEC23,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 22. "SEC22,Security enable on event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "SEC21,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 20. "SEC20,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 19. "SEC19,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 18. "SEC18,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 17. "SEC17,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 16. "SEC16,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 15. "SEC15,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,Security enable on event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "SEC11,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 5. "SEC5,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,Security enable on event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SEC1,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,Security enable on event input x" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PRIVCFGR1,EXTI privilege configuration register"
|
|
bitfld.long 0x00 31. "PRIV31,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 30. "PRIV30,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 29. "PRIV29,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 28. "PRIV28,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 27. "PRIV27,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 26. "PRIV26,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 25. "PRIV25,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 24. "PRIV24,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 23. "PRIV23,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 22. "PRIV22,Security enable on event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "PRIV21,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 20. "PRIV20,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 19. "PRIV19,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 18. "PRIV18,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 17. "PRIV17,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 16. "PRIV16,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 15. "PRIV15,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 14. "PRIV14,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 13. "PRIV13,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 12. "PRIV12,Security enable on event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "PRIV11,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 10. "PRIV10,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 9. "PRIV9,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 8. "PRIV8,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 7. "PRIV7,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 6. "PRIV6,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 5. "PRIV5,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 4. "PRIV4,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 3. "PRIV3,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 2. "PRIV2,Security enable on event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PRIV1,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 0. "PRIV0,Security enable on event input x" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTSR2,EXTI rising trigger selection register"
|
|
bitfld.long 0x00 6. "RT38,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 5. "RT37,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 4. "RT36,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 3. "RT35,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FTSR2,EXTI falling trigger selection register"
|
|
bitfld.long 0x00 6. "FT38,FT38" "0,1"
|
|
bitfld.long 0x00 5. "FT37,FT37" "0,1"
|
|
bitfld.long 0x00 4. "FT36,FT36" "0,1"
|
|
bitfld.long 0x00 3. "FT35,FT35" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SWIER2,EXTI software interrupt event register"
|
|
bitfld.long 0x00 6. "SWI38,SWI38" "0,1"
|
|
bitfld.long 0x00 5. "SWI37,SWI37" "0,1"
|
|
bitfld.long 0x00 4. "SWI36,SWI36" "0,1"
|
|
bitfld.long 0x00 3. "SWI35,SWI35" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RPR2,EXTI rising edge pending register"
|
|
bitfld.long 0x00 6. "RPIF38,RPIF38" "0,1"
|
|
bitfld.long 0x00 5. "RPIF37,RPIF37" "0,1"
|
|
bitfld.long 0x00 4. "RPIF36,RPIF36" "0,1"
|
|
bitfld.long 0x00 3. "RPIF35,RPIF35" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FPR2,EXTI falling edge pending register"
|
|
bitfld.long 0x00 6. "FPIF38,FPIF38" "0,1"
|
|
bitfld.long 0x00 5. "FPIF37,FPIF37" "0,1"
|
|
bitfld.long 0x00 4. "FPIF36,FPIF36" "0,1"
|
|
bitfld.long 0x00 3. "FPIF35,FPIF35" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SECCFGR2,EXTI security enable register"
|
|
bitfld.long 0x00 10. "SEC42,SEC42" "0,1"
|
|
bitfld.long 0x00 9. "SEC41,SEC41" "0,1"
|
|
bitfld.long 0x00 8. "SEC40,SEC40" "0,1"
|
|
bitfld.long 0x00 7. "SEC39,SEC39" "0,1"
|
|
bitfld.long 0x00 6. "SEC38,SEC38" "0,1"
|
|
bitfld.long 0x00 5. "SEC37,SEC37" "0,1"
|
|
bitfld.long 0x00 4. "SEC36,SEC36" "0,1"
|
|
bitfld.long 0x00 3. "SEC35,SEC35" "0,1"
|
|
bitfld.long 0x00 2. "SEC34,SEC34" "0,1"
|
|
bitfld.long 0x00 1. "SEC33,SEC33" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SEC32,SEC32" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PRIVCFGR2,EXTI security enable register"
|
|
bitfld.long 0x00 10. "PRIV42,PRIV42" "0,1"
|
|
bitfld.long 0x00 9. "PRIV41,PRIV41" "0,1"
|
|
bitfld.long 0x00 8. "PRIV40,PRIV40" "0,1"
|
|
bitfld.long 0x00 7. "PRIV39,PRIV39" "0,1"
|
|
bitfld.long 0x00 6. "PRIV38,PRIV38" "0,1"
|
|
bitfld.long 0x00 5. "PRIV37,PRIV37" "0,1"
|
|
bitfld.long 0x00 4. "PRIV36,PRIV36" "0,1"
|
|
bitfld.long 0x00 3. "PRIV35,PRIV35" "0,1"
|
|
bitfld.long 0x00 2. "PRIV34,PRIV34" "0,1"
|
|
bitfld.long 0x00 1. "PRIV33,PRIV33" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PRIV32,PRIV32" "0,1"
|
|
repeat 4. (strings "1" "2" "3" "4" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "EXTICR$1,EXTI external interrupt selection register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTI24_31,EXTIm+3 GPIO port selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EXTI16_23,EXTIm+2 GPIO port selection"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXTI8_15,EXTIm+1 GPIO port selection"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EXTI0_7,EXTIm GPIO port selection"
|
|
repeat.end
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "LOCKRG,EXTI lock register"
|
|
bitfld.long 0x00 0. "LOCK,LOCK" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "IMR1,EXTI CPU wakeup with interrupt mask register"
|
|
bitfld.long 0x00 31. "IM31,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 30. "IM30,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 29. "IM29,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 28. "IM28,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 27. "IM27,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 26. "IM26,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 25. "IM25,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 24. "IM24,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 23. "IM23,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 22. "IM22,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "IM21,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 20. "IM20,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 19. "IM19,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 18. "IM18,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 17. "IM17,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 16. "IM16,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 15. "IM15,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 14. "IM14,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 13. "IM13,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 12. "IM12,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IM11,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 10. "IM10,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 9. "IM9,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 8. "IM8,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 7. "IM7,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 6. "IM6,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 5. "IM5,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 4. "IM4,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 3. "IM3,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 2. "IM2,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IM1,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 0. "IM0,CPU wakeup with interrupt mask on event input" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "EMR1,EXTI CPU wakeup with event mask register"
|
|
bitfld.long 0x00 31. "EM31,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 30. "EM30,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 29. "EM29,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 28. "EM28,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 27. "EM27,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 26. "EM26,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 25. "EM25,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 24. "EM24,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 23. "EM23,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 22. "EM22,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "EM21,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 20. "EM20,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 19. "EM19,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 18. "EM18,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 17. "EM17,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 16. "EM16,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 15. "EM15,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 14. "EM14,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 13. "EM13,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 12. "EM12,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "EM11,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 10. "EM10,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 9. "EM9,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 8. "EM8,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 7. "EM7,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 6. "EM6,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 5. "EM5,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 4. "EM4,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 3. "EM3,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 2. "EM2,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EM1,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 0. "EM0,CPU wakeup with interrupt mask on event input" "0,1"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "IMR2,EXTI CPUm wakeup with interrupt mask register"
|
|
bitfld.long 0x00 10. "IM42,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 9. "IM41,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 8. "IM40,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 6. "IM38,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 5. "IM37,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 4. "IM36,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 3. "IM35,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 2. "IM34,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 1. "IM33,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 0. "IM32,CPU wakeup with interrupt mask on event input" "0,1"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "EMR2,EXTI CPU wakeup with event mask register"
|
|
bitfld.long 0x00 10. "EM42,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 9. "EM41,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 8. "EM40,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 6. "EM38,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 5. "EM37,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 4. "EM36,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 3. "EM35,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 2. "EM34,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 1. "EM33,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 0. "EM32,CPU wakeup with interrupt mask on event input" "0,1"
|
|
tree.end
|
|
tree "SEC_EXTI"
|
|
base ad:0x5002F400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTSR1,EXTI rising trigger selection register"
|
|
bitfld.long 0x00 22. "RT22,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 21. "RT21,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 16. "RT16,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 15. "RT15,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 14. "RT14,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 13. "RT13,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 12. "RT12,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 11. "RT11,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 10. "RT10,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 9. "RT9,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RT8,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 7. "RT7,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 6. "RT6,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 5. "RT5,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 4. "RT4,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 3. "RT3,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 2. "RT2,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 1. "RT1,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 0. "RT0,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "FTSR1,EXTI falling trigger selection register"
|
|
bitfld.long 0x00 22. "FT22,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 21. "FT21,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 16. "FT16,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 15. "FT15,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 14. "FT14,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 13. "FT13,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 12. "FT12,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 11. "FT11,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 10. "FT10,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 9. "FT9,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "FT8,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 7. "FT7,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 6. "FT6,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 5. "FT5,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 4. "FT4,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 3. "FT3,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 2. "FT2,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 1. "FT1,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 0. "FT0,Falling trigger event configuration bit of configurable event input x" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SWIER1,EXTI software interrupt event register"
|
|
bitfld.long 0x00 22. "SWI22,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 21. "SWI21,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 16. "SWI16,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 15. "SWI15,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 14. "SWI14,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 13. "SWI13,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 12. "SWI12,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 11. "SWI11,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 10. "SWI10,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 9. "SWI9,Software interrupt on event x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "SWI8,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 7. "SWI7,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 6. "SWI6,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 5. "SWI5,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 4. "SWI4,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 3. "SWI3,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 2. "SWI2,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 1. "SWI1,Software interrupt on event x" "0,1"
|
|
bitfld.long 0x00 0. "SWI0,Software interrupt on event x" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RPR1,EXTI rising edge pending register"
|
|
bitfld.long 0x00 22. "RPIF22,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 21. "RPIF21,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 16. "RPIF16,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 15. "RPIF15,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 14. "RPIF14,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 13. "RPIF13,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 12. "RPIF12,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 11. "RPIF11,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 10. "RPIF10,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 9. "RPIF9,configurable event inputs x rising edge pending bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RPIF8,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 7. "RPIF7,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 6. "RPIF6,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 5. "RPIF5,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 4. "RPIF4,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 3. "RPIF3,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 2. "RPIF2,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 1. "RPIF1,configurable event inputs x rising edge pending bit" "0,1"
|
|
bitfld.long 0x00 0. "RPIF0,configurable event inputs x rising edge pending bit" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FPR1,EXTI falling edge pending register"
|
|
bitfld.long 0x00 22. "FPIF22,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 21. "FPIF21,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 16. "FPIF16,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 15. "FPIF15,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 14. "FPIF14,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 13. "FPIF13,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 12. "FPIF12,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 11. "FPIF11,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 10. "FPIF10,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 9. "FPIF9,configurable event inputs x falling edge pending bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "FPIF8,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 7. "FPIF7,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 6. "FPIF6,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 5. "FPIF5,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 4. "FPIF4,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 3. "FPIF3,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 2. "FPIF2,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 1. "FPIF1,configurable event inputs x falling edge pending bit" "0,1"
|
|
bitfld.long 0x00 0. "FPIF0,configurable event inputs x falling edge pending bit" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SECCFGR1,EXTI security configuration register"
|
|
bitfld.long 0x00 31. "SEC31,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 30. "SEC30,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 29. "SEC29,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 28. "SEC28,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 27. "SEC27,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 26. "SEC26,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 25. "SEC25,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 24. "SEC24,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 23. "SEC23,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 22. "SEC22,Security enable on event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "SEC21,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 20. "SEC20,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 19. "SEC19,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 18. "SEC18,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 17. "SEC17,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 16. "SEC16,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 15. "SEC15,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,Security enable on event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "SEC11,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 5. "SEC5,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,Security enable on event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SEC1,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,Security enable on event input x" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PRIVCFGR1,EXTI privilege configuration register"
|
|
bitfld.long 0x00 31. "PRIV31,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 30. "PRIV30,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 29. "PRIV29,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 28. "PRIV28,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 27. "PRIV27,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 26. "PRIV26,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 25. "PRIV25,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 24. "PRIV24,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 23. "PRIV23,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 22. "PRIV22,Security enable on event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "PRIV21,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 20. "PRIV20,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 19. "PRIV19,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 18. "PRIV18,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 17. "PRIV17,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 16. "PRIV16,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 15. "PRIV15,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 14. "PRIV14,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 13. "PRIV13,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 12. "PRIV12,Security enable on event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "PRIV11,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 10. "PRIV10,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 9. "PRIV9,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 8. "PRIV8,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 7. "PRIV7,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 6. "PRIV6,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 5. "PRIV5,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 4. "PRIV4,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 3. "PRIV3,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 2. "PRIV2,Security enable on event input x" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PRIV1,Security enable on event input x" "0,1"
|
|
bitfld.long 0x00 0. "PRIV0,Security enable on event input x" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTSR2,EXTI rising trigger selection register"
|
|
bitfld.long 0x00 6. "RT38,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 5. "RT37,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 4. "RT36,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
bitfld.long 0x00 3. "RT35,Rising trigger event configuration bit of configurable event input x" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FTSR2,EXTI falling trigger selection register"
|
|
bitfld.long 0x00 6. "FT38,FT38" "0,1"
|
|
bitfld.long 0x00 5. "FT37,FT37" "0,1"
|
|
bitfld.long 0x00 4. "FT36,FT36" "0,1"
|
|
bitfld.long 0x00 3. "FT35,FT35" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SWIER2,EXTI software interrupt event register"
|
|
bitfld.long 0x00 6. "SWI38,SWI38" "0,1"
|
|
bitfld.long 0x00 5. "SWI37,SWI37" "0,1"
|
|
bitfld.long 0x00 4. "SWI36,SWI36" "0,1"
|
|
bitfld.long 0x00 3. "SWI35,SWI35" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RPR2,EXTI rising edge pending register"
|
|
bitfld.long 0x00 6. "RPIF38,RPIF38" "0,1"
|
|
bitfld.long 0x00 5. "RPIF37,RPIF37" "0,1"
|
|
bitfld.long 0x00 4. "RPIF36,RPIF36" "0,1"
|
|
bitfld.long 0x00 3. "RPIF35,RPIF35" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FPR2,EXTI falling edge pending register"
|
|
bitfld.long 0x00 6. "FPIF38,FPIF38" "0,1"
|
|
bitfld.long 0x00 5. "FPIF37,FPIF37" "0,1"
|
|
bitfld.long 0x00 4. "FPIF36,FPIF36" "0,1"
|
|
bitfld.long 0x00 3. "FPIF35,FPIF35" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SECCFGR2,EXTI security enable register"
|
|
bitfld.long 0x00 10. "SEC42,SEC42" "0,1"
|
|
bitfld.long 0x00 9. "SEC41,SEC41" "0,1"
|
|
bitfld.long 0x00 8. "SEC40,SEC40" "0,1"
|
|
bitfld.long 0x00 7. "SEC39,SEC39" "0,1"
|
|
bitfld.long 0x00 6. "SEC38,SEC38" "0,1"
|
|
bitfld.long 0x00 5. "SEC37,SEC37" "0,1"
|
|
bitfld.long 0x00 4. "SEC36,SEC36" "0,1"
|
|
bitfld.long 0x00 3. "SEC35,SEC35" "0,1"
|
|
bitfld.long 0x00 2. "SEC34,SEC34" "0,1"
|
|
bitfld.long 0x00 1. "SEC33,SEC33" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SEC32,SEC32" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PRIVCFGR2,EXTI security enable register"
|
|
bitfld.long 0x00 10. "PRIV42,PRIV42" "0,1"
|
|
bitfld.long 0x00 9. "PRIV41,PRIV41" "0,1"
|
|
bitfld.long 0x00 8. "PRIV40,PRIV40" "0,1"
|
|
bitfld.long 0x00 7. "PRIV39,PRIV39" "0,1"
|
|
bitfld.long 0x00 6. "PRIV38,PRIV38" "0,1"
|
|
bitfld.long 0x00 5. "PRIV37,PRIV37" "0,1"
|
|
bitfld.long 0x00 4. "PRIV36,PRIV36" "0,1"
|
|
bitfld.long 0x00 3. "PRIV35,PRIV35" "0,1"
|
|
bitfld.long 0x00 2. "PRIV34,PRIV34" "0,1"
|
|
bitfld.long 0x00 1. "PRIV33,PRIV33" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PRIV32,PRIV32" "0,1"
|
|
repeat 4. (strings "1" "2" "3" "4" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "EXTICR$1,EXTI external interrupt selection register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTI24_31,EXTIm+3 GPIO port selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EXTI16_23,EXTIm+2 GPIO port selection"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXTI8_15,EXTIm+1 GPIO port selection"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EXTI0_7,EXTIm GPIO port selection"
|
|
repeat.end
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "LOCKRG,EXTI lock register"
|
|
bitfld.long 0x00 0. "LOCK,LOCK" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "IMR1,EXTI CPU wakeup with interrupt mask register"
|
|
bitfld.long 0x00 31. "IM31,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 30. "IM30,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 29. "IM29,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 28. "IM28,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 27. "IM27,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 26. "IM26,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 25. "IM25,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 24. "IM24,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 23. "IM23,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 22. "IM22,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "IM21,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 20. "IM20,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 19. "IM19,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 18. "IM18,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 17. "IM17,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 16. "IM16,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 15. "IM15,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 14. "IM14,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 13. "IM13,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 12. "IM12,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "IM11,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 10. "IM10,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 9. "IM9,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 8. "IM8,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 7. "IM7,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 6. "IM6,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 5. "IM5,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 4. "IM4,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 3. "IM3,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 2. "IM2,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IM1,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 0. "IM0,CPU wakeup with interrupt mask on event input" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "EMR1,EXTI CPU wakeup with event mask register"
|
|
bitfld.long 0x00 31. "EM31,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 30. "EM30,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 29. "EM29,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 28. "EM28,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 27. "EM27,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 26. "EM26,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 25. "EM25,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 24. "EM24,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 23. "EM23,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 22. "EM22,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "EM21,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 20. "EM20,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 19. "EM19,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 18. "EM18,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 17. "EM17,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 16. "EM16,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 15. "EM15,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 14. "EM14,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 13. "EM13,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 12. "EM12,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "EM11,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 10. "EM10,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 9. "EM9,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 8. "EM8,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 7. "EM7,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 6. "EM6,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 5. "EM5,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 4. "EM4,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 3. "EM3,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 2. "EM2,CPU wakeup with interrupt mask on event input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EM1,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 0. "EM0,CPU wakeup with interrupt mask on event input" "0,1"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "IMR2,EXTI CPUm wakeup with interrupt mask register"
|
|
bitfld.long 0x00 10. "IM42,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 9. "IM41,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 8. "IM40,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 6. "IM38,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 5. "IM37,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 4. "IM36,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 3. "IM35,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 2. "IM34,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 1. "IM33,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 0. "IM32,CPU wakeup with interrupt mask on event input" "0,1"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "EMR2,EXTI CPU wakeup with event mask register"
|
|
bitfld.long 0x00 10. "EM42,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 9. "EM41,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 8. "EM40,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 6. "EM38,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 5. "EM37,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 4. "EM36,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 3. "EM35,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 2. "EM34,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 1. "EM33,CPU wakeup with interrupt mask on event input" "0,1"
|
|
bitfld.long 0x00 0. "EM32,CPU wakeup with interrupt mask on event input" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "FDCAN (FDCAN1)"
|
|
tree "FDCAN1"
|
|
base ad:0x4000A400
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "FDCAN_CREL,FDCAN Core Release Register"
|
|
bitfld.long 0x00 28.--31. "REL,Core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "STEP,Step of Core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-step of Core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "YEAR,Timestamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "MON,Timestamp Month"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAY,Timestamp Day"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FDCAN_ENDN,FDCAN Core Release Register"
|
|
hexmask.long 0x00 0.--31. 1. "ETV,Endiannes Test Value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x00 23. "TDC,Transceiver Delay Compensation" "0,1"
|
|
bitfld.long 0x00 16.--20. "DBRP,Data BIt Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. "DTSEG1,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DSJW,Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FDCAN_TEST,FDCAN Test Register"
|
|
rbitfld.long 0x00 7. "RX,Control of Transmit Pin" "0,1"
|
|
bitfld.long 0x00 5.--6. "TX,Loop Back mode" "0,1,2,3"
|
|
bitfld.long 0x00 4. "LBCK,Loop Back mode" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FDCAN_RWD,FDCAN RAM Watchdog Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WDC,Watchdog configuration"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FDCAN_CCCR,FDCAN CC Control Register"
|
|
bitfld.long 0x00 15. "NISO,Non ISO Operation" "0,1"
|
|
bitfld.long 0x00 14. "TXP,TXP" "0,1"
|
|
bitfld.long 0x00 13. "EFBI,Edge Filtering during Bus Integration" "0,1"
|
|
bitfld.long 0x00 12. "PXHD,Protocol Exception Handling Disable" "0,1"
|
|
bitfld.long 0x00 9. "BSE,FDCAN Bit Rate Switching" "0,1"
|
|
bitfld.long 0x00 8. "FDOE,FD Operation Enable" "0,1"
|
|
bitfld.long 0x00 7. "TEST,Test Mode Enable" "0,1"
|
|
bitfld.long 0x00 6. "DAR,Disable Automatic Retransmission" "0,1"
|
|
bitfld.long 0x00 5. "MON,Bus Monitoring Mode" "0,1"
|
|
bitfld.long 0x00 4. "CSR,Clock Stop Request" "0,1"
|
|
bitfld.long 0x00 3. "CSA,Clock Stop Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ASM,ASM Restricted Operation Mode" "0,1"
|
|
bitfld.long 0x00 1. "CCE,Configuration Change Enable" "0,1"
|
|
bitfld.long 0x00 0. "INIT,Initialization" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump Width"
|
|
hexmask.long.word 0x00 16.--24. 1. "NBRP,Bit Rate Prescaler"
|
|
hexmask.long.byte 0x00 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
|
|
hexmask.long.byte 0x00 0.--6. 1. "TSEG2,Nominal Time segment after sample point"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration Register"
|
|
bitfld.long 0x00 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "TSS,Timestamp Select" "0,1,2,3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FDCAN_TSCV,FDCAN Timestamp Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TSC,Timestamp Counter"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FDCAN_TOCC,FDCAN Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x00 1.--2. "TOS,Timeout Select" "0,1,2,3"
|
|
bitfld.long 0x00 0. "ETOC,Enable Timeout Counter" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FDCAN_TOCV,FDCAN Timeout Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TOC,Timeout Counter"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FDCAN_ECR,FDCAN Error Counter Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CEL,AN Error Logging"
|
|
bitfld.long 0x00 15. "RP,Receive Error Passive" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FDCAN_PSR,FDCAN Protocol Status Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x00 14. "PXE,Protocol Exception Event" "0,1"
|
|
bitfld.long 0x00 13. "REDL,Received FDCAN Message" "0,1"
|
|
bitfld.long 0x00 12. "RBRS,BRS flag of last received FDCAN Message" "0,1"
|
|
bitfld.long 0x00 11. "RESI,ESI flag of last received FDCAN Message" "0,1"
|
|
bitfld.long 0x00 8.--10. "DLEC,Data Last Error Code" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 7. "BO,Bus_Off Status" "0,1"
|
|
rbitfld.long 0x00 6. "EW,Warning Status" "0,1"
|
|
rbitfld.long 0x00 5. "EP,Error Passive" "0,1"
|
|
rbitfld.long 0x00 3.--4. "ACT,Activity" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x00 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FDCAN_IR,FDCAN Interrupt Register"
|
|
bitfld.long 0x00 23. "ARA,ARA" "0,1"
|
|
bitfld.long 0x00 22. "PED,PED" "0,1"
|
|
bitfld.long 0x00 21. "PEA,PEA" "0,1"
|
|
bitfld.long 0x00 20. "WDI,WDI" "0,1"
|
|
bitfld.long 0x00 19. "BO,BO" "0,1"
|
|
bitfld.long 0x00 18. "EW,EW" "0,1"
|
|
bitfld.long 0x00 17. "EP,EP" "0,1"
|
|
bitfld.long 0x00 16. "ELO,ELO" "0,1"
|
|
bitfld.long 0x00 15. "TOO,TOO" "0,1"
|
|
bitfld.long 0x00 14. "MRAF,MRAF" "0,1"
|
|
bitfld.long 0x00 13. "TSW,TSW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "TEFL,TEFL" "0,1"
|
|
bitfld.long 0x00 11. "TEFF,TEFF" "0,1"
|
|
bitfld.long 0x00 10. "TEFN,TEFN" "0,1"
|
|
bitfld.long 0x00 9. "TFE,TFE" "0,1"
|
|
bitfld.long 0x00 8. "TCF,TCF" "0,1"
|
|
bitfld.long 0x00 7. "TC,TC" "0,1"
|
|
bitfld.long 0x00 6. "HPM,HPM" "0,1"
|
|
bitfld.long 0x00 5. "RF1L,RF1L" "0,1"
|
|
bitfld.long 0x00 4. "RF1F,RF1F" "0,1"
|
|
bitfld.long 0x00 3. "RF1N,RF1N" "0,1"
|
|
bitfld.long 0x00 2. "RF0L,RF0L" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RF0F,RF0F" "0,1"
|
|
bitfld.long 0x00 0. "RF0N,RF0N" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FDCAN_IE,FDCAN Interrupt Enable Register"
|
|
bitfld.long 0x00 22. "ARAE,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x00 21. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
bitfld.long 0x00 20. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x00 19. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 18. "BOE,Bus_Off Status Enable" "0,1"
|
|
bitfld.long 0x00 17. "EWE,Warning Status Enable" "0,1"
|
|
bitfld.long 0x00 16. "EPE,Error Passive Enable" "0,1"
|
|
bitfld.long 0x00 15. "ELOE,Error Logging Overflow Enable" "0,1"
|
|
bitfld.long 0x00 14. "TOOE,Timeout Occurred Enable" "0,1"
|
|
bitfld.long 0x00 13. "MRAFE,Message RAM Access Failure Enable" "0,1"
|
|
bitfld.long 0x00 12. "TEFLE,Tx Event FIFO Element Lost Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "TEFFE,Tx Event FIFO Full Enable" "0,1"
|
|
bitfld.long 0x00 10. "TEFNE,Tx Event FIFO New Entry Enable" "0,1"
|
|
bitfld.long 0x00 9. "TEFE,Tx FIFO Empty Enable" "0,1"
|
|
bitfld.long 0x00 8. "TCFE,Transmission Cancellation Finished Enable" "0,1"
|
|
bitfld.long 0x00 7. "TCE,Transmission Completed Enable" "0,1"
|
|
bitfld.long 0x00 6. "HPME,High Priority Message Enable" "0,1"
|
|
bitfld.long 0x00 5. "RF1LE,Rx FIFO 1 Message Lost Enable" "0,1"
|
|
bitfld.long 0x00 4. "RF1FE,Rx FIFO 1 Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x00 3. "RF1NE,Rx FIFO 1 New Message Enable" "0,1"
|
|
bitfld.long 0x00 2. "RF0LE,Rx FIFO 0 Message Lost Enable" "0,1"
|
|
bitfld.long 0x00 1. "RF0FE,Rx FIFO 0 Full Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RF0NE,Rx FIFO 0 New Message Enable" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FDCAN_ILS,FDCAN Interrupt Line Select Register"
|
|
bitfld.long 0x00 6. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 5. "BERR,BERR" "0,1"
|
|
bitfld.long 0x00 4. "MISC,MISC" "0,1"
|
|
bitfld.long 0x00 3. "TFERR,TFERR" "0,1"
|
|
bitfld.long 0x00 2. "SMSG,SMSG" "0,1"
|
|
bitfld.long 0x00 1. "RxFIFO1,RxFIFO1" "0,1"
|
|
bitfld.long 0x00 0. "RxFIFO0,RxFIFO0" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "FDCAN_ILE,FDCAN Interrupt Line Enable Register"
|
|
bitfld.long 0x00 1. "EINT1,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0x00 0. "EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FDCAN_RXGFC,FDCAN Global Filter Configuration Register"
|
|
bitfld.long 0x00 24.--27. "LSE,LSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. "LSS,LSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. "F0OM,F0OM" "0,1"
|
|
bitfld.long 0x00 8. "F1OM,F1OM" "0,1"
|
|
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
|
|
bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "0,1"
|
|
bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FDCAN_XIDAM,FDCAN Extended ID and Mask Register"
|
|
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FDCAN_HPMS,FDCAN High Priority Message Status Register"
|
|
bitfld.long 0x00 15. "FLST,Filter List" "0,1"
|
|
bitfld.long 0x00 8.--12. "FIDX,Filter Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. "MSI,Message Storage Indicator" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status Register"
|
|
bitfld.long 0x00 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x00 24. "F0F,Rx FIFO 0 Full" "0,1"
|
|
bitfld.long 0x00 16.--17. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "F0FL,Rx FIFO 0 Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge Register"
|
|
bitfld.long 0x00 0.--2. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status Register"
|
|
rbitfld.long 0x00 25. "RF1L,Rx FIFO 1 Message Lost" "0,1"
|
|
rbitfld.long 0x00 24. "F1F,Rx FIFO 1 Full" "0,1"
|
|
rbitfld.long 0x00 16.--17. "F1PI,Rx FIFO 1 Put Index" "0,1,2,3"
|
|
rbitfld.long 0x00 8.--9. "F1GI,Rx FIFO 1 Get Index" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "F1FL,Rx FIFO 1 Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge Register"
|
|
bitfld.long 0x00 0.--2. "F1AI,Rx FIFO 1 Acknowledge Index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status Register"
|
|
bitfld.long 0x00 21. "TFQF,Tx FIFO/Queue Full" "0,1"
|
|
bitfld.long 0x00 16.--17. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "TFGI,TFGI" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending Register"
|
|
bitfld.long 0x00 0.--2. "TRP,Transmission Request Pending" "0,1,2,3,4,5,6,7"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request Register"
|
|
bitfld.long 0x00 0.--2. "AR,Add Request" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x00 0.--2. "CR,Cancellation Request" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred Register"
|
|
bitfld.long 0x00 0.--2. "TO,Transmission Occurred" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished Register"
|
|
bitfld.long 0x00 0.--2. "CF,Cancellation Finished" "0,1,2,3,4,5,6,7"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x00 0.--2. "TIE,Transmission Interrupt Enable" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x00 0.--2. "CF,Cancellation Finished Interrupt Enable" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status Register"
|
|
bitfld.long 0x00 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x00 24. "EFF,Event FIFO Full" "0,1"
|
|
bitfld.long 0x00 16.--17. "EFPI,Event FIFO Put Index" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "EFGI,Event FIFO Get Index" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "EFFL,Event FIFO Fill Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge Register"
|
|
bitfld.long 0x00 0.--1. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FDCAN_CKDIV,FDCAN TT Trigger Memory Configuration Register"
|
|
bitfld.long 0x00 0.--3. "PDIV,PDIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x00 24. "TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
tree.end
|
|
tree "SEC_FDCAN1"
|
|
base ad:0x5000A400
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "FDCAN_CREL,FDCAN Core Release Register"
|
|
bitfld.long 0x00 28.--31. "REL,Core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "STEP,Step of Core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-step of Core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "YEAR,Timestamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "MON,Timestamp Month"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAY,Timestamp Day"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FDCAN_ENDN,FDCAN Core Release Register"
|
|
hexmask.long 0x00 0.--31. 1. "ETV,Endiannes Test Value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x00 23. "TDC,Transceiver Delay Compensation" "0,1"
|
|
bitfld.long 0x00 16.--20. "DBRP,Data BIt Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. "DTSEG1,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DSJW,Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FDCAN_TEST,FDCAN Test Register"
|
|
rbitfld.long 0x00 7. "RX,Control of Transmit Pin" "0,1"
|
|
bitfld.long 0x00 5.--6. "TX,Loop Back mode" "0,1,2,3"
|
|
bitfld.long 0x00 4. "LBCK,Loop Back mode" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FDCAN_RWD,FDCAN RAM Watchdog Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WDC,Watchdog configuration"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FDCAN_CCCR,FDCAN CC Control Register"
|
|
bitfld.long 0x00 15. "NISO,Non ISO Operation" "0,1"
|
|
bitfld.long 0x00 14. "TXP,TXP" "0,1"
|
|
bitfld.long 0x00 13. "EFBI,Edge Filtering during Bus Integration" "0,1"
|
|
bitfld.long 0x00 12. "PXHD,Protocol Exception Handling Disable" "0,1"
|
|
bitfld.long 0x00 9. "BSE,FDCAN Bit Rate Switching" "0,1"
|
|
bitfld.long 0x00 8. "FDOE,FD Operation Enable" "0,1"
|
|
bitfld.long 0x00 7. "TEST,Test Mode Enable" "0,1"
|
|
bitfld.long 0x00 6. "DAR,Disable Automatic Retransmission" "0,1"
|
|
bitfld.long 0x00 5. "MON,Bus Monitoring Mode" "0,1"
|
|
bitfld.long 0x00 4. "CSR,Clock Stop Request" "0,1"
|
|
bitfld.long 0x00 3. "CSA,Clock Stop Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ASM,ASM Restricted Operation Mode" "0,1"
|
|
bitfld.long 0x00 1. "CCE,Configuration Change Enable" "0,1"
|
|
bitfld.long 0x00 0. "INIT,Initialization" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump Width"
|
|
hexmask.long.word 0x00 16.--24. 1. "NBRP,Bit Rate Prescaler"
|
|
hexmask.long.byte 0x00 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
|
|
hexmask.long.byte 0x00 0.--6. 1. "TSEG2,Nominal Time segment after sample point"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration Register"
|
|
bitfld.long 0x00 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "TSS,Timestamp Select" "0,1,2,3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FDCAN_TSCV,FDCAN Timestamp Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TSC,Timestamp Counter"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FDCAN_TOCC,FDCAN Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x00 1.--2. "TOS,Timeout Select" "0,1,2,3"
|
|
bitfld.long 0x00 0. "ETOC,Enable Timeout Counter" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FDCAN_TOCV,FDCAN Timeout Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TOC,Timeout Counter"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FDCAN_ECR,FDCAN Error Counter Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CEL,AN Error Logging"
|
|
bitfld.long 0x00 15. "RP,Receive Error Passive" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FDCAN_PSR,FDCAN Protocol Status Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x00 14. "PXE,Protocol Exception Event" "0,1"
|
|
bitfld.long 0x00 13. "REDL,Received FDCAN Message" "0,1"
|
|
bitfld.long 0x00 12. "RBRS,BRS flag of last received FDCAN Message" "0,1"
|
|
bitfld.long 0x00 11. "RESI,ESI flag of last received FDCAN Message" "0,1"
|
|
bitfld.long 0x00 8.--10. "DLEC,Data Last Error Code" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 7. "BO,Bus_Off Status" "0,1"
|
|
rbitfld.long 0x00 6. "EW,Warning Status" "0,1"
|
|
rbitfld.long 0x00 5. "EP,Error Passive" "0,1"
|
|
rbitfld.long 0x00 3.--4. "ACT,Activity" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x00 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FDCAN_IR,FDCAN Interrupt Register"
|
|
bitfld.long 0x00 23. "ARA,ARA" "0,1"
|
|
bitfld.long 0x00 22. "PED,PED" "0,1"
|
|
bitfld.long 0x00 21. "PEA,PEA" "0,1"
|
|
bitfld.long 0x00 20. "WDI,WDI" "0,1"
|
|
bitfld.long 0x00 19. "BO,BO" "0,1"
|
|
bitfld.long 0x00 18. "EW,EW" "0,1"
|
|
bitfld.long 0x00 17. "EP,EP" "0,1"
|
|
bitfld.long 0x00 16. "ELO,ELO" "0,1"
|
|
bitfld.long 0x00 15. "TOO,TOO" "0,1"
|
|
bitfld.long 0x00 14. "MRAF,MRAF" "0,1"
|
|
bitfld.long 0x00 13. "TSW,TSW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "TEFL,TEFL" "0,1"
|
|
bitfld.long 0x00 11. "TEFF,TEFF" "0,1"
|
|
bitfld.long 0x00 10. "TEFN,TEFN" "0,1"
|
|
bitfld.long 0x00 9. "TFE,TFE" "0,1"
|
|
bitfld.long 0x00 8. "TCF,TCF" "0,1"
|
|
bitfld.long 0x00 7. "TC,TC" "0,1"
|
|
bitfld.long 0x00 6. "HPM,HPM" "0,1"
|
|
bitfld.long 0x00 5. "RF1L,RF1L" "0,1"
|
|
bitfld.long 0x00 4. "RF1F,RF1F" "0,1"
|
|
bitfld.long 0x00 3. "RF1N,RF1N" "0,1"
|
|
bitfld.long 0x00 2. "RF0L,RF0L" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RF0F,RF0F" "0,1"
|
|
bitfld.long 0x00 0. "RF0N,RF0N" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FDCAN_IE,FDCAN Interrupt Enable Register"
|
|
bitfld.long 0x00 22. "ARAE,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x00 21. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
bitfld.long 0x00 20. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x00 19. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 18. "BOE,Bus_Off Status Enable" "0,1"
|
|
bitfld.long 0x00 17. "EWE,Warning Status Enable" "0,1"
|
|
bitfld.long 0x00 16. "EPE,Error Passive Enable" "0,1"
|
|
bitfld.long 0x00 15. "ELOE,Error Logging Overflow Enable" "0,1"
|
|
bitfld.long 0x00 14. "TOOE,Timeout Occurred Enable" "0,1"
|
|
bitfld.long 0x00 13. "MRAFE,Message RAM Access Failure Enable" "0,1"
|
|
bitfld.long 0x00 12. "TEFLE,Tx Event FIFO Element Lost Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "TEFFE,Tx Event FIFO Full Enable" "0,1"
|
|
bitfld.long 0x00 10. "TEFNE,Tx Event FIFO New Entry Enable" "0,1"
|
|
bitfld.long 0x00 9. "TEFE,Tx FIFO Empty Enable" "0,1"
|
|
bitfld.long 0x00 8. "TCFE,Transmission Cancellation Finished Enable" "0,1"
|
|
bitfld.long 0x00 7. "TCE,Transmission Completed Enable" "0,1"
|
|
bitfld.long 0x00 6. "HPME,High Priority Message Enable" "0,1"
|
|
bitfld.long 0x00 5. "RF1LE,Rx FIFO 1 Message Lost Enable" "0,1"
|
|
bitfld.long 0x00 4. "RF1FE,Rx FIFO 1 Watermark Reached Enable" "0,1"
|
|
bitfld.long 0x00 3. "RF1NE,Rx FIFO 1 New Message Enable" "0,1"
|
|
bitfld.long 0x00 2. "RF0LE,Rx FIFO 0 Message Lost Enable" "0,1"
|
|
bitfld.long 0x00 1. "RF0FE,Rx FIFO 0 Full Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RF0NE,Rx FIFO 0 New Message Enable" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FDCAN_ILS,FDCAN Interrupt Line Select Register"
|
|
bitfld.long 0x00 6. "PERR,PERR" "0,1"
|
|
bitfld.long 0x00 5. "BERR,BERR" "0,1"
|
|
bitfld.long 0x00 4. "MISC,MISC" "0,1"
|
|
bitfld.long 0x00 3. "TFERR,TFERR" "0,1"
|
|
bitfld.long 0x00 2. "SMSG,SMSG" "0,1"
|
|
bitfld.long 0x00 1. "RxFIFO1,RxFIFO1" "0,1"
|
|
bitfld.long 0x00 0. "RxFIFO0,RxFIFO0" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "FDCAN_ILE,FDCAN Interrupt Line Enable Register"
|
|
bitfld.long 0x00 1. "EINT1,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0x00 0. "EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FDCAN_RXGFC,FDCAN Global Filter Configuration Register"
|
|
bitfld.long 0x00 24.--27. "LSE,LSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. "LSS,LSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. "F0OM,F0OM" "0,1"
|
|
bitfld.long 0x00 8. "F1OM,F1OM" "0,1"
|
|
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
|
|
bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "0,1"
|
|
bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FDCAN_XIDAM,FDCAN Extended ID and Mask Register"
|
|
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "FDCAN_HPMS,FDCAN High Priority Message Status Register"
|
|
bitfld.long 0x00 15. "FLST,Filter List" "0,1"
|
|
bitfld.long 0x00 8.--12. "FIDX,Filter Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--7. "MSI,Message Storage Indicator" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status Register"
|
|
bitfld.long 0x00 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x00 24. "F0F,Rx FIFO 0 Full" "0,1"
|
|
bitfld.long 0x00 16.--17. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "F0FL,Rx FIFO 0 Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge Register"
|
|
bitfld.long 0x00 0.--2. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status Register"
|
|
rbitfld.long 0x00 25. "RF1L,Rx FIFO 1 Message Lost" "0,1"
|
|
rbitfld.long 0x00 24. "F1F,Rx FIFO 1 Full" "0,1"
|
|
rbitfld.long 0x00 16.--17. "F1PI,Rx FIFO 1 Put Index" "0,1,2,3"
|
|
rbitfld.long 0x00 8.--9. "F1GI,Rx FIFO 1 Get Index" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "F1FL,Rx FIFO 1 Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge Register"
|
|
bitfld.long 0x00 0.--2. "F1AI,Rx FIFO 1 Acknowledge Index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status Register"
|
|
bitfld.long 0x00 21. "TFQF,Tx FIFO/Queue Full" "0,1"
|
|
bitfld.long 0x00 16.--17. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "TFGI,TFGI" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending Register"
|
|
bitfld.long 0x00 0.--2. "TRP,Transmission Request Pending" "0,1,2,3,4,5,6,7"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request Register"
|
|
bitfld.long 0x00 0.--2. "AR,Add Request" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x00 0.--2. "CR,Cancellation Request" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred Register"
|
|
bitfld.long 0x00 0.--2. "TO,Transmission Occurred" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished Register"
|
|
bitfld.long 0x00 0.--2. "CF,Cancellation Finished" "0,1,2,3,4,5,6,7"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x00 0.--2. "TIE,Transmission Interrupt Enable" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x00 0.--2. "CF,Cancellation Finished Interrupt Enable" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status Register"
|
|
bitfld.long 0x00 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x00 24. "EFF,Event FIFO Full" "0,1"
|
|
bitfld.long 0x00 16.--17. "EFPI,Event FIFO Put Index" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "EFGI,Event FIFO Get Index" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "EFFL,Event FIFO Fill Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge Register"
|
|
bitfld.long 0x00 0.--1. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FDCAN_CKDIV,FDCAN TT Trigger Memory Configuration Register"
|
|
bitfld.long 0x00 0.--3. "PDIV,PDIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x00 24. "TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "FLASH (Flash)"
|
|
tree "FLASH"
|
|
base ad:0x40022000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ACR,Access control register"
|
|
bitfld.long 0x00 15. "LVEN,LVEN" "0,1"
|
|
bitfld.long 0x00 14. "SLEEP_PD,Flash Power-down mode during Low-power sleep mode" "0,1"
|
|
bitfld.long 0x00 13. "RUN_PD,Flash Power-down mode during Low-power run mode" "0,1"
|
|
bitfld.long 0x00 0.--3. "LATENCY,Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "PDKEYR,Power down key register"
|
|
hexmask.long 0x00 0.--31. 1. "PDKEYR,RUN_PD in FLASH_ACR key"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "NSKEYR,Flash non-secure key register"
|
|
hexmask.long 0x00 0.--31. 1. "NSKEYR,NSKEYR"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SECKEYR,Flash secure key register"
|
|
hexmask.long 0x00 0.--31. 1. "SECKEYR,SECKEYR"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "OPTKEYR,Flash option key register"
|
|
hexmask.long 0x00 0.--31. 1. "OPTKEYR,OPTKEYR"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "LVEKEYR,Flash low voltage key register"
|
|
hexmask.long 0x00 0.--31. 1. "LVEKEYR,LVEKEYR"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "NSSR,Flash status register"
|
|
rbitfld.long 0x00 16. "NSBSY,NSBusy" "0,1"
|
|
bitfld.long 0x00 15. "OPTVERR,OPTVERR" "0,1"
|
|
bitfld.long 0x00 13. "OPTWERR,OPTWERR" "0,1"
|
|
bitfld.long 0x00 7. "NSPGSERR,NSPGSERR" "0,1"
|
|
bitfld.long 0x00 6. "NSSIZERR,NSSIZERR" "0,1"
|
|
bitfld.long 0x00 5. "NSPGAERR,NSPGAERR" "0,1"
|
|
bitfld.long 0x00 4. "NSWRPERR,NSWRPERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "NSPROGERR,NSPROGERR" "0,1"
|
|
bitfld.long 0x00 1. "NSOPERR,NSOPERR" "0,1"
|
|
bitfld.long 0x00 0. "NSEOP,NSEOP" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SECSR,Flash status register"
|
|
rbitfld.long 0x00 16. "SECBSY,SECBusy" "0,1"
|
|
bitfld.long 0x00 14. "SECRDERR,Secure read protection error" "0,1"
|
|
bitfld.long 0x00 7. "SECPGSERR,SECPGSERR" "0,1"
|
|
bitfld.long 0x00 6. "SECSIZERR,SECSIZERR" "0,1"
|
|
bitfld.long 0x00 5. "SECPGAERR,SECPGAERR" "0,1"
|
|
bitfld.long 0x00 4. "SECWRPERR,SECWRPERR" "0,1"
|
|
bitfld.long 0x00 3. "SECPROGERR,SECPROGERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SECOPERR,SECOPERR" "0,1"
|
|
bitfld.long 0x00 0. "SECEOP,SECEOP" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "NSCR,Flash non-secure control register"
|
|
bitfld.long 0x00 31. "NSLOCK,NSLOCK" "0,1"
|
|
bitfld.long 0x00 30. "OPTLOCK,Options Lock" "0,1"
|
|
bitfld.long 0x00 27. "OBL_LAUNCH,Force the option byte loading" "0,1"
|
|
bitfld.long 0x00 25. "NSERRIE,NSERRIE" "0,1"
|
|
bitfld.long 0x00 24. "NSEOPIE,NSEOPIE" "0,1"
|
|
bitfld.long 0x00 17. "OPTSTRT,Options modification start" "0,1"
|
|
bitfld.long 0x00 16. "NSSTRT,Options modification start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "NSMER2,NSMER2" "0,1"
|
|
bitfld.long 0x00 11. "NSBKER,NSBKER" "0,1"
|
|
hexmask.long.byte 0x00 3.--9. 1. "NSPNB,NSPNB"
|
|
bitfld.long 0x00 2. "NSMER1,NSMER1" "0,1"
|
|
bitfld.long 0x00 1. "NSPER,NSPER" "0,1"
|
|
bitfld.long 0x00 0. "NSPG,NSPG" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SECCR,Flash secure control register"
|
|
bitfld.long 0x00 31. "SECLOCK,SECLOCK" "0,1"
|
|
bitfld.long 0x00 29. "SECINV,SECINV" "0,1"
|
|
bitfld.long 0x00 26. "SECRDERRIE,SECRDERRIE" "0,1"
|
|
bitfld.long 0x00 25. "SECERRIE,SECERRIE" "0,1"
|
|
bitfld.long 0x00 24. "SECEOPIE,SECEOPIE" "0,1"
|
|
bitfld.long 0x00 16. "SECSTRT,SECSTRT" "0,1"
|
|
bitfld.long 0x00 15. "SECMER2,SECMER2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "SECBKER,SECBKER" "0,1"
|
|
hexmask.long.byte 0x00 3.--9. 1. "SECPNB,SECPNB"
|
|
bitfld.long 0x00 2. "SECMER1,SECMER1" "0,1"
|
|
bitfld.long 0x00 1. "SECPER,SECPER" "0,1"
|
|
bitfld.long 0x00 0. "SECPG,SECPG" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ECCR,Flash ECC register"
|
|
bitfld.long 0x00 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x00 30. "ECCC,ECC correction" "0,1"
|
|
bitfld.long 0x00 29. "ECCD2,ECCD2" "0,1"
|
|
bitfld.long 0x00 28. "ECCC2,ECCC2" "0,1"
|
|
bitfld.long 0x00 24. "ECCIE,ECC correction interrupt enable" "0,1"
|
|
rbitfld.long 0x00 22. "SYSF_ECC,SYSF_ECC" "0,1"
|
|
rbitfld.long 0x00 21. "BK_ECC,BK_ECC" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--18. 1. "ADDR_ECC,ECC fail address"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "OPTR,Flash option register"
|
|
bitfld.long 0x00 31. "TZEN,TZEN" "0,1"
|
|
bitfld.long 0x00 28. "PA15_PUPEN,PA15_PUPEN" "0,1"
|
|
bitfld.long 0x00 27. "nBOOT0,nBOOT0" "0,1"
|
|
bitfld.long 0x00 26. "nSWBOOT0,nSWBOOT0" "0,1"
|
|
bitfld.long 0x00 25. "SRAM2_RST,SRAM2 Erase when system reset" "0,1"
|
|
bitfld.long 0x00 24. "SRAM2_PE,SRAM2 parity check enable" "0,1"
|
|
bitfld.long 0x00 22. "DBANK,DBANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "DB256K,DB256K" "0,1"
|
|
bitfld.long 0x00 20. "SWAP_BANK,SWAP_BANK" "0,1"
|
|
bitfld.long 0x00 19. "WWDG_SW,Window watchdog selection" "0,1"
|
|
bitfld.long 0x00 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0,1"
|
|
bitfld.long 0x00 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0,1"
|
|
bitfld.long 0x00 16. "IWDG_SW,Independent watchdog selection" "0,1"
|
|
bitfld.long 0x00 14. "nRST_SHDW,nRST_SHDW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "nRST_STDBY,nRST_STDBY" "0,1"
|
|
bitfld.long 0x00 12. "nRST_STOP,nRST_STOP" "0,1"
|
|
bitfld.long 0x00 8.--10. "BOR_LEV,BOR reset Level" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RDP,Read protection level"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "NSBOOTADD0R,Flash non-secure boot address 0 register"
|
|
hexmask.long 0x00 7.--31. 1. "NSBOOTADD0,NSBOOTADD0"
|
|
wgroup.long 0x48++0x03
|
|
line.long 0x00 "NSBOOTADD1R,Flash non-secure boot address 1 register"
|
|
hexmask.long 0x00 7.--31. 1. "NSBOOTADD1,NSBOOTADD1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SECBOOTADD0R,FFlash secure boot address 0 register"
|
|
hexmask.long 0x00 7.--31. 1. "SECBOOTADD0,SECBOOTADD0"
|
|
bitfld.long 0x00 0. "BOOT_LOCK,BOOT_LOCK" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SECWM1R1,Flash bank 1 secure watermak1 register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "SECWM1_PEND,SECWM1_PEND"
|
|
hexmask.long.byte 0x00 0.--6. 1. "SECWM1_PSTRT,SECWM1_PSTRT"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SECWM1R2,Flash secure watermak1 register 2"
|
|
bitfld.long 0x00 31. "HDP1EN,HDP1EN" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "HDP1_PEND,HDP1_PEND"
|
|
bitfld.long 0x00 15. "PCROP1EN,PCROP1EN" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "PCROP1_PSTRT,PCROP1_PSTRT"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "WRP1AR,Flash Bank 1 WRP area A address register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "WRP1A_PEND,WRP1A_PEND"
|
|
hexmask.long.byte 0x00 0.--6. 1. "WRP1A_PSTRT,WRP1A_PSTRT"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "WRP1BR,Flash Bank 1 WRP area B address register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "WRP1B_PEND,WRP1B_PEND"
|
|
hexmask.long.byte 0x00 0.--6. 1. "WRP1B_PSTRT,WRP1B_PSTRT"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SECWM2R1,Flash secure watermak2 register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "SECWM2_PEND,SECWM2_PEND"
|
|
hexmask.long.byte 0x00 0.--6. 1. "SECWM2_PSTRT,SECWM2_PSTRT"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SECWM2R2,Flash secure watermak2 register2"
|
|
bitfld.long 0x00 31. "HDP2EN,HDP2EN" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "HDP2_PEND,HDP2_PEND"
|
|
bitfld.long 0x00 15. "PCROP2EN,PCROP2EN" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "PCROP2_PSTRT,PCROP2_PSTRT"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "WRP2AR,Flash WPR2 area A address register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "WRP2A_PEND,WRP2A_PEND"
|
|
hexmask.long.byte 0x00 0.--6. 1. "WRP2A_PSTRT,WRP2A_PSTRT"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "WRP2BR,Flash WPR2 area B address register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "WRP2B_PEND,WRP2B_PEND"
|
|
hexmask.long.byte 0x00 0.--6. 1. "WRP2B_PSTRT,WRP2B_PSTRT"
|
|
repeat 4. (strings "1" "2" "3" "4" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "SECBB1R$1,FLASH secure block based bank 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "SECBB1,SECBB1"
|
|
repeat.end
|
|
repeat 4. (strings "1" "2" "3" "4" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0xA0)++0x03
|
|
line.long 0x00 "SECBB2R$1,FLASH secure block based bank 2 register"
|
|
hexmask.long 0x00 0.--31. 1. "SECBB2,SECBB2"
|
|
repeat.end
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "SECHDPCR,FLASH secure HDP control register"
|
|
bitfld.long 0x00 1. "HDP2_ACCDIS,HDP2_ACCDIS" "0,1"
|
|
bitfld.long 0x00 0. "HDP1_ACCDIS,HDP1_ACCDIS" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "PRIVCFGR,Power privilege configuration register"
|
|
bitfld.long 0x00 0. "PRIV,PRIV" "0,1"
|
|
tree.end
|
|
tree "SEC_FLASH"
|
|
base ad:0x50022000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ACR,Access control register"
|
|
bitfld.long 0x00 15. "LVEN,LVEN" "0,1"
|
|
bitfld.long 0x00 14. "SLEEP_PD,Flash Power-down mode during Low-power sleep mode" "0,1"
|
|
bitfld.long 0x00 13. "RUN_PD,Flash Power-down mode during Low-power run mode" "0,1"
|
|
bitfld.long 0x00 0.--3. "LATENCY,Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "PDKEYR,Power down key register"
|
|
hexmask.long 0x00 0.--31. 1. "PDKEYR,RUN_PD in FLASH_ACR key"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "NSKEYR,Flash non-secure key register"
|
|
hexmask.long 0x00 0.--31. 1. "NSKEYR,NSKEYR"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SECKEYR,Flash secure key register"
|
|
hexmask.long 0x00 0.--31. 1. "SECKEYR,SECKEYR"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "OPTKEYR,Flash option key register"
|
|
hexmask.long 0x00 0.--31. 1. "OPTKEYR,OPTKEYR"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "LVEKEYR,Flash low voltage key register"
|
|
hexmask.long 0x00 0.--31. 1. "LVEKEYR,LVEKEYR"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "NSSR,Flash status register"
|
|
rbitfld.long 0x00 16. "NSBSY,NSBusy" "0,1"
|
|
bitfld.long 0x00 15. "OPTVERR,OPTVERR" "0,1"
|
|
bitfld.long 0x00 13. "OPTWERR,OPTWERR" "0,1"
|
|
bitfld.long 0x00 7. "NSPGSERR,NSPGSERR" "0,1"
|
|
bitfld.long 0x00 6. "NSSIZERR,NSSIZERR" "0,1"
|
|
bitfld.long 0x00 5. "NSPGAERR,NSPGAERR" "0,1"
|
|
bitfld.long 0x00 4. "NSWRPERR,NSWRPERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "NSPROGERR,NSPROGERR" "0,1"
|
|
bitfld.long 0x00 1. "NSOPERR,NSOPERR" "0,1"
|
|
bitfld.long 0x00 0. "NSEOP,NSEOP" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SECSR,Flash status register"
|
|
rbitfld.long 0x00 16. "SECBSY,SECBusy" "0,1"
|
|
bitfld.long 0x00 14. "SECRDERR,Secure read protection error" "0,1"
|
|
bitfld.long 0x00 7. "SECPGSERR,SECPGSERR" "0,1"
|
|
bitfld.long 0x00 6. "SECSIZERR,SECSIZERR" "0,1"
|
|
bitfld.long 0x00 5. "SECPGAERR,SECPGAERR" "0,1"
|
|
bitfld.long 0x00 4. "SECWRPERR,SECWRPERR" "0,1"
|
|
bitfld.long 0x00 3. "SECPROGERR,SECPROGERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SECOPERR,SECOPERR" "0,1"
|
|
bitfld.long 0x00 0. "SECEOP,SECEOP" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "NSCR,Flash non-secure control register"
|
|
bitfld.long 0x00 31. "NSLOCK,NSLOCK" "0,1"
|
|
bitfld.long 0x00 30. "OPTLOCK,Options Lock" "0,1"
|
|
bitfld.long 0x00 27. "OBL_LAUNCH,Force the option byte loading" "0,1"
|
|
bitfld.long 0x00 25. "NSERRIE,NSERRIE" "0,1"
|
|
bitfld.long 0x00 24. "NSEOPIE,NSEOPIE" "0,1"
|
|
bitfld.long 0x00 17. "OPTSTRT,Options modification start" "0,1"
|
|
bitfld.long 0x00 16. "NSSTRT,Options modification start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "NSMER2,NSMER2" "0,1"
|
|
bitfld.long 0x00 11. "NSBKER,NSBKER" "0,1"
|
|
hexmask.long.byte 0x00 3.--9. 1. "NSPNB,NSPNB"
|
|
bitfld.long 0x00 2. "NSMER1,NSMER1" "0,1"
|
|
bitfld.long 0x00 1. "NSPER,NSPER" "0,1"
|
|
bitfld.long 0x00 0. "NSPG,NSPG" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SECCR,Flash secure control register"
|
|
bitfld.long 0x00 31. "SECLOCK,SECLOCK" "0,1"
|
|
bitfld.long 0x00 29. "SECINV,SECINV" "0,1"
|
|
bitfld.long 0x00 26. "SECRDERRIE,SECRDERRIE" "0,1"
|
|
bitfld.long 0x00 25. "SECERRIE,SECERRIE" "0,1"
|
|
bitfld.long 0x00 24. "SECEOPIE,SECEOPIE" "0,1"
|
|
bitfld.long 0x00 16. "SECSTRT,SECSTRT" "0,1"
|
|
bitfld.long 0x00 15. "SECMER2,SECMER2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "SECBKER,SECBKER" "0,1"
|
|
hexmask.long.byte 0x00 3.--9. 1. "SECPNB,SECPNB"
|
|
bitfld.long 0x00 2. "SECMER1,SECMER1" "0,1"
|
|
bitfld.long 0x00 1. "SECPER,SECPER" "0,1"
|
|
bitfld.long 0x00 0. "SECPG,SECPG" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ECCR,Flash ECC register"
|
|
bitfld.long 0x00 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x00 30. "ECCC,ECC correction" "0,1"
|
|
bitfld.long 0x00 29. "ECCD2,ECCD2" "0,1"
|
|
bitfld.long 0x00 28. "ECCC2,ECCC2" "0,1"
|
|
bitfld.long 0x00 24. "ECCIE,ECC correction interrupt enable" "0,1"
|
|
rbitfld.long 0x00 22. "SYSF_ECC,SYSF_ECC" "0,1"
|
|
rbitfld.long 0x00 21. "BK_ECC,BK_ECC" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--18. 1. "ADDR_ECC,ECC fail address"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "OPTR,Flash option register"
|
|
bitfld.long 0x00 31. "TZEN,TZEN" "0,1"
|
|
bitfld.long 0x00 28. "PA15_PUPEN,PA15_PUPEN" "0,1"
|
|
bitfld.long 0x00 27. "nBOOT0,nBOOT0" "0,1"
|
|
bitfld.long 0x00 26. "nSWBOOT0,nSWBOOT0" "0,1"
|
|
bitfld.long 0x00 25. "SRAM2_RST,SRAM2 Erase when system reset" "0,1"
|
|
bitfld.long 0x00 24. "SRAM2_PE,SRAM2 parity check enable" "0,1"
|
|
bitfld.long 0x00 22. "DBANK,DBANK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "DB256K,DB256K" "0,1"
|
|
bitfld.long 0x00 20. "SWAP_BANK,SWAP_BANK" "0,1"
|
|
bitfld.long 0x00 19. "WWDG_SW,Window watchdog selection" "0,1"
|
|
bitfld.long 0x00 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0,1"
|
|
bitfld.long 0x00 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0,1"
|
|
bitfld.long 0x00 16. "IWDG_SW,Independent watchdog selection" "0,1"
|
|
bitfld.long 0x00 14. "nRST_SHDW,nRST_SHDW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "nRST_STDBY,nRST_STDBY" "0,1"
|
|
bitfld.long 0x00 12. "nRST_STOP,nRST_STOP" "0,1"
|
|
bitfld.long 0x00 8.--10. "BOR_LEV,BOR reset Level" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RDP,Read protection level"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "NSBOOTADD0R,Flash non-secure boot address 0 register"
|
|
hexmask.long 0x00 7.--31. 1. "NSBOOTADD0,NSBOOTADD0"
|
|
wgroup.long 0x48++0x03
|
|
line.long 0x00 "NSBOOTADD1R,Flash non-secure boot address 1 register"
|
|
hexmask.long 0x00 7.--31. 1. "NSBOOTADD1,NSBOOTADD1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SECBOOTADD0R,FFlash secure boot address 0 register"
|
|
hexmask.long 0x00 7.--31. 1. "SECBOOTADD0,SECBOOTADD0"
|
|
bitfld.long 0x00 0. "BOOT_LOCK,BOOT_LOCK" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SECWM1R1,Flash bank 1 secure watermak1 register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "SECWM1_PEND,SECWM1_PEND"
|
|
hexmask.long.byte 0x00 0.--6. 1. "SECWM1_PSTRT,SECWM1_PSTRT"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SECWM1R2,Flash secure watermak1 register 2"
|
|
bitfld.long 0x00 31. "HDP1EN,HDP1EN" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "HDP1_PEND,HDP1_PEND"
|
|
bitfld.long 0x00 15. "PCROP1EN,PCROP1EN" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "PCROP1_PSTRT,PCROP1_PSTRT"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "WRP1AR,Flash Bank 1 WRP area A address register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "WRP1A_PEND,WRP1A_PEND"
|
|
hexmask.long.byte 0x00 0.--6. 1. "WRP1A_PSTRT,WRP1A_PSTRT"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "WRP1BR,Flash Bank 1 WRP area B address register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "WRP1B_PEND,WRP1B_PEND"
|
|
hexmask.long.byte 0x00 0.--6. 1. "WRP1B_PSTRT,WRP1B_PSTRT"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SECWM2R1,Flash secure watermak2 register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "SECWM2_PEND,SECWM2_PEND"
|
|
hexmask.long.byte 0x00 0.--6. 1. "SECWM2_PSTRT,SECWM2_PSTRT"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SECWM2R2,Flash secure watermak2 register2"
|
|
bitfld.long 0x00 31. "HDP2EN,HDP2EN" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "HDP2_PEND,HDP2_PEND"
|
|
bitfld.long 0x00 15. "PCROP2EN,PCROP2EN" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "PCROP2_PSTRT,PCROP2_PSTRT"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "WRP2AR,Flash WPR2 area A address register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "WRP2A_PEND,WRP2A_PEND"
|
|
hexmask.long.byte 0x00 0.--6. 1. "WRP2A_PSTRT,WRP2A_PSTRT"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "WRP2BR,Flash WPR2 area B address register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "WRP2B_PEND,WRP2B_PEND"
|
|
hexmask.long.byte 0x00 0.--6. 1. "WRP2B_PSTRT,WRP2B_PSTRT"
|
|
repeat 4. (strings "1" "2" "3" "4" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "SECBB1R$1,FLASH secure block based bank 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "SECBB1,SECBB1"
|
|
repeat.end
|
|
repeat 4. (strings "1" "2" "3" "4" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0xA0)++0x03
|
|
line.long 0x00 "SECBB2R$1,FLASH secure block based bank 2 register"
|
|
hexmask.long 0x00 0.--31. 1. "SECBB2,SECBB2"
|
|
repeat.end
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "SECHDPCR,FLASH secure HDP control register"
|
|
bitfld.long 0x00 1. "HDP2_ACCDIS,HDP2_ACCDIS" "0,1"
|
|
bitfld.long 0x00 0. "HDP1_ACCDIS,HDP1_ACCDIS" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "PRIVCFGR,Power privilege configuration register"
|
|
bitfld.long 0x00 0. "PRIV,PRIV" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "FMC"
|
|
tree "FMC"
|
|
base ad:0x44020000
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x8 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "FMC_BCR$1,FMC_BCR $1"
|
|
bitfld.long 0x00 22.--23. "NBLSET,NBLSET" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WFDIS,Write FIFO Disable This bit disables the Write FIFO used by the FMC controller" "0,1"
|
|
bitfld.long 0x00 20. "CCLKEN,Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices" "0,1"
|
|
bitfld.long 0x00 19. "CBURSTRW,Write burst enable For PSRAM (CRAM) operating in Burst mode the bit enables synchronous accesses during write operations" "0,1"
|
|
bitfld.long 0x00 16.--18. "CPSIZE,CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "ASYNCWAIT,Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol" "0,1"
|
|
bitfld.long 0x00 14. "EXTMOD,Extended mode enable" "0,1"
|
|
bitfld.long 0x00 13. "WAITEN,Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode" "0,1"
|
|
bitfld.long 0x00 12. "WREN,Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC" "0,1"
|
|
bitfld.long 0x00 11. "WAITCFG,Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "WAITPOL,Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode" "0,1"
|
|
bitfld.long 0x00 8. "BURSTEN,Burst enable bit This bit enables/disables synchronous accesses during read operations" "0,1"
|
|
bitfld.long 0x00 6. "FACCEN,Flash access enable This bit enables NOR Flash memory access operations" "0,1"
|
|
bitfld.long 0x00 4.--5. "MWID,Memory data bus width Defines the external memory device width valid for all type of memories" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MTYP,Memory type These bits define the type of external memory attached to the corresponding memory bank" "0,1,2,3"
|
|
bitfld.long 0x00 1. "MUXEN,Address/data multiplexing enable bit When this bit is set the address and data values are multiplexed on the data bus valid only with NOR and PSRAM memories" "0,1"
|
|
bitfld.long 0x00 0. "MBKEN,Memory bank enable bit This bit enables the memory bank" "0,1"
|
|
repeat.end
|
|
repeat 2. (strings "3" "4" )(list 0x0 0x8 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "FMC_BCR$1,>FMC_BCR $1"
|
|
bitfld.long 0x00 22.--23. "NBLSET,NBLSET" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WFDIS,Write FIFO Disable This bit disables the Write FIFO used by the FMC controller" "0,1"
|
|
bitfld.long 0x00 20. "CCLKEN,Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices" "0,1"
|
|
bitfld.long 0x00 19. "CBURSTRW,Write burst enable For PSRAM (CRAM) operating in Burst mode the bit enables synchronous accesses during write operations" "0,1"
|
|
bitfld.long 0x00 16.--18. "CPSIZE,CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "ASYNCWAIT,Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol" "0,1"
|
|
bitfld.long 0x00 14. "EXTMOD,Extended mode enable" "0,1"
|
|
bitfld.long 0x00 13. "WAITEN,Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode" "0,1"
|
|
bitfld.long 0x00 12. "WREN,Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC" "0,1"
|
|
bitfld.long 0x00 11. "WAITCFG,Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "WAITPOL,Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode" "0,1"
|
|
bitfld.long 0x00 8. "BURSTEN,Burst enable bit This bit enables/disables synchronous accesses during read operations" "0,1"
|
|
bitfld.long 0x00 6. "FACCEN,Flash access enable This bit enables NOR Flash memory access operations" "0,1"
|
|
bitfld.long 0x00 4.--5. "MWID,Memory data bus width Defines the external memory device width valid for all type of memories" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MTYP,Memory type These bits define the type of external memory attached to the corresponding memory bank" "0,1,2,3"
|
|
bitfld.long 0x00 1. "MUXEN,Address/data multiplexing enable bit When this bit is set the address and data values are multiplexed on the data bus valid only with NOR and PSRAM memories" "0,1"
|
|
bitfld.long 0x00 0. "MBKEN,Memory bank enable bit This bit enables the memory bank" "0,1"
|
|
repeat.end
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "FMC_BTR1,This register contains the control information of each memory bank used for SRAMs PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register then this register is partitioned for write and read access that is 2 registers are.."
|
|
bitfld.long 0x00 30.--31. "DATAHLD,DATAHLD" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "ACCMOD,Access mode These bits specify the asynchronous access modes as shown in the timing diagrams" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DATLAT,Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "CLKDIV,Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal expressed in number of KCK_FMC cycles: In asynchronous NOR Flash SRAM or PSRAM accesses this value is dont care" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "BUSTURN,Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATAST,Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93) used in asynchronous accesses: For each memory type and access mode data-phase duration please refer to the respective.."
|
|
bitfld.long 0x00 4.--7. "ADDHLD,Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93) used in mode D or multiplexed accesses: For each access mode address-hold phase duration please refer.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "ADDSET,Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93) used in SRAMs ROMs and asynchronous NOR Flash: For each access mode address setup phase duration.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (strings "2" "3" "4" )(list 0x0 0x8 0x10 )
|
|
group.long ($2+0x0C)++0x03
|
|
line.long 0x00 "FMC_BTR$1,FMC_BTR $1"
|
|
bitfld.long 0x00 30.--31. "DATAHLD,DATAHLD" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "ACCMOD,Access mode These bits specify the asynchronous access modes as shown in the timing diagrams" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DATLAT,Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "CLKDIV,Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal expressed in number of KCK_FMC cycles: In asynchronous NOR Flash SRAM or PSRAM accesses this value is dont care" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "BUSTURN,Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATAST,Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93) used in asynchronous accesses: For each memory type and access mode data-phase duration please refer to the respective.."
|
|
bitfld.long 0x00 4.--7. "ADDHLD,Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93) used in mode D or multiplexed accesses: For each access mode address-hold phase duration please refer.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "ADDSET,Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93) used in SRAMs ROMs and asynchronous NOR Flash: For each access mode address setup phase duration.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FMC_PCR,NAND Flash control registers"
|
|
bitfld.long 0x00 17.--19. "ECCPS,ECC page size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--16. "TAR,ALE to RE delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--12. "TCLR,CLE to RE delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "ECCEN,ECC computation logic enable bit" "0,1"
|
|
bitfld.long 0x00 4.--5. "PWID,Data bus width" "0,1,2,3"
|
|
bitfld.long 0x00 3. "PTYP,Memory type" "0,1"
|
|
bitfld.long 0x00 2. "PBKEN,NAND Flash memory bank enable bit" "0,1"
|
|
bitfld.long 0x00 1. "PWAITEN,Wait feature enable bit" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FMC_SR,This register contains information about the FIFO status and interrupt"
|
|
rbitfld.long 0x00 6. "FEMPT,FIFO empty" "0,1"
|
|
bitfld.long 0x00 5. "IFEN,Interrupt falling edge detection enable bit" "0,1"
|
|
bitfld.long 0x00 4. "ILEN,Interrupt high-level detection enable bit" "0,1"
|
|
bitfld.long 0x00 3. "IREN,Interrupt rising edge detection enable bit" "0,1"
|
|
bitfld.long 0x00 2. "IFS,Interrupt falling edge status The flag is set by hardware and reset by software" "0,1"
|
|
bitfld.long 0x00 1. "ILS,Interrupt high-level status The flag is set by hardware and reset by software" "0,1"
|
|
bitfld.long 0x00 0. "IRS,Interrupt rising edge status The flag is set by hardware and reset by software" "0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FMC_PMEM,The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MEMHOLD,Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE.."
|
|
hexmask.long.byte 0x00 8.--15. 1. "MEMWAIT,Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE NOE) for NAND Flash read or write access to common memory space"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MEMSET,Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE NOE) for NAND Flash read or write access to common memory space"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FMC_PATT,The FMC_PATT read/write register contains the timing information for NAND Flash memory bank"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE NOE) for NAND Flash read or write access to attribute memory space"
|
|
hexmask.long.byte 0x00 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE NOE) for NAND Flash read or write access to attribute memory space"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ATTSET,Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE NOE) for NAND Flash read or write access to attribute memory space"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "FMC_ECCR,This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller"
|
|
hexmask.long 0x00 0.--31. 1. "ECC,ECC result This field contains the value computed by the ECC computation logic"
|
|
repeat 4. (strings "1" "2" "3" "4" )(list 0x00 0x08 0x10 0x18 )
|
|
group.long ($2+0x104)++0x03
|
|
line.long 0x00 "FMC_BWTR$1,This register contains the control information of each memory bank"
|
|
bitfld.long 0x00 28.--29. "ACCMOD,Access mode" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "BUSTURN,Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATAST,Data-phase duration"
|
|
bitfld.long 0x00 4.--7. "ADDHLD,Address-hold phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "ADDSET,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCSCNTR,PCSCNTR"
|
|
bitfld.long 0x00 19. "CNTB4EN,Counter Bank 4 enable" "0,1"
|
|
bitfld.long 0x00 18. "CNTB3EN,Counter Bank 3 enable" "0,1"
|
|
bitfld.long 0x00 17. "CNTB2EN,Counter Bank 2 enable" "0,1"
|
|
bitfld.long 0x00 16. "CNTB1EN,Counter Bank 1 enable" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CSCOUNT,Chip select counter"
|
|
tree.end
|
|
tree "SEC_FMC"
|
|
base ad:0x54020000
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x8 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "FMC_BCR$1,FMC_BCR $1"
|
|
bitfld.long 0x00 22.--23. "NBLSET,NBLSET" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WFDIS,Write FIFO Disable This bit disables the Write FIFO used by the FMC controller" "0,1"
|
|
bitfld.long 0x00 20. "CCLKEN,Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices" "0,1"
|
|
bitfld.long 0x00 19. "CBURSTRW,Write burst enable For PSRAM (CRAM) operating in Burst mode the bit enables synchronous accesses during write operations" "0,1"
|
|
bitfld.long 0x00 16.--18. "CPSIZE,CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "ASYNCWAIT,Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol" "0,1"
|
|
bitfld.long 0x00 14. "EXTMOD,Extended mode enable" "0,1"
|
|
bitfld.long 0x00 13. "WAITEN,Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode" "0,1"
|
|
bitfld.long 0x00 12. "WREN,Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC" "0,1"
|
|
bitfld.long 0x00 11. "WAITCFG,Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "WAITPOL,Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode" "0,1"
|
|
bitfld.long 0x00 8. "BURSTEN,Burst enable bit This bit enables/disables synchronous accesses during read operations" "0,1"
|
|
bitfld.long 0x00 6. "FACCEN,Flash access enable This bit enables NOR Flash memory access operations" "0,1"
|
|
bitfld.long 0x00 4.--5. "MWID,Memory data bus width Defines the external memory device width valid for all type of memories" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MTYP,Memory type These bits define the type of external memory attached to the corresponding memory bank" "0,1,2,3"
|
|
bitfld.long 0x00 1. "MUXEN,Address/data multiplexing enable bit When this bit is set the address and data values are multiplexed on the data bus valid only with NOR and PSRAM memories" "0,1"
|
|
bitfld.long 0x00 0. "MBKEN,Memory bank enable bit This bit enables the memory bank" "0,1"
|
|
repeat.end
|
|
repeat 2. (strings "3" "4" )(list 0x0 0x8 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "FMC_BCR$1,>FMC_BCR $1"
|
|
bitfld.long 0x00 22.--23. "NBLSET,NBLSET" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WFDIS,Write FIFO Disable This bit disables the Write FIFO used by the FMC controller" "0,1"
|
|
bitfld.long 0x00 20. "CCLKEN,Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices" "0,1"
|
|
bitfld.long 0x00 19. "CBURSTRW,Write burst enable For PSRAM (CRAM) operating in Burst mode the bit enables synchronous accesses during write operations" "0,1"
|
|
bitfld.long 0x00 16.--18. "CPSIZE,CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "ASYNCWAIT,Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol" "0,1"
|
|
bitfld.long 0x00 14. "EXTMOD,Extended mode enable" "0,1"
|
|
bitfld.long 0x00 13. "WAITEN,Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode" "0,1"
|
|
bitfld.long 0x00 12. "WREN,Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC" "0,1"
|
|
bitfld.long 0x00 11. "WAITCFG,Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "WAITPOL,Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode" "0,1"
|
|
bitfld.long 0x00 8. "BURSTEN,Burst enable bit This bit enables/disables synchronous accesses during read operations" "0,1"
|
|
bitfld.long 0x00 6. "FACCEN,Flash access enable This bit enables NOR Flash memory access operations" "0,1"
|
|
bitfld.long 0x00 4.--5. "MWID,Memory data bus width Defines the external memory device width valid for all type of memories" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MTYP,Memory type These bits define the type of external memory attached to the corresponding memory bank" "0,1,2,3"
|
|
bitfld.long 0x00 1. "MUXEN,Address/data multiplexing enable bit When this bit is set the address and data values are multiplexed on the data bus valid only with NOR and PSRAM memories" "0,1"
|
|
bitfld.long 0x00 0. "MBKEN,Memory bank enable bit This bit enables the memory bank" "0,1"
|
|
repeat.end
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "FMC_BTR1,This register contains the control information of each memory bank used for SRAMs PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register then this register is partitioned for write and read access that is 2 registers are.."
|
|
bitfld.long 0x00 30.--31. "DATAHLD,DATAHLD" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "ACCMOD,Access mode These bits specify the asynchronous access modes as shown in the timing diagrams" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DATLAT,Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "CLKDIV,Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal expressed in number of KCK_FMC cycles: In asynchronous NOR Flash SRAM or PSRAM accesses this value is dont care" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "BUSTURN,Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATAST,Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93) used in asynchronous accesses: For each memory type and access mode data-phase duration please refer to the respective.."
|
|
bitfld.long 0x00 4.--7. "ADDHLD,Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93) used in mode D or multiplexed accesses: For each access mode address-hold phase duration please refer.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "ADDSET,Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93) used in SRAMs ROMs and asynchronous NOR Flash: For each access mode address setup phase duration.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (strings "2" "3" "4" )(list 0x0 0x8 0x10 )
|
|
group.long ($2+0x0C)++0x03
|
|
line.long 0x00 "FMC_BTR$1,FMC_BTR $1"
|
|
bitfld.long 0x00 30.--31. "DATAHLD,DATAHLD" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "ACCMOD,Access mode These bits specify the asynchronous access modes as shown in the timing diagrams" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DATLAT,Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "CLKDIV,Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal expressed in number of KCK_FMC cycles: In asynchronous NOR Flash SRAM or PSRAM accesses this value is dont care" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "BUSTURN,Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATAST,Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93) used in asynchronous accesses: For each memory type and access mode data-phase duration please refer to the respective.."
|
|
bitfld.long 0x00 4.--7. "ADDHLD,Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93) used in mode D or multiplexed accesses: For each access mode address-hold phase duration please refer.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "ADDSET,Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93) used in SRAMs ROMs and asynchronous NOR Flash: For each access mode address setup phase duration.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FMC_PCR,NAND Flash control registers"
|
|
bitfld.long 0x00 17.--19. "ECCPS,ECC page size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--16. "TAR,ALE to RE delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--12. "TCLR,CLE to RE delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6. "ECCEN,ECC computation logic enable bit" "0,1"
|
|
bitfld.long 0x00 4.--5. "PWID,Data bus width" "0,1,2,3"
|
|
bitfld.long 0x00 3. "PTYP,Memory type" "0,1"
|
|
bitfld.long 0x00 2. "PBKEN,NAND Flash memory bank enable bit" "0,1"
|
|
bitfld.long 0x00 1. "PWAITEN,Wait feature enable bit" "0,1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FMC_SR,This register contains information about the FIFO status and interrupt"
|
|
rbitfld.long 0x00 6. "FEMPT,FIFO empty" "0,1"
|
|
bitfld.long 0x00 5. "IFEN,Interrupt falling edge detection enable bit" "0,1"
|
|
bitfld.long 0x00 4. "ILEN,Interrupt high-level detection enable bit" "0,1"
|
|
bitfld.long 0x00 3. "IREN,Interrupt rising edge detection enable bit" "0,1"
|
|
bitfld.long 0x00 2. "IFS,Interrupt falling edge status The flag is set by hardware and reset by software" "0,1"
|
|
bitfld.long 0x00 1. "ILS,Interrupt high-level status The flag is set by hardware and reset by software" "0,1"
|
|
bitfld.long 0x00 0. "IRS,Interrupt rising edge status The flag is set by hardware and reset by software" "0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FMC_PMEM,The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MEMHOLD,Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE.."
|
|
hexmask.long.byte 0x00 8.--15. 1. "MEMWAIT,Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE NOE) for NAND Flash read or write access to common memory space"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MEMSET,Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE NOE) for NAND Flash read or write access to common memory space"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FMC_PATT,The FMC_PATT read/write register contains the timing information for NAND Flash memory bank"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE NOE) for NAND Flash read or write access to attribute memory space"
|
|
hexmask.long.byte 0x00 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE NOE) for NAND Flash read or write access to attribute memory space"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ATTSET,Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE NOE) for NAND Flash read or write access to attribute memory space"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "FMC_ECCR,This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller"
|
|
hexmask.long 0x00 0.--31. 1. "ECC,ECC result This field contains the value computed by the ECC computation logic"
|
|
repeat 4. (strings "1" "2" "3" "4" )(list 0x00 0x08 0x10 0x18 )
|
|
group.long ($2+0x104)++0x03
|
|
line.long 0x00 "FMC_BWTR$1,This register contains the control information of each memory bank"
|
|
bitfld.long 0x00 28.--29. "ACCMOD,Access mode" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "BUSTURN,Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATAST,Data-phase duration"
|
|
bitfld.long 0x00 4.--7. "ADDHLD,Address-hold phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "ADDSET,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCSCNTR,PCSCNTR"
|
|
bitfld.long 0x00 19. "CNTB4EN,Counter Bank 4 enable" "0,1"
|
|
bitfld.long 0x00 18. "CNTB3EN,Counter Bank 3 enable" "0,1"
|
|
bitfld.long 0x00 17. "CNTB2EN,Counter Bank 2 enable" "0,1"
|
|
bitfld.long 0x00 16. "CNTB1EN,Counter Bank 1 enable" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CSCOUNT,Chip select counter"
|
|
tree.end
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
tree "GPIOA"
|
|
base ad:0x42020000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "GPIOB"
|
|
base ad:0x42020400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "GPIOC"
|
|
base ad:0x42020800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "GPIOD"
|
|
base ad:0x42020C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "GPIOE"
|
|
base ad:0x42021000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "GPIOF"
|
|
base ad:0x42021400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "GPIOG"
|
|
base ad:0x42021800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "GPIOH"
|
|
base ad:0x42021C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "SEC_GPIOA"
|
|
base ad:0x52020000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "SEC_GPIOB"
|
|
base ad:0x52020400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "SEC_GPIOC"
|
|
base ad:0x52020800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "SEC_GPIOD"
|
|
base ad:0x52020C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "SEC_GPIOE"
|
|
base ad:0x52021000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "SEC_GPIOF"
|
|
base ad:0x52021400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "SEC_GPIOG"
|
|
base ad:0x52021800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree "SEC_GPIOH"
|
|
base ad:0x52021C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MODER,GPIO port mode register"
|
|
bitfld.long 0x00 30.--31. "MODER15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MODER14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "MODER13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "MODER12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "MODER11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "MODER10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "MODER9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "MODER8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "MODER7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "MODER6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "MODER5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "MODER4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "MODER3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "MODER2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "MODER1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODER0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x00 15. "OT15,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "OT14,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "OT13,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "OT12,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "OT11,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "OT10,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "OT9,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "OT8,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "OT7,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "OT6,Port x configuration bits (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "OT5,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "OT4,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "OT3,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "OT2,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "OT1,Port x configuration bits (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "OT0,Port x configuration bits (y = 0..15)" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x00 30.--31. "OSPEEDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OSPEEDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "OSPEEDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "OSPEEDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "OSPEEDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "OSPEEDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "OSPEEDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "OSPEEDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "OSPEEDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "OSPEEDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "OSPEEDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "OSPEEDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "OSPEEDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "OSPEEDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OSPEEDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "OSPEEDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0x00 30.--31. "PUPDR15,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "PUPDR14,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "PUPDR13,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "PUPDR12,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PUPDR11,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "PUPDR10,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "PUPDR9,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "PUPDR8,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "PUPDR7,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "PUPDR6,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUPDR5,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "PUPDR4,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PUPDR3,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PUPDR2,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "PUPDR1,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "PUPDR0,Port x configuration bits (y = 0..15)" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO port input data register"
|
|
bitfld.long 0x00 15. "IDR15,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "IDR14,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "IDR13,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "IDR12,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "IDR11,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "IDR10,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "IDR9,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "IDR8,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "IDR7,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "IDR6,Port input data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IDR5,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "IDR4,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "IDR3,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "IDR2,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "IDR1,Port input data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "IDR0,Port input data (y = 0..15)" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR,GPIO port output data register"
|
|
bitfld.long 0x00 15. "ODR15,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "ODR14,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "ODR13,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "ODR12,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "ODR11,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "ODR10,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "ODR9,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "ODR8,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "ODR7,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "ODR6,Port output data (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ODR5,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "ODR4,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "ODR3,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "ODR2,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "ODR1,Port output data (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "ODR0,Port output data (y = 0..15)" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x00 31. "BR15,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 30. "BR14,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 29. "BR13,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 28. "BR12,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 27. "BR11,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 26. "BR10,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 25. "BR9,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 24. "BR8,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 23. "BR7,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 22. "BR6,Port x reset bit y (y = 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "BR5,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 20. "BR4,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 19. "BR3,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 18. "BR2,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 17. "BR1,Port x reset bit y (y = 0..15)" "0,1"
|
|
bitfld.long 0x00 16. "BR0,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "BS15,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "BS14,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "BS13,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "BS12,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "BS11,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "BS10,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "BS9,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "BS8,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "BS7,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 6. "BS6,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "BS5,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "BS4,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "BS3,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "BS2,Port x set bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BS1,Port x set bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "BS0,Port x set bit y (y= 0..15)" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x00 16. "LCKK,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 15. "LCK15,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 14. "LCK14,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 13. "LCK13,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 12. "LCK12,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 11. "LCK11,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 10. "LCK10,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 9. "LCK9,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 8. "LCK8,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 7. "LCK7,Port x lock bit y (y= 0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LCK6,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 5. "LCK5,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 4. "LCK4,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 3. "LCK3,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 2. "LCK2,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 1. "LCK1,Port x lock bit y (y= 0..15)" "0,1"
|
|
bitfld.long 0x00 0. "LCK0,Port x lock bit y (y= 0..15)" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. "AFSEL7,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL6,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL5,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL4,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL3,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL2,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL1,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL0,Alternate function selection for port x bit y (y = 0..7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 28.--31. "AFSEL15,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "AFSEL14,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "AFSEL13,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "AFSEL12,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "AFSEL11,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "AFSEL10,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "AFSEL9,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "AFSEL8,Alternate function selection for port x bit y (y = 8..15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. "BR15,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 14. "BR14,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 13. "BR13,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 12. "BR12,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 11. "BR11,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 10. "BR10,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 9. "BR9,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 8. "BR8,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 7. "BR7,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 6. "BR6,Port x reset IO pin y" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BR5,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 4. "BR4,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 3. "BR3,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 2. "BR2,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 1. "BR1,Port x reset IO pin y" "0,1"
|
|
bitfld.long 0x00 0. "BR0,Port x reset IO pin y" "0,1"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SECCFGR,GPIO secure configuration register"
|
|
bitfld.long 0x00 15. "SEC15,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 14. "SEC14,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 13. "SEC13,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 12. "SEC12,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 11. "SEC11,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 10. "SEC10,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 9. "SEC9,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 8. "SEC8,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 7. "SEC7,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 6. "SEC6,I/O pin of Port x secure bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SEC5,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 4. "SEC4,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 3. "SEC3,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 2. "SEC2,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 1. "SEC1,I/O pin of Port x secure bit enable" "0,1"
|
|
bitfld.long 0x00 0. "SEC0,I/O pin of Port x secure bit enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "GTZC (MPCBB1)"
|
|
tree "MPCBB1"
|
|
base ad:0x40032C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MPCBB1_CR,MPCBB control register"
|
|
bitfld.long 0x00 31. "SRWILADIS,SRWILADIS" "0,1"
|
|
bitfld.long 0x00 30. "INVSECSTATE,INVSECSTATE" "0,1"
|
|
bitfld.long 0x00 0. "LCK,LCK" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MPCBB1_LCKVTR1,MPCBB control register"
|
|
bitfld.long 0x00 31. "LCKSB31,LCKSB31" "0,1"
|
|
bitfld.long 0x00 30. "LCKSB30,LCKSB30" "0,1"
|
|
bitfld.long 0x00 29. "LCKSB29,LCKSB29" "0,1"
|
|
bitfld.long 0x00 28. "LCKSB28,LCKSB28" "0,1"
|
|
bitfld.long 0x00 27. "LCKSB27,LCKSB27" "0,1"
|
|
bitfld.long 0x00 26. "LCKSB26,LCKSB26" "0,1"
|
|
bitfld.long 0x00 25. "LCKSB25,LCKSB25" "0,1"
|
|
bitfld.long 0x00 24. "LCKSB24,LCKSB24" "0,1"
|
|
bitfld.long 0x00 23. "LCKSB23,LCKSB23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "LCKSB22,LCKSB22" "0,1"
|
|
bitfld.long 0x00 21. "LCKSB21,LCKSB21" "0,1"
|
|
bitfld.long 0x00 20. "LCKSB20,LCKSB20" "0,1"
|
|
bitfld.long 0x00 19. "LCKSB19,LCKSB19" "0,1"
|
|
bitfld.long 0x00 18. "LCKSB18,LCKSB18" "0,1"
|
|
bitfld.long 0x00 17. "LCKSB17,LCKSB17" "0,1"
|
|
bitfld.long 0x00 16. "LCKSB16,LCKSB16" "0,1"
|
|
bitfld.long 0x00 15. "LCKSB15,LCKSB15" "0,1"
|
|
bitfld.long 0x00 14. "LCKSB14,LCKSB14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "LCKSB13,LCKSB13" "0,1"
|
|
bitfld.long 0x00 12. "LCKSB12,LCKSB12" "0,1"
|
|
bitfld.long 0x00 11. "LCKSB11,LCKSB11" "0,1"
|
|
bitfld.long 0x00 10. "LCKSB10,LCKSB10" "0,1"
|
|
bitfld.long 0x00 9. "LCKSB9,LCKSB9" "0,1"
|
|
bitfld.long 0x00 8. "LCKSB8,LCKSB8" "0,1"
|
|
bitfld.long 0x00 7. "LCKSB7,LCKSB7" "0,1"
|
|
bitfld.long 0x00 6. "LCKSB6,LCKSB6" "0,1"
|
|
bitfld.long 0x00 5. "LCKSB5,LCKSB5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LCKSB4,LCKSB4" "0,1"
|
|
bitfld.long 0x00 3. "LCKSB3,LCKSB3" "0,1"
|
|
bitfld.long 0x00 2. "LCKSB2,LCKSB2" "0,1"
|
|
bitfld.long 0x00 1. "LCKSB1,LCKSB1" "0,1"
|
|
bitfld.long 0x00 0. "LCKSB0,LCKSB0" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MPCBB1_LCKVTR2,MPCBB control register"
|
|
bitfld.long 0x00 31. "LCKSB63,LCKSB63" "0,1"
|
|
bitfld.long 0x00 30. "LCKSB62,LCKSB62" "0,1"
|
|
bitfld.long 0x00 29. "LCKSB61,LCKSB61" "0,1"
|
|
bitfld.long 0x00 28. "LCKSB60,LCKSB60" "0,1"
|
|
bitfld.long 0x00 27. "LCKSB59,LCKSB59" "0,1"
|
|
bitfld.long 0x00 26. "LCKSB58,LCKSB58" "0,1"
|
|
bitfld.long 0x00 25. "LCKSB57,LCKSB57" "0,1"
|
|
bitfld.long 0x00 24. "LCKSB56,LCKSB56" "0,1"
|
|
bitfld.long 0x00 23. "LCKSB55,LCKSB55" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "LCKSB54,LCKSB54" "0,1"
|
|
bitfld.long 0x00 21. "LCKSB53,LCKSB53" "0,1"
|
|
bitfld.long 0x00 20. "LCKSB52,LCKSB52" "0,1"
|
|
bitfld.long 0x00 19. "LCKSB51,LCKSB51" "0,1"
|
|
bitfld.long 0x00 18. "LCKSB50,LCKSB50" "0,1"
|
|
bitfld.long 0x00 17. "LCKSB49,LCKSB49" "0,1"
|
|
bitfld.long 0x00 16. "LCKSB48,LCKSB48" "0,1"
|
|
bitfld.long 0x00 15. "LCKSB47,LCKSB47" "0,1"
|
|
bitfld.long 0x00 14. "LCKSB46,LCKSB46" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "LCKSB45,LCKSB45" "0,1"
|
|
bitfld.long 0x00 12. "LCKSB44,LCKSB44" "0,1"
|
|
bitfld.long 0x00 11. "LCKSB43,LCKSB43" "0,1"
|
|
bitfld.long 0x00 10. "LCKSB42,LCKSB42" "0,1"
|
|
bitfld.long 0x00 9. "LCKSB41,LCKSB41" "0,1"
|
|
bitfld.long 0x00 8. "LCKSB40,LCKSB40" "0,1"
|
|
bitfld.long 0x00 7. "LCKSB39,LCKSB39" "0,1"
|
|
bitfld.long 0x00 6. "LCKSB38,LCKSB38" "0,1"
|
|
bitfld.long 0x00 5. "LCKSB37,LCKSB37" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LCKSB36,LCKSB36" "0,1"
|
|
bitfld.long 0x00 3. "LCKSB35,LCKSB35" "0,1"
|
|
bitfld.long 0x00 2. "LCKSB34,LCKSB34" "0,1"
|
|
bitfld.long 0x00 1. "LCKSB33,LCKSB33" "0,1"
|
|
bitfld.long 0x00 0. "LCKSB32,LCKSB32" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MPCBB1_VCTR0,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B31,B31" "0,1"
|
|
bitfld.long 0x00 30. "B30,B30" "0,1"
|
|
bitfld.long 0x00 29. "B29,B29" "0,1"
|
|
bitfld.long 0x00 28. "B28,B28" "0,1"
|
|
bitfld.long 0x00 27. "B27,B27" "0,1"
|
|
bitfld.long 0x00 26. "B26,B26" "0,1"
|
|
bitfld.long 0x00 25. "B25,B25" "0,1"
|
|
bitfld.long 0x00 24. "B24,B24" "0,1"
|
|
bitfld.long 0x00 23. "B23,B23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B22,B22" "0,1"
|
|
bitfld.long 0x00 21. "B21,B21" "0,1"
|
|
bitfld.long 0x00 20. "B20,B20" "0,1"
|
|
bitfld.long 0x00 19. "B19,B19" "0,1"
|
|
bitfld.long 0x00 18. "B18,B18" "0,1"
|
|
bitfld.long 0x00 17. "B17,B17" "0,1"
|
|
bitfld.long 0x00 16. "B16,B16" "0,1"
|
|
bitfld.long 0x00 15. "B15,B15" "0,1"
|
|
bitfld.long 0x00 14. "B14,B14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B13,B13" "0,1"
|
|
bitfld.long 0x00 12. "B12,B12" "0,1"
|
|
bitfld.long 0x00 11. "B11,B11" "0,1"
|
|
bitfld.long 0x00 10. "B10,B10" "0,1"
|
|
bitfld.long 0x00 9. "B9,B9" "0,1"
|
|
bitfld.long 0x00 8. "B8,B8" "0,1"
|
|
bitfld.long 0x00 7. "B7,B7" "0,1"
|
|
bitfld.long 0x00 6. "B6,B6" "0,1"
|
|
bitfld.long 0x00 5. "B5,B5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B4,B4" "0,1"
|
|
bitfld.long 0x00 3. "B3,B3" "0,1"
|
|
bitfld.long 0x00 2. "B2,B2" "0,1"
|
|
bitfld.long 0x00 1. "B1,B1" "0,1"
|
|
bitfld.long 0x00 0. "B0,B0" "0,1"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "MPCBB1_VCTR1,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B63,B63" "0,1"
|
|
bitfld.long 0x00 30. "B62,B62" "0,1"
|
|
bitfld.long 0x00 29. "B61,B61" "0,1"
|
|
bitfld.long 0x00 28. "B60,B60" "0,1"
|
|
bitfld.long 0x00 27. "B59,B59" "0,1"
|
|
bitfld.long 0x00 26. "B58,B58" "0,1"
|
|
bitfld.long 0x00 25. "B57,B57" "0,1"
|
|
bitfld.long 0x00 24. "B56,B56" "0,1"
|
|
bitfld.long 0x00 23. "B55,B55" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B54,B54" "0,1"
|
|
bitfld.long 0x00 21. "B53,B53" "0,1"
|
|
bitfld.long 0x00 20. "B52,B52" "0,1"
|
|
bitfld.long 0x00 19. "B51,B51" "0,1"
|
|
bitfld.long 0x00 18. "B50,B50" "0,1"
|
|
bitfld.long 0x00 17. "B49,B49" "0,1"
|
|
bitfld.long 0x00 16. "B48,B48" "0,1"
|
|
bitfld.long 0x00 15. "B47,B47" "0,1"
|
|
bitfld.long 0x00 14. "B46,B46" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B45,B45" "0,1"
|
|
bitfld.long 0x00 12. "B44,B44" "0,1"
|
|
bitfld.long 0x00 11. "B43,B43" "0,1"
|
|
bitfld.long 0x00 10. "B42,B42" "0,1"
|
|
bitfld.long 0x00 9. "B41,B41" "0,1"
|
|
bitfld.long 0x00 8. "B40,B40" "0,1"
|
|
bitfld.long 0x00 7. "B39,B39" "0,1"
|
|
bitfld.long 0x00 6. "B38,B38" "0,1"
|
|
bitfld.long 0x00 5. "B37,B37" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B36,B36" "0,1"
|
|
bitfld.long 0x00 3. "B35,B35" "0,1"
|
|
bitfld.long 0x00 2. "B34,B34" "0,1"
|
|
bitfld.long 0x00 1. "B33,B33" "0,1"
|
|
bitfld.long 0x00 0. "B32,B32" "0,1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "MPCBB1_VCTR2,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B95,B95" "0,1"
|
|
bitfld.long 0x00 30. "B94,B94" "0,1"
|
|
bitfld.long 0x00 29. "B93,B93" "0,1"
|
|
bitfld.long 0x00 28. "B92,B92" "0,1"
|
|
bitfld.long 0x00 27. "B91,B91" "0,1"
|
|
bitfld.long 0x00 26. "B90,B90" "0,1"
|
|
bitfld.long 0x00 25. "B89,B89" "0,1"
|
|
bitfld.long 0x00 24. "B88,B88" "0,1"
|
|
bitfld.long 0x00 23. "B87,B87" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B86,B86" "0,1"
|
|
bitfld.long 0x00 21. "B85,B85" "0,1"
|
|
bitfld.long 0x00 20. "B84,B84" "0,1"
|
|
bitfld.long 0x00 19. "B83,B83" "0,1"
|
|
bitfld.long 0x00 18. "B82,B82" "0,1"
|
|
bitfld.long 0x00 17. "B81,B81" "0,1"
|
|
bitfld.long 0x00 16. "B80,B80" "0,1"
|
|
bitfld.long 0x00 15. "B79,B79" "0,1"
|
|
bitfld.long 0x00 14. "B78,B78" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B77,B77" "0,1"
|
|
bitfld.long 0x00 12. "B76,B76" "0,1"
|
|
bitfld.long 0x00 11. "B75,B75" "0,1"
|
|
bitfld.long 0x00 10. "B74,B74" "0,1"
|
|
bitfld.long 0x00 9. "B73,B73" "0,1"
|
|
bitfld.long 0x00 8. "B72,B72" "0,1"
|
|
bitfld.long 0x00 7. "B71,B71" "0,1"
|
|
bitfld.long 0x00 6. "B70,B70" "0,1"
|
|
bitfld.long 0x00 5. "B69,B69" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B68,B68" "0,1"
|
|
bitfld.long 0x00 3. "B67,B67" "0,1"
|
|
bitfld.long 0x00 2. "B66,B66" "0,1"
|
|
bitfld.long 0x00 1. "B65,B65" "0,1"
|
|
bitfld.long 0x00 0. "B64,B64" "0,1"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR3,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B127,B127" "0,1"
|
|
bitfld.long 0x00 30. "B126,B126" "0,1"
|
|
bitfld.long 0x00 29. "B125,B125" "0,1"
|
|
bitfld.long 0x00 28. "B124,B124" "0,1"
|
|
bitfld.long 0x00 27. "B123,B123" "0,1"
|
|
bitfld.long 0x00 26. "B122,B122" "0,1"
|
|
bitfld.long 0x00 25. "B121,B121" "0,1"
|
|
bitfld.long 0x00 24. "B120,B120" "0,1"
|
|
bitfld.long 0x00 23. "B119,B119" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B118,B118" "0,1"
|
|
bitfld.long 0x00 21. "B117,B117" "0,1"
|
|
bitfld.long 0x00 20. "B116,B116" "0,1"
|
|
bitfld.long 0x00 19. "B115,B115" "0,1"
|
|
bitfld.long 0x00 18. "B114,B114" "0,1"
|
|
bitfld.long 0x00 17. "B113,B113" "0,1"
|
|
bitfld.long 0x00 16. "B112,B112" "0,1"
|
|
bitfld.long 0x00 15. "B111,B111" "0,1"
|
|
bitfld.long 0x00 14. "B110,B110" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B109,B109" "0,1"
|
|
bitfld.long 0x00 12. "B108,B108" "0,1"
|
|
bitfld.long 0x00 11. "B107,B107" "0,1"
|
|
bitfld.long 0x00 10. "B106,B106" "0,1"
|
|
bitfld.long 0x00 9. "B105,B105" "0,1"
|
|
bitfld.long 0x00 8. "B104,B104" "0,1"
|
|
bitfld.long 0x00 7. "B103,B103" "0,1"
|
|
bitfld.long 0x00 6. "B102,B102" "0,1"
|
|
bitfld.long 0x00 5. "B101,B101" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B100,B100" "0,1"
|
|
bitfld.long 0x00 3. "B99,B99" "0,1"
|
|
bitfld.long 0x00 2. "B98,B98" "0,1"
|
|
bitfld.long 0x00 1. "B97,B97" "0,1"
|
|
bitfld.long 0x00 0. "B96,B96" "0,1"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MPCBB1_VCTR4,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B159,B159" "0,1"
|
|
bitfld.long 0x00 30. "B158,B158" "0,1"
|
|
bitfld.long 0x00 29. "B157,B157" "0,1"
|
|
bitfld.long 0x00 28. "B156,B156" "0,1"
|
|
bitfld.long 0x00 27. "B155,B155" "0,1"
|
|
bitfld.long 0x00 26. "B154,B154" "0,1"
|
|
bitfld.long 0x00 25. "B153,B153" "0,1"
|
|
bitfld.long 0x00 24. "B152,B152" "0,1"
|
|
bitfld.long 0x00 23. "B151,B151" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B150,B150" "0,1"
|
|
bitfld.long 0x00 21. "B149,B149" "0,1"
|
|
bitfld.long 0x00 20. "B148,B148" "0,1"
|
|
bitfld.long 0x00 19. "B147,B147" "0,1"
|
|
bitfld.long 0x00 18. "B146,B146" "0,1"
|
|
bitfld.long 0x00 17. "B145,B145" "0,1"
|
|
bitfld.long 0x00 16. "B144,B144" "0,1"
|
|
bitfld.long 0x00 15. "B143,B143" "0,1"
|
|
bitfld.long 0x00 14. "B142,B142" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B141,B141" "0,1"
|
|
bitfld.long 0x00 12. "B140,B140" "0,1"
|
|
bitfld.long 0x00 11. "B139,B139" "0,1"
|
|
bitfld.long 0x00 10. "B138,B138" "0,1"
|
|
bitfld.long 0x00 9. "B137,B137" "0,1"
|
|
bitfld.long 0x00 8. "B136,B136" "0,1"
|
|
bitfld.long 0x00 7. "B135,B135" "0,1"
|
|
bitfld.long 0x00 6. "B134,B134" "0,1"
|
|
bitfld.long 0x00 5. "B133,B133" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B132,B132" "0,1"
|
|
bitfld.long 0x00 3. "B131,B131" "0,1"
|
|
bitfld.long 0x00 2. "B130,B130" "0,1"
|
|
bitfld.long 0x00 1. "B129,B129" "0,1"
|
|
bitfld.long 0x00 0. "B128,B128" "0,1"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MPCBB1_VCTR5,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B191,B191" "0,1"
|
|
bitfld.long 0x00 30. "B190,B190" "0,1"
|
|
bitfld.long 0x00 29. "B189,B189" "0,1"
|
|
bitfld.long 0x00 28. "B188,B188" "0,1"
|
|
bitfld.long 0x00 27. "B187,B187" "0,1"
|
|
bitfld.long 0x00 26. "B186,B186" "0,1"
|
|
bitfld.long 0x00 25. "B185,B185" "0,1"
|
|
bitfld.long 0x00 24. "B184,B184" "0,1"
|
|
bitfld.long 0x00 23. "B183,B183" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B182,B182" "0,1"
|
|
bitfld.long 0x00 21. "B181,B181" "0,1"
|
|
bitfld.long 0x00 20. "B180,B180" "0,1"
|
|
bitfld.long 0x00 19. "B179,B179" "0,1"
|
|
bitfld.long 0x00 18. "B178,B178" "0,1"
|
|
bitfld.long 0x00 17. "B177,B177" "0,1"
|
|
bitfld.long 0x00 16. "B176,B176" "0,1"
|
|
bitfld.long 0x00 15. "B175,B175" "0,1"
|
|
bitfld.long 0x00 14. "B174,B174" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B173,B173" "0,1"
|
|
bitfld.long 0x00 12. "B172,B172" "0,1"
|
|
bitfld.long 0x00 11. "B171,B171" "0,1"
|
|
bitfld.long 0x00 10. "B170,B170" "0,1"
|
|
bitfld.long 0x00 9. "B169,B169" "0,1"
|
|
bitfld.long 0x00 8. "B168,B168" "0,1"
|
|
bitfld.long 0x00 7. "B167,B167" "0,1"
|
|
bitfld.long 0x00 6. "B166,B166" "0,1"
|
|
bitfld.long 0x00 5. "B165,B165" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B164,B164" "0,1"
|
|
bitfld.long 0x00 3. "B163,B163" "0,1"
|
|
bitfld.long 0x00 2. "B162,B162" "0,1"
|
|
bitfld.long 0x00 1. "B161,B161" "0,1"
|
|
bitfld.long 0x00 0. "B160,B160" "0,1"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MPCBB1_VCTR6,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B223,B223" "0,1"
|
|
bitfld.long 0x00 30. "B222,B222" "0,1"
|
|
bitfld.long 0x00 29. "B221,B221" "0,1"
|
|
bitfld.long 0x00 28. "B220,B220" "0,1"
|
|
bitfld.long 0x00 27. "B219,B219" "0,1"
|
|
bitfld.long 0x00 26. "B218,B218" "0,1"
|
|
bitfld.long 0x00 25. "B217,B217" "0,1"
|
|
bitfld.long 0x00 24. "B216,B216" "0,1"
|
|
bitfld.long 0x00 23. "B215,B215" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B214,B214" "0,1"
|
|
bitfld.long 0x00 21. "B213,B213" "0,1"
|
|
bitfld.long 0x00 20. "B212,B212" "0,1"
|
|
bitfld.long 0x00 19. "B211,B211" "0,1"
|
|
bitfld.long 0x00 18. "B210,B210" "0,1"
|
|
bitfld.long 0x00 17. "B209,B209" "0,1"
|
|
bitfld.long 0x00 16. "B208,B208" "0,1"
|
|
bitfld.long 0x00 15. "B207,B207" "0,1"
|
|
bitfld.long 0x00 14. "B206,B206" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B205,B205" "0,1"
|
|
bitfld.long 0x00 12. "B204,B204" "0,1"
|
|
bitfld.long 0x00 11. "B203,B203" "0,1"
|
|
bitfld.long 0x00 10. "B202,B202" "0,1"
|
|
bitfld.long 0x00 9. "B201,B201" "0,1"
|
|
bitfld.long 0x00 8. "B200,B200" "0,1"
|
|
bitfld.long 0x00 7. "B199,B199" "0,1"
|
|
bitfld.long 0x00 6. "B198,B198" "0,1"
|
|
bitfld.long 0x00 5. "B197,B197" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B196,B196" "0,1"
|
|
bitfld.long 0x00 3. "B195,B195" "0,1"
|
|
bitfld.long 0x00 2. "B194,B194" "0,1"
|
|
bitfld.long 0x00 1. "B193,B193" "0,1"
|
|
bitfld.long 0x00 0. "B192,B192" "0,1"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR7,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B255,B255" "0,1"
|
|
bitfld.long 0x00 30. "B254,B254" "0,1"
|
|
bitfld.long 0x00 29. "B253,B253" "0,1"
|
|
bitfld.long 0x00 28. "B252,B252" "0,1"
|
|
bitfld.long 0x00 27. "B251,B251" "0,1"
|
|
bitfld.long 0x00 26. "B250,B250" "0,1"
|
|
bitfld.long 0x00 25. "B249,B249" "0,1"
|
|
bitfld.long 0x00 24. "B248,B248" "0,1"
|
|
bitfld.long 0x00 23. "B247,B247" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B246,B246" "0,1"
|
|
bitfld.long 0x00 21. "B245,B245" "0,1"
|
|
bitfld.long 0x00 20. "B244,B244" "0,1"
|
|
bitfld.long 0x00 19. "B243,B243" "0,1"
|
|
bitfld.long 0x00 18. "B242,B242" "0,1"
|
|
bitfld.long 0x00 17. "B241,B241" "0,1"
|
|
bitfld.long 0x00 16. "B240,B240" "0,1"
|
|
bitfld.long 0x00 15. "B239,B239" "0,1"
|
|
bitfld.long 0x00 14. "B238,B238" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B237,B237" "0,1"
|
|
bitfld.long 0x00 12. "B236,B236" "0,1"
|
|
bitfld.long 0x00 11. "B235,B235" "0,1"
|
|
bitfld.long 0x00 10. "B234,B234" "0,1"
|
|
bitfld.long 0x00 9. "B233,B233" "0,1"
|
|
bitfld.long 0x00 8. "B232,B232" "0,1"
|
|
bitfld.long 0x00 7. "B231,B231" "0,1"
|
|
bitfld.long 0x00 6. "B230,B230" "0,1"
|
|
bitfld.long 0x00 5. "B229,B229" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B228,B228" "0,1"
|
|
bitfld.long 0x00 3. "B227,B227" "0,1"
|
|
bitfld.long 0x00 2. "B226,B226" "0,1"
|
|
bitfld.long 0x00 1. "B225,B225" "0,1"
|
|
bitfld.long 0x00 0. "B224,B224" "0,1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "MPCBB1_VCTR8,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B287,B287" "0,1"
|
|
bitfld.long 0x00 30. "B286,B286" "0,1"
|
|
bitfld.long 0x00 29. "B285,B285" "0,1"
|
|
bitfld.long 0x00 28. "B284,B284" "0,1"
|
|
bitfld.long 0x00 27. "B283,B283" "0,1"
|
|
bitfld.long 0x00 26. "B282,B282" "0,1"
|
|
bitfld.long 0x00 25. "B281,B281" "0,1"
|
|
bitfld.long 0x00 24. "B280,B280" "0,1"
|
|
bitfld.long 0x00 23. "B279,B279" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B278,B278" "0,1"
|
|
bitfld.long 0x00 21. "B277,B277" "0,1"
|
|
bitfld.long 0x00 20. "B276,B276" "0,1"
|
|
bitfld.long 0x00 19. "B275,B275" "0,1"
|
|
bitfld.long 0x00 18. "B274,B274" "0,1"
|
|
bitfld.long 0x00 17. "B273,B273" "0,1"
|
|
bitfld.long 0x00 16. "B272,B272" "0,1"
|
|
bitfld.long 0x00 15. "B271,B271" "0,1"
|
|
bitfld.long 0x00 14. "B270,B270" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B269,B269" "0,1"
|
|
bitfld.long 0x00 12. "B268,B268" "0,1"
|
|
bitfld.long 0x00 11. "B267,B267" "0,1"
|
|
bitfld.long 0x00 10. "B266,B266" "0,1"
|
|
bitfld.long 0x00 9. "B265,B265" "0,1"
|
|
bitfld.long 0x00 8. "B264,B264" "0,1"
|
|
bitfld.long 0x00 7. "B263,B263" "0,1"
|
|
bitfld.long 0x00 6. "B262,B262" "0,1"
|
|
bitfld.long 0x00 5. "B261,B261" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B260,B260" "0,1"
|
|
bitfld.long 0x00 3. "B259,B259" "0,1"
|
|
bitfld.long 0x00 2. "B258,B258" "0,1"
|
|
bitfld.long 0x00 1. "B257,B257" "0,1"
|
|
bitfld.long 0x00 0. "B256,B256" "0,1"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MPCBB1_VCTR9,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B319,B319" "0,1"
|
|
bitfld.long 0x00 30. "B318,B318" "0,1"
|
|
bitfld.long 0x00 29. "B317,B317" "0,1"
|
|
bitfld.long 0x00 28. "B316,B316" "0,1"
|
|
bitfld.long 0x00 27. "B315,B315" "0,1"
|
|
bitfld.long 0x00 26. "B314,B314" "0,1"
|
|
bitfld.long 0x00 25. "B313,B313" "0,1"
|
|
bitfld.long 0x00 24. "B312,B312" "0,1"
|
|
bitfld.long 0x00 23. "B311,B311" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B310,B310" "0,1"
|
|
bitfld.long 0x00 21. "B309,B309" "0,1"
|
|
bitfld.long 0x00 20. "B308,B308" "0,1"
|
|
bitfld.long 0x00 19. "B307,B307" "0,1"
|
|
bitfld.long 0x00 18. "B306,B306" "0,1"
|
|
bitfld.long 0x00 17. "B305,B305" "0,1"
|
|
bitfld.long 0x00 16. "B304,B304" "0,1"
|
|
bitfld.long 0x00 15. "B303,B303" "0,1"
|
|
bitfld.long 0x00 14. "B302,B302" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B301,B301" "0,1"
|
|
bitfld.long 0x00 12. "B300,B300" "0,1"
|
|
bitfld.long 0x00 11. "B299,B299" "0,1"
|
|
bitfld.long 0x00 10. "B298,B298" "0,1"
|
|
bitfld.long 0x00 9. "B297,B297" "0,1"
|
|
bitfld.long 0x00 8. "B296,B296" "0,1"
|
|
bitfld.long 0x00 7. "B295,B295" "0,1"
|
|
bitfld.long 0x00 6. "B294,B294" "0,1"
|
|
bitfld.long 0x00 5. "B293,B293" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B292,B292" "0,1"
|
|
bitfld.long 0x00 3. "B291,B291" "0,1"
|
|
bitfld.long 0x00 2. "B290,B290" "0,1"
|
|
bitfld.long 0x00 1. "B289,B289" "0,1"
|
|
bitfld.long 0x00 0. "B288,B288" "0,1"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "MPCBB1_VCTR10,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B351,B351" "0,1"
|
|
bitfld.long 0x00 30. "B350,B350" "0,1"
|
|
bitfld.long 0x00 29. "B349,B349" "0,1"
|
|
bitfld.long 0x00 28. "B348,B348" "0,1"
|
|
bitfld.long 0x00 27. "B347,B347" "0,1"
|
|
bitfld.long 0x00 26. "B346,B346" "0,1"
|
|
bitfld.long 0x00 25. "B345,B345" "0,1"
|
|
bitfld.long 0x00 24. "B344,B344" "0,1"
|
|
bitfld.long 0x00 23. "B343,B343" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B342,B342" "0,1"
|
|
bitfld.long 0x00 21. "B341,B341" "0,1"
|
|
bitfld.long 0x00 20. "B340,B340" "0,1"
|
|
bitfld.long 0x00 19. "B339,B339" "0,1"
|
|
bitfld.long 0x00 18. "B338,B338" "0,1"
|
|
bitfld.long 0x00 17. "B337,B337" "0,1"
|
|
bitfld.long 0x00 16. "B336,B336" "0,1"
|
|
bitfld.long 0x00 15. "B335,B335" "0,1"
|
|
bitfld.long 0x00 14. "B334,B334" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B333,B333" "0,1"
|
|
bitfld.long 0x00 12. "B332,B332" "0,1"
|
|
bitfld.long 0x00 11. "B331,B331" "0,1"
|
|
bitfld.long 0x00 10. "B330,B330" "0,1"
|
|
bitfld.long 0x00 9. "B329,B329" "0,1"
|
|
bitfld.long 0x00 8. "B328,B328" "0,1"
|
|
bitfld.long 0x00 7. "B327,B327" "0,1"
|
|
bitfld.long 0x00 6. "B326,B326" "0,1"
|
|
bitfld.long 0x00 5. "B325,B325" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B324,B324" "0,1"
|
|
bitfld.long 0x00 3. "B323,B323" "0,1"
|
|
bitfld.long 0x00 2. "B322,B322" "0,1"
|
|
bitfld.long 0x00 1. "B321,B321" "0,1"
|
|
bitfld.long 0x00 0. "B320,B320" "0,1"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR11,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B383,B383" "0,1"
|
|
bitfld.long 0x00 30. "B382,B382" "0,1"
|
|
bitfld.long 0x00 29. "B381,B381" "0,1"
|
|
bitfld.long 0x00 28. "B380,B380" "0,1"
|
|
bitfld.long 0x00 27. "B379,B379" "0,1"
|
|
bitfld.long 0x00 26. "B378,B378" "0,1"
|
|
bitfld.long 0x00 25. "B377,B377" "0,1"
|
|
bitfld.long 0x00 24. "B376,B376" "0,1"
|
|
bitfld.long 0x00 23. "B375,B375" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B374,B374" "0,1"
|
|
bitfld.long 0x00 21. "B373,B373" "0,1"
|
|
bitfld.long 0x00 20. "B372,B372" "0,1"
|
|
bitfld.long 0x00 19. "B371,B371" "0,1"
|
|
bitfld.long 0x00 18. "B370,B370" "0,1"
|
|
bitfld.long 0x00 17. "B369,B369" "0,1"
|
|
bitfld.long 0x00 16. "B368,B368" "0,1"
|
|
bitfld.long 0x00 15. "B367,B367" "0,1"
|
|
bitfld.long 0x00 14. "B366,B366" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B365,B365" "0,1"
|
|
bitfld.long 0x00 12. "B364,B364" "0,1"
|
|
bitfld.long 0x00 11. "B363,B363" "0,1"
|
|
bitfld.long 0x00 10. "B362,B362" "0,1"
|
|
bitfld.long 0x00 9. "B361,B361" "0,1"
|
|
bitfld.long 0x00 8. "B360,B360" "0,1"
|
|
bitfld.long 0x00 7. "B359,B359" "0,1"
|
|
bitfld.long 0x00 6. "B358,B358" "0,1"
|
|
bitfld.long 0x00 5. "B357,B357" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B356,B356" "0,1"
|
|
bitfld.long 0x00 3. "B355,B355" "0,1"
|
|
bitfld.long 0x00 2. "B354,B354" "0,1"
|
|
bitfld.long 0x00 1. "B353,B353" "0,1"
|
|
bitfld.long 0x00 0. "B352,B352" "0,1"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "MPCBB1_VCTR12,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B415,B415" "0,1"
|
|
bitfld.long 0x00 30. "B414,B414" "0,1"
|
|
bitfld.long 0x00 29. "B413,B413" "0,1"
|
|
bitfld.long 0x00 28. "B412,B412" "0,1"
|
|
bitfld.long 0x00 27. "B411,B411" "0,1"
|
|
bitfld.long 0x00 26. "B410,B410" "0,1"
|
|
bitfld.long 0x00 25. "B409,B409" "0,1"
|
|
bitfld.long 0x00 24. "B408,B408" "0,1"
|
|
bitfld.long 0x00 23. "B407,B407" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B406,B406" "0,1"
|
|
bitfld.long 0x00 21. "B405,B405" "0,1"
|
|
bitfld.long 0x00 20. "B404,B404" "0,1"
|
|
bitfld.long 0x00 19. "B403,B403" "0,1"
|
|
bitfld.long 0x00 18. "B402,B402" "0,1"
|
|
bitfld.long 0x00 17. "B401,B401" "0,1"
|
|
bitfld.long 0x00 16. "B400,B400" "0,1"
|
|
bitfld.long 0x00 15. "B399,B399" "0,1"
|
|
bitfld.long 0x00 14. "B398,B398" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B397,B397" "0,1"
|
|
bitfld.long 0x00 12. "B396,B396" "0,1"
|
|
bitfld.long 0x00 11. "B395,B395" "0,1"
|
|
bitfld.long 0x00 10. "B394,B394" "0,1"
|
|
bitfld.long 0x00 9. "B393,B393" "0,1"
|
|
bitfld.long 0x00 8. "B392,B392" "0,1"
|
|
bitfld.long 0x00 7. "B391,B391" "0,1"
|
|
bitfld.long 0x00 6. "B390,B390" "0,1"
|
|
bitfld.long 0x00 5. "B389,B389" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B388,B388" "0,1"
|
|
bitfld.long 0x00 3. "B387,B387" "0,1"
|
|
bitfld.long 0x00 2. "B386,B386" "0,1"
|
|
bitfld.long 0x00 1. "B385,B385" "0,1"
|
|
bitfld.long 0x00 0. "B384,B384" "0,1"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "MPCBB1_VCTR13,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B447,B447" "0,1"
|
|
bitfld.long 0x00 30. "B446,B446" "0,1"
|
|
bitfld.long 0x00 29. "B445,B445" "0,1"
|
|
bitfld.long 0x00 28. "B444,B444" "0,1"
|
|
bitfld.long 0x00 27. "B443,B443" "0,1"
|
|
bitfld.long 0x00 26. "B442,B442" "0,1"
|
|
bitfld.long 0x00 25. "B441,B441" "0,1"
|
|
bitfld.long 0x00 24. "B440,B440" "0,1"
|
|
bitfld.long 0x00 23. "B439,B439" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B438,B438" "0,1"
|
|
bitfld.long 0x00 21. "B437,B437" "0,1"
|
|
bitfld.long 0x00 20. "B436,B436" "0,1"
|
|
bitfld.long 0x00 19. "B435,B435" "0,1"
|
|
bitfld.long 0x00 18. "B434,B434" "0,1"
|
|
bitfld.long 0x00 17. "B433,B433" "0,1"
|
|
bitfld.long 0x00 16. "B432,B432" "0,1"
|
|
bitfld.long 0x00 15. "B431,B431" "0,1"
|
|
bitfld.long 0x00 14. "B430,B430" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B429,B429" "0,1"
|
|
bitfld.long 0x00 12. "B428,B428" "0,1"
|
|
bitfld.long 0x00 11. "B427,B427" "0,1"
|
|
bitfld.long 0x00 10. "B426,B426" "0,1"
|
|
bitfld.long 0x00 9. "B425,B425" "0,1"
|
|
bitfld.long 0x00 8. "B424,B424" "0,1"
|
|
bitfld.long 0x00 7. "B423,B423" "0,1"
|
|
bitfld.long 0x00 6. "B422,B422" "0,1"
|
|
bitfld.long 0x00 5. "B421,B421" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B420,B420" "0,1"
|
|
bitfld.long 0x00 3. "B419,B419" "0,1"
|
|
bitfld.long 0x00 2. "B418,B418" "0,1"
|
|
bitfld.long 0x00 1. "B417,B417" "0,1"
|
|
bitfld.long 0x00 0. "B416,B416" "0,1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "MPCBB1_VCTR14,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B479,B479" "0,1"
|
|
bitfld.long 0x00 30. "B478,B478" "0,1"
|
|
bitfld.long 0x00 29. "B477,B477" "0,1"
|
|
bitfld.long 0x00 28. "B476,B476" "0,1"
|
|
bitfld.long 0x00 27. "B475,B475" "0,1"
|
|
bitfld.long 0x00 26. "B474,B474" "0,1"
|
|
bitfld.long 0x00 25. "B473,B473" "0,1"
|
|
bitfld.long 0x00 24. "B472,B472" "0,1"
|
|
bitfld.long 0x00 23. "B471,B471" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B470,B470" "0,1"
|
|
bitfld.long 0x00 21. "B469,B469" "0,1"
|
|
bitfld.long 0x00 20. "B468,B468" "0,1"
|
|
bitfld.long 0x00 19. "B467,B467" "0,1"
|
|
bitfld.long 0x00 18. "B466,B466" "0,1"
|
|
bitfld.long 0x00 17. "B465,B465" "0,1"
|
|
bitfld.long 0x00 16. "B464,B464" "0,1"
|
|
bitfld.long 0x00 15. "B463,B463" "0,1"
|
|
bitfld.long 0x00 14. "B462,B462" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B461,B461" "0,1"
|
|
bitfld.long 0x00 12. "B460,B460" "0,1"
|
|
bitfld.long 0x00 11. "B459,B459" "0,1"
|
|
bitfld.long 0x00 10. "B458,B458" "0,1"
|
|
bitfld.long 0x00 9. "B457,B457" "0,1"
|
|
bitfld.long 0x00 8. "B456,B456" "0,1"
|
|
bitfld.long 0x00 7. "B455,B455" "0,1"
|
|
bitfld.long 0x00 6. "B454,B454" "0,1"
|
|
bitfld.long 0x00 5. "B453,B453" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B452,B452" "0,1"
|
|
bitfld.long 0x00 3. "B451,B451" "0,1"
|
|
bitfld.long 0x00 2. "B450,B450" "0,1"
|
|
bitfld.long 0x00 1. "B449,B449" "0,1"
|
|
bitfld.long 0x00 0. "B448,B448" "0,1"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR15,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B511,B511" "0,1"
|
|
bitfld.long 0x00 30. "B510,B510" "0,1"
|
|
bitfld.long 0x00 29. "B509,B509" "0,1"
|
|
bitfld.long 0x00 28. "B508,B508" "0,1"
|
|
bitfld.long 0x00 27. "B507,B507" "0,1"
|
|
bitfld.long 0x00 26. "B506,B506" "0,1"
|
|
bitfld.long 0x00 25. "B505,B505" "0,1"
|
|
bitfld.long 0x00 24. "B504,B504" "0,1"
|
|
bitfld.long 0x00 23. "B503,B503" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B502,B502" "0,1"
|
|
bitfld.long 0x00 21. "B501,B501" "0,1"
|
|
bitfld.long 0x00 20. "B500,B500" "0,1"
|
|
bitfld.long 0x00 19. "B499,B499" "0,1"
|
|
bitfld.long 0x00 18. "B498,B498" "0,1"
|
|
bitfld.long 0x00 17. "B497,B497" "0,1"
|
|
bitfld.long 0x00 16. "B496,B496" "0,1"
|
|
bitfld.long 0x00 15. "B495,B495" "0,1"
|
|
bitfld.long 0x00 14. "B494,B494" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B493,B493" "0,1"
|
|
bitfld.long 0x00 12. "B492,B492" "0,1"
|
|
bitfld.long 0x00 11. "B491,B491" "0,1"
|
|
bitfld.long 0x00 10. "B490,B490" "0,1"
|
|
bitfld.long 0x00 9. "B489,B489" "0,1"
|
|
bitfld.long 0x00 8. "B488,B488" "0,1"
|
|
bitfld.long 0x00 7. "B487,B487" "0,1"
|
|
bitfld.long 0x00 6. "B486,B486" "0,1"
|
|
bitfld.long 0x00 5. "B485,B485" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B484,B484" "0,1"
|
|
bitfld.long 0x00 3. "B483,B483" "0,1"
|
|
bitfld.long 0x00 2. "B482,B482" "0,1"
|
|
bitfld.long 0x00 1. "B481,B481" "0,1"
|
|
bitfld.long 0x00 0. "B480,B480" "0,1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "MPCBB1_VCTR16,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B543,B543" "0,1"
|
|
bitfld.long 0x00 30. "B542,B542" "0,1"
|
|
bitfld.long 0x00 29. "B541,B541" "0,1"
|
|
bitfld.long 0x00 28. "B540,B540" "0,1"
|
|
bitfld.long 0x00 27. "B539,B539" "0,1"
|
|
bitfld.long 0x00 26. "B538,B538" "0,1"
|
|
bitfld.long 0x00 25. "B537,B537" "0,1"
|
|
bitfld.long 0x00 24. "B536,B536" "0,1"
|
|
bitfld.long 0x00 23. "B535,B535" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B534,B534" "0,1"
|
|
bitfld.long 0x00 21. "B533,B533" "0,1"
|
|
bitfld.long 0x00 20. "B532,B532" "0,1"
|
|
bitfld.long 0x00 19. "B531,B531" "0,1"
|
|
bitfld.long 0x00 18. "B530,B530" "0,1"
|
|
bitfld.long 0x00 17. "B529,B529" "0,1"
|
|
bitfld.long 0x00 16. "B528,B528" "0,1"
|
|
bitfld.long 0x00 15. "B527,B527" "0,1"
|
|
bitfld.long 0x00 14. "B526,B526" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B525,B525" "0,1"
|
|
bitfld.long 0x00 12. "B524,B524" "0,1"
|
|
bitfld.long 0x00 11. "B523,B523" "0,1"
|
|
bitfld.long 0x00 10. "B522,B522" "0,1"
|
|
bitfld.long 0x00 9. "B521,B521" "0,1"
|
|
bitfld.long 0x00 8. "B520,B520" "0,1"
|
|
bitfld.long 0x00 7. "B519,B519" "0,1"
|
|
bitfld.long 0x00 6. "B518,B518" "0,1"
|
|
bitfld.long 0x00 5. "B517,B517" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B516,B516" "0,1"
|
|
bitfld.long 0x00 3. "B515,B515" "0,1"
|
|
bitfld.long 0x00 2. "B514,B514" "0,1"
|
|
bitfld.long 0x00 1. "B513,B513" "0,1"
|
|
bitfld.long 0x00 0. "B512,B512" "0,1"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "MPCBB1_VCTR17,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B575,B575" "0,1"
|
|
bitfld.long 0x00 30. "B574,B574" "0,1"
|
|
bitfld.long 0x00 29. "B573,B573" "0,1"
|
|
bitfld.long 0x00 28. "B572,B572" "0,1"
|
|
bitfld.long 0x00 27. "B571,B571" "0,1"
|
|
bitfld.long 0x00 26. "B570,B570" "0,1"
|
|
bitfld.long 0x00 25. "B569,B569" "0,1"
|
|
bitfld.long 0x00 24. "B568,B568" "0,1"
|
|
bitfld.long 0x00 23. "B567,B567" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B566,B566" "0,1"
|
|
bitfld.long 0x00 21. "B565,B565" "0,1"
|
|
bitfld.long 0x00 20. "B564,B564" "0,1"
|
|
bitfld.long 0x00 19. "B563,B563" "0,1"
|
|
bitfld.long 0x00 18. "B562,B562" "0,1"
|
|
bitfld.long 0x00 17. "B561,B561" "0,1"
|
|
bitfld.long 0x00 16. "B560,B560" "0,1"
|
|
bitfld.long 0x00 15. "B559,B559" "0,1"
|
|
bitfld.long 0x00 14. "B558,B558" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B557,B557" "0,1"
|
|
bitfld.long 0x00 12. "B556,B556" "0,1"
|
|
bitfld.long 0x00 11. "B555,B555" "0,1"
|
|
bitfld.long 0x00 10. "B554,B554" "0,1"
|
|
bitfld.long 0x00 9. "B553,B553" "0,1"
|
|
bitfld.long 0x00 8. "B552,B552" "0,1"
|
|
bitfld.long 0x00 7. "B551,B551" "0,1"
|
|
bitfld.long 0x00 6. "B550,B550" "0,1"
|
|
bitfld.long 0x00 5. "B549,B549" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B548,B548" "0,1"
|
|
bitfld.long 0x00 3. "B547,B547" "0,1"
|
|
bitfld.long 0x00 2. "B546,B546" "0,1"
|
|
bitfld.long 0x00 1. "B545,B545" "0,1"
|
|
bitfld.long 0x00 0. "B544,B544" "0,1"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "MPCBB1_VCTR18,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B607,B607" "0,1"
|
|
bitfld.long 0x00 30. "B606,B606" "0,1"
|
|
bitfld.long 0x00 29. "B605,B605" "0,1"
|
|
bitfld.long 0x00 28. "B604,B604" "0,1"
|
|
bitfld.long 0x00 27. "B603,B603" "0,1"
|
|
bitfld.long 0x00 26. "B602,B602" "0,1"
|
|
bitfld.long 0x00 25. "B601,B601" "0,1"
|
|
bitfld.long 0x00 24. "B600,B600" "0,1"
|
|
bitfld.long 0x00 23. "B599,B599" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B598,B598" "0,1"
|
|
bitfld.long 0x00 21. "B597,B597" "0,1"
|
|
bitfld.long 0x00 20. "B596,B596" "0,1"
|
|
bitfld.long 0x00 19. "B595,B595" "0,1"
|
|
bitfld.long 0x00 18. "B594,B594" "0,1"
|
|
bitfld.long 0x00 17. "B593,B593" "0,1"
|
|
bitfld.long 0x00 16. "B592,B592" "0,1"
|
|
bitfld.long 0x00 15. "B591,B591" "0,1"
|
|
bitfld.long 0x00 14. "B590,B590" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B589,B589" "0,1"
|
|
bitfld.long 0x00 12. "B588,B588" "0,1"
|
|
bitfld.long 0x00 11. "B587,B587" "0,1"
|
|
bitfld.long 0x00 10. "B586,B586" "0,1"
|
|
bitfld.long 0x00 9. "B585,B585" "0,1"
|
|
bitfld.long 0x00 8. "B584,B584" "0,1"
|
|
bitfld.long 0x00 7. "B583,B583" "0,1"
|
|
bitfld.long 0x00 6. "B582,B582" "0,1"
|
|
bitfld.long 0x00 5. "B581,B581" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B580,B580" "0,1"
|
|
bitfld.long 0x00 3. "B579,B579" "0,1"
|
|
bitfld.long 0x00 2. "B578,B578" "0,1"
|
|
bitfld.long 0x00 1. "B577,B577" "0,1"
|
|
bitfld.long 0x00 0. "B576,B576" "0,1"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR19,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B639,B639" "0,1"
|
|
bitfld.long 0x00 30. "B638,B638" "0,1"
|
|
bitfld.long 0x00 29. "B637,B637" "0,1"
|
|
bitfld.long 0x00 28. "B636,B636" "0,1"
|
|
bitfld.long 0x00 27. "B635,B635" "0,1"
|
|
bitfld.long 0x00 26. "B634,B634" "0,1"
|
|
bitfld.long 0x00 25. "B633,B633" "0,1"
|
|
bitfld.long 0x00 24. "B632,B632" "0,1"
|
|
bitfld.long 0x00 23. "B631,B631" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B630,B630" "0,1"
|
|
bitfld.long 0x00 21. "B629,B629" "0,1"
|
|
bitfld.long 0x00 20. "B628,B628" "0,1"
|
|
bitfld.long 0x00 19. "B627,B627" "0,1"
|
|
bitfld.long 0x00 18. "B626,B626" "0,1"
|
|
bitfld.long 0x00 17. "B625,B625" "0,1"
|
|
bitfld.long 0x00 16. "B624,B624" "0,1"
|
|
bitfld.long 0x00 15. "B623,B623" "0,1"
|
|
bitfld.long 0x00 14. "B622,B622" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B621,B621" "0,1"
|
|
bitfld.long 0x00 12. "B620,B620" "0,1"
|
|
bitfld.long 0x00 11. "B619,B619" "0,1"
|
|
bitfld.long 0x00 10. "B618,B618" "0,1"
|
|
bitfld.long 0x00 9. "B617,B617" "0,1"
|
|
bitfld.long 0x00 8. "B616,B616" "0,1"
|
|
bitfld.long 0x00 7. "B615,B615" "0,1"
|
|
bitfld.long 0x00 6. "B614,B614" "0,1"
|
|
bitfld.long 0x00 5. "B613,B613" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B612,B612" "0,1"
|
|
bitfld.long 0x00 3. "B611,B611" "0,1"
|
|
bitfld.long 0x00 2. "B610,B610" "0,1"
|
|
bitfld.long 0x00 1. "B609,B609" "0,1"
|
|
bitfld.long 0x00 0. "B608,B608" "0,1"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "MPCBB1_VCTR20,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B671,B671" "0,1"
|
|
bitfld.long 0x00 30. "B670,B670" "0,1"
|
|
bitfld.long 0x00 29. "B669,B669" "0,1"
|
|
bitfld.long 0x00 28. "B668,B668" "0,1"
|
|
bitfld.long 0x00 27. "B667,B667" "0,1"
|
|
bitfld.long 0x00 26. "B666,B666" "0,1"
|
|
bitfld.long 0x00 25. "B665,B665" "0,1"
|
|
bitfld.long 0x00 24. "B664,B664" "0,1"
|
|
bitfld.long 0x00 23. "B663,B663" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B662,B662" "0,1"
|
|
bitfld.long 0x00 21. "B661,B661" "0,1"
|
|
bitfld.long 0x00 20. "B660,B660" "0,1"
|
|
bitfld.long 0x00 19. "B659,B659" "0,1"
|
|
bitfld.long 0x00 18. "B658,B658" "0,1"
|
|
bitfld.long 0x00 17. "B657,B657" "0,1"
|
|
bitfld.long 0x00 16. "B656,B656" "0,1"
|
|
bitfld.long 0x00 15. "B655,B655" "0,1"
|
|
bitfld.long 0x00 14. "B654,B654" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B653,B653" "0,1"
|
|
bitfld.long 0x00 12. "B652,B652" "0,1"
|
|
bitfld.long 0x00 11. "B651,B651" "0,1"
|
|
bitfld.long 0x00 10. "B650,B650" "0,1"
|
|
bitfld.long 0x00 9. "B649,B649" "0,1"
|
|
bitfld.long 0x00 8. "B648,B648" "0,1"
|
|
bitfld.long 0x00 7. "B647,B647" "0,1"
|
|
bitfld.long 0x00 6. "B646,B646" "0,1"
|
|
bitfld.long 0x00 5. "B645,B645" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B644,B644" "0,1"
|
|
bitfld.long 0x00 3. "B643,B643" "0,1"
|
|
bitfld.long 0x00 2. "B642,B642" "0,1"
|
|
bitfld.long 0x00 1. "B641,B641" "0,1"
|
|
bitfld.long 0x00 0. "B640,B640" "0,1"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "MPCBB1_VCTR21,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B703,B703" "0,1"
|
|
bitfld.long 0x00 30. "B702,B702" "0,1"
|
|
bitfld.long 0x00 29. "B701,B701" "0,1"
|
|
bitfld.long 0x00 28. "B700,B700" "0,1"
|
|
bitfld.long 0x00 27. "B699,B699" "0,1"
|
|
bitfld.long 0x00 26. "B698,B698" "0,1"
|
|
bitfld.long 0x00 25. "B697,B697" "0,1"
|
|
bitfld.long 0x00 24. "B696,B696" "0,1"
|
|
bitfld.long 0x00 23. "B695,B695" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B694,B694" "0,1"
|
|
bitfld.long 0x00 21. "B693,B693" "0,1"
|
|
bitfld.long 0x00 20. "B692,B692" "0,1"
|
|
bitfld.long 0x00 19. "B691,B691" "0,1"
|
|
bitfld.long 0x00 18. "B690,B690" "0,1"
|
|
bitfld.long 0x00 17. "B689,B689" "0,1"
|
|
bitfld.long 0x00 16. "B688,B688" "0,1"
|
|
bitfld.long 0x00 15. "B687,B687" "0,1"
|
|
bitfld.long 0x00 14. "B686,B686" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B685,B685" "0,1"
|
|
bitfld.long 0x00 12. "B684,B684" "0,1"
|
|
bitfld.long 0x00 11. "B683,B683" "0,1"
|
|
bitfld.long 0x00 10. "B682,B682" "0,1"
|
|
bitfld.long 0x00 9. "B681,B681" "0,1"
|
|
bitfld.long 0x00 8. "B680,B680" "0,1"
|
|
bitfld.long 0x00 7. "B679,B679" "0,1"
|
|
bitfld.long 0x00 6. "B678,B678" "0,1"
|
|
bitfld.long 0x00 5. "B677,B677" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B676,B676" "0,1"
|
|
bitfld.long 0x00 3. "B675,B675" "0,1"
|
|
bitfld.long 0x00 2. "B674,B674" "0,1"
|
|
bitfld.long 0x00 1. "B673,B673" "0,1"
|
|
bitfld.long 0x00 0. "B672,B672" "0,1"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "MPCBB1_VCTR22,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B735,B735" "0,1"
|
|
bitfld.long 0x00 30. "B734,B734" "0,1"
|
|
bitfld.long 0x00 29. "B733,B733" "0,1"
|
|
bitfld.long 0x00 28. "B732,B732" "0,1"
|
|
bitfld.long 0x00 27. "B731,B731" "0,1"
|
|
bitfld.long 0x00 26. "B730,B730" "0,1"
|
|
bitfld.long 0x00 25. "B729,B729" "0,1"
|
|
bitfld.long 0x00 24. "B728,B728" "0,1"
|
|
bitfld.long 0x00 23. "B727,B727" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B726,B726" "0,1"
|
|
bitfld.long 0x00 21. "B725,B725" "0,1"
|
|
bitfld.long 0x00 20. "B724,B724" "0,1"
|
|
bitfld.long 0x00 19. "B723,B723" "0,1"
|
|
bitfld.long 0x00 18. "B722,B722" "0,1"
|
|
bitfld.long 0x00 17. "B721,B721" "0,1"
|
|
bitfld.long 0x00 16. "B720,B720" "0,1"
|
|
bitfld.long 0x00 15. "B719,B719" "0,1"
|
|
bitfld.long 0x00 14. "B718,B718" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B717,B717" "0,1"
|
|
bitfld.long 0x00 12. "B716,B716" "0,1"
|
|
bitfld.long 0x00 11. "B715,B715" "0,1"
|
|
bitfld.long 0x00 10. "B714,B714" "0,1"
|
|
bitfld.long 0x00 9. "B713,B713" "0,1"
|
|
bitfld.long 0x00 8. "B712,B712" "0,1"
|
|
bitfld.long 0x00 7. "B711,B711" "0,1"
|
|
bitfld.long 0x00 6. "B710,B710" "0,1"
|
|
bitfld.long 0x00 5. "B709,B709" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B708,B708" "0,1"
|
|
bitfld.long 0x00 3. "B707,B707" "0,1"
|
|
bitfld.long 0x00 2. "B706,B706" "0,1"
|
|
bitfld.long 0x00 1. "B705,B705" "0,1"
|
|
bitfld.long 0x00 0. "B704,B704" "0,1"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR23,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B767,B767" "0,1"
|
|
bitfld.long 0x00 30. "B766,B766" "0,1"
|
|
bitfld.long 0x00 29. "B765,B765" "0,1"
|
|
bitfld.long 0x00 28. "B764,B764" "0,1"
|
|
bitfld.long 0x00 27. "B763,B763" "0,1"
|
|
bitfld.long 0x00 26. "B762,B762" "0,1"
|
|
bitfld.long 0x00 25. "B761,B761" "0,1"
|
|
bitfld.long 0x00 24. "B760,B760" "0,1"
|
|
bitfld.long 0x00 23. "B759,B759" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B758,B758" "0,1"
|
|
bitfld.long 0x00 21. "B757,B757" "0,1"
|
|
bitfld.long 0x00 20. "B756,B756" "0,1"
|
|
bitfld.long 0x00 19. "B755,B755" "0,1"
|
|
bitfld.long 0x00 18. "B754,B754" "0,1"
|
|
bitfld.long 0x00 17. "B753,B753" "0,1"
|
|
bitfld.long 0x00 16. "B752,B752" "0,1"
|
|
bitfld.long 0x00 15. "B751,B751" "0,1"
|
|
bitfld.long 0x00 14. "B750,B750" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B749,B749" "0,1"
|
|
bitfld.long 0x00 12. "B748,B748" "0,1"
|
|
bitfld.long 0x00 11. "B747,B747" "0,1"
|
|
bitfld.long 0x00 10. "B746,B746" "0,1"
|
|
bitfld.long 0x00 9. "B745,B745" "0,1"
|
|
bitfld.long 0x00 8. "B744,B744" "0,1"
|
|
bitfld.long 0x00 7. "B743,B743" "0,1"
|
|
bitfld.long 0x00 6. "B742,B742" "0,1"
|
|
bitfld.long 0x00 5. "B741,B741" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B740,B740" "0,1"
|
|
bitfld.long 0x00 3. "B739,B739" "0,1"
|
|
bitfld.long 0x00 2. "B738,B738" "0,1"
|
|
bitfld.long 0x00 1. "B737,B737" "0,1"
|
|
bitfld.long 0x00 0. "B736,B736" "0,1"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "MPCBB1_VCTR24,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B799,B799" "0,1"
|
|
bitfld.long 0x00 30. "B798,B798" "0,1"
|
|
bitfld.long 0x00 29. "B797,B797" "0,1"
|
|
bitfld.long 0x00 28. "B796,B796" "0,1"
|
|
bitfld.long 0x00 27. "B795,B795" "0,1"
|
|
bitfld.long 0x00 26. "B794,B794" "0,1"
|
|
bitfld.long 0x00 25. "B793,B793" "0,1"
|
|
bitfld.long 0x00 24. "B792,B792" "0,1"
|
|
bitfld.long 0x00 23. "B791,B791" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B790,B790" "0,1"
|
|
bitfld.long 0x00 21. "B789,B789" "0,1"
|
|
bitfld.long 0x00 20. "B788,B788" "0,1"
|
|
bitfld.long 0x00 19. "B787,B787" "0,1"
|
|
bitfld.long 0x00 18. "B786,B786" "0,1"
|
|
bitfld.long 0x00 17. "B785,B785" "0,1"
|
|
bitfld.long 0x00 16. "B784,B784" "0,1"
|
|
bitfld.long 0x00 15. "B783,B783" "0,1"
|
|
bitfld.long 0x00 14. "B782,B782" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B781,B781" "0,1"
|
|
bitfld.long 0x00 12. "B780,B780" "0,1"
|
|
bitfld.long 0x00 11. "B779,B779" "0,1"
|
|
bitfld.long 0x00 10. "B778,B778" "0,1"
|
|
bitfld.long 0x00 9. "B777,B777" "0,1"
|
|
bitfld.long 0x00 8. "B776,B776" "0,1"
|
|
bitfld.long 0x00 7. "B775,B775" "0,1"
|
|
bitfld.long 0x00 6. "B774,B774" "0,1"
|
|
bitfld.long 0x00 5. "B773,B773" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B772,B772" "0,1"
|
|
bitfld.long 0x00 3. "B771,B771" "0,1"
|
|
bitfld.long 0x00 2. "B770,B770" "0,1"
|
|
bitfld.long 0x00 1. "B769,B769" "0,1"
|
|
bitfld.long 0x00 0. "B768,B768" "0,1"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "MPCBB1_VCTR25,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B831,B831" "0,1"
|
|
bitfld.long 0x00 30. "B830,B830" "0,1"
|
|
bitfld.long 0x00 29. "B829,B829" "0,1"
|
|
bitfld.long 0x00 28. "B828,B828" "0,1"
|
|
bitfld.long 0x00 27. "B827,B827" "0,1"
|
|
bitfld.long 0x00 26. "B826,B826" "0,1"
|
|
bitfld.long 0x00 25. "B825,B825" "0,1"
|
|
bitfld.long 0x00 24. "B824,B824" "0,1"
|
|
bitfld.long 0x00 23. "B823,B823" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B822,B822" "0,1"
|
|
bitfld.long 0x00 21. "B821,B821" "0,1"
|
|
bitfld.long 0x00 20. "B820,B820" "0,1"
|
|
bitfld.long 0x00 19. "B819,B819" "0,1"
|
|
bitfld.long 0x00 18. "B818,B818" "0,1"
|
|
bitfld.long 0x00 17. "B817,B817" "0,1"
|
|
bitfld.long 0x00 16. "B816,B816" "0,1"
|
|
bitfld.long 0x00 15. "B815,B815" "0,1"
|
|
bitfld.long 0x00 14. "B814,B814" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B813,B813" "0,1"
|
|
bitfld.long 0x00 12. "B812,B812" "0,1"
|
|
bitfld.long 0x00 11. "B811,B811" "0,1"
|
|
bitfld.long 0x00 10. "B810,B810" "0,1"
|
|
bitfld.long 0x00 9. "B809,B809" "0,1"
|
|
bitfld.long 0x00 8. "B808,B808" "0,1"
|
|
bitfld.long 0x00 7. "B807,B807" "0,1"
|
|
bitfld.long 0x00 6. "B806,B806" "0,1"
|
|
bitfld.long 0x00 5. "B805,B805" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B804,B804" "0,1"
|
|
bitfld.long 0x00 3. "B803,B803" "0,1"
|
|
bitfld.long 0x00 2. "B802,B802" "0,1"
|
|
bitfld.long 0x00 1. "B801,B801" "0,1"
|
|
bitfld.long 0x00 0. "B800,B800" "0,1"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "MPCBB1_VCTR26,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B863,B863" "0,1"
|
|
bitfld.long 0x00 30. "B862,B862" "0,1"
|
|
bitfld.long 0x00 29. "B861,B861" "0,1"
|
|
bitfld.long 0x00 28. "B860,B860" "0,1"
|
|
bitfld.long 0x00 27. "B859,B859" "0,1"
|
|
bitfld.long 0x00 26. "B858,B858" "0,1"
|
|
bitfld.long 0x00 25. "B857,B857" "0,1"
|
|
bitfld.long 0x00 24. "B856,B856" "0,1"
|
|
bitfld.long 0x00 23. "B855,B855" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B854,B854" "0,1"
|
|
bitfld.long 0x00 21. "B853,B853" "0,1"
|
|
bitfld.long 0x00 20. "B852,B852" "0,1"
|
|
bitfld.long 0x00 19. "B851,B851" "0,1"
|
|
bitfld.long 0x00 18. "B850,B850" "0,1"
|
|
bitfld.long 0x00 17. "B849,B849" "0,1"
|
|
bitfld.long 0x00 16. "B848,B848" "0,1"
|
|
bitfld.long 0x00 15. "B847,B847" "0,1"
|
|
bitfld.long 0x00 14. "B846,B846" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B845,B845" "0,1"
|
|
bitfld.long 0x00 12. "B844,B844" "0,1"
|
|
bitfld.long 0x00 11. "B843,B843" "0,1"
|
|
bitfld.long 0x00 10. "B842,B842" "0,1"
|
|
bitfld.long 0x00 9. "B841,B841" "0,1"
|
|
bitfld.long 0x00 8. "B840,B840" "0,1"
|
|
bitfld.long 0x00 7. "B839,B839" "0,1"
|
|
bitfld.long 0x00 6. "B838,B838" "0,1"
|
|
bitfld.long 0x00 5. "B837,B837" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B836,B836" "0,1"
|
|
bitfld.long 0x00 3. "B835,B835" "0,1"
|
|
bitfld.long 0x00 2. "B834,B834" "0,1"
|
|
bitfld.long 0x00 1. "B833,B833" "0,1"
|
|
bitfld.long 0x00 0. "B832,B832" "0,1"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR27,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B895,B895" "0,1"
|
|
bitfld.long 0x00 30. "B894,B894" "0,1"
|
|
bitfld.long 0x00 29. "B893,B893" "0,1"
|
|
bitfld.long 0x00 28. "B892,B892" "0,1"
|
|
bitfld.long 0x00 27. "B891,B891" "0,1"
|
|
bitfld.long 0x00 26. "B890,B890" "0,1"
|
|
bitfld.long 0x00 25. "B889,B889" "0,1"
|
|
bitfld.long 0x00 24. "B888,B888" "0,1"
|
|
bitfld.long 0x00 23. "B887,B887" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B886,B886" "0,1"
|
|
bitfld.long 0x00 21. "B885,B885" "0,1"
|
|
bitfld.long 0x00 20. "B884,B884" "0,1"
|
|
bitfld.long 0x00 19. "B883,B883" "0,1"
|
|
bitfld.long 0x00 18. "B882,B882" "0,1"
|
|
bitfld.long 0x00 17. "B881,B881" "0,1"
|
|
bitfld.long 0x00 16. "B880,B880" "0,1"
|
|
bitfld.long 0x00 15. "B879,B879" "0,1"
|
|
bitfld.long 0x00 14. "B878,B878" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B877,B877" "0,1"
|
|
bitfld.long 0x00 12. "B876,B876" "0,1"
|
|
bitfld.long 0x00 11. "B875,B875" "0,1"
|
|
bitfld.long 0x00 10. "B874,B874" "0,1"
|
|
bitfld.long 0x00 9. "B873,B873" "0,1"
|
|
bitfld.long 0x00 8. "B872,B872" "0,1"
|
|
bitfld.long 0x00 7. "B871,B871" "0,1"
|
|
bitfld.long 0x00 6. "B870,B870" "0,1"
|
|
bitfld.long 0x00 5. "B869,B869" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B868,B868" "0,1"
|
|
bitfld.long 0x00 3. "B867,B867" "0,1"
|
|
bitfld.long 0x00 2. "B866,B866" "0,1"
|
|
bitfld.long 0x00 1. "B865,B865" "0,1"
|
|
bitfld.long 0x00 0. "B864,B864" "0,1"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "MPCBB1_VCTR28,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B927,B927" "0,1"
|
|
bitfld.long 0x00 30. "B926,B926" "0,1"
|
|
bitfld.long 0x00 29. "B925,B925" "0,1"
|
|
bitfld.long 0x00 28. "B924,B924" "0,1"
|
|
bitfld.long 0x00 27. "B923,B923" "0,1"
|
|
bitfld.long 0x00 26. "B922,B922" "0,1"
|
|
bitfld.long 0x00 25. "B921,B921" "0,1"
|
|
bitfld.long 0x00 24. "B920,B920" "0,1"
|
|
bitfld.long 0x00 23. "B919,B919" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B918,B918" "0,1"
|
|
bitfld.long 0x00 21. "B917,B917" "0,1"
|
|
bitfld.long 0x00 20. "B916,B916" "0,1"
|
|
bitfld.long 0x00 19. "B915,B915" "0,1"
|
|
bitfld.long 0x00 18. "B914,B914" "0,1"
|
|
bitfld.long 0x00 17. "B913,B913" "0,1"
|
|
bitfld.long 0x00 16. "B912,B912" "0,1"
|
|
bitfld.long 0x00 15. "B911,B911" "0,1"
|
|
bitfld.long 0x00 14. "B910,B910" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B909,B909" "0,1"
|
|
bitfld.long 0x00 12. "B908,B908" "0,1"
|
|
bitfld.long 0x00 11. "B907,B907" "0,1"
|
|
bitfld.long 0x00 10. "B906,B906" "0,1"
|
|
bitfld.long 0x00 9. "B905,B905" "0,1"
|
|
bitfld.long 0x00 8. "B904,B904" "0,1"
|
|
bitfld.long 0x00 7. "B903,B903" "0,1"
|
|
bitfld.long 0x00 6. "B902,B902" "0,1"
|
|
bitfld.long 0x00 5. "B901,B901" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B900,B900" "0,1"
|
|
bitfld.long 0x00 3. "B899,B899" "0,1"
|
|
bitfld.long 0x00 2. "B898,B898" "0,1"
|
|
bitfld.long 0x00 1. "B897,B897" "0,1"
|
|
bitfld.long 0x00 0. "B896,B896" "0,1"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "MPCBB1_VCTR29,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B959,B959" "0,1"
|
|
bitfld.long 0x00 30. "B958,B958" "0,1"
|
|
bitfld.long 0x00 29. "B957,B957" "0,1"
|
|
bitfld.long 0x00 28. "B956,B956" "0,1"
|
|
bitfld.long 0x00 27. "B955,B955" "0,1"
|
|
bitfld.long 0x00 26. "B954,B954" "0,1"
|
|
bitfld.long 0x00 25. "B953,B953" "0,1"
|
|
bitfld.long 0x00 24. "B952,B952" "0,1"
|
|
bitfld.long 0x00 23. "B951,B951" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B950,B950" "0,1"
|
|
bitfld.long 0x00 21. "B949,B949" "0,1"
|
|
bitfld.long 0x00 20. "B948,B948" "0,1"
|
|
bitfld.long 0x00 19. "B947,B947" "0,1"
|
|
bitfld.long 0x00 18. "B946,B946" "0,1"
|
|
bitfld.long 0x00 17. "B945,B945" "0,1"
|
|
bitfld.long 0x00 16. "B944,B944" "0,1"
|
|
bitfld.long 0x00 15. "B943,B943" "0,1"
|
|
bitfld.long 0x00 14. "B942,B942" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B941,B941" "0,1"
|
|
bitfld.long 0x00 12. "B940,B940" "0,1"
|
|
bitfld.long 0x00 11. "B939,B939" "0,1"
|
|
bitfld.long 0x00 10. "B938,B938" "0,1"
|
|
bitfld.long 0x00 9. "B937,B937" "0,1"
|
|
bitfld.long 0x00 8. "B936,B936" "0,1"
|
|
bitfld.long 0x00 7. "B935,B935" "0,1"
|
|
bitfld.long 0x00 6. "B934,B934" "0,1"
|
|
bitfld.long 0x00 5. "B933,B933" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B932,B932" "0,1"
|
|
bitfld.long 0x00 3. "B931,B931" "0,1"
|
|
bitfld.long 0x00 2. "B930,B930" "0,1"
|
|
bitfld.long 0x00 1. "B929,B929" "0,1"
|
|
bitfld.long 0x00 0. "B928,B928" "0,1"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "MPCBB1_VCTR30,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B991,B991" "0,1"
|
|
bitfld.long 0x00 30. "B990,B990" "0,1"
|
|
bitfld.long 0x00 29. "B989,B989" "0,1"
|
|
bitfld.long 0x00 28. "B988,B988" "0,1"
|
|
bitfld.long 0x00 27. "B987,B987" "0,1"
|
|
bitfld.long 0x00 26. "B986,B986" "0,1"
|
|
bitfld.long 0x00 25. "B985,B985" "0,1"
|
|
bitfld.long 0x00 24. "B984,B984" "0,1"
|
|
bitfld.long 0x00 23. "B983,B983" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B982,B982" "0,1"
|
|
bitfld.long 0x00 21. "B981,B981" "0,1"
|
|
bitfld.long 0x00 20. "B980,B980" "0,1"
|
|
bitfld.long 0x00 19. "B979,B979" "0,1"
|
|
bitfld.long 0x00 18. "B978,B978" "0,1"
|
|
bitfld.long 0x00 17. "B977,B977" "0,1"
|
|
bitfld.long 0x00 16. "B976,B976" "0,1"
|
|
bitfld.long 0x00 15. "B975,B975" "0,1"
|
|
bitfld.long 0x00 14. "B974,B974" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B973,B973" "0,1"
|
|
bitfld.long 0x00 12. "B972,B972" "0,1"
|
|
bitfld.long 0x00 11. "B971,B971" "0,1"
|
|
bitfld.long 0x00 10. "B970,B970" "0,1"
|
|
bitfld.long 0x00 9. "B969,B969" "0,1"
|
|
bitfld.long 0x00 8. "B968,B968" "0,1"
|
|
bitfld.long 0x00 7. "B967,B967" "0,1"
|
|
bitfld.long 0x00 6. "B966,B966" "0,1"
|
|
bitfld.long 0x00 5. "B965,B965" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B964,B964" "0,1"
|
|
bitfld.long 0x00 3. "B963,B963" "0,1"
|
|
bitfld.long 0x00 2. "B962,B962" "0,1"
|
|
bitfld.long 0x00 1. "B961,B961" "0,1"
|
|
bitfld.long 0x00 0. "B960,B960" "0,1"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR31,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1023,B1023" "0,1"
|
|
bitfld.long 0x00 30. "B1022,B1022" "0,1"
|
|
bitfld.long 0x00 29. "B1021,B1021" "0,1"
|
|
bitfld.long 0x00 28. "B1020,B1020" "0,1"
|
|
bitfld.long 0x00 27. "B1019,B1019" "0,1"
|
|
bitfld.long 0x00 26. "B1018,B1018" "0,1"
|
|
bitfld.long 0x00 25. "B1017,B1017" "0,1"
|
|
bitfld.long 0x00 24. "B1016,B1016" "0,1"
|
|
bitfld.long 0x00 23. "B1015,B1015" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1014,B1014" "0,1"
|
|
bitfld.long 0x00 21. "B1013,B1013" "0,1"
|
|
bitfld.long 0x00 20. "B1012,B1012" "0,1"
|
|
bitfld.long 0x00 19. "B1011,B1011" "0,1"
|
|
bitfld.long 0x00 18. "B1010,B1010" "0,1"
|
|
bitfld.long 0x00 17. "B1009,B1009" "0,1"
|
|
bitfld.long 0x00 16. "B1008,B1008" "0,1"
|
|
bitfld.long 0x00 15. "B1007,B1007" "0,1"
|
|
bitfld.long 0x00 14. "B1006,B1006" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1005,B1005" "0,1"
|
|
bitfld.long 0x00 12. "B1004,B1004" "0,1"
|
|
bitfld.long 0x00 11. "B1003,B1003" "0,1"
|
|
bitfld.long 0x00 10. "B1002,B1002" "0,1"
|
|
bitfld.long 0x00 9. "B1001,B1001" "0,1"
|
|
bitfld.long 0x00 8. "B1000,B1000" "0,1"
|
|
bitfld.long 0x00 7. "B999,B999" "0,1"
|
|
bitfld.long 0x00 6. "B998,B998" "0,1"
|
|
bitfld.long 0x00 5. "B997,B997" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B996,B996" "0,1"
|
|
bitfld.long 0x00 3. "B995,B995" "0,1"
|
|
bitfld.long 0x00 2. "B994,B994" "0,1"
|
|
bitfld.long 0x00 1. "B993,B993" "0,1"
|
|
bitfld.long 0x00 0. "B992,B992" "0,1"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "MPCBB1_VCTR32,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1055,B1055" "0,1"
|
|
bitfld.long 0x00 30. "B1054,B1054" "0,1"
|
|
bitfld.long 0x00 29. "B1053,B1053" "0,1"
|
|
bitfld.long 0x00 28. "B1052,B1052" "0,1"
|
|
bitfld.long 0x00 27. "B1051,B1051" "0,1"
|
|
bitfld.long 0x00 26. "B1050,B1050" "0,1"
|
|
bitfld.long 0x00 25. "B1049,B1049" "0,1"
|
|
bitfld.long 0x00 24. "B1048,B1048" "0,1"
|
|
bitfld.long 0x00 23. "B1047,B1047" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1046,B1046" "0,1"
|
|
bitfld.long 0x00 21. "B1045,B1045" "0,1"
|
|
bitfld.long 0x00 20. "B1044,B1044" "0,1"
|
|
bitfld.long 0x00 19. "B1043,B1043" "0,1"
|
|
bitfld.long 0x00 18. "B1042,B1042" "0,1"
|
|
bitfld.long 0x00 17. "B1041,B1041" "0,1"
|
|
bitfld.long 0x00 16. "B1040,B1040" "0,1"
|
|
bitfld.long 0x00 15. "B1039,B1039" "0,1"
|
|
bitfld.long 0x00 14. "B1038,B1038" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1037,B1037" "0,1"
|
|
bitfld.long 0x00 12. "B1036,B1036" "0,1"
|
|
bitfld.long 0x00 11. "B1035,B1035" "0,1"
|
|
bitfld.long 0x00 10. "B1034,B1034" "0,1"
|
|
bitfld.long 0x00 9. "B1033,B1033" "0,1"
|
|
bitfld.long 0x00 8. "B1032,B1032" "0,1"
|
|
bitfld.long 0x00 7. "B1031,B1031" "0,1"
|
|
bitfld.long 0x00 6. "B1030,B1030" "0,1"
|
|
bitfld.long 0x00 5. "B1029,B1029" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1028,B1028" "0,1"
|
|
bitfld.long 0x00 3. "B1027,B1027" "0,1"
|
|
bitfld.long 0x00 2. "B1026,B1026" "0,1"
|
|
bitfld.long 0x00 1. "B1025,B1025" "0,1"
|
|
bitfld.long 0x00 0. "B1024,B1024" "0,1"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "MPCBB1_VCTR33,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1087,B1087" "0,1"
|
|
bitfld.long 0x00 30. "B1086,B1086" "0,1"
|
|
bitfld.long 0x00 29. "B1085,B1085" "0,1"
|
|
bitfld.long 0x00 28. "B1084,B1084" "0,1"
|
|
bitfld.long 0x00 27. "B1083,B1083" "0,1"
|
|
bitfld.long 0x00 26. "B1082,B1082" "0,1"
|
|
bitfld.long 0x00 25. "B1081,B1081" "0,1"
|
|
bitfld.long 0x00 24. "B1080,B1080" "0,1"
|
|
bitfld.long 0x00 23. "B1079,B1079" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1078,B1078" "0,1"
|
|
bitfld.long 0x00 21. "B1077,B1077" "0,1"
|
|
bitfld.long 0x00 20. "B1076,B1076" "0,1"
|
|
bitfld.long 0x00 19. "B1075,B1075" "0,1"
|
|
bitfld.long 0x00 18. "B1074,B1074" "0,1"
|
|
bitfld.long 0x00 17. "B1073,B1073" "0,1"
|
|
bitfld.long 0x00 16. "B1072,B1072" "0,1"
|
|
bitfld.long 0x00 15. "B1071,B1071" "0,1"
|
|
bitfld.long 0x00 14. "B1070,B1070" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1069,B1069" "0,1"
|
|
bitfld.long 0x00 12. "B1068,B1068" "0,1"
|
|
bitfld.long 0x00 11. "B1067,B1067" "0,1"
|
|
bitfld.long 0x00 10. "B1066,B1066" "0,1"
|
|
bitfld.long 0x00 9. "B1065,B1065" "0,1"
|
|
bitfld.long 0x00 8. "B1064,B1064" "0,1"
|
|
bitfld.long 0x00 7. "B1063,B1063" "0,1"
|
|
bitfld.long 0x00 6. "B1062,B1062" "0,1"
|
|
bitfld.long 0x00 5. "B1061,B1061" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1060,B1060" "0,1"
|
|
bitfld.long 0x00 3. "B1059,B1059" "0,1"
|
|
bitfld.long 0x00 2. "B1058,B1058" "0,1"
|
|
bitfld.long 0x00 1. "B1057,B1057" "0,1"
|
|
bitfld.long 0x00 0. "B1056,B1056" "0,1"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "MPCBB1_VCTR34,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1119,B1119" "0,1"
|
|
bitfld.long 0x00 30. "B1118,B1118" "0,1"
|
|
bitfld.long 0x00 29. "B1117,B1117" "0,1"
|
|
bitfld.long 0x00 28. "B1116,B1116" "0,1"
|
|
bitfld.long 0x00 27. "B1115,B1115" "0,1"
|
|
bitfld.long 0x00 26. "B1114,B1114" "0,1"
|
|
bitfld.long 0x00 25. "B1113,B1113" "0,1"
|
|
bitfld.long 0x00 24. "B1112,B1112" "0,1"
|
|
bitfld.long 0x00 23. "B1111,B1111" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1110,B1110" "0,1"
|
|
bitfld.long 0x00 21. "B1109,B1109" "0,1"
|
|
bitfld.long 0x00 20. "B1108,B1108" "0,1"
|
|
bitfld.long 0x00 19. "B1107,B1107" "0,1"
|
|
bitfld.long 0x00 18. "B1106,B1106" "0,1"
|
|
bitfld.long 0x00 17. "B1105,B1105" "0,1"
|
|
bitfld.long 0x00 16. "B1104,B1104" "0,1"
|
|
bitfld.long 0x00 15. "B1103,B1103" "0,1"
|
|
bitfld.long 0x00 14. "B1102,B1102" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1101,B1101" "0,1"
|
|
bitfld.long 0x00 12. "B1100,B1100" "0,1"
|
|
bitfld.long 0x00 11. "B1099,B1099" "0,1"
|
|
bitfld.long 0x00 10. "B1098,B1098" "0,1"
|
|
bitfld.long 0x00 9. "B1097,B1097" "0,1"
|
|
bitfld.long 0x00 8. "B1096,B1096" "0,1"
|
|
bitfld.long 0x00 7. "B1095,B1095" "0,1"
|
|
bitfld.long 0x00 6. "B1094,B1094" "0,1"
|
|
bitfld.long 0x00 5. "B1093,B1093" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1092,B1092" "0,1"
|
|
bitfld.long 0x00 3. "B1091,B1091" "0,1"
|
|
bitfld.long 0x00 2. "B1090,B1090" "0,1"
|
|
bitfld.long 0x00 1. "B1089,B1089" "0,1"
|
|
bitfld.long 0x00 0. "B1088,B1088" "0,1"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR35,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1151,B1151" "0,1"
|
|
bitfld.long 0x00 30. "B1150,B1150" "0,1"
|
|
bitfld.long 0x00 29. "B1149,B1149" "0,1"
|
|
bitfld.long 0x00 28. "B1148,B1148" "0,1"
|
|
bitfld.long 0x00 27. "B1147,B1147" "0,1"
|
|
bitfld.long 0x00 26. "B1146,B1146" "0,1"
|
|
bitfld.long 0x00 25. "B1145,B1145" "0,1"
|
|
bitfld.long 0x00 24. "B1144,B1144" "0,1"
|
|
bitfld.long 0x00 23. "B1143,B1143" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1142,B1142" "0,1"
|
|
bitfld.long 0x00 21. "B1141,B1141" "0,1"
|
|
bitfld.long 0x00 20. "B1140,B1140" "0,1"
|
|
bitfld.long 0x00 19. "B1139,B1139" "0,1"
|
|
bitfld.long 0x00 18. "B1138,B1138" "0,1"
|
|
bitfld.long 0x00 17. "B1137,B1137" "0,1"
|
|
bitfld.long 0x00 16. "B1136,B1136" "0,1"
|
|
bitfld.long 0x00 15. "B1135,B1135" "0,1"
|
|
bitfld.long 0x00 14. "B1134,B1134" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1133,B1133" "0,1"
|
|
bitfld.long 0x00 12. "B1132,B1132" "0,1"
|
|
bitfld.long 0x00 11. "B1131,B1131" "0,1"
|
|
bitfld.long 0x00 10. "B1130,B1130" "0,1"
|
|
bitfld.long 0x00 9. "B1129,B1129" "0,1"
|
|
bitfld.long 0x00 8. "B1128,B1128" "0,1"
|
|
bitfld.long 0x00 7. "B1127,B1127" "0,1"
|
|
bitfld.long 0x00 6. "B1126,B1126" "0,1"
|
|
bitfld.long 0x00 5. "B1125,B1125" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1124,B1124" "0,1"
|
|
bitfld.long 0x00 3. "B1123,B1123" "0,1"
|
|
bitfld.long 0x00 2. "B1122,B1122" "0,1"
|
|
bitfld.long 0x00 1. "B1121,B1121" "0,1"
|
|
bitfld.long 0x00 0. "B1120,B1120" "0,1"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "MPCBB1_VCTR36,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1183,B1183" "0,1"
|
|
bitfld.long 0x00 30. "B1182,B1182" "0,1"
|
|
bitfld.long 0x00 29. "B1181,B1181" "0,1"
|
|
bitfld.long 0x00 28. "B1180,B1180" "0,1"
|
|
bitfld.long 0x00 27. "B1179,B1179" "0,1"
|
|
bitfld.long 0x00 26. "B1178,B1178" "0,1"
|
|
bitfld.long 0x00 25. "B1177,B1177" "0,1"
|
|
bitfld.long 0x00 24. "B1176,B1176" "0,1"
|
|
bitfld.long 0x00 23. "B1175,B1175" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1174,B1174" "0,1"
|
|
bitfld.long 0x00 21. "B1173,B1173" "0,1"
|
|
bitfld.long 0x00 20. "B1172,B1172" "0,1"
|
|
bitfld.long 0x00 19. "B1171,B1171" "0,1"
|
|
bitfld.long 0x00 18. "B1170,B1170" "0,1"
|
|
bitfld.long 0x00 17. "B1169,B1169" "0,1"
|
|
bitfld.long 0x00 16. "B1168,B1168" "0,1"
|
|
bitfld.long 0x00 15. "B1167,B1167" "0,1"
|
|
bitfld.long 0x00 14. "B1166,B1166" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1165,B1165" "0,1"
|
|
bitfld.long 0x00 12. "B1164,B1164" "0,1"
|
|
bitfld.long 0x00 11. "B1163,B1163" "0,1"
|
|
bitfld.long 0x00 10. "B1162,B1162" "0,1"
|
|
bitfld.long 0x00 9. "B1161,B1161" "0,1"
|
|
bitfld.long 0x00 8. "B1160,B1160" "0,1"
|
|
bitfld.long 0x00 7. "B1159,B1159" "0,1"
|
|
bitfld.long 0x00 6. "B1158,B1158" "0,1"
|
|
bitfld.long 0x00 5. "B1157,B1157" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1156,B1156" "0,1"
|
|
bitfld.long 0x00 3. "B1155,B1155" "0,1"
|
|
bitfld.long 0x00 2. "B1154,B1154" "0,1"
|
|
bitfld.long 0x00 1. "B1153,B1153" "0,1"
|
|
bitfld.long 0x00 0. "B1152,B1152" "0,1"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "MPCBB1_VCTR37,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1215,B1215" "0,1"
|
|
bitfld.long 0x00 30. "B1214,B1214" "0,1"
|
|
bitfld.long 0x00 29. "B1213,B1213" "0,1"
|
|
bitfld.long 0x00 28. "B1212,B1212" "0,1"
|
|
bitfld.long 0x00 27. "B1211,B1211" "0,1"
|
|
bitfld.long 0x00 26. "B1210,B1210" "0,1"
|
|
bitfld.long 0x00 25. "B1209,B1209" "0,1"
|
|
bitfld.long 0x00 24. "B1208,B1208" "0,1"
|
|
bitfld.long 0x00 23. "B1207,B1207" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1206,B1206" "0,1"
|
|
bitfld.long 0x00 21. "B1205,B1205" "0,1"
|
|
bitfld.long 0x00 20. "B1204,B1204" "0,1"
|
|
bitfld.long 0x00 19. "B1203,B1203" "0,1"
|
|
bitfld.long 0x00 18. "B1202,B1202" "0,1"
|
|
bitfld.long 0x00 17. "B1201,B1201" "0,1"
|
|
bitfld.long 0x00 16. "B1200,B1200" "0,1"
|
|
bitfld.long 0x00 15. "B1199,B1199" "0,1"
|
|
bitfld.long 0x00 14. "B1198,B1198" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1197,B1197" "0,1"
|
|
bitfld.long 0x00 12. "B1196,B1196" "0,1"
|
|
bitfld.long 0x00 11. "B1195,B1195" "0,1"
|
|
bitfld.long 0x00 10. "B1194,B1194" "0,1"
|
|
bitfld.long 0x00 9. "B1193,B1193" "0,1"
|
|
bitfld.long 0x00 8. "B1192,B1192" "0,1"
|
|
bitfld.long 0x00 7. "B1191,B1191" "0,1"
|
|
bitfld.long 0x00 6. "B1190,B1190" "0,1"
|
|
bitfld.long 0x00 5. "B1189,B1189" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1188,B1188" "0,1"
|
|
bitfld.long 0x00 3. "B1187,B1187" "0,1"
|
|
bitfld.long 0x00 2. "B1186,B1186" "0,1"
|
|
bitfld.long 0x00 1. "B1185,B1185" "0,1"
|
|
bitfld.long 0x00 0. "B1184,B1184" "0,1"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "MPCBB1_VCTR38,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1247,B1247" "0,1"
|
|
bitfld.long 0x00 30. "B1246,B1246" "0,1"
|
|
bitfld.long 0x00 29. "B1245,B1245" "0,1"
|
|
bitfld.long 0x00 28. "B1244,B1244" "0,1"
|
|
bitfld.long 0x00 27. "B1243,B1243" "0,1"
|
|
bitfld.long 0x00 26. "B1242,B1242" "0,1"
|
|
bitfld.long 0x00 25. "B1241,B1241" "0,1"
|
|
bitfld.long 0x00 24. "B1240,B1240" "0,1"
|
|
bitfld.long 0x00 23. "B1239,B1239" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1238,B1238" "0,1"
|
|
bitfld.long 0x00 21. "B1237,B1237" "0,1"
|
|
bitfld.long 0x00 20. "B1236,B1236" "0,1"
|
|
bitfld.long 0x00 19. "B1235,B1235" "0,1"
|
|
bitfld.long 0x00 18. "B1234,B1234" "0,1"
|
|
bitfld.long 0x00 17. "B1233,B1233" "0,1"
|
|
bitfld.long 0x00 16. "B1232,B1232" "0,1"
|
|
bitfld.long 0x00 15. "B1231,B1231" "0,1"
|
|
bitfld.long 0x00 14. "B1230,B1230" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1229,B1229" "0,1"
|
|
bitfld.long 0x00 12. "B1228,B1228" "0,1"
|
|
bitfld.long 0x00 11. "B1227,B1227" "0,1"
|
|
bitfld.long 0x00 10. "B1226,B1226" "0,1"
|
|
bitfld.long 0x00 9. "B1225,B1225" "0,1"
|
|
bitfld.long 0x00 8. "B1224,B1224" "0,1"
|
|
bitfld.long 0x00 7. "B1223,B1223" "0,1"
|
|
bitfld.long 0x00 6. "B1222,B1222" "0,1"
|
|
bitfld.long 0x00 5. "B1221,B1221" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1220,B1220" "0,1"
|
|
bitfld.long 0x00 3. "B1219,B1219" "0,1"
|
|
bitfld.long 0x00 2. "B1218,B1218" "0,1"
|
|
bitfld.long 0x00 1. "B1217,B1217" "0,1"
|
|
bitfld.long 0x00 0. "B1216,B1216" "0,1"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR39,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1279,B1279" "0,1"
|
|
bitfld.long 0x00 30. "B1278,B1278" "0,1"
|
|
bitfld.long 0x00 29. "B1277,B1277" "0,1"
|
|
bitfld.long 0x00 28. "B1276,B1276" "0,1"
|
|
bitfld.long 0x00 27. "B1275,B1275" "0,1"
|
|
bitfld.long 0x00 26. "B1274,B1274" "0,1"
|
|
bitfld.long 0x00 25. "B1273,B1273" "0,1"
|
|
bitfld.long 0x00 24. "B1272,B1272" "0,1"
|
|
bitfld.long 0x00 23. "B1271,B1271" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1270,B1270" "0,1"
|
|
bitfld.long 0x00 21. "B1269,B1269" "0,1"
|
|
bitfld.long 0x00 20. "B1268,B1268" "0,1"
|
|
bitfld.long 0x00 19. "B1267,B1267" "0,1"
|
|
bitfld.long 0x00 18. "B1266,B1266" "0,1"
|
|
bitfld.long 0x00 17. "B1265,B1265" "0,1"
|
|
bitfld.long 0x00 16. "B1264,B1264" "0,1"
|
|
bitfld.long 0x00 15. "B1263,B1263" "0,1"
|
|
bitfld.long 0x00 14. "B1262,B1262" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1261,B1261" "0,1"
|
|
bitfld.long 0x00 12. "B1260,B1260" "0,1"
|
|
bitfld.long 0x00 11. "B1259,B1259" "0,1"
|
|
bitfld.long 0x00 10. "B1258,B1258" "0,1"
|
|
bitfld.long 0x00 9. "B1257,B1257" "0,1"
|
|
bitfld.long 0x00 8. "B1256,B1256" "0,1"
|
|
bitfld.long 0x00 7. "B1255,B1255" "0,1"
|
|
bitfld.long 0x00 6. "B1254,B1254" "0,1"
|
|
bitfld.long 0x00 5. "B1253,B1253" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1252,B1252" "0,1"
|
|
bitfld.long 0x00 3. "B1251,B1251" "0,1"
|
|
bitfld.long 0x00 2. "B1250,B1250" "0,1"
|
|
bitfld.long 0x00 1. "B1249,B1249" "0,1"
|
|
bitfld.long 0x00 0. "B1248,B1248" "0,1"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "MPCBB1_VCTR40,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1311,B1311" "0,1"
|
|
bitfld.long 0x00 30. "B1310,B1310" "0,1"
|
|
bitfld.long 0x00 29. "B1309,B1309" "0,1"
|
|
bitfld.long 0x00 28. "B1308,B1308" "0,1"
|
|
bitfld.long 0x00 27. "B1307,B1307" "0,1"
|
|
bitfld.long 0x00 26. "B1306,B1306" "0,1"
|
|
bitfld.long 0x00 25. "B1305,B1305" "0,1"
|
|
bitfld.long 0x00 24. "B1304,B1304" "0,1"
|
|
bitfld.long 0x00 23. "B1303,B1303" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1302,B1302" "0,1"
|
|
bitfld.long 0x00 21. "B1301,B1301" "0,1"
|
|
bitfld.long 0x00 20. "B1300,B1300" "0,1"
|
|
bitfld.long 0x00 19. "B1299,B1299" "0,1"
|
|
bitfld.long 0x00 18. "B1298,B1298" "0,1"
|
|
bitfld.long 0x00 17. "B1297,B1297" "0,1"
|
|
bitfld.long 0x00 16. "B1296,B1296" "0,1"
|
|
bitfld.long 0x00 15. "B1295,B1295" "0,1"
|
|
bitfld.long 0x00 14. "B1294,B1294" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1293,B1293" "0,1"
|
|
bitfld.long 0x00 12. "B1292,B1292" "0,1"
|
|
bitfld.long 0x00 11. "B1291,B1291" "0,1"
|
|
bitfld.long 0x00 10. "B1290,B1290" "0,1"
|
|
bitfld.long 0x00 9. "B1289,B1289" "0,1"
|
|
bitfld.long 0x00 8. "B1288,B1288" "0,1"
|
|
bitfld.long 0x00 7. "B1287,B1287" "0,1"
|
|
bitfld.long 0x00 6. "B1286,B1286" "0,1"
|
|
bitfld.long 0x00 5. "B1285,B1285" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1284,B1284" "0,1"
|
|
bitfld.long 0x00 3. "B1283,B1283" "0,1"
|
|
bitfld.long 0x00 2. "B1282,B1282" "0,1"
|
|
bitfld.long 0x00 1. "B1281,B1281" "0,1"
|
|
bitfld.long 0x00 0. "B1280,B1280" "0,1"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "MPCBB1_VCTR41,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1343,B1343" "0,1"
|
|
bitfld.long 0x00 30. "B1342,B1342" "0,1"
|
|
bitfld.long 0x00 29. "B1341,B1341" "0,1"
|
|
bitfld.long 0x00 28. "B1340,B1340" "0,1"
|
|
bitfld.long 0x00 27. "B1339,B1339" "0,1"
|
|
bitfld.long 0x00 26. "B1338,B1338" "0,1"
|
|
bitfld.long 0x00 25. "B1337,B1337" "0,1"
|
|
bitfld.long 0x00 24. "B1336,B1336" "0,1"
|
|
bitfld.long 0x00 23. "B1335,B1335" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1334,B1334" "0,1"
|
|
bitfld.long 0x00 21. "B1333,B1333" "0,1"
|
|
bitfld.long 0x00 20. "B1332,B1332" "0,1"
|
|
bitfld.long 0x00 19. "B1331,B1331" "0,1"
|
|
bitfld.long 0x00 18. "B1330,B1330" "0,1"
|
|
bitfld.long 0x00 17. "B1329,B1329" "0,1"
|
|
bitfld.long 0x00 16. "B1328,B1328" "0,1"
|
|
bitfld.long 0x00 15. "B1327,B1327" "0,1"
|
|
bitfld.long 0x00 14. "B1326,B1326" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1325,B1325" "0,1"
|
|
bitfld.long 0x00 12. "B1324,B1324" "0,1"
|
|
bitfld.long 0x00 11. "B1323,B1323" "0,1"
|
|
bitfld.long 0x00 10. "B1322,B1322" "0,1"
|
|
bitfld.long 0x00 9. "B1321,B1321" "0,1"
|
|
bitfld.long 0x00 8. "B1320,B1320" "0,1"
|
|
bitfld.long 0x00 7. "B1319,B1319" "0,1"
|
|
bitfld.long 0x00 6. "B1318,B1318" "0,1"
|
|
bitfld.long 0x00 5. "B1317,B1317" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1316,B1316" "0,1"
|
|
bitfld.long 0x00 3. "B1315,B1315" "0,1"
|
|
bitfld.long 0x00 2. "B1314,B1314" "0,1"
|
|
bitfld.long 0x00 1. "B1313,B1313" "0,1"
|
|
bitfld.long 0x00 0. "B1312,B1312" "0,1"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "MPCBB1_VCTR42,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1375,B1375" "0,1"
|
|
bitfld.long 0x00 30. "B1374,B1374" "0,1"
|
|
bitfld.long 0x00 29. "B1373,B1373" "0,1"
|
|
bitfld.long 0x00 28. "B1372,B1372" "0,1"
|
|
bitfld.long 0x00 27. "B1371,B1371" "0,1"
|
|
bitfld.long 0x00 26. "B1370,B1370" "0,1"
|
|
bitfld.long 0x00 25. "B1369,B1369" "0,1"
|
|
bitfld.long 0x00 24. "B1368,B1368" "0,1"
|
|
bitfld.long 0x00 23. "B1367,B1367" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1366,B1366" "0,1"
|
|
bitfld.long 0x00 21. "B1365,B1365" "0,1"
|
|
bitfld.long 0x00 20. "B1364,B1364" "0,1"
|
|
bitfld.long 0x00 19. "B1363,B1363" "0,1"
|
|
bitfld.long 0x00 18. "B1362,B1362" "0,1"
|
|
bitfld.long 0x00 17. "B1361,B1361" "0,1"
|
|
bitfld.long 0x00 16. "B1360,B1360" "0,1"
|
|
bitfld.long 0x00 15. "B1359,B1359" "0,1"
|
|
bitfld.long 0x00 14. "B1358,B1358" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1357,B1357" "0,1"
|
|
bitfld.long 0x00 12. "B1356,B1356" "0,1"
|
|
bitfld.long 0x00 11. "B1355,B1355" "0,1"
|
|
bitfld.long 0x00 10. "B1354,B1354" "0,1"
|
|
bitfld.long 0x00 9. "B1353,B1353" "0,1"
|
|
bitfld.long 0x00 8. "B1352,B1352" "0,1"
|
|
bitfld.long 0x00 7. "B1351,B1351" "0,1"
|
|
bitfld.long 0x00 6. "B1350,B1350" "0,1"
|
|
bitfld.long 0x00 5. "B1349,B1349" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1348,B1348" "0,1"
|
|
bitfld.long 0x00 3. "B1347,B1347" "0,1"
|
|
bitfld.long 0x00 2. "B1346,B1346" "0,1"
|
|
bitfld.long 0x00 1. "B1345,B1345" "0,1"
|
|
bitfld.long 0x00 0. "B1344,B1344" "0,1"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "MPCBB1_VCTR43,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1407,B1407" "0,1"
|
|
bitfld.long 0x00 30. "B1406,B1406" "0,1"
|
|
bitfld.long 0x00 29. "B1405,B1405" "0,1"
|
|
bitfld.long 0x00 28. "B1404,B1404" "0,1"
|
|
bitfld.long 0x00 27. "B1403,B1403" "0,1"
|
|
bitfld.long 0x00 26. "B1402,B1402" "0,1"
|
|
bitfld.long 0x00 25. "B1401,B1401" "0,1"
|
|
bitfld.long 0x00 24. "B1400,B1400" "0,1"
|
|
bitfld.long 0x00 23. "B1399,B1399" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1398,B1398" "0,1"
|
|
bitfld.long 0x00 21. "B1397,B1397" "0,1"
|
|
bitfld.long 0x00 20. "B1396,B1396" "0,1"
|
|
bitfld.long 0x00 19. "B1395,B1395" "0,1"
|
|
bitfld.long 0x00 18. "B1394,B1394" "0,1"
|
|
bitfld.long 0x00 17. "B1393,B1393" "0,1"
|
|
bitfld.long 0x00 16. "B1392,B1392" "0,1"
|
|
bitfld.long 0x00 15. "B1391,B1391" "0,1"
|
|
bitfld.long 0x00 14. "B1390,B1390" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1389,B1389" "0,1"
|
|
bitfld.long 0x00 12. "B1388,B1388" "0,1"
|
|
bitfld.long 0x00 11. "B1387,B1387" "0,1"
|
|
bitfld.long 0x00 10. "B1386,B1386" "0,1"
|
|
bitfld.long 0x00 9. "B1385,B1385" "0,1"
|
|
bitfld.long 0x00 8. "B1384,B1384" "0,1"
|
|
bitfld.long 0x00 7. "B1383,B1383" "0,1"
|
|
bitfld.long 0x00 6. "B1382,B1382" "0,1"
|
|
bitfld.long 0x00 5. "B1381,B1381" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1380,B1380" "0,1"
|
|
bitfld.long 0x00 3. "B1379,B1379" "0,1"
|
|
bitfld.long 0x00 2. "B1378,B1378" "0,1"
|
|
bitfld.long 0x00 1. "B1377,B1377" "0,1"
|
|
bitfld.long 0x00 0. "B1376,B1376" "0,1"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "MPCBB1_VCTR44,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1439,B1439" "0,1"
|
|
bitfld.long 0x00 30. "B1438,B1438" "0,1"
|
|
bitfld.long 0x00 29. "B1437,B1437" "0,1"
|
|
bitfld.long 0x00 28. "B1436,B1436" "0,1"
|
|
bitfld.long 0x00 27. "B1435,B1435" "0,1"
|
|
bitfld.long 0x00 26. "B1434,B1434" "0,1"
|
|
bitfld.long 0x00 25. "B1433,B1433" "0,1"
|
|
bitfld.long 0x00 24. "B1432,B1432" "0,1"
|
|
bitfld.long 0x00 23. "B1431,B1431" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1430,B1430" "0,1"
|
|
bitfld.long 0x00 21. "B1429,B1429" "0,1"
|
|
bitfld.long 0x00 20. "B1428,B1428" "0,1"
|
|
bitfld.long 0x00 19. "B1427,B1427" "0,1"
|
|
bitfld.long 0x00 18. "B1426,B1426" "0,1"
|
|
bitfld.long 0x00 17. "B1425,B1425" "0,1"
|
|
bitfld.long 0x00 16. "B1424,B1424" "0,1"
|
|
bitfld.long 0x00 15. "B1423,B1423" "0,1"
|
|
bitfld.long 0x00 14. "B1422,B1422" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1421,B1421" "0,1"
|
|
bitfld.long 0x00 12. "B1420,B1420" "0,1"
|
|
bitfld.long 0x00 11. "B1419,B1419" "0,1"
|
|
bitfld.long 0x00 10. "B1418,B1418" "0,1"
|
|
bitfld.long 0x00 9. "B1417,B1417" "0,1"
|
|
bitfld.long 0x00 8. "B1416,B1416" "0,1"
|
|
bitfld.long 0x00 7. "B1415,B1415" "0,1"
|
|
bitfld.long 0x00 6. "B1414,B1414" "0,1"
|
|
bitfld.long 0x00 5. "B1413,B1413" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1412,B1412" "0,1"
|
|
bitfld.long 0x00 3. "B1411,B1411" "0,1"
|
|
bitfld.long 0x00 2. "B1410,B1410" "0,1"
|
|
bitfld.long 0x00 1. "B1409,B1409" "0,1"
|
|
bitfld.long 0x00 0. "B1408,B1408" "0,1"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "MPCBB1_VCTR45,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1471,B1471" "0,1"
|
|
bitfld.long 0x00 30. "B1470,B1470" "0,1"
|
|
bitfld.long 0x00 29. "B1469,B1469" "0,1"
|
|
bitfld.long 0x00 28. "B1468,B1468" "0,1"
|
|
bitfld.long 0x00 27. "B1467,B1467" "0,1"
|
|
bitfld.long 0x00 26. "B1466,B1466" "0,1"
|
|
bitfld.long 0x00 25. "B1465,B1465" "0,1"
|
|
bitfld.long 0x00 24. "B1464,B1464" "0,1"
|
|
bitfld.long 0x00 23. "B1463,B1463" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1462,B1462" "0,1"
|
|
bitfld.long 0x00 21. "B1461,B1461" "0,1"
|
|
bitfld.long 0x00 20. "B1460,B1460" "0,1"
|
|
bitfld.long 0x00 19. "B1459,B1459" "0,1"
|
|
bitfld.long 0x00 18. "B1458,B1458" "0,1"
|
|
bitfld.long 0x00 17. "B1457,B1457" "0,1"
|
|
bitfld.long 0x00 16. "B1456,B1456" "0,1"
|
|
bitfld.long 0x00 15. "B1455,B1455" "0,1"
|
|
bitfld.long 0x00 14. "B1454,B1454" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1453,B1453" "0,1"
|
|
bitfld.long 0x00 12. "B1452,B1452" "0,1"
|
|
bitfld.long 0x00 11. "B1451,B1451" "0,1"
|
|
bitfld.long 0x00 10. "B1450,B1450" "0,1"
|
|
bitfld.long 0x00 9. "B1449,B1449" "0,1"
|
|
bitfld.long 0x00 8. "B1448,B1448" "0,1"
|
|
bitfld.long 0x00 7. "B1447,B1447" "0,1"
|
|
bitfld.long 0x00 6. "B1446,B1446" "0,1"
|
|
bitfld.long 0x00 5. "B1445,B1445" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1444,B1444" "0,1"
|
|
bitfld.long 0x00 3. "B1443,B1443" "0,1"
|
|
bitfld.long 0x00 2. "B1442,B1442" "0,1"
|
|
bitfld.long 0x00 1. "B1441,B1441" "0,1"
|
|
bitfld.long 0x00 0. "B1440,B1440" "0,1"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "MPCBB1_VCTR46,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1503,B1503" "0,1"
|
|
bitfld.long 0x00 30. "B1502,B1502" "0,1"
|
|
bitfld.long 0x00 29. "B1501,B1501" "0,1"
|
|
bitfld.long 0x00 28. "B1500,B1500" "0,1"
|
|
bitfld.long 0x00 27. "B1499,B1499" "0,1"
|
|
bitfld.long 0x00 26. "B1498,B1498" "0,1"
|
|
bitfld.long 0x00 25. "B1497,B1497" "0,1"
|
|
bitfld.long 0x00 24. "B1496,B1496" "0,1"
|
|
bitfld.long 0x00 23. "B1495,B1495" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1494,B1494" "0,1"
|
|
bitfld.long 0x00 21. "B1493,B1493" "0,1"
|
|
bitfld.long 0x00 20. "B1492,B1492" "0,1"
|
|
bitfld.long 0x00 19. "B1491,B1491" "0,1"
|
|
bitfld.long 0x00 18. "B1490,B1490" "0,1"
|
|
bitfld.long 0x00 17. "B1489,B1489" "0,1"
|
|
bitfld.long 0x00 16. "B1488,B1488" "0,1"
|
|
bitfld.long 0x00 15. "B1487,B1487" "0,1"
|
|
bitfld.long 0x00 14. "B1486,B1486" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1485,B1485" "0,1"
|
|
bitfld.long 0x00 12. "B1484,B1484" "0,1"
|
|
bitfld.long 0x00 11. "B1483,B1483" "0,1"
|
|
bitfld.long 0x00 10. "B1482,B1482" "0,1"
|
|
bitfld.long 0x00 9. "B1481,B1481" "0,1"
|
|
bitfld.long 0x00 8. "B1480,B1480" "0,1"
|
|
bitfld.long 0x00 7. "B1479,B1479" "0,1"
|
|
bitfld.long 0x00 6. "B1478,B1478" "0,1"
|
|
bitfld.long 0x00 5. "B1477,B1477" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1476,B1476" "0,1"
|
|
bitfld.long 0x00 3. "B1475,B1475" "0,1"
|
|
bitfld.long 0x00 2. "B1474,B1474" "0,1"
|
|
bitfld.long 0x00 1. "B1473,B1473" "0,1"
|
|
bitfld.long 0x00 0. "B1472,B1472" "0,1"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "MPCBB1_VCTR47,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1535,B1535" "0,1"
|
|
bitfld.long 0x00 30. "B1534,B1534" "0,1"
|
|
bitfld.long 0x00 29. "B1533,B1533" "0,1"
|
|
bitfld.long 0x00 28. "B1532,B1532" "0,1"
|
|
bitfld.long 0x00 27. "B1531,B1531" "0,1"
|
|
bitfld.long 0x00 26. "B1530,B1530" "0,1"
|
|
bitfld.long 0x00 25. "B1529,B1529" "0,1"
|
|
bitfld.long 0x00 24. "B1528,B1528" "0,1"
|
|
bitfld.long 0x00 23. "B1527,B1527" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1526,B1526" "0,1"
|
|
bitfld.long 0x00 21. "B1525,B1525" "0,1"
|
|
bitfld.long 0x00 20. "B1524,B1524" "0,1"
|
|
bitfld.long 0x00 19. "B1523,B1523" "0,1"
|
|
bitfld.long 0x00 18. "B1522,B1522" "0,1"
|
|
bitfld.long 0x00 17. "B1521,B1521" "0,1"
|
|
bitfld.long 0x00 16. "B1520,B1520" "0,1"
|
|
bitfld.long 0x00 15. "B1519,B1519" "0,1"
|
|
bitfld.long 0x00 14. "B1518,B1518" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1517,B1517" "0,1"
|
|
bitfld.long 0x00 12. "B1516,B1516" "0,1"
|
|
bitfld.long 0x00 11. "B1515,B1515" "0,1"
|
|
bitfld.long 0x00 10. "B1514,B1514" "0,1"
|
|
bitfld.long 0x00 9. "B1513,B1513" "0,1"
|
|
bitfld.long 0x00 8. "B1512,B1512" "0,1"
|
|
bitfld.long 0x00 7. "B1511,B1511" "0,1"
|
|
bitfld.long 0x00 6. "B1510,B1510" "0,1"
|
|
bitfld.long 0x00 5. "B1509,B1509" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1508,B1508" "0,1"
|
|
bitfld.long 0x00 3. "B1507,B1507" "0,1"
|
|
bitfld.long 0x00 2. "B1506,B1506" "0,1"
|
|
bitfld.long 0x00 1. "B1505,B1505" "0,1"
|
|
bitfld.long 0x00 0. "B1504,B1504" "0,1"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "MPCBB1_VCTR48,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1567,B1567" "0,1"
|
|
bitfld.long 0x00 30. "B1566,B1566" "0,1"
|
|
bitfld.long 0x00 29. "B1565,B1565" "0,1"
|
|
bitfld.long 0x00 28. "B1564,B1564" "0,1"
|
|
bitfld.long 0x00 27. "B1563,B1563" "0,1"
|
|
bitfld.long 0x00 26. "B1562,B1562" "0,1"
|
|
bitfld.long 0x00 25. "B1561,B1561" "0,1"
|
|
bitfld.long 0x00 24. "B1560,B1560" "0,1"
|
|
bitfld.long 0x00 23. "B1559,B1559" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1558,B1558" "0,1"
|
|
bitfld.long 0x00 21. "B1557,B1557" "0,1"
|
|
bitfld.long 0x00 20. "B1556,B1556" "0,1"
|
|
bitfld.long 0x00 19. "B1555,B1555" "0,1"
|
|
bitfld.long 0x00 18. "B1554,B1554" "0,1"
|
|
bitfld.long 0x00 17. "B1553,B1553" "0,1"
|
|
bitfld.long 0x00 16. "B1552,B1552" "0,1"
|
|
bitfld.long 0x00 15. "B1551,B1551" "0,1"
|
|
bitfld.long 0x00 14. "B1550,B1550" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1549,B1549" "0,1"
|
|
bitfld.long 0x00 12. "B1548,B1548" "0,1"
|
|
bitfld.long 0x00 11. "B1547,B1547" "0,1"
|
|
bitfld.long 0x00 10. "B1546,B1546" "0,1"
|
|
bitfld.long 0x00 9. "B1545,B1545" "0,1"
|
|
bitfld.long 0x00 8. "B1544,B1544" "0,1"
|
|
bitfld.long 0x00 7. "B1543,B1543" "0,1"
|
|
bitfld.long 0x00 6. "B1542,B1542" "0,1"
|
|
bitfld.long 0x00 5. "B1541,B1541" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1540,B1540" "0,1"
|
|
bitfld.long 0x00 3. "B1539,B1539" "0,1"
|
|
bitfld.long 0x00 2. "B1538,B1538" "0,1"
|
|
bitfld.long 0x00 1. "B1537,B1537" "0,1"
|
|
bitfld.long 0x00 0. "B1536,B1536" "0,1"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "MPCBB1_VCTR49,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1599,B1599" "0,1"
|
|
bitfld.long 0x00 30. "B1598,B1598" "0,1"
|
|
bitfld.long 0x00 29. "B1597,B1597" "0,1"
|
|
bitfld.long 0x00 28. "B1596,B1596" "0,1"
|
|
bitfld.long 0x00 27. "B1595,B1595" "0,1"
|
|
bitfld.long 0x00 26. "B1594,B1594" "0,1"
|
|
bitfld.long 0x00 25. "B1593,B1593" "0,1"
|
|
bitfld.long 0x00 24. "B1592,B1592" "0,1"
|
|
bitfld.long 0x00 23. "B1591,B1591" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1590,B1590" "0,1"
|
|
bitfld.long 0x00 21. "B1589,B1589" "0,1"
|
|
bitfld.long 0x00 20. "B1588,B1588" "0,1"
|
|
bitfld.long 0x00 19. "B1587,B1587" "0,1"
|
|
bitfld.long 0x00 18. "B1586,B1586" "0,1"
|
|
bitfld.long 0x00 17. "B1585,B1585" "0,1"
|
|
bitfld.long 0x00 16. "B1584,B1584" "0,1"
|
|
bitfld.long 0x00 15. "B1583,B1583" "0,1"
|
|
bitfld.long 0x00 14. "B1582,B1582" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1581,B1581" "0,1"
|
|
bitfld.long 0x00 12. "B1580,B1580" "0,1"
|
|
bitfld.long 0x00 11. "B1579,B1579" "0,1"
|
|
bitfld.long 0x00 10. "B1578,B1578" "0,1"
|
|
bitfld.long 0x00 9. "B1577,B1577" "0,1"
|
|
bitfld.long 0x00 8. "B1576,B1576" "0,1"
|
|
bitfld.long 0x00 7. "B1575,B1575" "0,1"
|
|
bitfld.long 0x00 6. "B1574,B1574" "0,1"
|
|
bitfld.long 0x00 5. "B1573,B1573" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1572,B1572" "0,1"
|
|
bitfld.long 0x00 3. "B1571,B1571" "0,1"
|
|
bitfld.long 0x00 2. "B1570,B1570" "0,1"
|
|
bitfld.long 0x00 1. "B1569,B1569" "0,1"
|
|
bitfld.long 0x00 0. "B1568,B1568" "0,1"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "MPCBB1_VCTR50,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1631,B1631" "0,1"
|
|
bitfld.long 0x00 30. "B1630,B1630" "0,1"
|
|
bitfld.long 0x00 29. "B1629,B1629" "0,1"
|
|
bitfld.long 0x00 28. "B1628,B1628" "0,1"
|
|
bitfld.long 0x00 27. "B1627,B1627" "0,1"
|
|
bitfld.long 0x00 26. "B1626,B1626" "0,1"
|
|
bitfld.long 0x00 25. "B1625,B1625" "0,1"
|
|
bitfld.long 0x00 24. "B1624,B1624" "0,1"
|
|
bitfld.long 0x00 23. "B1623,B1623" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1622,B1622" "0,1"
|
|
bitfld.long 0x00 21. "B1621,B1621" "0,1"
|
|
bitfld.long 0x00 20. "B1620,B1620" "0,1"
|
|
bitfld.long 0x00 19. "B1619,B1619" "0,1"
|
|
bitfld.long 0x00 18. "B1618,B1618" "0,1"
|
|
bitfld.long 0x00 17. "B1617,B1617" "0,1"
|
|
bitfld.long 0x00 16. "B1616,B1616" "0,1"
|
|
bitfld.long 0x00 15. "B1615,B1615" "0,1"
|
|
bitfld.long 0x00 14. "B1614,B1614" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1613,B1613" "0,1"
|
|
bitfld.long 0x00 12. "B1612,B1612" "0,1"
|
|
bitfld.long 0x00 11. "B1611,B1611" "0,1"
|
|
bitfld.long 0x00 10. "B1610,B1610" "0,1"
|
|
bitfld.long 0x00 9. "B1609,B1609" "0,1"
|
|
bitfld.long 0x00 8. "B1608,B1608" "0,1"
|
|
bitfld.long 0x00 7. "B1607,B1607" "0,1"
|
|
bitfld.long 0x00 6. "B1606,B1606" "0,1"
|
|
bitfld.long 0x00 5. "B1605,B1605" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1604,B1604" "0,1"
|
|
bitfld.long 0x00 3. "B1603,B1603" "0,1"
|
|
bitfld.long 0x00 2. "B1602,B1602" "0,1"
|
|
bitfld.long 0x00 1. "B1601,B1601" "0,1"
|
|
bitfld.long 0x00 0. "B1600,B1600" "0,1"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "MPCBB1_VCTR51,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1663,B1663" "0,1"
|
|
bitfld.long 0x00 30. "B1662,B1662" "0,1"
|
|
bitfld.long 0x00 29. "B1661,B1661" "0,1"
|
|
bitfld.long 0x00 28. "B1660,B1660" "0,1"
|
|
bitfld.long 0x00 27. "B1659,B1659" "0,1"
|
|
bitfld.long 0x00 26. "B1658,B1658" "0,1"
|
|
bitfld.long 0x00 25. "B1657,B1657" "0,1"
|
|
bitfld.long 0x00 24. "B1656,B1656" "0,1"
|
|
bitfld.long 0x00 23. "B1655,B1655" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1654,B1654" "0,1"
|
|
bitfld.long 0x00 21. "B1653,B1653" "0,1"
|
|
bitfld.long 0x00 20. "B1652,B1652" "0,1"
|
|
bitfld.long 0x00 19. "B1651,B1651" "0,1"
|
|
bitfld.long 0x00 18. "B1650,B1650" "0,1"
|
|
bitfld.long 0x00 17. "B1649,B1649" "0,1"
|
|
bitfld.long 0x00 16. "B1648,B1648" "0,1"
|
|
bitfld.long 0x00 15. "B1647,B1647" "0,1"
|
|
bitfld.long 0x00 14. "B1646,B1646" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1645,B1645" "0,1"
|
|
bitfld.long 0x00 12. "B1644,B1644" "0,1"
|
|
bitfld.long 0x00 11. "B1643,B1643" "0,1"
|
|
bitfld.long 0x00 10. "B1642,B1642" "0,1"
|
|
bitfld.long 0x00 9. "B1641,B1641" "0,1"
|
|
bitfld.long 0x00 8. "B1640,B1640" "0,1"
|
|
bitfld.long 0x00 7. "B1639,B1639" "0,1"
|
|
bitfld.long 0x00 6. "B1638,B1638" "0,1"
|
|
bitfld.long 0x00 5. "B1637,B1637" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1636,B1636" "0,1"
|
|
bitfld.long 0x00 3. "B1635,B1635" "0,1"
|
|
bitfld.long 0x00 2. "B1634,B1634" "0,1"
|
|
bitfld.long 0x00 1. "B1633,B1633" "0,1"
|
|
bitfld.long 0x00 0. "B1632,B1632" "0,1"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "MPCBB1_VCTR52,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1695,B1695" "0,1"
|
|
bitfld.long 0x00 30. "B1694,B1694" "0,1"
|
|
bitfld.long 0x00 29. "B1693,B1693" "0,1"
|
|
bitfld.long 0x00 28. "B1692,B1692" "0,1"
|
|
bitfld.long 0x00 27. "B1691,B1691" "0,1"
|
|
bitfld.long 0x00 26. "B1690,B1690" "0,1"
|
|
bitfld.long 0x00 25. "B1689,B1689" "0,1"
|
|
bitfld.long 0x00 24. "B1688,B1688" "0,1"
|
|
bitfld.long 0x00 23. "B1687,B1687" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1686,B1686" "0,1"
|
|
bitfld.long 0x00 21. "B1685,B1685" "0,1"
|
|
bitfld.long 0x00 20. "B1684,B1684" "0,1"
|
|
bitfld.long 0x00 19. "B1683,B1683" "0,1"
|
|
bitfld.long 0x00 18. "B1682,B1682" "0,1"
|
|
bitfld.long 0x00 17. "B1681,B1681" "0,1"
|
|
bitfld.long 0x00 16. "B1680,B1680" "0,1"
|
|
bitfld.long 0x00 15. "B1679,B1679" "0,1"
|
|
bitfld.long 0x00 14. "B1678,B1678" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1677,B1677" "0,1"
|
|
bitfld.long 0x00 12. "B1676,B1676" "0,1"
|
|
bitfld.long 0x00 11. "B1675,B1675" "0,1"
|
|
bitfld.long 0x00 10. "B1674,B1674" "0,1"
|
|
bitfld.long 0x00 9. "B1673,B1673" "0,1"
|
|
bitfld.long 0x00 8. "B1672,B1672" "0,1"
|
|
bitfld.long 0x00 7. "B1671,B1671" "0,1"
|
|
bitfld.long 0x00 6. "B1670,B1670" "0,1"
|
|
bitfld.long 0x00 5. "B1669,B1669" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1668,B1668" "0,1"
|
|
bitfld.long 0x00 3. "B1667,B1667" "0,1"
|
|
bitfld.long 0x00 2. "B1666,B1666" "0,1"
|
|
bitfld.long 0x00 1. "B1665,B1665" "0,1"
|
|
bitfld.long 0x00 0. "B1664,B1664" "0,1"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "MPCBB1_VCTR53,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1727,B1727" "0,1"
|
|
bitfld.long 0x00 30. "B1726,B1726" "0,1"
|
|
bitfld.long 0x00 29. "B1725,B1725" "0,1"
|
|
bitfld.long 0x00 28. "B1724,B1724" "0,1"
|
|
bitfld.long 0x00 27. "B1723,B1723" "0,1"
|
|
bitfld.long 0x00 26. "B1722,B1722" "0,1"
|
|
bitfld.long 0x00 25. "B1721,B1721" "0,1"
|
|
bitfld.long 0x00 24. "B1720,B1720" "0,1"
|
|
bitfld.long 0x00 23. "B1719,B1719" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1718,B1718" "0,1"
|
|
bitfld.long 0x00 21. "B1717,B1717" "0,1"
|
|
bitfld.long 0x00 20. "B1716,B1716" "0,1"
|
|
bitfld.long 0x00 19. "B1715,B1715" "0,1"
|
|
bitfld.long 0x00 18. "B1714,B1714" "0,1"
|
|
bitfld.long 0x00 17. "B1713,B1713" "0,1"
|
|
bitfld.long 0x00 16. "B1712,B1712" "0,1"
|
|
bitfld.long 0x00 15. "B1711,B1711" "0,1"
|
|
bitfld.long 0x00 14. "B1710,B1710" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1709,B1709" "0,1"
|
|
bitfld.long 0x00 12. "B1708,B1708" "0,1"
|
|
bitfld.long 0x00 11. "B1707,B1707" "0,1"
|
|
bitfld.long 0x00 10. "B1706,B1706" "0,1"
|
|
bitfld.long 0x00 9. "B1705,B1705" "0,1"
|
|
bitfld.long 0x00 8. "B1704,B1704" "0,1"
|
|
bitfld.long 0x00 7. "B1703,B1703" "0,1"
|
|
bitfld.long 0x00 6. "B1702,B1702" "0,1"
|
|
bitfld.long 0x00 5. "B1701,B1701" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1700,B1700" "0,1"
|
|
bitfld.long 0x00 3. "B1699,B1699" "0,1"
|
|
bitfld.long 0x00 2. "B1698,B1698" "0,1"
|
|
bitfld.long 0x00 1. "B1697,B1697" "0,1"
|
|
bitfld.long 0x00 0. "B1696,B1696" "0,1"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "MPCBB1_VCTR54,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1759,B1759" "0,1"
|
|
bitfld.long 0x00 30. "B1758,B1758" "0,1"
|
|
bitfld.long 0x00 29. "B1757,B1757" "0,1"
|
|
bitfld.long 0x00 28. "B1756,B1756" "0,1"
|
|
bitfld.long 0x00 27. "B1755,B1755" "0,1"
|
|
bitfld.long 0x00 26. "B1754,B1754" "0,1"
|
|
bitfld.long 0x00 25. "B1753,B1753" "0,1"
|
|
bitfld.long 0x00 24. "B1752,B1752" "0,1"
|
|
bitfld.long 0x00 23. "B1751,B1751" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1750,B1750" "0,1"
|
|
bitfld.long 0x00 21. "B1749,B1749" "0,1"
|
|
bitfld.long 0x00 20. "B1748,B1748" "0,1"
|
|
bitfld.long 0x00 19. "B1747,B1747" "0,1"
|
|
bitfld.long 0x00 18. "B1746,B1746" "0,1"
|
|
bitfld.long 0x00 17. "B1745,B1745" "0,1"
|
|
bitfld.long 0x00 16. "B1744,B1744" "0,1"
|
|
bitfld.long 0x00 15. "B1743,B1743" "0,1"
|
|
bitfld.long 0x00 14. "B1742,B1742" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1741,B1741" "0,1"
|
|
bitfld.long 0x00 12. "B1740,B1740" "0,1"
|
|
bitfld.long 0x00 11. "B1739,B1739" "0,1"
|
|
bitfld.long 0x00 10. "B1738,B1738" "0,1"
|
|
bitfld.long 0x00 9. "B1737,B1737" "0,1"
|
|
bitfld.long 0x00 8. "B1736,B1736" "0,1"
|
|
bitfld.long 0x00 7. "B1735,B1735" "0,1"
|
|
bitfld.long 0x00 6. "B1734,B1734" "0,1"
|
|
bitfld.long 0x00 5. "B1733,B1733" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1732,B1732" "0,1"
|
|
bitfld.long 0x00 3. "B1731,B1731" "0,1"
|
|
bitfld.long 0x00 2. "B1730,B1730" "0,1"
|
|
bitfld.long 0x00 1. "B1729,B1729" "0,1"
|
|
bitfld.long 0x00 0. "B1728,B1728" "0,1"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "MPCBB1_VCTR55,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1791,B1791" "0,1"
|
|
bitfld.long 0x00 30. "B1790,B1790" "0,1"
|
|
bitfld.long 0x00 29. "B1789,B1789" "0,1"
|
|
bitfld.long 0x00 28. "B1788,B1788" "0,1"
|
|
bitfld.long 0x00 27. "B1787,B1787" "0,1"
|
|
bitfld.long 0x00 26. "B1786,B1786" "0,1"
|
|
bitfld.long 0x00 25. "B1785,B1785" "0,1"
|
|
bitfld.long 0x00 24. "B1784,B1784" "0,1"
|
|
bitfld.long 0x00 23. "B1783,B1783" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1782,B1782" "0,1"
|
|
bitfld.long 0x00 21. "B1781,B1781" "0,1"
|
|
bitfld.long 0x00 20. "B1780,B1780" "0,1"
|
|
bitfld.long 0x00 19. "B1779,B1779" "0,1"
|
|
bitfld.long 0x00 18. "B1778,B1778" "0,1"
|
|
bitfld.long 0x00 17. "B1777,B1777" "0,1"
|
|
bitfld.long 0x00 16. "B1776,B1776" "0,1"
|
|
bitfld.long 0x00 15. "B1775,B1775" "0,1"
|
|
bitfld.long 0x00 14. "B1774,B1774" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1773,B1773" "0,1"
|
|
bitfld.long 0x00 12. "B1772,B1772" "0,1"
|
|
bitfld.long 0x00 11. "B1771,B1771" "0,1"
|
|
bitfld.long 0x00 10. "B1770,B1770" "0,1"
|
|
bitfld.long 0x00 9. "B1769,B1769" "0,1"
|
|
bitfld.long 0x00 8. "B1768,B1768" "0,1"
|
|
bitfld.long 0x00 7. "B1767,B1767" "0,1"
|
|
bitfld.long 0x00 6. "B1766,B1766" "0,1"
|
|
bitfld.long 0x00 5. "B1765,B1765" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1764,B1764" "0,1"
|
|
bitfld.long 0x00 3. "B1763,B1763" "0,1"
|
|
bitfld.long 0x00 2. "B1762,B1762" "0,1"
|
|
bitfld.long 0x00 1. "B1761,B1761" "0,1"
|
|
bitfld.long 0x00 0. "B1760,B1760" "0,1"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "MPCBB1_VCTR56,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1823,B1823" "0,1"
|
|
bitfld.long 0x00 30. "B1822,B1822" "0,1"
|
|
bitfld.long 0x00 29. "B1821,B1821" "0,1"
|
|
bitfld.long 0x00 28. "B1820,B1820" "0,1"
|
|
bitfld.long 0x00 27. "B1819,B1819" "0,1"
|
|
bitfld.long 0x00 26. "B1818,B1818" "0,1"
|
|
bitfld.long 0x00 25. "B1817,B1817" "0,1"
|
|
bitfld.long 0x00 24. "B1816,B1816" "0,1"
|
|
bitfld.long 0x00 23. "B1815,B1815" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1814,B1814" "0,1"
|
|
bitfld.long 0x00 21. "B1813,B1813" "0,1"
|
|
bitfld.long 0x00 20. "B1812,B1812" "0,1"
|
|
bitfld.long 0x00 19. "B1811,B1811" "0,1"
|
|
bitfld.long 0x00 18. "B1810,B1810" "0,1"
|
|
bitfld.long 0x00 17. "B1809,B1809" "0,1"
|
|
bitfld.long 0x00 16. "B1808,B1808" "0,1"
|
|
bitfld.long 0x00 15. "B1807,B1807" "0,1"
|
|
bitfld.long 0x00 14. "B1806,B1806" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1805,B1805" "0,1"
|
|
bitfld.long 0x00 12. "B1804,B1804" "0,1"
|
|
bitfld.long 0x00 11. "B1803,B1803" "0,1"
|
|
bitfld.long 0x00 10. "B1802,B1802" "0,1"
|
|
bitfld.long 0x00 9. "B1801,B1801" "0,1"
|
|
bitfld.long 0x00 8. "B1800,B1800" "0,1"
|
|
bitfld.long 0x00 7. "B1799,B1799" "0,1"
|
|
bitfld.long 0x00 6. "B1798,B1798" "0,1"
|
|
bitfld.long 0x00 5. "B1797,B1797" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1796,B1796" "0,1"
|
|
bitfld.long 0x00 3. "B1795,B1795" "0,1"
|
|
bitfld.long 0x00 2. "B1794,B1794" "0,1"
|
|
bitfld.long 0x00 1. "B1793,B1793" "0,1"
|
|
bitfld.long 0x00 0. "B1792,B1792" "0,1"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "MPCBB1_VCTR57,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1855,B1855" "0,1"
|
|
bitfld.long 0x00 30. "B1854,B1854" "0,1"
|
|
bitfld.long 0x00 29. "B1853,B1853" "0,1"
|
|
bitfld.long 0x00 28. "B1852,B1852" "0,1"
|
|
bitfld.long 0x00 27. "B1851,B1851" "0,1"
|
|
bitfld.long 0x00 26. "B1850,B1850" "0,1"
|
|
bitfld.long 0x00 25. "B1849,B1849" "0,1"
|
|
bitfld.long 0x00 24. "B1848,B1848" "0,1"
|
|
bitfld.long 0x00 23. "B1847,B1847" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1846,B1846" "0,1"
|
|
bitfld.long 0x00 21. "B1845,B1845" "0,1"
|
|
bitfld.long 0x00 20. "B1844,B1844" "0,1"
|
|
bitfld.long 0x00 19. "B1843,B1843" "0,1"
|
|
bitfld.long 0x00 18. "B1842,B1842" "0,1"
|
|
bitfld.long 0x00 17. "B1841,B1841" "0,1"
|
|
bitfld.long 0x00 16. "B1840,B1840" "0,1"
|
|
bitfld.long 0x00 15. "B1839,B1839" "0,1"
|
|
bitfld.long 0x00 14. "B1838,B1838" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1837,B1837" "0,1"
|
|
bitfld.long 0x00 12. "B1836,B1836" "0,1"
|
|
bitfld.long 0x00 11. "B1835,B1835" "0,1"
|
|
bitfld.long 0x00 10. "B1834,B1834" "0,1"
|
|
bitfld.long 0x00 9. "B1833,B1833" "0,1"
|
|
bitfld.long 0x00 8. "B1832,B1832" "0,1"
|
|
bitfld.long 0x00 7. "B1831,B1831" "0,1"
|
|
bitfld.long 0x00 6. "B1830,B1830" "0,1"
|
|
bitfld.long 0x00 5. "B1829,B1829" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1828,B1828" "0,1"
|
|
bitfld.long 0x00 3. "B1827,B1827" "0,1"
|
|
bitfld.long 0x00 2. "B1826,B1826" "0,1"
|
|
bitfld.long 0x00 1. "B1825,B1825" "0,1"
|
|
bitfld.long 0x00 0. "B1824,B1824" "0,1"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "MPCBB1_VCTR58,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1887,B1887" "0,1"
|
|
bitfld.long 0x00 30. "B1886,B1886" "0,1"
|
|
bitfld.long 0x00 29. "B1885,B1885" "0,1"
|
|
bitfld.long 0x00 28. "B1884,B1884" "0,1"
|
|
bitfld.long 0x00 27. "B1883,B1883" "0,1"
|
|
bitfld.long 0x00 26. "B1882,B1882" "0,1"
|
|
bitfld.long 0x00 25. "B1881,B1881" "0,1"
|
|
bitfld.long 0x00 24. "B1880,B1880" "0,1"
|
|
bitfld.long 0x00 23. "B1879,B1879" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1878,B1878" "0,1"
|
|
bitfld.long 0x00 21. "B1877,B1877" "0,1"
|
|
bitfld.long 0x00 20. "B1876,B1876" "0,1"
|
|
bitfld.long 0x00 19. "B1875,B1875" "0,1"
|
|
bitfld.long 0x00 18. "B1874,B1874" "0,1"
|
|
bitfld.long 0x00 17. "B1873,B1873" "0,1"
|
|
bitfld.long 0x00 16. "B1872,B1872" "0,1"
|
|
bitfld.long 0x00 15. "B1871,B1871" "0,1"
|
|
bitfld.long 0x00 14. "B1870,B1870" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1869,B1869" "0,1"
|
|
bitfld.long 0x00 12. "B1868,B1868" "0,1"
|
|
bitfld.long 0x00 11. "B1867,B1867" "0,1"
|
|
bitfld.long 0x00 10. "B1866,B1866" "0,1"
|
|
bitfld.long 0x00 9. "B1865,B1865" "0,1"
|
|
bitfld.long 0x00 8. "B1864,B1864" "0,1"
|
|
bitfld.long 0x00 7. "B1863,B1863" "0,1"
|
|
bitfld.long 0x00 6. "B1862,B1862" "0,1"
|
|
bitfld.long 0x00 5. "B1861,B1861" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1860,B1860" "0,1"
|
|
bitfld.long 0x00 3. "B1859,B1859" "0,1"
|
|
bitfld.long 0x00 2. "B1858,B1858" "0,1"
|
|
bitfld.long 0x00 1. "B1857,B1857" "0,1"
|
|
bitfld.long 0x00 0. "B1856,B1856" "0,1"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "MPCBB1_VCTR59,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1919,B1919" "0,1"
|
|
bitfld.long 0x00 30. "B1918,B1918" "0,1"
|
|
bitfld.long 0x00 29. "B1917,B1917" "0,1"
|
|
bitfld.long 0x00 28. "B1916,B1916" "0,1"
|
|
bitfld.long 0x00 27. "B1915,B1915" "0,1"
|
|
bitfld.long 0x00 26. "B1914,B1914" "0,1"
|
|
bitfld.long 0x00 25. "B1913,B1913" "0,1"
|
|
bitfld.long 0x00 24. "B1912,B1912" "0,1"
|
|
bitfld.long 0x00 23. "B1911,B1911" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1910,B1910" "0,1"
|
|
bitfld.long 0x00 21. "B1909,B1909" "0,1"
|
|
bitfld.long 0x00 20. "B1908,B1908" "0,1"
|
|
bitfld.long 0x00 19. "B1907,B1907" "0,1"
|
|
bitfld.long 0x00 18. "B1906,B1906" "0,1"
|
|
bitfld.long 0x00 17. "B1905,B1905" "0,1"
|
|
bitfld.long 0x00 16. "B1904,B1904" "0,1"
|
|
bitfld.long 0x00 15. "B1903,B1903" "0,1"
|
|
bitfld.long 0x00 14. "B1902,B1902" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1901,B1901" "0,1"
|
|
bitfld.long 0x00 12. "B1900,B1900" "0,1"
|
|
bitfld.long 0x00 11. "B1899,B1899" "0,1"
|
|
bitfld.long 0x00 10. "B1898,B1898" "0,1"
|
|
bitfld.long 0x00 9. "B1897,B1897" "0,1"
|
|
bitfld.long 0x00 8. "B1896,B1896" "0,1"
|
|
bitfld.long 0x00 7. "B1895,B1895" "0,1"
|
|
bitfld.long 0x00 6. "B1894,B1894" "0,1"
|
|
bitfld.long 0x00 5. "B1893,B1893" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1892,B1892" "0,1"
|
|
bitfld.long 0x00 3. "B1891,B1891" "0,1"
|
|
bitfld.long 0x00 2. "B1890,B1890" "0,1"
|
|
bitfld.long 0x00 1. "B1889,B1889" "0,1"
|
|
bitfld.long 0x00 0. "B1888,B1888" "0,1"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "MPCBB1_VCTR60,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1951,B1951" "0,1"
|
|
bitfld.long 0x00 30. "B1950,B1950" "0,1"
|
|
bitfld.long 0x00 29. "B1949,B1949" "0,1"
|
|
bitfld.long 0x00 28. "B1948,B1948" "0,1"
|
|
bitfld.long 0x00 27. "B1947,B1947" "0,1"
|
|
bitfld.long 0x00 26. "B1946,B1946" "0,1"
|
|
bitfld.long 0x00 25. "B1945,B1945" "0,1"
|
|
bitfld.long 0x00 24. "B1944,B1944" "0,1"
|
|
bitfld.long 0x00 23. "B1943,B1943" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1942,B1942" "0,1"
|
|
bitfld.long 0x00 21. "B1941,B1941" "0,1"
|
|
bitfld.long 0x00 20. "B1940,B1940" "0,1"
|
|
bitfld.long 0x00 19. "B1939,B1939" "0,1"
|
|
bitfld.long 0x00 18. "B1938,B1938" "0,1"
|
|
bitfld.long 0x00 17. "B1937,B1937" "0,1"
|
|
bitfld.long 0x00 16. "B1936,B1936" "0,1"
|
|
bitfld.long 0x00 15. "B1935,B1935" "0,1"
|
|
bitfld.long 0x00 14. "B1934,B1934" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1933,B1933" "0,1"
|
|
bitfld.long 0x00 12. "B1932,B1932" "0,1"
|
|
bitfld.long 0x00 11. "B1931,B1931" "0,1"
|
|
bitfld.long 0x00 10. "B1930,B1930" "0,1"
|
|
bitfld.long 0x00 9. "B1929,B1929" "0,1"
|
|
bitfld.long 0x00 8. "B1928,B1928" "0,1"
|
|
bitfld.long 0x00 7. "B1927,B1927" "0,1"
|
|
bitfld.long 0x00 6. "B1926,B1926" "0,1"
|
|
bitfld.long 0x00 5. "B1925,B1925" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1924,B1924" "0,1"
|
|
bitfld.long 0x00 3. "B1923,B1923" "0,1"
|
|
bitfld.long 0x00 2. "B1922,B1922" "0,1"
|
|
bitfld.long 0x00 1. "B1921,B1921" "0,1"
|
|
bitfld.long 0x00 0. "B1920,B1920" "0,1"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "MPCBB1_VCTR61,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1983,B1983" "0,1"
|
|
bitfld.long 0x00 30. "B1982,B1982" "0,1"
|
|
bitfld.long 0x00 29. "B1981,B1981" "0,1"
|
|
bitfld.long 0x00 28. "B1980,B1980" "0,1"
|
|
bitfld.long 0x00 27. "B1979,B1979" "0,1"
|
|
bitfld.long 0x00 26. "B1978,B1978" "0,1"
|
|
bitfld.long 0x00 25. "B1977,B1977" "0,1"
|
|
bitfld.long 0x00 24. "B1976,B1976" "0,1"
|
|
bitfld.long 0x00 23. "B1975,B1975" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1974,B1974" "0,1"
|
|
bitfld.long 0x00 21. "B1973,B1973" "0,1"
|
|
bitfld.long 0x00 20. "B1972,B1972" "0,1"
|
|
bitfld.long 0x00 19. "B1971,B1971" "0,1"
|
|
bitfld.long 0x00 18. "B1970,B1970" "0,1"
|
|
bitfld.long 0x00 17. "B1969,B1969" "0,1"
|
|
bitfld.long 0x00 16. "B1968,B1968" "0,1"
|
|
bitfld.long 0x00 15. "B1967,B1967" "0,1"
|
|
bitfld.long 0x00 14. "B1966,B1966" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1965,B1965" "0,1"
|
|
bitfld.long 0x00 12. "B1964,B1964" "0,1"
|
|
bitfld.long 0x00 11. "B1963,B1963" "0,1"
|
|
bitfld.long 0x00 10. "B1962,B1962" "0,1"
|
|
bitfld.long 0x00 9. "B1961,B1961" "0,1"
|
|
bitfld.long 0x00 8. "B1960,B1960" "0,1"
|
|
bitfld.long 0x00 7. "B1959,B1959" "0,1"
|
|
bitfld.long 0x00 6. "B1958,B1958" "0,1"
|
|
bitfld.long 0x00 5. "B1957,B1957" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1956,B1956" "0,1"
|
|
bitfld.long 0x00 3. "B1955,B1955" "0,1"
|
|
bitfld.long 0x00 2. "B1954,B1954" "0,1"
|
|
bitfld.long 0x00 1. "B1953,B1953" "0,1"
|
|
bitfld.long 0x00 0. "B1952,B1952" "0,1"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "MPCBB1_VCTR62,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B2015,B2015" "0,1"
|
|
bitfld.long 0x00 30. "B2014,B2014" "0,1"
|
|
bitfld.long 0x00 29. "B2013,B2013" "0,1"
|
|
bitfld.long 0x00 28. "B2012,B2012" "0,1"
|
|
bitfld.long 0x00 27. "B2011,B2011" "0,1"
|
|
bitfld.long 0x00 26. "B2010,B2010" "0,1"
|
|
bitfld.long 0x00 25. "B2009,B2009" "0,1"
|
|
bitfld.long 0x00 24. "B2008,B2008" "0,1"
|
|
bitfld.long 0x00 23. "B2007,B2007" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B2006,B2006" "0,1"
|
|
bitfld.long 0x00 21. "B2005,B2005" "0,1"
|
|
bitfld.long 0x00 20. "B2004,B2004" "0,1"
|
|
bitfld.long 0x00 19. "B2003,B2003" "0,1"
|
|
bitfld.long 0x00 18. "B2002,B2002" "0,1"
|
|
bitfld.long 0x00 17. "B2001,B2001" "0,1"
|
|
bitfld.long 0x00 16. "B2000,B2000" "0,1"
|
|
bitfld.long 0x00 15. "B1999,B1999" "0,1"
|
|
bitfld.long 0x00 14. "B1998,B1998" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1997,B1997" "0,1"
|
|
bitfld.long 0x00 12. "B1996,B1996" "0,1"
|
|
bitfld.long 0x00 11. "B1995,B1995" "0,1"
|
|
bitfld.long 0x00 10. "B1994,B1994" "0,1"
|
|
bitfld.long 0x00 9. "B1993,B1993" "0,1"
|
|
bitfld.long 0x00 8. "B1992,B1992" "0,1"
|
|
bitfld.long 0x00 7. "B1991,B1991" "0,1"
|
|
bitfld.long 0x00 6. "B1990,B1990" "0,1"
|
|
bitfld.long 0x00 5. "B1989,B1989" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1988,B1988" "0,1"
|
|
bitfld.long 0x00 3. "B1987,B1987" "0,1"
|
|
bitfld.long 0x00 2. "B1986,B1986" "0,1"
|
|
bitfld.long 0x00 1. "B1985,B1985" "0,1"
|
|
bitfld.long 0x00 0. "B1984,B1984" "0,1"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "MPCBB1_VCTR63,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B2047,B2047" "0,1"
|
|
bitfld.long 0x00 30. "B2046,B2046" "0,1"
|
|
bitfld.long 0x00 29. "B2045,B2045" "0,1"
|
|
bitfld.long 0x00 28. "B2044,B2044" "0,1"
|
|
bitfld.long 0x00 27. "B2043,B2043" "0,1"
|
|
bitfld.long 0x00 26. "B2042,B2042" "0,1"
|
|
bitfld.long 0x00 25. "B2041,B2041" "0,1"
|
|
bitfld.long 0x00 24. "B2040,B2040" "0,1"
|
|
bitfld.long 0x00 23. "B2039,B2039" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B2038,B2038" "0,1"
|
|
bitfld.long 0x00 21. "B2037,B2037" "0,1"
|
|
bitfld.long 0x00 20. "B2036,B2036" "0,1"
|
|
bitfld.long 0x00 19. "B2035,B2035" "0,1"
|
|
bitfld.long 0x00 18. "B2034,B2034" "0,1"
|
|
bitfld.long 0x00 17. "B2033,B2033" "0,1"
|
|
bitfld.long 0x00 16. "B2032,B2032" "0,1"
|
|
bitfld.long 0x00 15. "B2031,B2031" "0,1"
|
|
bitfld.long 0x00 14. "B2030,B2030" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B2029,B2029" "0,1"
|
|
bitfld.long 0x00 12. "B2028,B2028" "0,1"
|
|
bitfld.long 0x00 11. "B2027,B2027" "0,1"
|
|
bitfld.long 0x00 10. "B2026,B2026" "0,1"
|
|
bitfld.long 0x00 9. "B2025,B2025" "0,1"
|
|
bitfld.long 0x00 8. "B2024,B2024" "0,1"
|
|
bitfld.long 0x00 7. "B2023,B2023" "0,1"
|
|
bitfld.long 0x00 6. "B2022,B2022" "0,1"
|
|
bitfld.long 0x00 5. "B2021,B2021" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B2020,B2020" "0,1"
|
|
bitfld.long 0x00 3. "B2019,B2019" "0,1"
|
|
bitfld.long 0x00 2. "B2018,B2018" "0,1"
|
|
bitfld.long 0x00 1. "B2017,B2017" "0,1"
|
|
bitfld.long 0x00 0. "B2016,B2016" "0,1"
|
|
tree.end
|
|
tree "MPCBB2"
|
|
base ad:0x40033000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MPCBB2_CR,MPCBB control register"
|
|
bitfld.long 0x00 31. "SRWILADIS,SRWILADIS" "0,1"
|
|
bitfld.long 0x00 30. "INVSECSTATE,INVSECSTATE" "0,1"
|
|
bitfld.long 0x00 0. "LCK,LCK" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MPCBB2_LCKVTR1,MPCBB control register"
|
|
bitfld.long 0x00 31. "LCKSB31,LCKSB31" "0,1"
|
|
bitfld.long 0x00 30. "LCKSB30,LCKSB30" "0,1"
|
|
bitfld.long 0x00 29. "LCKSB29,LCKSB29" "0,1"
|
|
bitfld.long 0x00 28. "LCKSB28,LCKSB28" "0,1"
|
|
bitfld.long 0x00 27. "LCKSB27,LCKSB27" "0,1"
|
|
bitfld.long 0x00 26. "LCKSB26,LCKSB26" "0,1"
|
|
bitfld.long 0x00 25. "LCKSB25,LCKSB25" "0,1"
|
|
bitfld.long 0x00 24. "LCKSB24,LCKSB24" "0,1"
|
|
bitfld.long 0x00 23. "LCKSB23,LCKSB23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "LCKSB22,LCKSB22" "0,1"
|
|
bitfld.long 0x00 21. "LCKSB21,LCKSB21" "0,1"
|
|
bitfld.long 0x00 20. "LCKSB20,LCKSB20" "0,1"
|
|
bitfld.long 0x00 19. "LCKSB19,LCKSB19" "0,1"
|
|
bitfld.long 0x00 18. "LCKSB18,LCKSB18" "0,1"
|
|
bitfld.long 0x00 17. "LCKSB17,LCKSB17" "0,1"
|
|
bitfld.long 0x00 16. "LCKSB16,LCKSB16" "0,1"
|
|
bitfld.long 0x00 15. "LCKSB15,LCKSB15" "0,1"
|
|
bitfld.long 0x00 14. "LCKSB14,LCKSB14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "LCKSB13,LCKSB13" "0,1"
|
|
bitfld.long 0x00 12. "LCKSB12,LCKSB12" "0,1"
|
|
bitfld.long 0x00 11. "LCKSB11,LCKSB11" "0,1"
|
|
bitfld.long 0x00 10. "LCKSB10,LCKSB10" "0,1"
|
|
bitfld.long 0x00 9. "LCKSB9,LCKSB9" "0,1"
|
|
bitfld.long 0x00 8. "LCKSB8,LCKSB8" "0,1"
|
|
bitfld.long 0x00 7. "LCKSB7,LCKSB7" "0,1"
|
|
bitfld.long 0x00 6. "LCKSB6,LCKSB6" "0,1"
|
|
bitfld.long 0x00 5. "LCKSB5,LCKSB5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LCKSB4,LCKSB4" "0,1"
|
|
bitfld.long 0x00 3. "LCKSB3,LCKSB3" "0,1"
|
|
bitfld.long 0x00 2. "LCKSB2,LCKSB2" "0,1"
|
|
bitfld.long 0x00 1. "LCKSB1,LCKSB1" "0,1"
|
|
bitfld.long 0x00 0. "LCKSB0,LCKSB0" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MPCBB2_LCKVTR2,MPCBB control register"
|
|
bitfld.long 0x00 31. "LCKSB63,LCKSB63" "0,1"
|
|
bitfld.long 0x00 30. "LCKSB62,LCKSB62" "0,1"
|
|
bitfld.long 0x00 29. "LCKSB61,LCKSB61" "0,1"
|
|
bitfld.long 0x00 28. "LCKSB60,LCKSB60" "0,1"
|
|
bitfld.long 0x00 27. "LCKSB59,LCKSB59" "0,1"
|
|
bitfld.long 0x00 26. "LCKSB58,LCKSB58" "0,1"
|
|
bitfld.long 0x00 25. "LCKSB57,LCKSB57" "0,1"
|
|
bitfld.long 0x00 24. "LCKSB56,LCKSB56" "0,1"
|
|
bitfld.long 0x00 23. "LCKSB55,LCKSB55" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "LCKSB54,LCKSB54" "0,1"
|
|
bitfld.long 0x00 21. "LCKSB53,LCKSB53" "0,1"
|
|
bitfld.long 0x00 20. "LCKSB52,LCKSB52" "0,1"
|
|
bitfld.long 0x00 19. "LCKSB51,LCKSB51" "0,1"
|
|
bitfld.long 0x00 18. "LCKSB50,LCKSB50" "0,1"
|
|
bitfld.long 0x00 17. "LCKSB49,LCKSB49" "0,1"
|
|
bitfld.long 0x00 16. "LCKSB48,LCKSB48" "0,1"
|
|
bitfld.long 0x00 15. "LCKSB47,LCKSB47" "0,1"
|
|
bitfld.long 0x00 14. "LCKSB46,LCKSB46" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "LCKSB45,LCKSB45" "0,1"
|
|
bitfld.long 0x00 12. "LCKSB44,LCKSB44" "0,1"
|
|
bitfld.long 0x00 11. "LCKSB43,LCKSB43" "0,1"
|
|
bitfld.long 0x00 10. "LCKSB42,LCKSB42" "0,1"
|
|
bitfld.long 0x00 9. "LCKSB41,LCKSB41" "0,1"
|
|
bitfld.long 0x00 8. "LCKSB40,LCKSB40" "0,1"
|
|
bitfld.long 0x00 7. "LCKSB39,LCKSB39" "0,1"
|
|
bitfld.long 0x00 6. "LCKSB38,LCKSB38" "0,1"
|
|
bitfld.long 0x00 5. "LCKSB37,LCKSB37" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LCKSB36,LCKSB36" "0,1"
|
|
bitfld.long 0x00 3. "LCKSB35,LCKSB35" "0,1"
|
|
bitfld.long 0x00 2. "LCKSB34,LCKSB34" "0,1"
|
|
bitfld.long 0x00 1. "LCKSB33,LCKSB33" "0,1"
|
|
bitfld.long 0x00 0. "LCKSB32,LCKSB32" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MPCBB2_VCTR0,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B31,B31" "0,1"
|
|
bitfld.long 0x00 30. "B30,B30" "0,1"
|
|
bitfld.long 0x00 29. "B29,B29" "0,1"
|
|
bitfld.long 0x00 28. "B28,B28" "0,1"
|
|
bitfld.long 0x00 27. "B27,B27" "0,1"
|
|
bitfld.long 0x00 26. "B26,B26" "0,1"
|
|
bitfld.long 0x00 25. "B25,B25" "0,1"
|
|
bitfld.long 0x00 24. "B24,B24" "0,1"
|
|
bitfld.long 0x00 23. "B23,B23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B22,B22" "0,1"
|
|
bitfld.long 0x00 21. "B21,B21" "0,1"
|
|
bitfld.long 0x00 20. "B20,B20" "0,1"
|
|
bitfld.long 0x00 19. "B19,B19" "0,1"
|
|
bitfld.long 0x00 18. "B18,B18" "0,1"
|
|
bitfld.long 0x00 17. "B17,B17" "0,1"
|
|
bitfld.long 0x00 16. "B16,B16" "0,1"
|
|
bitfld.long 0x00 15. "B15,B15" "0,1"
|
|
bitfld.long 0x00 14. "B14,B14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B13,B13" "0,1"
|
|
bitfld.long 0x00 12. "B12,B12" "0,1"
|
|
bitfld.long 0x00 11. "B11,B11" "0,1"
|
|
bitfld.long 0x00 10. "B10,B10" "0,1"
|
|
bitfld.long 0x00 9. "B9,B9" "0,1"
|
|
bitfld.long 0x00 8. "B8,B8" "0,1"
|
|
bitfld.long 0x00 7. "B7,B7" "0,1"
|
|
bitfld.long 0x00 6. "B6,B6" "0,1"
|
|
bitfld.long 0x00 5. "B5,B5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B4,B4" "0,1"
|
|
bitfld.long 0x00 3. "B3,B3" "0,1"
|
|
bitfld.long 0x00 2. "B2,B2" "0,1"
|
|
bitfld.long 0x00 1. "B1,B1" "0,1"
|
|
bitfld.long 0x00 0. "B0,B0" "0,1"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "MPCBB2_VCTR1,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B63,B63" "0,1"
|
|
bitfld.long 0x00 30. "B62,B62" "0,1"
|
|
bitfld.long 0x00 29. "B61,B61" "0,1"
|
|
bitfld.long 0x00 28. "B60,B60" "0,1"
|
|
bitfld.long 0x00 27. "B59,B59" "0,1"
|
|
bitfld.long 0x00 26. "B58,B58" "0,1"
|
|
bitfld.long 0x00 25. "B57,B57" "0,1"
|
|
bitfld.long 0x00 24. "B56,B56" "0,1"
|
|
bitfld.long 0x00 23. "B55,B55" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B54,B54" "0,1"
|
|
bitfld.long 0x00 21. "B53,B53" "0,1"
|
|
bitfld.long 0x00 20. "B52,B52" "0,1"
|
|
bitfld.long 0x00 19. "B51,B51" "0,1"
|
|
bitfld.long 0x00 18. "B50,B50" "0,1"
|
|
bitfld.long 0x00 17. "B49,B49" "0,1"
|
|
bitfld.long 0x00 16. "B48,B48" "0,1"
|
|
bitfld.long 0x00 15. "B47,B47" "0,1"
|
|
bitfld.long 0x00 14. "B46,B46" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B45,B45" "0,1"
|
|
bitfld.long 0x00 12. "B44,B44" "0,1"
|
|
bitfld.long 0x00 11. "B43,B43" "0,1"
|
|
bitfld.long 0x00 10. "B42,B42" "0,1"
|
|
bitfld.long 0x00 9. "B41,B41" "0,1"
|
|
bitfld.long 0x00 8. "B40,B40" "0,1"
|
|
bitfld.long 0x00 7. "B39,B39" "0,1"
|
|
bitfld.long 0x00 6. "B38,B38" "0,1"
|
|
bitfld.long 0x00 5. "B37,B37" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B36,B36" "0,1"
|
|
bitfld.long 0x00 3. "B35,B35" "0,1"
|
|
bitfld.long 0x00 2. "B34,B34" "0,1"
|
|
bitfld.long 0x00 1. "B33,B33" "0,1"
|
|
bitfld.long 0x00 0. "B32,B32" "0,1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "MPCBB2_VCTR2,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B95,B95" "0,1"
|
|
bitfld.long 0x00 30. "B94,B94" "0,1"
|
|
bitfld.long 0x00 29. "B93,B93" "0,1"
|
|
bitfld.long 0x00 28. "B92,B92" "0,1"
|
|
bitfld.long 0x00 27. "B91,B91" "0,1"
|
|
bitfld.long 0x00 26. "B90,B90" "0,1"
|
|
bitfld.long 0x00 25. "B89,B89" "0,1"
|
|
bitfld.long 0x00 24. "B88,B88" "0,1"
|
|
bitfld.long 0x00 23. "B87,B87" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B86,B86" "0,1"
|
|
bitfld.long 0x00 21. "B85,B85" "0,1"
|
|
bitfld.long 0x00 20. "B84,B84" "0,1"
|
|
bitfld.long 0x00 19. "B83,B83" "0,1"
|
|
bitfld.long 0x00 18. "B82,B82" "0,1"
|
|
bitfld.long 0x00 17. "B81,B81" "0,1"
|
|
bitfld.long 0x00 16. "B80,B80" "0,1"
|
|
bitfld.long 0x00 15. "B79,B79" "0,1"
|
|
bitfld.long 0x00 14. "B78,B78" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B77,B77" "0,1"
|
|
bitfld.long 0x00 12. "B76,B76" "0,1"
|
|
bitfld.long 0x00 11. "B75,B75" "0,1"
|
|
bitfld.long 0x00 10. "B74,B74" "0,1"
|
|
bitfld.long 0x00 9. "B73,B73" "0,1"
|
|
bitfld.long 0x00 8. "B72,B72" "0,1"
|
|
bitfld.long 0x00 7. "B71,B71" "0,1"
|
|
bitfld.long 0x00 6. "B70,B70" "0,1"
|
|
bitfld.long 0x00 5. "B69,B69" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B68,B68" "0,1"
|
|
bitfld.long 0x00 3. "B67,B67" "0,1"
|
|
bitfld.long 0x00 2. "B66,B66" "0,1"
|
|
bitfld.long 0x00 1. "B65,B65" "0,1"
|
|
bitfld.long 0x00 0. "B64,B64" "0,1"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR3,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B127,B127" "0,1"
|
|
bitfld.long 0x00 30. "B126,B126" "0,1"
|
|
bitfld.long 0x00 29. "B125,B125" "0,1"
|
|
bitfld.long 0x00 28. "B124,B124" "0,1"
|
|
bitfld.long 0x00 27. "B123,B123" "0,1"
|
|
bitfld.long 0x00 26. "B122,B122" "0,1"
|
|
bitfld.long 0x00 25. "B121,B121" "0,1"
|
|
bitfld.long 0x00 24. "B120,B120" "0,1"
|
|
bitfld.long 0x00 23. "B119,B119" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B118,B118" "0,1"
|
|
bitfld.long 0x00 21. "B117,B117" "0,1"
|
|
bitfld.long 0x00 20. "B116,B116" "0,1"
|
|
bitfld.long 0x00 19. "B115,B115" "0,1"
|
|
bitfld.long 0x00 18. "B114,B114" "0,1"
|
|
bitfld.long 0x00 17. "B113,B113" "0,1"
|
|
bitfld.long 0x00 16. "B112,B112" "0,1"
|
|
bitfld.long 0x00 15. "B111,B111" "0,1"
|
|
bitfld.long 0x00 14. "B110,B110" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B109,B109" "0,1"
|
|
bitfld.long 0x00 12. "B108,B108" "0,1"
|
|
bitfld.long 0x00 11. "B107,B107" "0,1"
|
|
bitfld.long 0x00 10. "B106,B106" "0,1"
|
|
bitfld.long 0x00 9. "B105,B105" "0,1"
|
|
bitfld.long 0x00 8. "B104,B104" "0,1"
|
|
bitfld.long 0x00 7. "B103,B103" "0,1"
|
|
bitfld.long 0x00 6. "B102,B102" "0,1"
|
|
bitfld.long 0x00 5. "B101,B101" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B100,B100" "0,1"
|
|
bitfld.long 0x00 3. "B99,B99" "0,1"
|
|
bitfld.long 0x00 2. "B98,B98" "0,1"
|
|
bitfld.long 0x00 1. "B97,B97" "0,1"
|
|
bitfld.long 0x00 0. "B96,B96" "0,1"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MPCBB2_VCTR4,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B159,B159" "0,1"
|
|
bitfld.long 0x00 30. "B158,B158" "0,1"
|
|
bitfld.long 0x00 29. "B157,B157" "0,1"
|
|
bitfld.long 0x00 28. "B156,B156" "0,1"
|
|
bitfld.long 0x00 27. "B155,B155" "0,1"
|
|
bitfld.long 0x00 26. "B154,B154" "0,1"
|
|
bitfld.long 0x00 25. "B153,B153" "0,1"
|
|
bitfld.long 0x00 24. "B152,B152" "0,1"
|
|
bitfld.long 0x00 23. "B151,B151" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B150,B150" "0,1"
|
|
bitfld.long 0x00 21. "B149,B149" "0,1"
|
|
bitfld.long 0x00 20. "B148,B148" "0,1"
|
|
bitfld.long 0x00 19. "B147,B147" "0,1"
|
|
bitfld.long 0x00 18. "B146,B146" "0,1"
|
|
bitfld.long 0x00 17. "B145,B145" "0,1"
|
|
bitfld.long 0x00 16. "B144,B144" "0,1"
|
|
bitfld.long 0x00 15. "B143,B143" "0,1"
|
|
bitfld.long 0x00 14. "B142,B142" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B141,B141" "0,1"
|
|
bitfld.long 0x00 12. "B140,B140" "0,1"
|
|
bitfld.long 0x00 11. "B139,B139" "0,1"
|
|
bitfld.long 0x00 10. "B138,B138" "0,1"
|
|
bitfld.long 0x00 9. "B137,B137" "0,1"
|
|
bitfld.long 0x00 8. "B136,B136" "0,1"
|
|
bitfld.long 0x00 7. "B135,B135" "0,1"
|
|
bitfld.long 0x00 6. "B134,B134" "0,1"
|
|
bitfld.long 0x00 5. "B133,B133" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B132,B132" "0,1"
|
|
bitfld.long 0x00 3. "B131,B131" "0,1"
|
|
bitfld.long 0x00 2. "B130,B130" "0,1"
|
|
bitfld.long 0x00 1. "B129,B129" "0,1"
|
|
bitfld.long 0x00 0. "B128,B128" "0,1"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MPCBB2_VCTR5,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B191,B191" "0,1"
|
|
bitfld.long 0x00 30. "B190,B190" "0,1"
|
|
bitfld.long 0x00 29. "B189,B189" "0,1"
|
|
bitfld.long 0x00 28. "B188,B188" "0,1"
|
|
bitfld.long 0x00 27. "B187,B187" "0,1"
|
|
bitfld.long 0x00 26. "B186,B186" "0,1"
|
|
bitfld.long 0x00 25. "B185,B185" "0,1"
|
|
bitfld.long 0x00 24. "B184,B184" "0,1"
|
|
bitfld.long 0x00 23. "B183,B183" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B182,B182" "0,1"
|
|
bitfld.long 0x00 21. "B181,B181" "0,1"
|
|
bitfld.long 0x00 20. "B180,B180" "0,1"
|
|
bitfld.long 0x00 19. "B179,B179" "0,1"
|
|
bitfld.long 0x00 18. "B178,B178" "0,1"
|
|
bitfld.long 0x00 17. "B177,B177" "0,1"
|
|
bitfld.long 0x00 16. "B176,B176" "0,1"
|
|
bitfld.long 0x00 15. "B175,B175" "0,1"
|
|
bitfld.long 0x00 14. "B174,B174" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B173,B173" "0,1"
|
|
bitfld.long 0x00 12. "B172,B172" "0,1"
|
|
bitfld.long 0x00 11. "B171,B171" "0,1"
|
|
bitfld.long 0x00 10. "B170,B170" "0,1"
|
|
bitfld.long 0x00 9. "B169,B169" "0,1"
|
|
bitfld.long 0x00 8. "B168,B168" "0,1"
|
|
bitfld.long 0x00 7. "B167,B167" "0,1"
|
|
bitfld.long 0x00 6. "B166,B166" "0,1"
|
|
bitfld.long 0x00 5. "B165,B165" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B164,B164" "0,1"
|
|
bitfld.long 0x00 3. "B163,B163" "0,1"
|
|
bitfld.long 0x00 2. "B162,B162" "0,1"
|
|
bitfld.long 0x00 1. "B161,B161" "0,1"
|
|
bitfld.long 0x00 0. "B160,B160" "0,1"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MPCBB2_VCTR6,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B223,B223" "0,1"
|
|
bitfld.long 0x00 30. "B222,B222" "0,1"
|
|
bitfld.long 0x00 29. "B221,B221" "0,1"
|
|
bitfld.long 0x00 28. "B220,B220" "0,1"
|
|
bitfld.long 0x00 27. "B219,B219" "0,1"
|
|
bitfld.long 0x00 26. "B218,B218" "0,1"
|
|
bitfld.long 0x00 25. "B217,B217" "0,1"
|
|
bitfld.long 0x00 24. "B216,B216" "0,1"
|
|
bitfld.long 0x00 23. "B215,B215" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B214,B214" "0,1"
|
|
bitfld.long 0x00 21. "B213,B213" "0,1"
|
|
bitfld.long 0x00 20. "B212,B212" "0,1"
|
|
bitfld.long 0x00 19. "B211,B211" "0,1"
|
|
bitfld.long 0x00 18. "B210,B210" "0,1"
|
|
bitfld.long 0x00 17. "B209,B209" "0,1"
|
|
bitfld.long 0x00 16. "B208,B208" "0,1"
|
|
bitfld.long 0x00 15. "B207,B207" "0,1"
|
|
bitfld.long 0x00 14. "B206,B206" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B205,B205" "0,1"
|
|
bitfld.long 0x00 12. "B204,B204" "0,1"
|
|
bitfld.long 0x00 11. "B203,B203" "0,1"
|
|
bitfld.long 0x00 10. "B202,B202" "0,1"
|
|
bitfld.long 0x00 9. "B201,B201" "0,1"
|
|
bitfld.long 0x00 8. "B200,B200" "0,1"
|
|
bitfld.long 0x00 7. "B199,B199" "0,1"
|
|
bitfld.long 0x00 6. "B198,B198" "0,1"
|
|
bitfld.long 0x00 5. "B197,B197" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B196,B196" "0,1"
|
|
bitfld.long 0x00 3. "B195,B195" "0,1"
|
|
bitfld.long 0x00 2. "B194,B194" "0,1"
|
|
bitfld.long 0x00 1. "B193,B193" "0,1"
|
|
bitfld.long 0x00 0. "B192,B192" "0,1"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR7,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B255,B255" "0,1"
|
|
bitfld.long 0x00 30. "B254,B254" "0,1"
|
|
bitfld.long 0x00 29. "B253,B253" "0,1"
|
|
bitfld.long 0x00 28. "B252,B252" "0,1"
|
|
bitfld.long 0x00 27. "B251,B251" "0,1"
|
|
bitfld.long 0x00 26. "B250,B250" "0,1"
|
|
bitfld.long 0x00 25. "B249,B249" "0,1"
|
|
bitfld.long 0x00 24. "B248,B248" "0,1"
|
|
bitfld.long 0x00 23. "B247,B247" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B246,B246" "0,1"
|
|
bitfld.long 0x00 21. "B245,B245" "0,1"
|
|
bitfld.long 0x00 20. "B244,B244" "0,1"
|
|
bitfld.long 0x00 19. "B243,B243" "0,1"
|
|
bitfld.long 0x00 18. "B242,B242" "0,1"
|
|
bitfld.long 0x00 17. "B241,B241" "0,1"
|
|
bitfld.long 0x00 16. "B240,B240" "0,1"
|
|
bitfld.long 0x00 15. "B239,B239" "0,1"
|
|
bitfld.long 0x00 14. "B238,B238" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B237,B237" "0,1"
|
|
bitfld.long 0x00 12. "B236,B236" "0,1"
|
|
bitfld.long 0x00 11. "B235,B235" "0,1"
|
|
bitfld.long 0x00 10. "B234,B234" "0,1"
|
|
bitfld.long 0x00 9. "B233,B233" "0,1"
|
|
bitfld.long 0x00 8. "B232,B232" "0,1"
|
|
bitfld.long 0x00 7. "B231,B231" "0,1"
|
|
bitfld.long 0x00 6. "B230,B230" "0,1"
|
|
bitfld.long 0x00 5. "B229,B229" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B228,B228" "0,1"
|
|
bitfld.long 0x00 3. "B227,B227" "0,1"
|
|
bitfld.long 0x00 2. "B226,B226" "0,1"
|
|
bitfld.long 0x00 1. "B225,B225" "0,1"
|
|
bitfld.long 0x00 0. "B224,B224" "0,1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "MPCBB2_VCTR8,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B287,B287" "0,1"
|
|
bitfld.long 0x00 30. "B286,B286" "0,1"
|
|
bitfld.long 0x00 29. "B285,B285" "0,1"
|
|
bitfld.long 0x00 28. "B284,B284" "0,1"
|
|
bitfld.long 0x00 27. "B283,B283" "0,1"
|
|
bitfld.long 0x00 26. "B282,B282" "0,1"
|
|
bitfld.long 0x00 25. "B281,B281" "0,1"
|
|
bitfld.long 0x00 24. "B280,B280" "0,1"
|
|
bitfld.long 0x00 23. "B279,B279" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B278,B278" "0,1"
|
|
bitfld.long 0x00 21. "B277,B277" "0,1"
|
|
bitfld.long 0x00 20. "B276,B276" "0,1"
|
|
bitfld.long 0x00 19. "B275,B275" "0,1"
|
|
bitfld.long 0x00 18. "B274,B274" "0,1"
|
|
bitfld.long 0x00 17. "B273,B273" "0,1"
|
|
bitfld.long 0x00 16. "B272,B272" "0,1"
|
|
bitfld.long 0x00 15. "B271,B271" "0,1"
|
|
bitfld.long 0x00 14. "B270,B270" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B269,B269" "0,1"
|
|
bitfld.long 0x00 12. "B268,B268" "0,1"
|
|
bitfld.long 0x00 11. "B267,B267" "0,1"
|
|
bitfld.long 0x00 10. "B266,B266" "0,1"
|
|
bitfld.long 0x00 9. "B265,B265" "0,1"
|
|
bitfld.long 0x00 8. "B264,B264" "0,1"
|
|
bitfld.long 0x00 7. "B263,B263" "0,1"
|
|
bitfld.long 0x00 6. "B262,B262" "0,1"
|
|
bitfld.long 0x00 5. "B261,B261" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B260,B260" "0,1"
|
|
bitfld.long 0x00 3. "B259,B259" "0,1"
|
|
bitfld.long 0x00 2. "B258,B258" "0,1"
|
|
bitfld.long 0x00 1. "B257,B257" "0,1"
|
|
bitfld.long 0x00 0. "B256,B256" "0,1"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MPCBB2_VCTR9,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B319,B319" "0,1"
|
|
bitfld.long 0x00 30. "B318,B318" "0,1"
|
|
bitfld.long 0x00 29. "B317,B317" "0,1"
|
|
bitfld.long 0x00 28. "B316,B316" "0,1"
|
|
bitfld.long 0x00 27. "B315,B315" "0,1"
|
|
bitfld.long 0x00 26. "B314,B314" "0,1"
|
|
bitfld.long 0x00 25. "B313,B313" "0,1"
|
|
bitfld.long 0x00 24. "B312,B312" "0,1"
|
|
bitfld.long 0x00 23. "B311,B311" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B310,B310" "0,1"
|
|
bitfld.long 0x00 21. "B309,B309" "0,1"
|
|
bitfld.long 0x00 20. "B308,B308" "0,1"
|
|
bitfld.long 0x00 19. "B307,B307" "0,1"
|
|
bitfld.long 0x00 18. "B306,B306" "0,1"
|
|
bitfld.long 0x00 17. "B305,B305" "0,1"
|
|
bitfld.long 0x00 16. "B304,B304" "0,1"
|
|
bitfld.long 0x00 15. "B303,B303" "0,1"
|
|
bitfld.long 0x00 14. "B302,B302" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B301,B301" "0,1"
|
|
bitfld.long 0x00 12. "B300,B300" "0,1"
|
|
bitfld.long 0x00 11. "B299,B299" "0,1"
|
|
bitfld.long 0x00 10. "B298,B298" "0,1"
|
|
bitfld.long 0x00 9. "B297,B297" "0,1"
|
|
bitfld.long 0x00 8. "B296,B296" "0,1"
|
|
bitfld.long 0x00 7. "B295,B295" "0,1"
|
|
bitfld.long 0x00 6. "B294,B294" "0,1"
|
|
bitfld.long 0x00 5. "B293,B293" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B292,B292" "0,1"
|
|
bitfld.long 0x00 3. "B291,B291" "0,1"
|
|
bitfld.long 0x00 2. "B290,B290" "0,1"
|
|
bitfld.long 0x00 1. "B289,B289" "0,1"
|
|
bitfld.long 0x00 0. "B288,B288" "0,1"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "MPCBB2_VCTR10,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B351,B351" "0,1"
|
|
bitfld.long 0x00 30. "B350,B350" "0,1"
|
|
bitfld.long 0x00 29. "B349,B349" "0,1"
|
|
bitfld.long 0x00 28. "B348,B348" "0,1"
|
|
bitfld.long 0x00 27. "B347,B347" "0,1"
|
|
bitfld.long 0x00 26. "B346,B346" "0,1"
|
|
bitfld.long 0x00 25. "B345,B345" "0,1"
|
|
bitfld.long 0x00 24. "B344,B344" "0,1"
|
|
bitfld.long 0x00 23. "B343,B343" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B342,B342" "0,1"
|
|
bitfld.long 0x00 21. "B341,B341" "0,1"
|
|
bitfld.long 0x00 20. "B340,B340" "0,1"
|
|
bitfld.long 0x00 19. "B339,B339" "0,1"
|
|
bitfld.long 0x00 18. "B338,B338" "0,1"
|
|
bitfld.long 0x00 17. "B337,B337" "0,1"
|
|
bitfld.long 0x00 16. "B336,B336" "0,1"
|
|
bitfld.long 0x00 15. "B335,B335" "0,1"
|
|
bitfld.long 0x00 14. "B334,B334" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B333,B333" "0,1"
|
|
bitfld.long 0x00 12. "B332,B332" "0,1"
|
|
bitfld.long 0x00 11. "B331,B331" "0,1"
|
|
bitfld.long 0x00 10. "B330,B330" "0,1"
|
|
bitfld.long 0x00 9. "B329,B329" "0,1"
|
|
bitfld.long 0x00 8. "B328,B328" "0,1"
|
|
bitfld.long 0x00 7. "B327,B327" "0,1"
|
|
bitfld.long 0x00 6. "B326,B326" "0,1"
|
|
bitfld.long 0x00 5. "B325,B325" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B324,B324" "0,1"
|
|
bitfld.long 0x00 3. "B323,B323" "0,1"
|
|
bitfld.long 0x00 2. "B322,B322" "0,1"
|
|
bitfld.long 0x00 1. "B321,B321" "0,1"
|
|
bitfld.long 0x00 0. "B320,B320" "0,1"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR11,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B383,B383" "0,1"
|
|
bitfld.long 0x00 30. "B382,B382" "0,1"
|
|
bitfld.long 0x00 29. "B381,B381" "0,1"
|
|
bitfld.long 0x00 28. "B380,B380" "0,1"
|
|
bitfld.long 0x00 27. "B379,B379" "0,1"
|
|
bitfld.long 0x00 26. "B378,B378" "0,1"
|
|
bitfld.long 0x00 25. "B377,B377" "0,1"
|
|
bitfld.long 0x00 24. "B376,B376" "0,1"
|
|
bitfld.long 0x00 23. "B375,B375" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B374,B374" "0,1"
|
|
bitfld.long 0x00 21. "B373,B373" "0,1"
|
|
bitfld.long 0x00 20. "B372,B372" "0,1"
|
|
bitfld.long 0x00 19. "B371,B371" "0,1"
|
|
bitfld.long 0x00 18. "B370,B370" "0,1"
|
|
bitfld.long 0x00 17. "B369,B369" "0,1"
|
|
bitfld.long 0x00 16. "B368,B368" "0,1"
|
|
bitfld.long 0x00 15. "B367,B367" "0,1"
|
|
bitfld.long 0x00 14. "B366,B366" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B365,B365" "0,1"
|
|
bitfld.long 0x00 12. "B364,B364" "0,1"
|
|
bitfld.long 0x00 11. "B363,B363" "0,1"
|
|
bitfld.long 0x00 10. "B362,B362" "0,1"
|
|
bitfld.long 0x00 9. "B361,B361" "0,1"
|
|
bitfld.long 0x00 8. "B360,B360" "0,1"
|
|
bitfld.long 0x00 7. "B359,B359" "0,1"
|
|
bitfld.long 0x00 6. "B358,B358" "0,1"
|
|
bitfld.long 0x00 5. "B357,B357" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B356,B356" "0,1"
|
|
bitfld.long 0x00 3. "B355,B355" "0,1"
|
|
bitfld.long 0x00 2. "B354,B354" "0,1"
|
|
bitfld.long 0x00 1. "B353,B353" "0,1"
|
|
bitfld.long 0x00 0. "B352,B352" "0,1"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "MPCBB2_VCTR12,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B415,B415" "0,1"
|
|
bitfld.long 0x00 30. "B414,B414" "0,1"
|
|
bitfld.long 0x00 29. "B413,B413" "0,1"
|
|
bitfld.long 0x00 28. "B412,B412" "0,1"
|
|
bitfld.long 0x00 27. "B411,B411" "0,1"
|
|
bitfld.long 0x00 26. "B410,B410" "0,1"
|
|
bitfld.long 0x00 25. "B409,B409" "0,1"
|
|
bitfld.long 0x00 24. "B408,B408" "0,1"
|
|
bitfld.long 0x00 23. "B407,B407" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B406,B406" "0,1"
|
|
bitfld.long 0x00 21. "B405,B405" "0,1"
|
|
bitfld.long 0x00 20. "B404,B404" "0,1"
|
|
bitfld.long 0x00 19. "B403,B403" "0,1"
|
|
bitfld.long 0x00 18. "B402,B402" "0,1"
|
|
bitfld.long 0x00 17. "B401,B401" "0,1"
|
|
bitfld.long 0x00 16. "B400,B400" "0,1"
|
|
bitfld.long 0x00 15. "B399,B399" "0,1"
|
|
bitfld.long 0x00 14. "B398,B398" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B397,B397" "0,1"
|
|
bitfld.long 0x00 12. "B396,B396" "0,1"
|
|
bitfld.long 0x00 11. "B395,B395" "0,1"
|
|
bitfld.long 0x00 10. "B394,B394" "0,1"
|
|
bitfld.long 0x00 9. "B393,B393" "0,1"
|
|
bitfld.long 0x00 8. "B392,B392" "0,1"
|
|
bitfld.long 0x00 7. "B391,B391" "0,1"
|
|
bitfld.long 0x00 6. "B390,B390" "0,1"
|
|
bitfld.long 0x00 5. "B389,B389" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B388,B388" "0,1"
|
|
bitfld.long 0x00 3. "B387,B387" "0,1"
|
|
bitfld.long 0x00 2. "B386,B386" "0,1"
|
|
bitfld.long 0x00 1. "B385,B385" "0,1"
|
|
bitfld.long 0x00 0. "B384,B384" "0,1"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "MPCBB2_VCTR13,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B447,B447" "0,1"
|
|
bitfld.long 0x00 30. "B446,B446" "0,1"
|
|
bitfld.long 0x00 29. "B445,B445" "0,1"
|
|
bitfld.long 0x00 28. "B444,B444" "0,1"
|
|
bitfld.long 0x00 27. "B443,B443" "0,1"
|
|
bitfld.long 0x00 26. "B442,B442" "0,1"
|
|
bitfld.long 0x00 25. "B441,B441" "0,1"
|
|
bitfld.long 0x00 24. "B440,B440" "0,1"
|
|
bitfld.long 0x00 23. "B439,B439" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B438,B438" "0,1"
|
|
bitfld.long 0x00 21. "B437,B437" "0,1"
|
|
bitfld.long 0x00 20. "B436,B436" "0,1"
|
|
bitfld.long 0x00 19. "B435,B435" "0,1"
|
|
bitfld.long 0x00 18. "B434,B434" "0,1"
|
|
bitfld.long 0x00 17. "B433,B433" "0,1"
|
|
bitfld.long 0x00 16. "B432,B432" "0,1"
|
|
bitfld.long 0x00 15. "B431,B431" "0,1"
|
|
bitfld.long 0x00 14. "B430,B430" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B429,B429" "0,1"
|
|
bitfld.long 0x00 12. "B428,B428" "0,1"
|
|
bitfld.long 0x00 11. "B427,B427" "0,1"
|
|
bitfld.long 0x00 10. "B426,B426" "0,1"
|
|
bitfld.long 0x00 9. "B425,B425" "0,1"
|
|
bitfld.long 0x00 8. "B424,B424" "0,1"
|
|
bitfld.long 0x00 7. "B423,B423" "0,1"
|
|
bitfld.long 0x00 6. "B422,B422" "0,1"
|
|
bitfld.long 0x00 5. "B421,B421" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B420,B420" "0,1"
|
|
bitfld.long 0x00 3. "B419,B419" "0,1"
|
|
bitfld.long 0x00 2. "B418,B418" "0,1"
|
|
bitfld.long 0x00 1. "B417,B417" "0,1"
|
|
bitfld.long 0x00 0. "B416,B416" "0,1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "MPCBB2_VCTR14,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B479,B479" "0,1"
|
|
bitfld.long 0x00 30. "B478,B478" "0,1"
|
|
bitfld.long 0x00 29. "B477,B477" "0,1"
|
|
bitfld.long 0x00 28. "B476,B476" "0,1"
|
|
bitfld.long 0x00 27. "B475,B475" "0,1"
|
|
bitfld.long 0x00 26. "B474,B474" "0,1"
|
|
bitfld.long 0x00 25. "B473,B473" "0,1"
|
|
bitfld.long 0x00 24. "B472,B472" "0,1"
|
|
bitfld.long 0x00 23. "B471,B471" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B470,B470" "0,1"
|
|
bitfld.long 0x00 21. "B469,B469" "0,1"
|
|
bitfld.long 0x00 20. "B468,B468" "0,1"
|
|
bitfld.long 0x00 19. "B467,B467" "0,1"
|
|
bitfld.long 0x00 18. "B466,B466" "0,1"
|
|
bitfld.long 0x00 17. "B465,B465" "0,1"
|
|
bitfld.long 0x00 16. "B464,B464" "0,1"
|
|
bitfld.long 0x00 15. "B463,B463" "0,1"
|
|
bitfld.long 0x00 14. "B462,B462" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B461,B461" "0,1"
|
|
bitfld.long 0x00 12. "B460,B460" "0,1"
|
|
bitfld.long 0x00 11. "B459,B459" "0,1"
|
|
bitfld.long 0x00 10. "B458,B458" "0,1"
|
|
bitfld.long 0x00 9. "B457,B457" "0,1"
|
|
bitfld.long 0x00 8. "B456,B456" "0,1"
|
|
bitfld.long 0x00 7. "B455,B455" "0,1"
|
|
bitfld.long 0x00 6. "B454,B454" "0,1"
|
|
bitfld.long 0x00 5. "B453,B453" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B452,B452" "0,1"
|
|
bitfld.long 0x00 3. "B451,B451" "0,1"
|
|
bitfld.long 0x00 2. "B450,B450" "0,1"
|
|
bitfld.long 0x00 1. "B449,B449" "0,1"
|
|
bitfld.long 0x00 0. "B448,B448" "0,1"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR15,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B511,B511" "0,1"
|
|
bitfld.long 0x00 30. "B510,B510" "0,1"
|
|
bitfld.long 0x00 29. "B509,B509" "0,1"
|
|
bitfld.long 0x00 28. "B508,B508" "0,1"
|
|
bitfld.long 0x00 27. "B507,B507" "0,1"
|
|
bitfld.long 0x00 26. "B506,B506" "0,1"
|
|
bitfld.long 0x00 25. "B505,B505" "0,1"
|
|
bitfld.long 0x00 24. "B504,B504" "0,1"
|
|
bitfld.long 0x00 23. "B503,B503" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B502,B502" "0,1"
|
|
bitfld.long 0x00 21. "B501,B501" "0,1"
|
|
bitfld.long 0x00 20. "B500,B500" "0,1"
|
|
bitfld.long 0x00 19. "B499,B499" "0,1"
|
|
bitfld.long 0x00 18. "B498,B498" "0,1"
|
|
bitfld.long 0x00 17. "B497,B497" "0,1"
|
|
bitfld.long 0x00 16. "B496,B496" "0,1"
|
|
bitfld.long 0x00 15. "B495,B495" "0,1"
|
|
bitfld.long 0x00 14. "B494,B494" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B493,B493" "0,1"
|
|
bitfld.long 0x00 12. "B492,B492" "0,1"
|
|
bitfld.long 0x00 11. "B491,B491" "0,1"
|
|
bitfld.long 0x00 10. "B490,B490" "0,1"
|
|
bitfld.long 0x00 9. "B489,B489" "0,1"
|
|
bitfld.long 0x00 8. "B488,B488" "0,1"
|
|
bitfld.long 0x00 7. "B487,B487" "0,1"
|
|
bitfld.long 0x00 6. "B486,B486" "0,1"
|
|
bitfld.long 0x00 5. "B485,B485" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B484,B484" "0,1"
|
|
bitfld.long 0x00 3. "B483,B483" "0,1"
|
|
bitfld.long 0x00 2. "B482,B482" "0,1"
|
|
bitfld.long 0x00 1. "B481,B481" "0,1"
|
|
bitfld.long 0x00 0. "B480,B480" "0,1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "MPCBB2_VCTR16,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B543,B543" "0,1"
|
|
bitfld.long 0x00 30. "B542,B542" "0,1"
|
|
bitfld.long 0x00 29. "B541,B541" "0,1"
|
|
bitfld.long 0x00 28. "B540,B540" "0,1"
|
|
bitfld.long 0x00 27. "B539,B539" "0,1"
|
|
bitfld.long 0x00 26. "B538,B538" "0,1"
|
|
bitfld.long 0x00 25. "B537,B537" "0,1"
|
|
bitfld.long 0x00 24. "B536,B536" "0,1"
|
|
bitfld.long 0x00 23. "B535,B535" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B534,B534" "0,1"
|
|
bitfld.long 0x00 21. "B533,B533" "0,1"
|
|
bitfld.long 0x00 20. "B532,B532" "0,1"
|
|
bitfld.long 0x00 19. "B531,B531" "0,1"
|
|
bitfld.long 0x00 18. "B530,B530" "0,1"
|
|
bitfld.long 0x00 17. "B529,B529" "0,1"
|
|
bitfld.long 0x00 16. "B528,B528" "0,1"
|
|
bitfld.long 0x00 15. "B527,B527" "0,1"
|
|
bitfld.long 0x00 14. "B526,B526" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B525,B525" "0,1"
|
|
bitfld.long 0x00 12. "B524,B524" "0,1"
|
|
bitfld.long 0x00 11. "B523,B523" "0,1"
|
|
bitfld.long 0x00 10. "B522,B522" "0,1"
|
|
bitfld.long 0x00 9. "B521,B521" "0,1"
|
|
bitfld.long 0x00 8. "B520,B520" "0,1"
|
|
bitfld.long 0x00 7. "B519,B519" "0,1"
|
|
bitfld.long 0x00 6. "B518,B518" "0,1"
|
|
bitfld.long 0x00 5. "B517,B517" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B516,B516" "0,1"
|
|
bitfld.long 0x00 3. "B515,B515" "0,1"
|
|
bitfld.long 0x00 2. "B514,B514" "0,1"
|
|
bitfld.long 0x00 1. "B513,B513" "0,1"
|
|
bitfld.long 0x00 0. "B512,B512" "0,1"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "MPCBB2_VCTR17,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B575,B575" "0,1"
|
|
bitfld.long 0x00 30. "B574,B574" "0,1"
|
|
bitfld.long 0x00 29. "B573,B573" "0,1"
|
|
bitfld.long 0x00 28. "B572,B572" "0,1"
|
|
bitfld.long 0x00 27. "B571,B571" "0,1"
|
|
bitfld.long 0x00 26. "B570,B570" "0,1"
|
|
bitfld.long 0x00 25. "B569,B569" "0,1"
|
|
bitfld.long 0x00 24. "B568,B568" "0,1"
|
|
bitfld.long 0x00 23. "B567,B567" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B566,B566" "0,1"
|
|
bitfld.long 0x00 21. "B565,B565" "0,1"
|
|
bitfld.long 0x00 20. "B564,B564" "0,1"
|
|
bitfld.long 0x00 19. "B563,B563" "0,1"
|
|
bitfld.long 0x00 18. "B562,B562" "0,1"
|
|
bitfld.long 0x00 17. "B561,B561" "0,1"
|
|
bitfld.long 0x00 16. "B560,B560" "0,1"
|
|
bitfld.long 0x00 15. "B559,B559" "0,1"
|
|
bitfld.long 0x00 14. "B558,B558" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B557,B557" "0,1"
|
|
bitfld.long 0x00 12. "B556,B556" "0,1"
|
|
bitfld.long 0x00 11. "B555,B555" "0,1"
|
|
bitfld.long 0x00 10. "B554,B554" "0,1"
|
|
bitfld.long 0x00 9. "B553,B553" "0,1"
|
|
bitfld.long 0x00 8. "B552,B552" "0,1"
|
|
bitfld.long 0x00 7. "B551,B551" "0,1"
|
|
bitfld.long 0x00 6. "B550,B550" "0,1"
|
|
bitfld.long 0x00 5. "B549,B549" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B548,B548" "0,1"
|
|
bitfld.long 0x00 3. "B547,B547" "0,1"
|
|
bitfld.long 0x00 2. "B546,B546" "0,1"
|
|
bitfld.long 0x00 1. "B545,B545" "0,1"
|
|
bitfld.long 0x00 0. "B544,B544" "0,1"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "MPCBB2_VCTR18,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B607,B607" "0,1"
|
|
bitfld.long 0x00 30. "B606,B606" "0,1"
|
|
bitfld.long 0x00 29. "B605,B605" "0,1"
|
|
bitfld.long 0x00 28. "B604,B604" "0,1"
|
|
bitfld.long 0x00 27. "B603,B603" "0,1"
|
|
bitfld.long 0x00 26. "B602,B602" "0,1"
|
|
bitfld.long 0x00 25. "B601,B601" "0,1"
|
|
bitfld.long 0x00 24. "B600,B600" "0,1"
|
|
bitfld.long 0x00 23. "B599,B599" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B598,B598" "0,1"
|
|
bitfld.long 0x00 21. "B597,B597" "0,1"
|
|
bitfld.long 0x00 20. "B596,B596" "0,1"
|
|
bitfld.long 0x00 19. "B595,B595" "0,1"
|
|
bitfld.long 0x00 18. "B594,B594" "0,1"
|
|
bitfld.long 0x00 17. "B593,B593" "0,1"
|
|
bitfld.long 0x00 16. "B592,B592" "0,1"
|
|
bitfld.long 0x00 15. "B591,B591" "0,1"
|
|
bitfld.long 0x00 14. "B590,B590" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B589,B589" "0,1"
|
|
bitfld.long 0x00 12. "B588,B588" "0,1"
|
|
bitfld.long 0x00 11. "B587,B587" "0,1"
|
|
bitfld.long 0x00 10. "B586,B586" "0,1"
|
|
bitfld.long 0x00 9. "B585,B585" "0,1"
|
|
bitfld.long 0x00 8. "B584,B584" "0,1"
|
|
bitfld.long 0x00 7. "B583,B583" "0,1"
|
|
bitfld.long 0x00 6. "B582,B582" "0,1"
|
|
bitfld.long 0x00 5. "B581,B581" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B580,B580" "0,1"
|
|
bitfld.long 0x00 3. "B579,B579" "0,1"
|
|
bitfld.long 0x00 2. "B578,B578" "0,1"
|
|
bitfld.long 0x00 1. "B577,B577" "0,1"
|
|
bitfld.long 0x00 0. "B576,B576" "0,1"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR19,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B639,B639" "0,1"
|
|
bitfld.long 0x00 30. "B638,B638" "0,1"
|
|
bitfld.long 0x00 29. "B637,B637" "0,1"
|
|
bitfld.long 0x00 28. "B636,B636" "0,1"
|
|
bitfld.long 0x00 27. "B635,B635" "0,1"
|
|
bitfld.long 0x00 26. "B634,B634" "0,1"
|
|
bitfld.long 0x00 25. "B633,B633" "0,1"
|
|
bitfld.long 0x00 24. "B632,B632" "0,1"
|
|
bitfld.long 0x00 23. "B631,B631" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B630,B630" "0,1"
|
|
bitfld.long 0x00 21. "B629,B629" "0,1"
|
|
bitfld.long 0x00 20. "B628,B628" "0,1"
|
|
bitfld.long 0x00 19. "B627,B627" "0,1"
|
|
bitfld.long 0x00 18. "B626,B626" "0,1"
|
|
bitfld.long 0x00 17. "B625,B625" "0,1"
|
|
bitfld.long 0x00 16. "B624,B624" "0,1"
|
|
bitfld.long 0x00 15. "B623,B623" "0,1"
|
|
bitfld.long 0x00 14. "B622,B622" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B621,B621" "0,1"
|
|
bitfld.long 0x00 12. "B620,B620" "0,1"
|
|
bitfld.long 0x00 11. "B619,B619" "0,1"
|
|
bitfld.long 0x00 10. "B618,B618" "0,1"
|
|
bitfld.long 0x00 9. "B617,B617" "0,1"
|
|
bitfld.long 0x00 8. "B616,B616" "0,1"
|
|
bitfld.long 0x00 7. "B615,B615" "0,1"
|
|
bitfld.long 0x00 6. "B614,B614" "0,1"
|
|
bitfld.long 0x00 5. "B613,B613" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B612,B612" "0,1"
|
|
bitfld.long 0x00 3. "B611,B611" "0,1"
|
|
bitfld.long 0x00 2. "B610,B610" "0,1"
|
|
bitfld.long 0x00 1. "B609,B609" "0,1"
|
|
bitfld.long 0x00 0. "B608,B608" "0,1"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "MPCBB2_VCTR20,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B671,B671" "0,1"
|
|
bitfld.long 0x00 30. "B670,B670" "0,1"
|
|
bitfld.long 0x00 29. "B669,B669" "0,1"
|
|
bitfld.long 0x00 28. "B668,B668" "0,1"
|
|
bitfld.long 0x00 27. "B667,B667" "0,1"
|
|
bitfld.long 0x00 26. "B666,B666" "0,1"
|
|
bitfld.long 0x00 25. "B665,B665" "0,1"
|
|
bitfld.long 0x00 24. "B664,B664" "0,1"
|
|
bitfld.long 0x00 23. "B663,B663" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B662,B662" "0,1"
|
|
bitfld.long 0x00 21. "B661,B661" "0,1"
|
|
bitfld.long 0x00 20. "B660,B660" "0,1"
|
|
bitfld.long 0x00 19. "B659,B659" "0,1"
|
|
bitfld.long 0x00 18. "B658,B658" "0,1"
|
|
bitfld.long 0x00 17. "B657,B657" "0,1"
|
|
bitfld.long 0x00 16. "B656,B656" "0,1"
|
|
bitfld.long 0x00 15. "B655,B655" "0,1"
|
|
bitfld.long 0x00 14. "B654,B654" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B653,B653" "0,1"
|
|
bitfld.long 0x00 12. "B652,B652" "0,1"
|
|
bitfld.long 0x00 11. "B651,B651" "0,1"
|
|
bitfld.long 0x00 10. "B650,B650" "0,1"
|
|
bitfld.long 0x00 9. "B649,B649" "0,1"
|
|
bitfld.long 0x00 8. "B648,B648" "0,1"
|
|
bitfld.long 0x00 7. "B647,B647" "0,1"
|
|
bitfld.long 0x00 6. "B646,B646" "0,1"
|
|
bitfld.long 0x00 5. "B645,B645" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B644,B644" "0,1"
|
|
bitfld.long 0x00 3. "B643,B643" "0,1"
|
|
bitfld.long 0x00 2. "B642,B642" "0,1"
|
|
bitfld.long 0x00 1. "B641,B641" "0,1"
|
|
bitfld.long 0x00 0. "B640,B640" "0,1"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "MPCBB2_VCTR21,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B703,B703" "0,1"
|
|
bitfld.long 0x00 30. "B702,B702" "0,1"
|
|
bitfld.long 0x00 29. "B701,B701" "0,1"
|
|
bitfld.long 0x00 28. "B700,B700" "0,1"
|
|
bitfld.long 0x00 27. "B699,B699" "0,1"
|
|
bitfld.long 0x00 26. "B698,B698" "0,1"
|
|
bitfld.long 0x00 25. "B697,B697" "0,1"
|
|
bitfld.long 0x00 24. "B696,B696" "0,1"
|
|
bitfld.long 0x00 23. "B695,B695" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B694,B694" "0,1"
|
|
bitfld.long 0x00 21. "B693,B693" "0,1"
|
|
bitfld.long 0x00 20. "B692,B692" "0,1"
|
|
bitfld.long 0x00 19. "B691,B691" "0,1"
|
|
bitfld.long 0x00 18. "B690,B690" "0,1"
|
|
bitfld.long 0x00 17. "B689,B689" "0,1"
|
|
bitfld.long 0x00 16. "B688,B688" "0,1"
|
|
bitfld.long 0x00 15. "B687,B687" "0,1"
|
|
bitfld.long 0x00 14. "B686,B686" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B685,B685" "0,1"
|
|
bitfld.long 0x00 12. "B684,B684" "0,1"
|
|
bitfld.long 0x00 11. "B683,B683" "0,1"
|
|
bitfld.long 0x00 10. "B682,B682" "0,1"
|
|
bitfld.long 0x00 9. "B681,B681" "0,1"
|
|
bitfld.long 0x00 8. "B680,B680" "0,1"
|
|
bitfld.long 0x00 7. "B679,B679" "0,1"
|
|
bitfld.long 0x00 6. "B678,B678" "0,1"
|
|
bitfld.long 0x00 5. "B677,B677" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B676,B676" "0,1"
|
|
bitfld.long 0x00 3. "B675,B675" "0,1"
|
|
bitfld.long 0x00 2. "B674,B674" "0,1"
|
|
bitfld.long 0x00 1. "B673,B673" "0,1"
|
|
bitfld.long 0x00 0. "B672,B672" "0,1"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "MPCBB2_VCTR22,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B735,B735" "0,1"
|
|
bitfld.long 0x00 30. "B734,B734" "0,1"
|
|
bitfld.long 0x00 29. "B733,B733" "0,1"
|
|
bitfld.long 0x00 28. "B732,B732" "0,1"
|
|
bitfld.long 0x00 27. "B731,B731" "0,1"
|
|
bitfld.long 0x00 26. "B730,B730" "0,1"
|
|
bitfld.long 0x00 25. "B729,B729" "0,1"
|
|
bitfld.long 0x00 24. "B728,B728" "0,1"
|
|
bitfld.long 0x00 23. "B727,B727" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B726,B726" "0,1"
|
|
bitfld.long 0x00 21. "B725,B725" "0,1"
|
|
bitfld.long 0x00 20. "B724,B724" "0,1"
|
|
bitfld.long 0x00 19. "B723,B723" "0,1"
|
|
bitfld.long 0x00 18. "B722,B722" "0,1"
|
|
bitfld.long 0x00 17. "B721,B721" "0,1"
|
|
bitfld.long 0x00 16. "B720,B720" "0,1"
|
|
bitfld.long 0x00 15. "B719,B719" "0,1"
|
|
bitfld.long 0x00 14. "B718,B718" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B717,B717" "0,1"
|
|
bitfld.long 0x00 12. "B716,B716" "0,1"
|
|
bitfld.long 0x00 11. "B715,B715" "0,1"
|
|
bitfld.long 0x00 10. "B714,B714" "0,1"
|
|
bitfld.long 0x00 9. "B713,B713" "0,1"
|
|
bitfld.long 0x00 8. "B712,B712" "0,1"
|
|
bitfld.long 0x00 7. "B711,B711" "0,1"
|
|
bitfld.long 0x00 6. "B710,B710" "0,1"
|
|
bitfld.long 0x00 5. "B709,B709" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B708,B708" "0,1"
|
|
bitfld.long 0x00 3. "B707,B707" "0,1"
|
|
bitfld.long 0x00 2. "B706,B706" "0,1"
|
|
bitfld.long 0x00 1. "B705,B705" "0,1"
|
|
bitfld.long 0x00 0. "B704,B704" "0,1"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR23,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B767,B767" "0,1"
|
|
bitfld.long 0x00 30. "B766,B766" "0,1"
|
|
bitfld.long 0x00 29. "B765,B765" "0,1"
|
|
bitfld.long 0x00 28. "B764,B764" "0,1"
|
|
bitfld.long 0x00 27. "B763,B763" "0,1"
|
|
bitfld.long 0x00 26. "B762,B762" "0,1"
|
|
bitfld.long 0x00 25. "B761,B761" "0,1"
|
|
bitfld.long 0x00 24. "B760,B760" "0,1"
|
|
bitfld.long 0x00 23. "B759,B759" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B758,B758" "0,1"
|
|
bitfld.long 0x00 21. "B757,B757" "0,1"
|
|
bitfld.long 0x00 20. "B756,B756" "0,1"
|
|
bitfld.long 0x00 19. "B755,B755" "0,1"
|
|
bitfld.long 0x00 18. "B754,B754" "0,1"
|
|
bitfld.long 0x00 17. "B753,B753" "0,1"
|
|
bitfld.long 0x00 16. "B752,B752" "0,1"
|
|
bitfld.long 0x00 15. "B751,B751" "0,1"
|
|
bitfld.long 0x00 14. "B750,B750" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B749,B749" "0,1"
|
|
bitfld.long 0x00 12. "B748,B748" "0,1"
|
|
bitfld.long 0x00 11. "B747,B747" "0,1"
|
|
bitfld.long 0x00 10. "B746,B746" "0,1"
|
|
bitfld.long 0x00 9. "B745,B745" "0,1"
|
|
bitfld.long 0x00 8. "B744,B744" "0,1"
|
|
bitfld.long 0x00 7. "B743,B743" "0,1"
|
|
bitfld.long 0x00 6. "B742,B742" "0,1"
|
|
bitfld.long 0x00 5. "B741,B741" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B740,B740" "0,1"
|
|
bitfld.long 0x00 3. "B739,B739" "0,1"
|
|
bitfld.long 0x00 2. "B738,B738" "0,1"
|
|
bitfld.long 0x00 1. "B737,B737" "0,1"
|
|
bitfld.long 0x00 0. "B736,B736" "0,1"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "MPCBB2_VCTR24,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B799,B799" "0,1"
|
|
bitfld.long 0x00 30. "B798,B798" "0,1"
|
|
bitfld.long 0x00 29. "B797,B797" "0,1"
|
|
bitfld.long 0x00 28. "B796,B796" "0,1"
|
|
bitfld.long 0x00 27. "B795,B795" "0,1"
|
|
bitfld.long 0x00 26. "B794,B794" "0,1"
|
|
bitfld.long 0x00 25. "B793,B793" "0,1"
|
|
bitfld.long 0x00 24. "B792,B792" "0,1"
|
|
bitfld.long 0x00 23. "B791,B791" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B790,B790" "0,1"
|
|
bitfld.long 0x00 21. "B789,B789" "0,1"
|
|
bitfld.long 0x00 20. "B788,B788" "0,1"
|
|
bitfld.long 0x00 19. "B787,B787" "0,1"
|
|
bitfld.long 0x00 18. "B786,B786" "0,1"
|
|
bitfld.long 0x00 17. "B785,B785" "0,1"
|
|
bitfld.long 0x00 16. "B784,B784" "0,1"
|
|
bitfld.long 0x00 15. "B783,B783" "0,1"
|
|
bitfld.long 0x00 14. "B782,B782" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B781,B781" "0,1"
|
|
bitfld.long 0x00 12. "B780,B780" "0,1"
|
|
bitfld.long 0x00 11. "B779,B779" "0,1"
|
|
bitfld.long 0x00 10. "B778,B778" "0,1"
|
|
bitfld.long 0x00 9. "B777,B777" "0,1"
|
|
bitfld.long 0x00 8. "B776,B776" "0,1"
|
|
bitfld.long 0x00 7. "B775,B775" "0,1"
|
|
bitfld.long 0x00 6. "B774,B774" "0,1"
|
|
bitfld.long 0x00 5. "B773,B773" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B772,B772" "0,1"
|
|
bitfld.long 0x00 3. "B771,B771" "0,1"
|
|
bitfld.long 0x00 2. "B770,B770" "0,1"
|
|
bitfld.long 0x00 1. "B769,B769" "0,1"
|
|
bitfld.long 0x00 0. "B768,B768" "0,1"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "MPCBB2_VCTR25,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B831,B831" "0,1"
|
|
bitfld.long 0x00 30. "B830,B830" "0,1"
|
|
bitfld.long 0x00 29. "B829,B829" "0,1"
|
|
bitfld.long 0x00 28. "B828,B828" "0,1"
|
|
bitfld.long 0x00 27. "B827,B827" "0,1"
|
|
bitfld.long 0x00 26. "B826,B826" "0,1"
|
|
bitfld.long 0x00 25. "B825,B825" "0,1"
|
|
bitfld.long 0x00 24. "B824,B824" "0,1"
|
|
bitfld.long 0x00 23. "B823,B823" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B822,B822" "0,1"
|
|
bitfld.long 0x00 21. "B821,B821" "0,1"
|
|
bitfld.long 0x00 20. "B820,B820" "0,1"
|
|
bitfld.long 0x00 19. "B819,B819" "0,1"
|
|
bitfld.long 0x00 18. "B818,B818" "0,1"
|
|
bitfld.long 0x00 17. "B817,B817" "0,1"
|
|
bitfld.long 0x00 16. "B816,B816" "0,1"
|
|
bitfld.long 0x00 15. "B815,B815" "0,1"
|
|
bitfld.long 0x00 14. "B814,B814" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B813,B813" "0,1"
|
|
bitfld.long 0x00 12. "B812,B812" "0,1"
|
|
bitfld.long 0x00 11. "B811,B811" "0,1"
|
|
bitfld.long 0x00 10. "B810,B810" "0,1"
|
|
bitfld.long 0x00 9. "B809,B809" "0,1"
|
|
bitfld.long 0x00 8. "B808,B808" "0,1"
|
|
bitfld.long 0x00 7. "B807,B807" "0,1"
|
|
bitfld.long 0x00 6. "B806,B806" "0,1"
|
|
bitfld.long 0x00 5. "B805,B805" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B804,B804" "0,1"
|
|
bitfld.long 0x00 3. "B803,B803" "0,1"
|
|
bitfld.long 0x00 2. "B802,B802" "0,1"
|
|
bitfld.long 0x00 1. "B801,B801" "0,1"
|
|
bitfld.long 0x00 0. "B800,B800" "0,1"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "MPCBB2_VCTR26,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B863,B863" "0,1"
|
|
bitfld.long 0x00 30. "B862,B862" "0,1"
|
|
bitfld.long 0x00 29. "B861,B861" "0,1"
|
|
bitfld.long 0x00 28. "B860,B860" "0,1"
|
|
bitfld.long 0x00 27. "B859,B859" "0,1"
|
|
bitfld.long 0x00 26. "B858,B858" "0,1"
|
|
bitfld.long 0x00 25. "B857,B857" "0,1"
|
|
bitfld.long 0x00 24. "B856,B856" "0,1"
|
|
bitfld.long 0x00 23. "B855,B855" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B854,B854" "0,1"
|
|
bitfld.long 0x00 21. "B853,B853" "0,1"
|
|
bitfld.long 0x00 20. "B852,B852" "0,1"
|
|
bitfld.long 0x00 19. "B851,B851" "0,1"
|
|
bitfld.long 0x00 18. "B850,B850" "0,1"
|
|
bitfld.long 0x00 17. "B849,B849" "0,1"
|
|
bitfld.long 0x00 16. "B848,B848" "0,1"
|
|
bitfld.long 0x00 15. "B847,B847" "0,1"
|
|
bitfld.long 0x00 14. "B846,B846" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B845,B845" "0,1"
|
|
bitfld.long 0x00 12. "B844,B844" "0,1"
|
|
bitfld.long 0x00 11. "B843,B843" "0,1"
|
|
bitfld.long 0x00 10. "B842,B842" "0,1"
|
|
bitfld.long 0x00 9. "B841,B841" "0,1"
|
|
bitfld.long 0x00 8. "B840,B840" "0,1"
|
|
bitfld.long 0x00 7. "B839,B839" "0,1"
|
|
bitfld.long 0x00 6. "B838,B838" "0,1"
|
|
bitfld.long 0x00 5. "B837,B837" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B836,B836" "0,1"
|
|
bitfld.long 0x00 3. "B835,B835" "0,1"
|
|
bitfld.long 0x00 2. "B834,B834" "0,1"
|
|
bitfld.long 0x00 1. "B833,B833" "0,1"
|
|
bitfld.long 0x00 0. "B832,B832" "0,1"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR27,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B895,B895" "0,1"
|
|
bitfld.long 0x00 30. "B894,B894" "0,1"
|
|
bitfld.long 0x00 29. "B893,B893" "0,1"
|
|
bitfld.long 0x00 28. "B892,B892" "0,1"
|
|
bitfld.long 0x00 27. "B891,B891" "0,1"
|
|
bitfld.long 0x00 26. "B890,B890" "0,1"
|
|
bitfld.long 0x00 25. "B889,B889" "0,1"
|
|
bitfld.long 0x00 24. "B888,B888" "0,1"
|
|
bitfld.long 0x00 23. "B887,B887" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B886,B886" "0,1"
|
|
bitfld.long 0x00 21. "B885,B885" "0,1"
|
|
bitfld.long 0x00 20. "B884,B884" "0,1"
|
|
bitfld.long 0x00 19. "B883,B883" "0,1"
|
|
bitfld.long 0x00 18. "B882,B882" "0,1"
|
|
bitfld.long 0x00 17. "B881,B881" "0,1"
|
|
bitfld.long 0x00 16. "B880,B880" "0,1"
|
|
bitfld.long 0x00 15. "B879,B879" "0,1"
|
|
bitfld.long 0x00 14. "B878,B878" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B877,B877" "0,1"
|
|
bitfld.long 0x00 12. "B876,B876" "0,1"
|
|
bitfld.long 0x00 11. "B875,B875" "0,1"
|
|
bitfld.long 0x00 10. "B874,B874" "0,1"
|
|
bitfld.long 0x00 9. "B873,B873" "0,1"
|
|
bitfld.long 0x00 8. "B872,B872" "0,1"
|
|
bitfld.long 0x00 7. "B871,B871" "0,1"
|
|
bitfld.long 0x00 6. "B870,B870" "0,1"
|
|
bitfld.long 0x00 5. "B869,B869" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B868,B868" "0,1"
|
|
bitfld.long 0x00 3. "B867,B867" "0,1"
|
|
bitfld.long 0x00 2. "B866,B866" "0,1"
|
|
bitfld.long 0x00 1. "B865,B865" "0,1"
|
|
bitfld.long 0x00 0. "B864,B864" "0,1"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "MPCBB2_VCTR28,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B927,B927" "0,1"
|
|
bitfld.long 0x00 30. "B926,B926" "0,1"
|
|
bitfld.long 0x00 29. "B925,B925" "0,1"
|
|
bitfld.long 0x00 28. "B924,B924" "0,1"
|
|
bitfld.long 0x00 27. "B923,B923" "0,1"
|
|
bitfld.long 0x00 26. "B922,B922" "0,1"
|
|
bitfld.long 0x00 25. "B921,B921" "0,1"
|
|
bitfld.long 0x00 24. "B920,B920" "0,1"
|
|
bitfld.long 0x00 23. "B919,B919" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B918,B918" "0,1"
|
|
bitfld.long 0x00 21. "B917,B917" "0,1"
|
|
bitfld.long 0x00 20. "B916,B916" "0,1"
|
|
bitfld.long 0x00 19. "B915,B915" "0,1"
|
|
bitfld.long 0x00 18. "B914,B914" "0,1"
|
|
bitfld.long 0x00 17. "B913,B913" "0,1"
|
|
bitfld.long 0x00 16. "B912,B912" "0,1"
|
|
bitfld.long 0x00 15. "B911,B911" "0,1"
|
|
bitfld.long 0x00 14. "B910,B910" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B909,B909" "0,1"
|
|
bitfld.long 0x00 12. "B908,B908" "0,1"
|
|
bitfld.long 0x00 11. "B907,B907" "0,1"
|
|
bitfld.long 0x00 10. "B906,B906" "0,1"
|
|
bitfld.long 0x00 9. "B905,B905" "0,1"
|
|
bitfld.long 0x00 8. "B904,B904" "0,1"
|
|
bitfld.long 0x00 7. "B903,B903" "0,1"
|
|
bitfld.long 0x00 6. "B902,B902" "0,1"
|
|
bitfld.long 0x00 5. "B901,B901" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B900,B900" "0,1"
|
|
bitfld.long 0x00 3. "B899,B899" "0,1"
|
|
bitfld.long 0x00 2. "B898,B898" "0,1"
|
|
bitfld.long 0x00 1. "B897,B897" "0,1"
|
|
bitfld.long 0x00 0. "B896,B896" "0,1"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "MPCBB2_VCTR29,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B959,B959" "0,1"
|
|
bitfld.long 0x00 30. "B958,B958" "0,1"
|
|
bitfld.long 0x00 29. "B957,B957" "0,1"
|
|
bitfld.long 0x00 28. "B956,B956" "0,1"
|
|
bitfld.long 0x00 27. "B955,B955" "0,1"
|
|
bitfld.long 0x00 26. "B954,B954" "0,1"
|
|
bitfld.long 0x00 25. "B953,B953" "0,1"
|
|
bitfld.long 0x00 24. "B952,B952" "0,1"
|
|
bitfld.long 0x00 23. "B951,B951" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B950,B950" "0,1"
|
|
bitfld.long 0x00 21. "B949,B949" "0,1"
|
|
bitfld.long 0x00 20. "B948,B948" "0,1"
|
|
bitfld.long 0x00 19. "B947,B947" "0,1"
|
|
bitfld.long 0x00 18. "B946,B946" "0,1"
|
|
bitfld.long 0x00 17. "B945,B945" "0,1"
|
|
bitfld.long 0x00 16. "B944,B944" "0,1"
|
|
bitfld.long 0x00 15. "B943,B943" "0,1"
|
|
bitfld.long 0x00 14. "B942,B942" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B941,B941" "0,1"
|
|
bitfld.long 0x00 12. "B940,B940" "0,1"
|
|
bitfld.long 0x00 11. "B939,B939" "0,1"
|
|
bitfld.long 0x00 10. "B938,B938" "0,1"
|
|
bitfld.long 0x00 9. "B937,B937" "0,1"
|
|
bitfld.long 0x00 8. "B936,B936" "0,1"
|
|
bitfld.long 0x00 7. "B935,B935" "0,1"
|
|
bitfld.long 0x00 6. "B934,B934" "0,1"
|
|
bitfld.long 0x00 5. "B933,B933" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B932,B932" "0,1"
|
|
bitfld.long 0x00 3. "B931,B931" "0,1"
|
|
bitfld.long 0x00 2. "B930,B930" "0,1"
|
|
bitfld.long 0x00 1. "B929,B929" "0,1"
|
|
bitfld.long 0x00 0. "B928,B928" "0,1"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "MPCBB2_VCTR30,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B991,B991" "0,1"
|
|
bitfld.long 0x00 30. "B990,B990" "0,1"
|
|
bitfld.long 0x00 29. "B989,B989" "0,1"
|
|
bitfld.long 0x00 28. "B988,B988" "0,1"
|
|
bitfld.long 0x00 27. "B987,B987" "0,1"
|
|
bitfld.long 0x00 26. "B986,B986" "0,1"
|
|
bitfld.long 0x00 25. "B985,B985" "0,1"
|
|
bitfld.long 0x00 24. "B984,B984" "0,1"
|
|
bitfld.long 0x00 23. "B983,B983" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B982,B982" "0,1"
|
|
bitfld.long 0x00 21. "B981,B981" "0,1"
|
|
bitfld.long 0x00 20. "B980,B980" "0,1"
|
|
bitfld.long 0x00 19. "B979,B979" "0,1"
|
|
bitfld.long 0x00 18. "B978,B978" "0,1"
|
|
bitfld.long 0x00 17. "B977,B977" "0,1"
|
|
bitfld.long 0x00 16. "B976,B976" "0,1"
|
|
bitfld.long 0x00 15. "B975,B975" "0,1"
|
|
bitfld.long 0x00 14. "B974,B974" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B973,B973" "0,1"
|
|
bitfld.long 0x00 12. "B972,B972" "0,1"
|
|
bitfld.long 0x00 11. "B971,B971" "0,1"
|
|
bitfld.long 0x00 10. "B970,B970" "0,1"
|
|
bitfld.long 0x00 9. "B969,B969" "0,1"
|
|
bitfld.long 0x00 8. "B968,B968" "0,1"
|
|
bitfld.long 0x00 7. "B967,B967" "0,1"
|
|
bitfld.long 0x00 6. "B966,B966" "0,1"
|
|
bitfld.long 0x00 5. "B965,B965" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B964,B964" "0,1"
|
|
bitfld.long 0x00 3. "B963,B963" "0,1"
|
|
bitfld.long 0x00 2. "B962,B962" "0,1"
|
|
bitfld.long 0x00 1. "B961,B961" "0,1"
|
|
bitfld.long 0x00 0. "B960,B960" "0,1"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR31,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1023,B1023" "0,1"
|
|
bitfld.long 0x00 30. "B1022,B1022" "0,1"
|
|
bitfld.long 0x00 29. "B1021,B1021" "0,1"
|
|
bitfld.long 0x00 28. "B1020,B1020" "0,1"
|
|
bitfld.long 0x00 27. "B1019,B1019" "0,1"
|
|
bitfld.long 0x00 26. "B1018,B1018" "0,1"
|
|
bitfld.long 0x00 25. "B1017,B1017" "0,1"
|
|
bitfld.long 0x00 24. "B1016,B1016" "0,1"
|
|
bitfld.long 0x00 23. "B1015,B1015" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1014,B1014" "0,1"
|
|
bitfld.long 0x00 21. "B1013,B1013" "0,1"
|
|
bitfld.long 0x00 20. "B1012,B1012" "0,1"
|
|
bitfld.long 0x00 19. "B1011,B1011" "0,1"
|
|
bitfld.long 0x00 18. "B1010,B1010" "0,1"
|
|
bitfld.long 0x00 17. "B1009,B1009" "0,1"
|
|
bitfld.long 0x00 16. "B1008,B1008" "0,1"
|
|
bitfld.long 0x00 15. "B1007,B1007" "0,1"
|
|
bitfld.long 0x00 14. "B1006,B1006" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1005,B1005" "0,1"
|
|
bitfld.long 0x00 12. "B1004,B1004" "0,1"
|
|
bitfld.long 0x00 11. "B1003,B1003" "0,1"
|
|
bitfld.long 0x00 10. "B1002,B1002" "0,1"
|
|
bitfld.long 0x00 9. "B1001,B1001" "0,1"
|
|
bitfld.long 0x00 8. "B1000,B1000" "0,1"
|
|
bitfld.long 0x00 7. "B999,B999" "0,1"
|
|
bitfld.long 0x00 6. "B998,B998" "0,1"
|
|
bitfld.long 0x00 5. "B997,B997" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B996,B996" "0,1"
|
|
bitfld.long 0x00 3. "B995,B995" "0,1"
|
|
bitfld.long 0x00 2. "B994,B994" "0,1"
|
|
bitfld.long 0x00 1. "B993,B993" "0,1"
|
|
bitfld.long 0x00 0. "B992,B992" "0,1"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "MPCBB2_VCTR32,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1055,B1055" "0,1"
|
|
bitfld.long 0x00 30. "B1054,B1054" "0,1"
|
|
bitfld.long 0x00 29. "B1053,B1053" "0,1"
|
|
bitfld.long 0x00 28. "B1052,B1052" "0,1"
|
|
bitfld.long 0x00 27. "B1051,B1051" "0,1"
|
|
bitfld.long 0x00 26. "B1050,B1050" "0,1"
|
|
bitfld.long 0x00 25. "B1049,B1049" "0,1"
|
|
bitfld.long 0x00 24. "B1048,B1048" "0,1"
|
|
bitfld.long 0x00 23. "B1047,B1047" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1046,B1046" "0,1"
|
|
bitfld.long 0x00 21. "B1045,B1045" "0,1"
|
|
bitfld.long 0x00 20. "B1044,B1044" "0,1"
|
|
bitfld.long 0x00 19. "B1043,B1043" "0,1"
|
|
bitfld.long 0x00 18. "B1042,B1042" "0,1"
|
|
bitfld.long 0x00 17. "B1041,B1041" "0,1"
|
|
bitfld.long 0x00 16. "B1040,B1040" "0,1"
|
|
bitfld.long 0x00 15. "B1039,B1039" "0,1"
|
|
bitfld.long 0x00 14. "B1038,B1038" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1037,B1037" "0,1"
|
|
bitfld.long 0x00 12. "B1036,B1036" "0,1"
|
|
bitfld.long 0x00 11. "B1035,B1035" "0,1"
|
|
bitfld.long 0x00 10. "B1034,B1034" "0,1"
|
|
bitfld.long 0x00 9. "B1033,B1033" "0,1"
|
|
bitfld.long 0x00 8. "B1032,B1032" "0,1"
|
|
bitfld.long 0x00 7. "B1031,B1031" "0,1"
|
|
bitfld.long 0x00 6. "B1030,B1030" "0,1"
|
|
bitfld.long 0x00 5. "B1029,B1029" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1028,B1028" "0,1"
|
|
bitfld.long 0x00 3. "B1027,B1027" "0,1"
|
|
bitfld.long 0x00 2. "B1026,B1026" "0,1"
|
|
bitfld.long 0x00 1. "B1025,B1025" "0,1"
|
|
bitfld.long 0x00 0. "B1024,B1024" "0,1"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "MPCBB2_VCTR33,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1087,B1087" "0,1"
|
|
bitfld.long 0x00 30. "B1086,B1086" "0,1"
|
|
bitfld.long 0x00 29. "B1085,B1085" "0,1"
|
|
bitfld.long 0x00 28. "B1084,B1084" "0,1"
|
|
bitfld.long 0x00 27. "B1083,B1083" "0,1"
|
|
bitfld.long 0x00 26. "B1082,B1082" "0,1"
|
|
bitfld.long 0x00 25. "B1081,B1081" "0,1"
|
|
bitfld.long 0x00 24. "B1080,B1080" "0,1"
|
|
bitfld.long 0x00 23. "B1079,B1079" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1078,B1078" "0,1"
|
|
bitfld.long 0x00 21. "B1077,B1077" "0,1"
|
|
bitfld.long 0x00 20. "B1076,B1076" "0,1"
|
|
bitfld.long 0x00 19. "B1075,B1075" "0,1"
|
|
bitfld.long 0x00 18. "B1074,B1074" "0,1"
|
|
bitfld.long 0x00 17. "B1073,B1073" "0,1"
|
|
bitfld.long 0x00 16. "B1072,B1072" "0,1"
|
|
bitfld.long 0x00 15. "B1071,B1071" "0,1"
|
|
bitfld.long 0x00 14. "B1070,B1070" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1069,B1069" "0,1"
|
|
bitfld.long 0x00 12. "B1068,B1068" "0,1"
|
|
bitfld.long 0x00 11. "B1067,B1067" "0,1"
|
|
bitfld.long 0x00 10. "B1066,B1066" "0,1"
|
|
bitfld.long 0x00 9. "B1065,B1065" "0,1"
|
|
bitfld.long 0x00 8. "B1064,B1064" "0,1"
|
|
bitfld.long 0x00 7. "B1063,B1063" "0,1"
|
|
bitfld.long 0x00 6. "B1062,B1062" "0,1"
|
|
bitfld.long 0x00 5. "B1061,B1061" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1060,B1060" "0,1"
|
|
bitfld.long 0x00 3. "B1059,B1059" "0,1"
|
|
bitfld.long 0x00 2. "B1058,B1058" "0,1"
|
|
bitfld.long 0x00 1. "B1057,B1057" "0,1"
|
|
bitfld.long 0x00 0. "B1056,B1056" "0,1"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "MPCBB2_VCTR34,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1119,B1119" "0,1"
|
|
bitfld.long 0x00 30. "B1118,B1118" "0,1"
|
|
bitfld.long 0x00 29. "B1117,B1117" "0,1"
|
|
bitfld.long 0x00 28. "B1116,B1116" "0,1"
|
|
bitfld.long 0x00 27. "B1115,B1115" "0,1"
|
|
bitfld.long 0x00 26. "B1114,B1114" "0,1"
|
|
bitfld.long 0x00 25. "B1113,B1113" "0,1"
|
|
bitfld.long 0x00 24. "B1112,B1112" "0,1"
|
|
bitfld.long 0x00 23. "B1111,B1111" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1110,B1110" "0,1"
|
|
bitfld.long 0x00 21. "B1109,B1109" "0,1"
|
|
bitfld.long 0x00 20. "B1108,B1108" "0,1"
|
|
bitfld.long 0x00 19. "B1107,B1107" "0,1"
|
|
bitfld.long 0x00 18. "B1106,B1106" "0,1"
|
|
bitfld.long 0x00 17. "B1105,B1105" "0,1"
|
|
bitfld.long 0x00 16. "B1104,B1104" "0,1"
|
|
bitfld.long 0x00 15. "B1103,B1103" "0,1"
|
|
bitfld.long 0x00 14. "B1102,B1102" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1101,B1101" "0,1"
|
|
bitfld.long 0x00 12. "B1100,B1100" "0,1"
|
|
bitfld.long 0x00 11. "B1099,B1099" "0,1"
|
|
bitfld.long 0x00 10. "B1098,B1098" "0,1"
|
|
bitfld.long 0x00 9. "B1097,B1097" "0,1"
|
|
bitfld.long 0x00 8. "B1096,B1096" "0,1"
|
|
bitfld.long 0x00 7. "B1095,B1095" "0,1"
|
|
bitfld.long 0x00 6. "B1094,B1094" "0,1"
|
|
bitfld.long 0x00 5. "B1093,B1093" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1092,B1092" "0,1"
|
|
bitfld.long 0x00 3. "B1091,B1091" "0,1"
|
|
bitfld.long 0x00 2. "B1090,B1090" "0,1"
|
|
bitfld.long 0x00 1. "B1089,B1089" "0,1"
|
|
bitfld.long 0x00 0. "B1088,B1088" "0,1"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR35,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1151,B1151" "0,1"
|
|
bitfld.long 0x00 30. "B1150,B1150" "0,1"
|
|
bitfld.long 0x00 29. "B1149,B1149" "0,1"
|
|
bitfld.long 0x00 28. "B1148,B1148" "0,1"
|
|
bitfld.long 0x00 27. "B1147,B1147" "0,1"
|
|
bitfld.long 0x00 26. "B1146,B1146" "0,1"
|
|
bitfld.long 0x00 25. "B1145,B1145" "0,1"
|
|
bitfld.long 0x00 24. "B1144,B1144" "0,1"
|
|
bitfld.long 0x00 23. "B1143,B1143" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1142,B1142" "0,1"
|
|
bitfld.long 0x00 21. "B1141,B1141" "0,1"
|
|
bitfld.long 0x00 20. "B1140,B1140" "0,1"
|
|
bitfld.long 0x00 19. "B1139,B1139" "0,1"
|
|
bitfld.long 0x00 18. "B1138,B1138" "0,1"
|
|
bitfld.long 0x00 17. "B1137,B1137" "0,1"
|
|
bitfld.long 0x00 16. "B1136,B1136" "0,1"
|
|
bitfld.long 0x00 15. "B1135,B1135" "0,1"
|
|
bitfld.long 0x00 14. "B1134,B1134" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1133,B1133" "0,1"
|
|
bitfld.long 0x00 12. "B1132,B1132" "0,1"
|
|
bitfld.long 0x00 11. "B1131,B1131" "0,1"
|
|
bitfld.long 0x00 10. "B1130,B1130" "0,1"
|
|
bitfld.long 0x00 9. "B1129,B1129" "0,1"
|
|
bitfld.long 0x00 8. "B1128,B1128" "0,1"
|
|
bitfld.long 0x00 7. "B1127,B1127" "0,1"
|
|
bitfld.long 0x00 6. "B1126,B1126" "0,1"
|
|
bitfld.long 0x00 5. "B1125,B1125" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1124,B1124" "0,1"
|
|
bitfld.long 0x00 3. "B1123,B1123" "0,1"
|
|
bitfld.long 0x00 2. "B1122,B1122" "0,1"
|
|
bitfld.long 0x00 1. "B1121,B1121" "0,1"
|
|
bitfld.long 0x00 0. "B1120,B1120" "0,1"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "MPCBB2_VCTR36,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1183,B1183" "0,1"
|
|
bitfld.long 0x00 30. "B1182,B1182" "0,1"
|
|
bitfld.long 0x00 29. "B1181,B1181" "0,1"
|
|
bitfld.long 0x00 28. "B1180,B1180" "0,1"
|
|
bitfld.long 0x00 27. "B1179,B1179" "0,1"
|
|
bitfld.long 0x00 26. "B1178,B1178" "0,1"
|
|
bitfld.long 0x00 25. "B1177,B1177" "0,1"
|
|
bitfld.long 0x00 24. "B1176,B1176" "0,1"
|
|
bitfld.long 0x00 23. "B1175,B1175" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1174,B1174" "0,1"
|
|
bitfld.long 0x00 21. "B1173,B1173" "0,1"
|
|
bitfld.long 0x00 20. "B1172,B1172" "0,1"
|
|
bitfld.long 0x00 19. "B1171,B1171" "0,1"
|
|
bitfld.long 0x00 18. "B1170,B1170" "0,1"
|
|
bitfld.long 0x00 17. "B1169,B1169" "0,1"
|
|
bitfld.long 0x00 16. "B1168,B1168" "0,1"
|
|
bitfld.long 0x00 15. "B1167,B1167" "0,1"
|
|
bitfld.long 0x00 14. "B1166,B1166" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1165,B1165" "0,1"
|
|
bitfld.long 0x00 12. "B1164,B1164" "0,1"
|
|
bitfld.long 0x00 11. "B1163,B1163" "0,1"
|
|
bitfld.long 0x00 10. "B1162,B1162" "0,1"
|
|
bitfld.long 0x00 9. "B1161,B1161" "0,1"
|
|
bitfld.long 0x00 8. "B1160,B1160" "0,1"
|
|
bitfld.long 0x00 7. "B1159,B1159" "0,1"
|
|
bitfld.long 0x00 6. "B1158,B1158" "0,1"
|
|
bitfld.long 0x00 5. "B1157,B1157" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1156,B1156" "0,1"
|
|
bitfld.long 0x00 3. "B1155,B1155" "0,1"
|
|
bitfld.long 0x00 2. "B1154,B1154" "0,1"
|
|
bitfld.long 0x00 1. "B1153,B1153" "0,1"
|
|
bitfld.long 0x00 0. "B1152,B1152" "0,1"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "MPCBB2_VCTR37,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1215,B1215" "0,1"
|
|
bitfld.long 0x00 30. "B1214,B1214" "0,1"
|
|
bitfld.long 0x00 29. "B1213,B1213" "0,1"
|
|
bitfld.long 0x00 28. "B1212,B1212" "0,1"
|
|
bitfld.long 0x00 27. "B1211,B1211" "0,1"
|
|
bitfld.long 0x00 26. "B1210,B1210" "0,1"
|
|
bitfld.long 0x00 25. "B1209,B1209" "0,1"
|
|
bitfld.long 0x00 24. "B1208,B1208" "0,1"
|
|
bitfld.long 0x00 23. "B1207,B1207" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1206,B1206" "0,1"
|
|
bitfld.long 0x00 21. "B1205,B1205" "0,1"
|
|
bitfld.long 0x00 20. "B1204,B1204" "0,1"
|
|
bitfld.long 0x00 19. "B1203,B1203" "0,1"
|
|
bitfld.long 0x00 18. "B1202,B1202" "0,1"
|
|
bitfld.long 0x00 17. "B1201,B1201" "0,1"
|
|
bitfld.long 0x00 16. "B1200,B1200" "0,1"
|
|
bitfld.long 0x00 15. "B1199,B1199" "0,1"
|
|
bitfld.long 0x00 14. "B1198,B1198" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1197,B1197" "0,1"
|
|
bitfld.long 0x00 12. "B1196,B1196" "0,1"
|
|
bitfld.long 0x00 11. "B1195,B1195" "0,1"
|
|
bitfld.long 0x00 10. "B1194,B1194" "0,1"
|
|
bitfld.long 0x00 9. "B1193,B1193" "0,1"
|
|
bitfld.long 0x00 8. "B1192,B1192" "0,1"
|
|
bitfld.long 0x00 7. "B1191,B1191" "0,1"
|
|
bitfld.long 0x00 6. "B1190,B1190" "0,1"
|
|
bitfld.long 0x00 5. "B1189,B1189" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1188,B1188" "0,1"
|
|
bitfld.long 0x00 3. "B1187,B1187" "0,1"
|
|
bitfld.long 0x00 2. "B1186,B1186" "0,1"
|
|
bitfld.long 0x00 1. "B1185,B1185" "0,1"
|
|
bitfld.long 0x00 0. "B1184,B1184" "0,1"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "MPCBB2_VCTR38,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1247,B1247" "0,1"
|
|
bitfld.long 0x00 30. "B1246,B1246" "0,1"
|
|
bitfld.long 0x00 29. "B1245,B1245" "0,1"
|
|
bitfld.long 0x00 28. "B1244,B1244" "0,1"
|
|
bitfld.long 0x00 27. "B1243,B1243" "0,1"
|
|
bitfld.long 0x00 26. "B1242,B1242" "0,1"
|
|
bitfld.long 0x00 25. "B1241,B1241" "0,1"
|
|
bitfld.long 0x00 24. "B1240,B1240" "0,1"
|
|
bitfld.long 0x00 23. "B1239,B1239" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1238,B1238" "0,1"
|
|
bitfld.long 0x00 21. "B1237,B1237" "0,1"
|
|
bitfld.long 0x00 20. "B1236,B1236" "0,1"
|
|
bitfld.long 0x00 19. "B1235,B1235" "0,1"
|
|
bitfld.long 0x00 18. "B1234,B1234" "0,1"
|
|
bitfld.long 0x00 17. "B1233,B1233" "0,1"
|
|
bitfld.long 0x00 16. "B1232,B1232" "0,1"
|
|
bitfld.long 0x00 15. "B1231,B1231" "0,1"
|
|
bitfld.long 0x00 14. "B1230,B1230" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1229,B1229" "0,1"
|
|
bitfld.long 0x00 12. "B1228,B1228" "0,1"
|
|
bitfld.long 0x00 11. "B1227,B1227" "0,1"
|
|
bitfld.long 0x00 10. "B1226,B1226" "0,1"
|
|
bitfld.long 0x00 9. "B1225,B1225" "0,1"
|
|
bitfld.long 0x00 8. "B1224,B1224" "0,1"
|
|
bitfld.long 0x00 7. "B1223,B1223" "0,1"
|
|
bitfld.long 0x00 6. "B1222,B1222" "0,1"
|
|
bitfld.long 0x00 5. "B1221,B1221" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1220,B1220" "0,1"
|
|
bitfld.long 0x00 3. "B1219,B1219" "0,1"
|
|
bitfld.long 0x00 2. "B1218,B1218" "0,1"
|
|
bitfld.long 0x00 1. "B1217,B1217" "0,1"
|
|
bitfld.long 0x00 0. "B1216,B1216" "0,1"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR39,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1279,B1279" "0,1"
|
|
bitfld.long 0x00 30. "B1278,B1278" "0,1"
|
|
bitfld.long 0x00 29. "B1277,B1277" "0,1"
|
|
bitfld.long 0x00 28. "B1276,B1276" "0,1"
|
|
bitfld.long 0x00 27. "B1275,B1275" "0,1"
|
|
bitfld.long 0x00 26. "B1274,B1274" "0,1"
|
|
bitfld.long 0x00 25. "B1273,B1273" "0,1"
|
|
bitfld.long 0x00 24. "B1272,B1272" "0,1"
|
|
bitfld.long 0x00 23. "B1271,B1271" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1270,B1270" "0,1"
|
|
bitfld.long 0x00 21. "B1269,B1269" "0,1"
|
|
bitfld.long 0x00 20. "B1268,B1268" "0,1"
|
|
bitfld.long 0x00 19. "B1267,B1267" "0,1"
|
|
bitfld.long 0x00 18. "B1266,B1266" "0,1"
|
|
bitfld.long 0x00 17. "B1265,B1265" "0,1"
|
|
bitfld.long 0x00 16. "B1264,B1264" "0,1"
|
|
bitfld.long 0x00 15. "B1263,B1263" "0,1"
|
|
bitfld.long 0x00 14. "B1262,B1262" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1261,B1261" "0,1"
|
|
bitfld.long 0x00 12. "B1260,B1260" "0,1"
|
|
bitfld.long 0x00 11. "B1259,B1259" "0,1"
|
|
bitfld.long 0x00 10. "B1258,B1258" "0,1"
|
|
bitfld.long 0x00 9. "B1257,B1257" "0,1"
|
|
bitfld.long 0x00 8. "B1256,B1256" "0,1"
|
|
bitfld.long 0x00 7. "B1255,B1255" "0,1"
|
|
bitfld.long 0x00 6. "B1254,B1254" "0,1"
|
|
bitfld.long 0x00 5. "B1253,B1253" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1252,B1252" "0,1"
|
|
bitfld.long 0x00 3. "B1251,B1251" "0,1"
|
|
bitfld.long 0x00 2. "B1250,B1250" "0,1"
|
|
bitfld.long 0x00 1. "B1249,B1249" "0,1"
|
|
bitfld.long 0x00 0. "B1248,B1248" "0,1"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "MPCBB2_VCTR40,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1311,B1311" "0,1"
|
|
bitfld.long 0x00 30. "B1310,B1310" "0,1"
|
|
bitfld.long 0x00 29. "B1309,B1309" "0,1"
|
|
bitfld.long 0x00 28. "B1308,B1308" "0,1"
|
|
bitfld.long 0x00 27. "B1307,B1307" "0,1"
|
|
bitfld.long 0x00 26. "B1306,B1306" "0,1"
|
|
bitfld.long 0x00 25. "B1305,B1305" "0,1"
|
|
bitfld.long 0x00 24. "B1304,B1304" "0,1"
|
|
bitfld.long 0x00 23. "B1303,B1303" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1302,B1302" "0,1"
|
|
bitfld.long 0x00 21. "B1301,B1301" "0,1"
|
|
bitfld.long 0x00 20. "B1300,B1300" "0,1"
|
|
bitfld.long 0x00 19. "B1299,B1299" "0,1"
|
|
bitfld.long 0x00 18. "B1298,B1298" "0,1"
|
|
bitfld.long 0x00 17. "B1297,B1297" "0,1"
|
|
bitfld.long 0x00 16. "B1296,B1296" "0,1"
|
|
bitfld.long 0x00 15. "B1295,B1295" "0,1"
|
|
bitfld.long 0x00 14. "B1294,B1294" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1293,B1293" "0,1"
|
|
bitfld.long 0x00 12. "B1292,B1292" "0,1"
|
|
bitfld.long 0x00 11. "B1291,B1291" "0,1"
|
|
bitfld.long 0x00 10. "B1290,B1290" "0,1"
|
|
bitfld.long 0x00 9. "B1289,B1289" "0,1"
|
|
bitfld.long 0x00 8. "B1288,B1288" "0,1"
|
|
bitfld.long 0x00 7. "B1287,B1287" "0,1"
|
|
bitfld.long 0x00 6. "B1286,B1286" "0,1"
|
|
bitfld.long 0x00 5. "B1285,B1285" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1284,B1284" "0,1"
|
|
bitfld.long 0x00 3. "B1283,B1283" "0,1"
|
|
bitfld.long 0x00 2. "B1282,B1282" "0,1"
|
|
bitfld.long 0x00 1. "B1281,B1281" "0,1"
|
|
bitfld.long 0x00 0. "B1280,B1280" "0,1"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "MPCBB2_VCTR41,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1343,B1343" "0,1"
|
|
bitfld.long 0x00 30. "B1342,B1342" "0,1"
|
|
bitfld.long 0x00 29. "B1341,B1341" "0,1"
|
|
bitfld.long 0x00 28. "B1340,B1340" "0,1"
|
|
bitfld.long 0x00 27. "B1339,B1339" "0,1"
|
|
bitfld.long 0x00 26. "B1338,B1338" "0,1"
|
|
bitfld.long 0x00 25. "B1337,B1337" "0,1"
|
|
bitfld.long 0x00 24. "B1336,B1336" "0,1"
|
|
bitfld.long 0x00 23. "B1335,B1335" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1334,B1334" "0,1"
|
|
bitfld.long 0x00 21. "B1333,B1333" "0,1"
|
|
bitfld.long 0x00 20. "B1332,B1332" "0,1"
|
|
bitfld.long 0x00 19. "B1331,B1331" "0,1"
|
|
bitfld.long 0x00 18. "B1330,B1330" "0,1"
|
|
bitfld.long 0x00 17. "B1329,B1329" "0,1"
|
|
bitfld.long 0x00 16. "B1328,B1328" "0,1"
|
|
bitfld.long 0x00 15. "B1327,B1327" "0,1"
|
|
bitfld.long 0x00 14. "B1326,B1326" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1325,B1325" "0,1"
|
|
bitfld.long 0x00 12. "B1324,B1324" "0,1"
|
|
bitfld.long 0x00 11. "B1323,B1323" "0,1"
|
|
bitfld.long 0x00 10. "B1322,B1322" "0,1"
|
|
bitfld.long 0x00 9. "B1321,B1321" "0,1"
|
|
bitfld.long 0x00 8. "B1320,B1320" "0,1"
|
|
bitfld.long 0x00 7. "B1319,B1319" "0,1"
|
|
bitfld.long 0x00 6. "B1318,B1318" "0,1"
|
|
bitfld.long 0x00 5. "B1317,B1317" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1316,B1316" "0,1"
|
|
bitfld.long 0x00 3. "B1315,B1315" "0,1"
|
|
bitfld.long 0x00 2. "B1314,B1314" "0,1"
|
|
bitfld.long 0x00 1. "B1313,B1313" "0,1"
|
|
bitfld.long 0x00 0. "B1312,B1312" "0,1"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "MPCBB2_VCTR42,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1375,B1375" "0,1"
|
|
bitfld.long 0x00 30. "B1374,B1374" "0,1"
|
|
bitfld.long 0x00 29. "B1373,B1373" "0,1"
|
|
bitfld.long 0x00 28. "B1372,B1372" "0,1"
|
|
bitfld.long 0x00 27. "B1371,B1371" "0,1"
|
|
bitfld.long 0x00 26. "B1370,B1370" "0,1"
|
|
bitfld.long 0x00 25. "B1369,B1369" "0,1"
|
|
bitfld.long 0x00 24. "B1368,B1368" "0,1"
|
|
bitfld.long 0x00 23. "B1367,B1367" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1366,B1366" "0,1"
|
|
bitfld.long 0x00 21. "B1365,B1365" "0,1"
|
|
bitfld.long 0x00 20. "B1364,B1364" "0,1"
|
|
bitfld.long 0x00 19. "B1363,B1363" "0,1"
|
|
bitfld.long 0x00 18. "B1362,B1362" "0,1"
|
|
bitfld.long 0x00 17. "B1361,B1361" "0,1"
|
|
bitfld.long 0x00 16. "B1360,B1360" "0,1"
|
|
bitfld.long 0x00 15. "B1359,B1359" "0,1"
|
|
bitfld.long 0x00 14. "B1358,B1358" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1357,B1357" "0,1"
|
|
bitfld.long 0x00 12. "B1356,B1356" "0,1"
|
|
bitfld.long 0x00 11. "B1355,B1355" "0,1"
|
|
bitfld.long 0x00 10. "B1354,B1354" "0,1"
|
|
bitfld.long 0x00 9. "B1353,B1353" "0,1"
|
|
bitfld.long 0x00 8. "B1352,B1352" "0,1"
|
|
bitfld.long 0x00 7. "B1351,B1351" "0,1"
|
|
bitfld.long 0x00 6. "B1350,B1350" "0,1"
|
|
bitfld.long 0x00 5. "B1349,B1349" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1348,B1348" "0,1"
|
|
bitfld.long 0x00 3. "B1347,B1347" "0,1"
|
|
bitfld.long 0x00 2. "B1346,B1346" "0,1"
|
|
bitfld.long 0x00 1. "B1345,B1345" "0,1"
|
|
bitfld.long 0x00 0. "B1344,B1344" "0,1"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "MPCBB2_VCTR43,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1407,B1407" "0,1"
|
|
bitfld.long 0x00 30. "B1406,B1406" "0,1"
|
|
bitfld.long 0x00 29. "B1405,B1405" "0,1"
|
|
bitfld.long 0x00 28. "B1404,B1404" "0,1"
|
|
bitfld.long 0x00 27. "B1403,B1403" "0,1"
|
|
bitfld.long 0x00 26. "B1402,B1402" "0,1"
|
|
bitfld.long 0x00 25. "B1401,B1401" "0,1"
|
|
bitfld.long 0x00 24. "B1400,B1400" "0,1"
|
|
bitfld.long 0x00 23. "B1399,B1399" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1398,B1398" "0,1"
|
|
bitfld.long 0x00 21. "B1397,B1397" "0,1"
|
|
bitfld.long 0x00 20. "B1396,B1396" "0,1"
|
|
bitfld.long 0x00 19. "B1395,B1395" "0,1"
|
|
bitfld.long 0x00 18. "B1394,B1394" "0,1"
|
|
bitfld.long 0x00 17. "B1393,B1393" "0,1"
|
|
bitfld.long 0x00 16. "B1392,B1392" "0,1"
|
|
bitfld.long 0x00 15. "B1391,B1391" "0,1"
|
|
bitfld.long 0x00 14. "B1390,B1390" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1389,B1389" "0,1"
|
|
bitfld.long 0x00 12. "B1388,B1388" "0,1"
|
|
bitfld.long 0x00 11. "B1387,B1387" "0,1"
|
|
bitfld.long 0x00 10. "B1386,B1386" "0,1"
|
|
bitfld.long 0x00 9. "B1385,B1385" "0,1"
|
|
bitfld.long 0x00 8. "B1384,B1384" "0,1"
|
|
bitfld.long 0x00 7. "B1383,B1383" "0,1"
|
|
bitfld.long 0x00 6. "B1382,B1382" "0,1"
|
|
bitfld.long 0x00 5. "B1381,B1381" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1380,B1380" "0,1"
|
|
bitfld.long 0x00 3. "B1379,B1379" "0,1"
|
|
bitfld.long 0x00 2. "B1378,B1378" "0,1"
|
|
bitfld.long 0x00 1. "B1377,B1377" "0,1"
|
|
bitfld.long 0x00 0. "B1376,B1376" "0,1"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "MPCBB2_VCTR44,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1439,B1439" "0,1"
|
|
bitfld.long 0x00 30. "B1438,B1438" "0,1"
|
|
bitfld.long 0x00 29. "B1437,B1437" "0,1"
|
|
bitfld.long 0x00 28. "B1436,B1436" "0,1"
|
|
bitfld.long 0x00 27. "B1435,B1435" "0,1"
|
|
bitfld.long 0x00 26. "B1434,B1434" "0,1"
|
|
bitfld.long 0x00 25. "B1433,B1433" "0,1"
|
|
bitfld.long 0x00 24. "B1432,B1432" "0,1"
|
|
bitfld.long 0x00 23. "B1431,B1431" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1430,B1430" "0,1"
|
|
bitfld.long 0x00 21. "B1429,B1429" "0,1"
|
|
bitfld.long 0x00 20. "B1428,B1428" "0,1"
|
|
bitfld.long 0x00 19. "B1427,B1427" "0,1"
|
|
bitfld.long 0x00 18. "B1426,B1426" "0,1"
|
|
bitfld.long 0x00 17. "B1425,B1425" "0,1"
|
|
bitfld.long 0x00 16. "B1424,B1424" "0,1"
|
|
bitfld.long 0x00 15. "B1423,B1423" "0,1"
|
|
bitfld.long 0x00 14. "B1422,B1422" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1421,B1421" "0,1"
|
|
bitfld.long 0x00 12. "B1420,B1420" "0,1"
|
|
bitfld.long 0x00 11. "B1419,B1419" "0,1"
|
|
bitfld.long 0x00 10. "B1418,B1418" "0,1"
|
|
bitfld.long 0x00 9. "B1417,B1417" "0,1"
|
|
bitfld.long 0x00 8. "B1416,B1416" "0,1"
|
|
bitfld.long 0x00 7. "B1415,B1415" "0,1"
|
|
bitfld.long 0x00 6. "B1414,B1414" "0,1"
|
|
bitfld.long 0x00 5. "B1413,B1413" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1412,B1412" "0,1"
|
|
bitfld.long 0x00 3. "B1411,B1411" "0,1"
|
|
bitfld.long 0x00 2. "B1410,B1410" "0,1"
|
|
bitfld.long 0x00 1. "B1409,B1409" "0,1"
|
|
bitfld.long 0x00 0. "B1408,B1408" "0,1"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "MPCBB2_VCTR45,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1471,B1471" "0,1"
|
|
bitfld.long 0x00 30. "B1470,B1470" "0,1"
|
|
bitfld.long 0x00 29. "B1469,B1469" "0,1"
|
|
bitfld.long 0x00 28. "B1468,B1468" "0,1"
|
|
bitfld.long 0x00 27. "B1467,B1467" "0,1"
|
|
bitfld.long 0x00 26. "B1466,B1466" "0,1"
|
|
bitfld.long 0x00 25. "B1465,B1465" "0,1"
|
|
bitfld.long 0x00 24. "B1464,B1464" "0,1"
|
|
bitfld.long 0x00 23. "B1463,B1463" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1462,B1462" "0,1"
|
|
bitfld.long 0x00 21. "B1461,B1461" "0,1"
|
|
bitfld.long 0x00 20. "B1460,B1460" "0,1"
|
|
bitfld.long 0x00 19. "B1459,B1459" "0,1"
|
|
bitfld.long 0x00 18. "B1458,B1458" "0,1"
|
|
bitfld.long 0x00 17. "B1457,B1457" "0,1"
|
|
bitfld.long 0x00 16. "B1456,B1456" "0,1"
|
|
bitfld.long 0x00 15. "B1455,B1455" "0,1"
|
|
bitfld.long 0x00 14. "B1454,B1454" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1453,B1453" "0,1"
|
|
bitfld.long 0x00 12. "B1452,B1452" "0,1"
|
|
bitfld.long 0x00 11. "B1451,B1451" "0,1"
|
|
bitfld.long 0x00 10. "B1450,B1450" "0,1"
|
|
bitfld.long 0x00 9. "B1449,B1449" "0,1"
|
|
bitfld.long 0x00 8. "B1448,B1448" "0,1"
|
|
bitfld.long 0x00 7. "B1447,B1447" "0,1"
|
|
bitfld.long 0x00 6. "B1446,B1446" "0,1"
|
|
bitfld.long 0x00 5. "B1445,B1445" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1444,B1444" "0,1"
|
|
bitfld.long 0x00 3. "B1443,B1443" "0,1"
|
|
bitfld.long 0x00 2. "B1442,B1442" "0,1"
|
|
bitfld.long 0x00 1. "B1441,B1441" "0,1"
|
|
bitfld.long 0x00 0. "B1440,B1440" "0,1"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "MPCBB2_VCTR46,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1503,B1503" "0,1"
|
|
bitfld.long 0x00 30. "B1502,B1502" "0,1"
|
|
bitfld.long 0x00 29. "B1501,B1501" "0,1"
|
|
bitfld.long 0x00 28. "B1500,B1500" "0,1"
|
|
bitfld.long 0x00 27. "B1499,B1499" "0,1"
|
|
bitfld.long 0x00 26. "B1498,B1498" "0,1"
|
|
bitfld.long 0x00 25. "B1497,B1497" "0,1"
|
|
bitfld.long 0x00 24. "B1496,B1496" "0,1"
|
|
bitfld.long 0x00 23. "B1495,B1495" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1494,B1494" "0,1"
|
|
bitfld.long 0x00 21. "B1493,B1493" "0,1"
|
|
bitfld.long 0x00 20. "B1492,B1492" "0,1"
|
|
bitfld.long 0x00 19. "B1491,B1491" "0,1"
|
|
bitfld.long 0x00 18. "B1490,B1490" "0,1"
|
|
bitfld.long 0x00 17. "B1489,B1489" "0,1"
|
|
bitfld.long 0x00 16. "B1488,B1488" "0,1"
|
|
bitfld.long 0x00 15. "B1487,B1487" "0,1"
|
|
bitfld.long 0x00 14. "B1486,B1486" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1485,B1485" "0,1"
|
|
bitfld.long 0x00 12. "B1484,B1484" "0,1"
|
|
bitfld.long 0x00 11. "B1483,B1483" "0,1"
|
|
bitfld.long 0x00 10. "B1482,B1482" "0,1"
|
|
bitfld.long 0x00 9. "B1481,B1481" "0,1"
|
|
bitfld.long 0x00 8. "B1480,B1480" "0,1"
|
|
bitfld.long 0x00 7. "B1479,B1479" "0,1"
|
|
bitfld.long 0x00 6. "B1478,B1478" "0,1"
|
|
bitfld.long 0x00 5. "B1477,B1477" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1476,B1476" "0,1"
|
|
bitfld.long 0x00 3. "B1475,B1475" "0,1"
|
|
bitfld.long 0x00 2. "B1474,B1474" "0,1"
|
|
bitfld.long 0x00 1. "B1473,B1473" "0,1"
|
|
bitfld.long 0x00 0. "B1472,B1472" "0,1"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "MPCBB2_VCTR47,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1535,B1535" "0,1"
|
|
bitfld.long 0x00 30. "B1534,B1534" "0,1"
|
|
bitfld.long 0x00 29. "B1533,B1533" "0,1"
|
|
bitfld.long 0x00 28. "B1532,B1532" "0,1"
|
|
bitfld.long 0x00 27. "B1531,B1531" "0,1"
|
|
bitfld.long 0x00 26. "B1530,B1530" "0,1"
|
|
bitfld.long 0x00 25. "B1529,B1529" "0,1"
|
|
bitfld.long 0x00 24. "B1528,B1528" "0,1"
|
|
bitfld.long 0x00 23. "B1527,B1527" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1526,B1526" "0,1"
|
|
bitfld.long 0x00 21. "B1525,B1525" "0,1"
|
|
bitfld.long 0x00 20. "B1524,B1524" "0,1"
|
|
bitfld.long 0x00 19. "B1523,B1523" "0,1"
|
|
bitfld.long 0x00 18. "B1522,B1522" "0,1"
|
|
bitfld.long 0x00 17. "B1521,B1521" "0,1"
|
|
bitfld.long 0x00 16. "B1520,B1520" "0,1"
|
|
bitfld.long 0x00 15. "B1519,B1519" "0,1"
|
|
bitfld.long 0x00 14. "B1518,B1518" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1517,B1517" "0,1"
|
|
bitfld.long 0x00 12. "B1516,B1516" "0,1"
|
|
bitfld.long 0x00 11. "B1515,B1515" "0,1"
|
|
bitfld.long 0x00 10. "B1514,B1514" "0,1"
|
|
bitfld.long 0x00 9. "B1513,B1513" "0,1"
|
|
bitfld.long 0x00 8. "B1512,B1512" "0,1"
|
|
bitfld.long 0x00 7. "B1511,B1511" "0,1"
|
|
bitfld.long 0x00 6. "B1510,B1510" "0,1"
|
|
bitfld.long 0x00 5. "B1509,B1509" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1508,B1508" "0,1"
|
|
bitfld.long 0x00 3. "B1507,B1507" "0,1"
|
|
bitfld.long 0x00 2. "B1506,B1506" "0,1"
|
|
bitfld.long 0x00 1. "B1505,B1505" "0,1"
|
|
bitfld.long 0x00 0. "B1504,B1504" "0,1"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "MPCBB2_VCTR48,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1567,B1567" "0,1"
|
|
bitfld.long 0x00 30. "B1566,B1566" "0,1"
|
|
bitfld.long 0x00 29. "B1565,B1565" "0,1"
|
|
bitfld.long 0x00 28. "B1564,B1564" "0,1"
|
|
bitfld.long 0x00 27. "B1563,B1563" "0,1"
|
|
bitfld.long 0x00 26. "B1562,B1562" "0,1"
|
|
bitfld.long 0x00 25. "B1561,B1561" "0,1"
|
|
bitfld.long 0x00 24. "B1560,B1560" "0,1"
|
|
bitfld.long 0x00 23. "B1559,B1559" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1558,B1558" "0,1"
|
|
bitfld.long 0x00 21. "B1557,B1557" "0,1"
|
|
bitfld.long 0x00 20. "B1556,B1556" "0,1"
|
|
bitfld.long 0x00 19. "B1555,B1555" "0,1"
|
|
bitfld.long 0x00 18. "B1554,B1554" "0,1"
|
|
bitfld.long 0x00 17. "B1553,B1553" "0,1"
|
|
bitfld.long 0x00 16. "B1552,B1552" "0,1"
|
|
bitfld.long 0x00 15. "B1551,B1551" "0,1"
|
|
bitfld.long 0x00 14. "B1550,B1550" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1549,B1549" "0,1"
|
|
bitfld.long 0x00 12. "B1548,B1548" "0,1"
|
|
bitfld.long 0x00 11. "B1547,B1547" "0,1"
|
|
bitfld.long 0x00 10. "B1546,B1546" "0,1"
|
|
bitfld.long 0x00 9. "B1545,B1545" "0,1"
|
|
bitfld.long 0x00 8. "B1544,B1544" "0,1"
|
|
bitfld.long 0x00 7. "B1543,B1543" "0,1"
|
|
bitfld.long 0x00 6. "B1542,B1542" "0,1"
|
|
bitfld.long 0x00 5. "B1541,B1541" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1540,B1540" "0,1"
|
|
bitfld.long 0x00 3. "B1539,B1539" "0,1"
|
|
bitfld.long 0x00 2. "B1538,B1538" "0,1"
|
|
bitfld.long 0x00 1. "B1537,B1537" "0,1"
|
|
bitfld.long 0x00 0. "B1536,B1536" "0,1"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "MPCBB2_VCTR49,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1599,B1599" "0,1"
|
|
bitfld.long 0x00 30. "B1598,B1598" "0,1"
|
|
bitfld.long 0x00 29. "B1597,B1597" "0,1"
|
|
bitfld.long 0x00 28. "B1596,B1596" "0,1"
|
|
bitfld.long 0x00 27. "B1595,B1595" "0,1"
|
|
bitfld.long 0x00 26. "B1594,B1594" "0,1"
|
|
bitfld.long 0x00 25. "B1593,B1593" "0,1"
|
|
bitfld.long 0x00 24. "B1592,B1592" "0,1"
|
|
bitfld.long 0x00 23. "B1591,B1591" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1590,B1590" "0,1"
|
|
bitfld.long 0x00 21. "B1589,B1589" "0,1"
|
|
bitfld.long 0x00 20. "B1588,B1588" "0,1"
|
|
bitfld.long 0x00 19. "B1587,B1587" "0,1"
|
|
bitfld.long 0x00 18. "B1586,B1586" "0,1"
|
|
bitfld.long 0x00 17. "B1585,B1585" "0,1"
|
|
bitfld.long 0x00 16. "B1584,B1584" "0,1"
|
|
bitfld.long 0x00 15. "B1583,B1583" "0,1"
|
|
bitfld.long 0x00 14. "B1582,B1582" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1581,B1581" "0,1"
|
|
bitfld.long 0x00 12. "B1580,B1580" "0,1"
|
|
bitfld.long 0x00 11. "B1579,B1579" "0,1"
|
|
bitfld.long 0x00 10. "B1578,B1578" "0,1"
|
|
bitfld.long 0x00 9. "B1577,B1577" "0,1"
|
|
bitfld.long 0x00 8. "B1576,B1576" "0,1"
|
|
bitfld.long 0x00 7. "B1575,B1575" "0,1"
|
|
bitfld.long 0x00 6. "B1574,B1574" "0,1"
|
|
bitfld.long 0x00 5. "B1573,B1573" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1572,B1572" "0,1"
|
|
bitfld.long 0x00 3. "B1571,B1571" "0,1"
|
|
bitfld.long 0x00 2. "B1570,B1570" "0,1"
|
|
bitfld.long 0x00 1. "B1569,B1569" "0,1"
|
|
bitfld.long 0x00 0. "B1568,B1568" "0,1"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "MPCBB2_VCTR50,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1631,B1631" "0,1"
|
|
bitfld.long 0x00 30. "B1630,B1630" "0,1"
|
|
bitfld.long 0x00 29. "B1629,B1629" "0,1"
|
|
bitfld.long 0x00 28. "B1628,B1628" "0,1"
|
|
bitfld.long 0x00 27. "B1627,B1627" "0,1"
|
|
bitfld.long 0x00 26. "B1626,B1626" "0,1"
|
|
bitfld.long 0x00 25. "B1625,B1625" "0,1"
|
|
bitfld.long 0x00 24. "B1624,B1624" "0,1"
|
|
bitfld.long 0x00 23. "B1623,B1623" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1622,B1622" "0,1"
|
|
bitfld.long 0x00 21. "B1621,B1621" "0,1"
|
|
bitfld.long 0x00 20. "B1620,B1620" "0,1"
|
|
bitfld.long 0x00 19. "B1619,B1619" "0,1"
|
|
bitfld.long 0x00 18. "B1618,B1618" "0,1"
|
|
bitfld.long 0x00 17. "B1617,B1617" "0,1"
|
|
bitfld.long 0x00 16. "B1616,B1616" "0,1"
|
|
bitfld.long 0x00 15. "B1615,B1615" "0,1"
|
|
bitfld.long 0x00 14. "B1614,B1614" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1613,B1613" "0,1"
|
|
bitfld.long 0x00 12. "B1612,B1612" "0,1"
|
|
bitfld.long 0x00 11. "B1611,B1611" "0,1"
|
|
bitfld.long 0x00 10. "B1610,B1610" "0,1"
|
|
bitfld.long 0x00 9. "B1609,B1609" "0,1"
|
|
bitfld.long 0x00 8. "B1608,B1608" "0,1"
|
|
bitfld.long 0x00 7. "B1607,B1607" "0,1"
|
|
bitfld.long 0x00 6. "B1606,B1606" "0,1"
|
|
bitfld.long 0x00 5. "B1605,B1605" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1604,B1604" "0,1"
|
|
bitfld.long 0x00 3. "B1603,B1603" "0,1"
|
|
bitfld.long 0x00 2. "B1602,B1602" "0,1"
|
|
bitfld.long 0x00 1. "B1601,B1601" "0,1"
|
|
bitfld.long 0x00 0. "B1600,B1600" "0,1"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "MPCBB2_VCTR51,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1663,B1663" "0,1"
|
|
bitfld.long 0x00 30. "B1662,B1662" "0,1"
|
|
bitfld.long 0x00 29. "B1661,B1661" "0,1"
|
|
bitfld.long 0x00 28. "B1660,B1660" "0,1"
|
|
bitfld.long 0x00 27. "B1659,B1659" "0,1"
|
|
bitfld.long 0x00 26. "B1658,B1658" "0,1"
|
|
bitfld.long 0x00 25. "B1657,B1657" "0,1"
|
|
bitfld.long 0x00 24. "B1656,B1656" "0,1"
|
|
bitfld.long 0x00 23. "B1655,B1655" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1654,B1654" "0,1"
|
|
bitfld.long 0x00 21. "B1653,B1653" "0,1"
|
|
bitfld.long 0x00 20. "B1652,B1652" "0,1"
|
|
bitfld.long 0x00 19. "B1651,B1651" "0,1"
|
|
bitfld.long 0x00 18. "B1650,B1650" "0,1"
|
|
bitfld.long 0x00 17. "B1649,B1649" "0,1"
|
|
bitfld.long 0x00 16. "B1648,B1648" "0,1"
|
|
bitfld.long 0x00 15. "B1647,B1647" "0,1"
|
|
bitfld.long 0x00 14. "B1646,B1646" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1645,B1645" "0,1"
|
|
bitfld.long 0x00 12. "B1644,B1644" "0,1"
|
|
bitfld.long 0x00 11. "B1643,B1643" "0,1"
|
|
bitfld.long 0x00 10. "B1642,B1642" "0,1"
|
|
bitfld.long 0x00 9. "B1641,B1641" "0,1"
|
|
bitfld.long 0x00 8. "B1640,B1640" "0,1"
|
|
bitfld.long 0x00 7. "B1639,B1639" "0,1"
|
|
bitfld.long 0x00 6. "B1638,B1638" "0,1"
|
|
bitfld.long 0x00 5. "B1637,B1637" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1636,B1636" "0,1"
|
|
bitfld.long 0x00 3. "B1635,B1635" "0,1"
|
|
bitfld.long 0x00 2. "B1634,B1634" "0,1"
|
|
bitfld.long 0x00 1. "B1633,B1633" "0,1"
|
|
bitfld.long 0x00 0. "B1632,B1632" "0,1"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "MPCBB2_VCTR52,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1695,B1695" "0,1"
|
|
bitfld.long 0x00 30. "B1694,B1694" "0,1"
|
|
bitfld.long 0x00 29. "B1693,B1693" "0,1"
|
|
bitfld.long 0x00 28. "B1692,B1692" "0,1"
|
|
bitfld.long 0x00 27. "B1691,B1691" "0,1"
|
|
bitfld.long 0x00 26. "B1690,B1690" "0,1"
|
|
bitfld.long 0x00 25. "B1689,B1689" "0,1"
|
|
bitfld.long 0x00 24. "B1688,B1688" "0,1"
|
|
bitfld.long 0x00 23. "B1687,B1687" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1686,B1686" "0,1"
|
|
bitfld.long 0x00 21. "B1685,B1685" "0,1"
|
|
bitfld.long 0x00 20. "B1684,B1684" "0,1"
|
|
bitfld.long 0x00 19. "B1683,B1683" "0,1"
|
|
bitfld.long 0x00 18. "B1682,B1682" "0,1"
|
|
bitfld.long 0x00 17. "B1681,B1681" "0,1"
|
|
bitfld.long 0x00 16. "B1680,B1680" "0,1"
|
|
bitfld.long 0x00 15. "B1679,B1679" "0,1"
|
|
bitfld.long 0x00 14. "B1678,B1678" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1677,B1677" "0,1"
|
|
bitfld.long 0x00 12. "B1676,B1676" "0,1"
|
|
bitfld.long 0x00 11. "B1675,B1675" "0,1"
|
|
bitfld.long 0x00 10. "B1674,B1674" "0,1"
|
|
bitfld.long 0x00 9. "B1673,B1673" "0,1"
|
|
bitfld.long 0x00 8. "B1672,B1672" "0,1"
|
|
bitfld.long 0x00 7. "B1671,B1671" "0,1"
|
|
bitfld.long 0x00 6. "B1670,B1670" "0,1"
|
|
bitfld.long 0x00 5. "B1669,B1669" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1668,B1668" "0,1"
|
|
bitfld.long 0x00 3. "B1667,B1667" "0,1"
|
|
bitfld.long 0x00 2. "B1666,B1666" "0,1"
|
|
bitfld.long 0x00 1. "B1665,B1665" "0,1"
|
|
bitfld.long 0x00 0. "B1664,B1664" "0,1"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "MPCBB2_VCTR53,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1727,B1727" "0,1"
|
|
bitfld.long 0x00 30. "B1726,B1726" "0,1"
|
|
bitfld.long 0x00 29. "B1725,B1725" "0,1"
|
|
bitfld.long 0x00 28. "B1724,B1724" "0,1"
|
|
bitfld.long 0x00 27. "B1723,B1723" "0,1"
|
|
bitfld.long 0x00 26. "B1722,B1722" "0,1"
|
|
bitfld.long 0x00 25. "B1721,B1721" "0,1"
|
|
bitfld.long 0x00 24. "B1720,B1720" "0,1"
|
|
bitfld.long 0x00 23. "B1719,B1719" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1718,B1718" "0,1"
|
|
bitfld.long 0x00 21. "B1717,B1717" "0,1"
|
|
bitfld.long 0x00 20. "B1716,B1716" "0,1"
|
|
bitfld.long 0x00 19. "B1715,B1715" "0,1"
|
|
bitfld.long 0x00 18. "B1714,B1714" "0,1"
|
|
bitfld.long 0x00 17. "B1713,B1713" "0,1"
|
|
bitfld.long 0x00 16. "B1712,B1712" "0,1"
|
|
bitfld.long 0x00 15. "B1711,B1711" "0,1"
|
|
bitfld.long 0x00 14. "B1710,B1710" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1709,B1709" "0,1"
|
|
bitfld.long 0x00 12. "B1708,B1708" "0,1"
|
|
bitfld.long 0x00 11. "B1707,B1707" "0,1"
|
|
bitfld.long 0x00 10. "B1706,B1706" "0,1"
|
|
bitfld.long 0x00 9. "B1705,B1705" "0,1"
|
|
bitfld.long 0x00 8. "B1704,B1704" "0,1"
|
|
bitfld.long 0x00 7. "B1703,B1703" "0,1"
|
|
bitfld.long 0x00 6. "B1702,B1702" "0,1"
|
|
bitfld.long 0x00 5. "B1701,B1701" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1700,B1700" "0,1"
|
|
bitfld.long 0x00 3. "B1699,B1699" "0,1"
|
|
bitfld.long 0x00 2. "B1698,B1698" "0,1"
|
|
bitfld.long 0x00 1. "B1697,B1697" "0,1"
|
|
bitfld.long 0x00 0. "B1696,B1696" "0,1"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "MPCBB2_VCTR54,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1759,B1759" "0,1"
|
|
bitfld.long 0x00 30. "B1758,B1758" "0,1"
|
|
bitfld.long 0x00 29. "B1757,B1757" "0,1"
|
|
bitfld.long 0x00 28. "B1756,B1756" "0,1"
|
|
bitfld.long 0x00 27. "B1755,B1755" "0,1"
|
|
bitfld.long 0x00 26. "B1754,B1754" "0,1"
|
|
bitfld.long 0x00 25. "B1753,B1753" "0,1"
|
|
bitfld.long 0x00 24. "B1752,B1752" "0,1"
|
|
bitfld.long 0x00 23. "B1751,B1751" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1750,B1750" "0,1"
|
|
bitfld.long 0x00 21. "B1749,B1749" "0,1"
|
|
bitfld.long 0x00 20. "B1748,B1748" "0,1"
|
|
bitfld.long 0x00 19. "B1747,B1747" "0,1"
|
|
bitfld.long 0x00 18. "B1746,B1746" "0,1"
|
|
bitfld.long 0x00 17. "B1745,B1745" "0,1"
|
|
bitfld.long 0x00 16. "B1744,B1744" "0,1"
|
|
bitfld.long 0x00 15. "B1743,B1743" "0,1"
|
|
bitfld.long 0x00 14. "B1742,B1742" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1741,B1741" "0,1"
|
|
bitfld.long 0x00 12. "B1740,B1740" "0,1"
|
|
bitfld.long 0x00 11. "B1739,B1739" "0,1"
|
|
bitfld.long 0x00 10. "B1738,B1738" "0,1"
|
|
bitfld.long 0x00 9. "B1737,B1737" "0,1"
|
|
bitfld.long 0x00 8. "B1736,B1736" "0,1"
|
|
bitfld.long 0x00 7. "B1735,B1735" "0,1"
|
|
bitfld.long 0x00 6. "B1734,B1734" "0,1"
|
|
bitfld.long 0x00 5. "B1733,B1733" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1732,B1732" "0,1"
|
|
bitfld.long 0x00 3. "B1731,B1731" "0,1"
|
|
bitfld.long 0x00 2. "B1730,B1730" "0,1"
|
|
bitfld.long 0x00 1. "B1729,B1729" "0,1"
|
|
bitfld.long 0x00 0. "B1728,B1728" "0,1"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "MPCBB2_VCTR55,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1791,B1791" "0,1"
|
|
bitfld.long 0x00 30. "B1790,B1790" "0,1"
|
|
bitfld.long 0x00 29. "B1789,B1789" "0,1"
|
|
bitfld.long 0x00 28. "B1788,B1788" "0,1"
|
|
bitfld.long 0x00 27. "B1787,B1787" "0,1"
|
|
bitfld.long 0x00 26. "B1786,B1786" "0,1"
|
|
bitfld.long 0x00 25. "B1785,B1785" "0,1"
|
|
bitfld.long 0x00 24. "B1784,B1784" "0,1"
|
|
bitfld.long 0x00 23. "B1783,B1783" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1782,B1782" "0,1"
|
|
bitfld.long 0x00 21. "B1781,B1781" "0,1"
|
|
bitfld.long 0x00 20. "B1780,B1780" "0,1"
|
|
bitfld.long 0x00 19. "B1779,B1779" "0,1"
|
|
bitfld.long 0x00 18. "B1778,B1778" "0,1"
|
|
bitfld.long 0x00 17. "B1777,B1777" "0,1"
|
|
bitfld.long 0x00 16. "B1776,B1776" "0,1"
|
|
bitfld.long 0x00 15. "B1775,B1775" "0,1"
|
|
bitfld.long 0x00 14. "B1774,B1774" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1773,B1773" "0,1"
|
|
bitfld.long 0x00 12. "B1772,B1772" "0,1"
|
|
bitfld.long 0x00 11. "B1771,B1771" "0,1"
|
|
bitfld.long 0x00 10. "B1770,B1770" "0,1"
|
|
bitfld.long 0x00 9. "B1769,B1769" "0,1"
|
|
bitfld.long 0x00 8. "B1768,B1768" "0,1"
|
|
bitfld.long 0x00 7. "B1767,B1767" "0,1"
|
|
bitfld.long 0x00 6. "B1766,B1766" "0,1"
|
|
bitfld.long 0x00 5. "B1765,B1765" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1764,B1764" "0,1"
|
|
bitfld.long 0x00 3. "B1763,B1763" "0,1"
|
|
bitfld.long 0x00 2. "B1762,B1762" "0,1"
|
|
bitfld.long 0x00 1. "B1761,B1761" "0,1"
|
|
bitfld.long 0x00 0. "B1760,B1760" "0,1"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "MPCBB2_VCTR56,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1823,B1823" "0,1"
|
|
bitfld.long 0x00 30. "B1822,B1822" "0,1"
|
|
bitfld.long 0x00 29. "B1821,B1821" "0,1"
|
|
bitfld.long 0x00 28. "B1820,B1820" "0,1"
|
|
bitfld.long 0x00 27. "B1819,B1819" "0,1"
|
|
bitfld.long 0x00 26. "B1818,B1818" "0,1"
|
|
bitfld.long 0x00 25. "B1817,B1817" "0,1"
|
|
bitfld.long 0x00 24. "B1816,B1816" "0,1"
|
|
bitfld.long 0x00 23. "B1815,B1815" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1814,B1814" "0,1"
|
|
bitfld.long 0x00 21. "B1813,B1813" "0,1"
|
|
bitfld.long 0x00 20. "B1812,B1812" "0,1"
|
|
bitfld.long 0x00 19. "B1811,B1811" "0,1"
|
|
bitfld.long 0x00 18. "B1810,B1810" "0,1"
|
|
bitfld.long 0x00 17. "B1809,B1809" "0,1"
|
|
bitfld.long 0x00 16. "B1808,B1808" "0,1"
|
|
bitfld.long 0x00 15. "B1807,B1807" "0,1"
|
|
bitfld.long 0x00 14. "B1806,B1806" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1805,B1805" "0,1"
|
|
bitfld.long 0x00 12. "B1804,B1804" "0,1"
|
|
bitfld.long 0x00 11. "B1803,B1803" "0,1"
|
|
bitfld.long 0x00 10. "B1802,B1802" "0,1"
|
|
bitfld.long 0x00 9. "B1801,B1801" "0,1"
|
|
bitfld.long 0x00 8. "B1800,B1800" "0,1"
|
|
bitfld.long 0x00 7. "B1799,B1799" "0,1"
|
|
bitfld.long 0x00 6. "B1798,B1798" "0,1"
|
|
bitfld.long 0x00 5. "B1797,B1797" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1796,B1796" "0,1"
|
|
bitfld.long 0x00 3. "B1795,B1795" "0,1"
|
|
bitfld.long 0x00 2. "B1794,B1794" "0,1"
|
|
bitfld.long 0x00 1. "B1793,B1793" "0,1"
|
|
bitfld.long 0x00 0. "B1792,B1792" "0,1"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "MPCBB2_VCTR57,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1855,B1855" "0,1"
|
|
bitfld.long 0x00 30. "B1854,B1854" "0,1"
|
|
bitfld.long 0x00 29. "B1853,B1853" "0,1"
|
|
bitfld.long 0x00 28. "B1852,B1852" "0,1"
|
|
bitfld.long 0x00 27. "B1851,B1851" "0,1"
|
|
bitfld.long 0x00 26. "B1850,B1850" "0,1"
|
|
bitfld.long 0x00 25. "B1849,B1849" "0,1"
|
|
bitfld.long 0x00 24. "B1848,B1848" "0,1"
|
|
bitfld.long 0x00 23. "B1847,B1847" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1846,B1846" "0,1"
|
|
bitfld.long 0x00 21. "B1845,B1845" "0,1"
|
|
bitfld.long 0x00 20. "B1844,B1844" "0,1"
|
|
bitfld.long 0x00 19. "B1843,B1843" "0,1"
|
|
bitfld.long 0x00 18. "B1842,B1842" "0,1"
|
|
bitfld.long 0x00 17. "B1841,B1841" "0,1"
|
|
bitfld.long 0x00 16. "B1840,B1840" "0,1"
|
|
bitfld.long 0x00 15. "B1839,B1839" "0,1"
|
|
bitfld.long 0x00 14. "B1838,B1838" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1837,B1837" "0,1"
|
|
bitfld.long 0x00 12. "B1836,B1836" "0,1"
|
|
bitfld.long 0x00 11. "B1835,B1835" "0,1"
|
|
bitfld.long 0x00 10. "B1834,B1834" "0,1"
|
|
bitfld.long 0x00 9. "B1833,B1833" "0,1"
|
|
bitfld.long 0x00 8. "B1832,B1832" "0,1"
|
|
bitfld.long 0x00 7. "B1831,B1831" "0,1"
|
|
bitfld.long 0x00 6. "B1830,B1830" "0,1"
|
|
bitfld.long 0x00 5. "B1829,B1829" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1828,B1828" "0,1"
|
|
bitfld.long 0x00 3. "B1827,B1827" "0,1"
|
|
bitfld.long 0x00 2. "B1826,B1826" "0,1"
|
|
bitfld.long 0x00 1. "B1825,B1825" "0,1"
|
|
bitfld.long 0x00 0. "B1824,B1824" "0,1"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "MPCBB2_VCTR58,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1887,B1887" "0,1"
|
|
bitfld.long 0x00 30. "B1886,B1886" "0,1"
|
|
bitfld.long 0x00 29. "B1885,B1885" "0,1"
|
|
bitfld.long 0x00 28. "B1884,B1884" "0,1"
|
|
bitfld.long 0x00 27. "B1883,B1883" "0,1"
|
|
bitfld.long 0x00 26. "B1882,B1882" "0,1"
|
|
bitfld.long 0x00 25. "B1881,B1881" "0,1"
|
|
bitfld.long 0x00 24. "B1880,B1880" "0,1"
|
|
bitfld.long 0x00 23. "B1879,B1879" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1878,B1878" "0,1"
|
|
bitfld.long 0x00 21. "B1877,B1877" "0,1"
|
|
bitfld.long 0x00 20. "B1876,B1876" "0,1"
|
|
bitfld.long 0x00 19. "B1875,B1875" "0,1"
|
|
bitfld.long 0x00 18. "B1874,B1874" "0,1"
|
|
bitfld.long 0x00 17. "B1873,B1873" "0,1"
|
|
bitfld.long 0x00 16. "B1872,B1872" "0,1"
|
|
bitfld.long 0x00 15. "B1871,B1871" "0,1"
|
|
bitfld.long 0x00 14. "B1870,B1870" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1869,B1869" "0,1"
|
|
bitfld.long 0x00 12. "B1868,B1868" "0,1"
|
|
bitfld.long 0x00 11. "B1867,B1867" "0,1"
|
|
bitfld.long 0x00 10. "B1866,B1866" "0,1"
|
|
bitfld.long 0x00 9. "B1865,B1865" "0,1"
|
|
bitfld.long 0x00 8. "B1864,B1864" "0,1"
|
|
bitfld.long 0x00 7. "B1863,B1863" "0,1"
|
|
bitfld.long 0x00 6. "B1862,B1862" "0,1"
|
|
bitfld.long 0x00 5. "B1861,B1861" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1860,B1860" "0,1"
|
|
bitfld.long 0x00 3. "B1859,B1859" "0,1"
|
|
bitfld.long 0x00 2. "B1858,B1858" "0,1"
|
|
bitfld.long 0x00 1. "B1857,B1857" "0,1"
|
|
bitfld.long 0x00 0. "B1856,B1856" "0,1"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "MPCBB2_VCTR59,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1919,B1919" "0,1"
|
|
bitfld.long 0x00 30. "B1918,B1918" "0,1"
|
|
bitfld.long 0x00 29. "B1917,B1917" "0,1"
|
|
bitfld.long 0x00 28. "B1916,B1916" "0,1"
|
|
bitfld.long 0x00 27. "B1915,B1915" "0,1"
|
|
bitfld.long 0x00 26. "B1914,B1914" "0,1"
|
|
bitfld.long 0x00 25. "B1913,B1913" "0,1"
|
|
bitfld.long 0x00 24. "B1912,B1912" "0,1"
|
|
bitfld.long 0x00 23. "B1911,B1911" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1910,B1910" "0,1"
|
|
bitfld.long 0x00 21. "B1909,B1909" "0,1"
|
|
bitfld.long 0x00 20. "B1908,B1908" "0,1"
|
|
bitfld.long 0x00 19. "B1907,B1907" "0,1"
|
|
bitfld.long 0x00 18. "B1906,B1906" "0,1"
|
|
bitfld.long 0x00 17. "B1905,B1905" "0,1"
|
|
bitfld.long 0x00 16. "B1904,B1904" "0,1"
|
|
bitfld.long 0x00 15. "B1903,B1903" "0,1"
|
|
bitfld.long 0x00 14. "B1902,B1902" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1901,B1901" "0,1"
|
|
bitfld.long 0x00 12. "B1900,B1900" "0,1"
|
|
bitfld.long 0x00 11. "B1899,B1899" "0,1"
|
|
bitfld.long 0x00 10. "B1898,B1898" "0,1"
|
|
bitfld.long 0x00 9. "B1897,B1897" "0,1"
|
|
bitfld.long 0x00 8. "B1896,B1896" "0,1"
|
|
bitfld.long 0x00 7. "B1895,B1895" "0,1"
|
|
bitfld.long 0x00 6. "B1894,B1894" "0,1"
|
|
bitfld.long 0x00 5. "B1893,B1893" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1892,B1892" "0,1"
|
|
bitfld.long 0x00 3. "B1891,B1891" "0,1"
|
|
bitfld.long 0x00 2. "B1890,B1890" "0,1"
|
|
bitfld.long 0x00 1. "B1889,B1889" "0,1"
|
|
bitfld.long 0x00 0. "B1888,B1888" "0,1"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "MPCBB2_VCTR60,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1951,B1951" "0,1"
|
|
bitfld.long 0x00 30. "B1950,B1950" "0,1"
|
|
bitfld.long 0x00 29. "B1949,B1949" "0,1"
|
|
bitfld.long 0x00 28. "B1948,B1948" "0,1"
|
|
bitfld.long 0x00 27. "B1947,B1947" "0,1"
|
|
bitfld.long 0x00 26. "B1946,B1946" "0,1"
|
|
bitfld.long 0x00 25. "B1945,B1945" "0,1"
|
|
bitfld.long 0x00 24. "B1944,B1944" "0,1"
|
|
bitfld.long 0x00 23. "B1943,B1943" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1942,B1942" "0,1"
|
|
bitfld.long 0x00 21. "B1941,B1941" "0,1"
|
|
bitfld.long 0x00 20. "B1940,B1940" "0,1"
|
|
bitfld.long 0x00 19. "B1939,B1939" "0,1"
|
|
bitfld.long 0x00 18. "B1938,B1938" "0,1"
|
|
bitfld.long 0x00 17. "B1937,B1937" "0,1"
|
|
bitfld.long 0x00 16. "B1936,B1936" "0,1"
|
|
bitfld.long 0x00 15. "B1935,B1935" "0,1"
|
|
bitfld.long 0x00 14. "B1934,B1934" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1933,B1933" "0,1"
|
|
bitfld.long 0x00 12. "B1932,B1932" "0,1"
|
|
bitfld.long 0x00 11. "B1931,B1931" "0,1"
|
|
bitfld.long 0x00 10. "B1930,B1930" "0,1"
|
|
bitfld.long 0x00 9. "B1929,B1929" "0,1"
|
|
bitfld.long 0x00 8. "B1928,B1928" "0,1"
|
|
bitfld.long 0x00 7. "B1927,B1927" "0,1"
|
|
bitfld.long 0x00 6. "B1926,B1926" "0,1"
|
|
bitfld.long 0x00 5. "B1925,B1925" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1924,B1924" "0,1"
|
|
bitfld.long 0x00 3. "B1923,B1923" "0,1"
|
|
bitfld.long 0x00 2. "B1922,B1922" "0,1"
|
|
bitfld.long 0x00 1. "B1921,B1921" "0,1"
|
|
bitfld.long 0x00 0. "B1920,B1920" "0,1"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "MPCBB2_VCTR61,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1983,B1983" "0,1"
|
|
bitfld.long 0x00 30. "B1982,B1982" "0,1"
|
|
bitfld.long 0x00 29. "B1981,B1981" "0,1"
|
|
bitfld.long 0x00 28. "B1980,B1980" "0,1"
|
|
bitfld.long 0x00 27. "B1979,B1979" "0,1"
|
|
bitfld.long 0x00 26. "B1978,B1978" "0,1"
|
|
bitfld.long 0x00 25. "B1977,B1977" "0,1"
|
|
bitfld.long 0x00 24. "B1976,B1976" "0,1"
|
|
bitfld.long 0x00 23. "B1975,B1975" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1974,B1974" "0,1"
|
|
bitfld.long 0x00 21. "B1973,B1973" "0,1"
|
|
bitfld.long 0x00 20. "B1972,B1972" "0,1"
|
|
bitfld.long 0x00 19. "B1971,B1971" "0,1"
|
|
bitfld.long 0x00 18. "B1970,B1970" "0,1"
|
|
bitfld.long 0x00 17. "B1969,B1969" "0,1"
|
|
bitfld.long 0x00 16. "B1968,B1968" "0,1"
|
|
bitfld.long 0x00 15. "B1967,B1967" "0,1"
|
|
bitfld.long 0x00 14. "B1966,B1966" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1965,B1965" "0,1"
|
|
bitfld.long 0x00 12. "B1964,B1964" "0,1"
|
|
bitfld.long 0x00 11. "B1963,B1963" "0,1"
|
|
bitfld.long 0x00 10. "B1962,B1962" "0,1"
|
|
bitfld.long 0x00 9. "B1961,B1961" "0,1"
|
|
bitfld.long 0x00 8. "B1960,B1960" "0,1"
|
|
bitfld.long 0x00 7. "B1959,B1959" "0,1"
|
|
bitfld.long 0x00 6. "B1958,B1958" "0,1"
|
|
bitfld.long 0x00 5. "B1957,B1957" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1956,B1956" "0,1"
|
|
bitfld.long 0x00 3. "B1955,B1955" "0,1"
|
|
bitfld.long 0x00 2. "B1954,B1954" "0,1"
|
|
bitfld.long 0x00 1. "B1953,B1953" "0,1"
|
|
bitfld.long 0x00 0. "B1952,B1952" "0,1"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "MPCBB2_VCTR62,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B2015,B2015" "0,1"
|
|
bitfld.long 0x00 30. "B2014,B2014" "0,1"
|
|
bitfld.long 0x00 29. "B2013,B2013" "0,1"
|
|
bitfld.long 0x00 28. "B2012,B2012" "0,1"
|
|
bitfld.long 0x00 27. "B2011,B2011" "0,1"
|
|
bitfld.long 0x00 26. "B2010,B2010" "0,1"
|
|
bitfld.long 0x00 25. "B2009,B2009" "0,1"
|
|
bitfld.long 0x00 24. "B2008,B2008" "0,1"
|
|
bitfld.long 0x00 23. "B2007,B2007" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B2006,B2006" "0,1"
|
|
bitfld.long 0x00 21. "B2005,B2005" "0,1"
|
|
bitfld.long 0x00 20. "B2004,B2004" "0,1"
|
|
bitfld.long 0x00 19. "B2003,B2003" "0,1"
|
|
bitfld.long 0x00 18. "B2002,B2002" "0,1"
|
|
bitfld.long 0x00 17. "B2001,B2001" "0,1"
|
|
bitfld.long 0x00 16. "B2000,B2000" "0,1"
|
|
bitfld.long 0x00 15. "B1999,B1999" "0,1"
|
|
bitfld.long 0x00 14. "B1998,B1998" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1997,B1997" "0,1"
|
|
bitfld.long 0x00 12. "B1996,B1996" "0,1"
|
|
bitfld.long 0x00 11. "B1995,B1995" "0,1"
|
|
bitfld.long 0x00 10. "B1994,B1994" "0,1"
|
|
bitfld.long 0x00 9. "B1993,B1993" "0,1"
|
|
bitfld.long 0x00 8. "B1992,B1992" "0,1"
|
|
bitfld.long 0x00 7. "B1991,B1991" "0,1"
|
|
bitfld.long 0x00 6. "B1990,B1990" "0,1"
|
|
bitfld.long 0x00 5. "B1989,B1989" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1988,B1988" "0,1"
|
|
bitfld.long 0x00 3. "B1987,B1987" "0,1"
|
|
bitfld.long 0x00 2. "B1986,B1986" "0,1"
|
|
bitfld.long 0x00 1. "B1985,B1985" "0,1"
|
|
bitfld.long 0x00 0. "B1984,B1984" "0,1"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "MPCBB2_VCTR63,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B2047,B2047" "0,1"
|
|
bitfld.long 0x00 30. "B2046,B2046" "0,1"
|
|
bitfld.long 0x00 29. "B2045,B2045" "0,1"
|
|
bitfld.long 0x00 28. "B2044,B2044" "0,1"
|
|
bitfld.long 0x00 27. "B2043,B2043" "0,1"
|
|
bitfld.long 0x00 26. "B2042,B2042" "0,1"
|
|
bitfld.long 0x00 25. "B2041,B2041" "0,1"
|
|
bitfld.long 0x00 24. "B2040,B2040" "0,1"
|
|
bitfld.long 0x00 23. "B2039,B2039" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B2038,B2038" "0,1"
|
|
bitfld.long 0x00 21. "B2037,B2037" "0,1"
|
|
bitfld.long 0x00 20. "B2036,B2036" "0,1"
|
|
bitfld.long 0x00 19. "B2035,B2035" "0,1"
|
|
bitfld.long 0x00 18. "B2034,B2034" "0,1"
|
|
bitfld.long 0x00 17. "B2033,B2033" "0,1"
|
|
bitfld.long 0x00 16. "B2032,B2032" "0,1"
|
|
bitfld.long 0x00 15. "B2031,B2031" "0,1"
|
|
bitfld.long 0x00 14. "B2030,B2030" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B2029,B2029" "0,1"
|
|
bitfld.long 0x00 12. "B2028,B2028" "0,1"
|
|
bitfld.long 0x00 11. "B2027,B2027" "0,1"
|
|
bitfld.long 0x00 10. "B2026,B2026" "0,1"
|
|
bitfld.long 0x00 9. "B2025,B2025" "0,1"
|
|
bitfld.long 0x00 8. "B2024,B2024" "0,1"
|
|
bitfld.long 0x00 7. "B2023,B2023" "0,1"
|
|
bitfld.long 0x00 6. "B2022,B2022" "0,1"
|
|
bitfld.long 0x00 5. "B2021,B2021" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B2020,B2020" "0,1"
|
|
bitfld.long 0x00 3. "B2019,B2019" "0,1"
|
|
bitfld.long 0x00 2. "B2018,B2018" "0,1"
|
|
bitfld.long 0x00 1. "B2017,B2017" "0,1"
|
|
bitfld.long 0x00 0. "B2016,B2016" "0,1"
|
|
tree.end
|
|
tree "TZIC"
|
|
base ad:0x40032800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IER1,TZIC interrupt enable register 1"
|
|
bitfld.long 0x00 31. "SPI1IE,SPI1IE" "0,1"
|
|
bitfld.long 0x00 30. "TIM1IE,TIM1IE" "0,1"
|
|
bitfld.long 0x00 29. "COMPIE,COMPIE" "0,1"
|
|
bitfld.long 0x00 28. "VREFBUFIE,VREFBUFIE" "0,1"
|
|
bitfld.long 0x00 27. "UCPD1IE,UCPD1IE" "0,1"
|
|
bitfld.long 0x00 26. "USBFSIE,USBFSIE" "0,1"
|
|
bitfld.long 0x00 25. "FDCAN1IE,FDCAN1IE" "0,1"
|
|
bitfld.long 0x00 24. "LPTIM3IE,LPTIM3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "LPTIM2IE,LPTIM2IE" "0,1"
|
|
bitfld.long 0x00 22. "I2C4IE,I2C4IE" "0,1"
|
|
bitfld.long 0x00 21. "LPUART1IE,LPUART1IE" "0,1"
|
|
bitfld.long 0x00 20. "LPTIM1IE,LPTIM1IE" "0,1"
|
|
bitfld.long 0x00 19. "OPAMPIE,OPAMPIE" "0,1"
|
|
bitfld.long 0x00 18. "DACIE,DACIE" "0,1"
|
|
bitfld.long 0x00 17. "CRSIE,CRSIE" "0,1"
|
|
bitfld.long 0x00 16. "I2C3IE,I2C3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "I2C2IE,I2C2IE" "0,1"
|
|
bitfld.long 0x00 14. "I2C1IE,I2C1IE" "0,1"
|
|
bitfld.long 0x00 13. "UART5IE,UART5IE" "0,1"
|
|
bitfld.long 0x00 12. "UART4IE,UART4IE" "0,1"
|
|
bitfld.long 0x00 11. "USART3IE,USART3IE" "0,1"
|
|
bitfld.long 0x00 10. "USART2IE,USART2IE" "0,1"
|
|
bitfld.long 0x00 9. "SPI3IE,SPI3IE" "0,1"
|
|
bitfld.long 0x00 8. "SPI2IE,SPI2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IWDGIE,IWDGIE" "0,1"
|
|
bitfld.long 0x00 6. "WWDGIE,WWDGIE" "0,1"
|
|
bitfld.long 0x00 5. "TIM7IE,TIM7IE" "0,1"
|
|
bitfld.long 0x00 4. "TIM6IE,TIM6IE" "0,1"
|
|
bitfld.long 0x00 3. "TIM5IE,TIM5IE" "0,1"
|
|
bitfld.long 0x00 2. "TIM4IE,TIM4IE" "0,1"
|
|
bitfld.long 0x00 1. "TIM3IE,TIM3IE" "0,1"
|
|
bitfld.long 0x00 0. "TIM2IE,TIM2IE" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER2,TZIC interrupt enable register 2"
|
|
bitfld.long 0x00 29. "OTFDEC1IE,OTFDEC1IE" "0,1"
|
|
bitfld.long 0x00 28. "EXTIIE,EXTIIE" "0,1"
|
|
bitfld.long 0x00 27. "FLASH_REGIE,FLASH_REGIE" "0,1"
|
|
bitfld.long 0x00 26. "FLASHIE,FLASHIE" "0,1"
|
|
bitfld.long 0x00 25. "RCCIE,RCCIE" "0,1"
|
|
bitfld.long 0x00 24. "DMAMUX1IE,DMAMUX1IE" "0,1"
|
|
bitfld.long 0x00 23. "DMA2IE,DMA2IE" "0,1"
|
|
bitfld.long 0x00 22. "DMA1IE,DMA1IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "SYSCFGIE,SYSCFGIE" "0,1"
|
|
bitfld.long 0x00 20. "PWRIE,PWRIE" "0,1"
|
|
bitfld.long 0x00 19. "RTCIE,RTCIE" "0,1"
|
|
bitfld.long 0x00 18. "OCTOSPI1_REGIE,OCTOSPI1_REGIE" "0,1"
|
|
bitfld.long 0x00 17. "FMC_REGIE,FMC_REGIE" "0,1"
|
|
bitfld.long 0x00 16. "SDMMC1IE,SDMMC1IE" "0,1"
|
|
bitfld.long 0x00 15. "PKAIE,PKAIE" "0,1"
|
|
bitfld.long 0x00 14. "RNGIE,RNGIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "HASHIE,HASHIE" "0,1"
|
|
bitfld.long 0x00 12. "AESIE,AESIE" "0,1"
|
|
bitfld.long 0x00 11. "ADCIE,ADCIE" "0,1"
|
|
bitfld.long 0x00 10. "ICACHEIE,ICACHEIE" "0,1"
|
|
bitfld.long 0x00 9. "TSCIE,TSCIE" "0,1"
|
|
bitfld.long 0x00 8. "CRCIE,CRCIE" "0,1"
|
|
bitfld.long 0x00 7. "DFSDM1IE,DFSDM1IE" "0,1"
|
|
bitfld.long 0x00 6. "SAI2IE,SAI2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SAI1IE,SAI1IE" "0,1"
|
|
bitfld.long 0x00 4. "TIM17IE,TIM17IE" "0,1"
|
|
bitfld.long 0x00 3. "TIM16IE,TIM16IE" "0,1"
|
|
bitfld.long 0x00 2. "TIM15IE,TIM15IE" "0,1"
|
|
bitfld.long 0x00 1. "USART1IE,USART1IE" "0,1"
|
|
bitfld.long 0x00 0. "TIM8IE,TIM8IE" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IER3,TZIC interrupt enable register 3"
|
|
bitfld.long 0x00 7. "MPCBB2_REGIE,MPCBB2_REGIE" "0,1"
|
|
bitfld.long 0x00 6. "MPCBB2IE,MPCBB2IE" "0,1"
|
|
bitfld.long 0x00 5. "MPCBB1_REGIE,MPCBB1_REGIE" "0,1"
|
|
bitfld.long 0x00 4. "MPCBB1IE,MPCBB1IE" "0,1"
|
|
bitfld.long 0x00 3. "MPCWM2IE,MPCWM2IE" "0,1"
|
|
bitfld.long 0x00 2. "MPCWM1IE,MPCWM1IE" "0,1"
|
|
bitfld.long 0x00 1. "TZICIE,TZICIE" "0,1"
|
|
bitfld.long 0x00 0. "TZSCIE,TZSCIE" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SR1,TZIC interrupt status register 1"
|
|
bitfld.long 0x00 31. "SPI1F,SPI1F" "0,1"
|
|
bitfld.long 0x00 30. "TIM1F,TIM1F" "0,1"
|
|
bitfld.long 0x00 29. "COMPF,COMPF" "0,1"
|
|
bitfld.long 0x00 28. "VREFBUFF,VREFBUFF" "0,1"
|
|
bitfld.long 0x00 27. "UCPD1F,UCPD1F" "0,1"
|
|
bitfld.long 0x00 26. "USBFSF,USBFSF" "0,1"
|
|
bitfld.long 0x00 25. "FDCAN1F,FDCAN1F" "0,1"
|
|
bitfld.long 0x00 24. "LPTIM3F,LPTIM3F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "LPTIM2F,LPTIM2F" "0,1"
|
|
bitfld.long 0x00 22. "I2C4F,I2C4F" "0,1"
|
|
bitfld.long 0x00 21. "LPUART1F,LPUART1F" "0,1"
|
|
bitfld.long 0x00 20. "LPTIM1F,LPTIM1F" "0,1"
|
|
bitfld.long 0x00 19. "OPAMPF,OPAMPF" "0,1"
|
|
bitfld.long 0x00 18. "DACF,DACF" "0,1"
|
|
bitfld.long 0x00 17. "CRSF,CRSF" "0,1"
|
|
bitfld.long 0x00 16. "I2C3F,I2C3F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "I2C2F,I2C2F" "0,1"
|
|
bitfld.long 0x00 14. "I2C1F,I2C1F" "0,1"
|
|
bitfld.long 0x00 13. "UART5F,UART5F" "0,1"
|
|
bitfld.long 0x00 12. "UART4F,UART4F" "0,1"
|
|
bitfld.long 0x00 11. "USART3F,USART3F" "0,1"
|
|
bitfld.long 0x00 10. "USART2F,USART2F" "0,1"
|
|
bitfld.long 0x00 9. "SPI3F,SPI3F" "0,1"
|
|
bitfld.long 0x00 8. "SPI2F,SPI2F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IWDGF,IWDGF" "0,1"
|
|
bitfld.long 0x00 6. "WWDGF,WWDGF" "0,1"
|
|
bitfld.long 0x00 5. "TIM7F,TIM7F" "0,1"
|
|
bitfld.long 0x00 4. "TIM6F,TIM6F" "0,1"
|
|
bitfld.long 0x00 3. "TIM5F,TIM5F" "0,1"
|
|
bitfld.long 0x00 2. "TIM4F,TIM4F" "0,1"
|
|
bitfld.long 0x00 1. "TIM3F,TIM3F" "0,1"
|
|
bitfld.long 0x00 0. "TIM2F,TIM2F" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR2,TZIC interrupt status register 2"
|
|
bitfld.long 0x00 29. "OTFDEC1F,OTFDEC1F" "0,1"
|
|
bitfld.long 0x00 28. "EXTIF,EXTIF" "0,1"
|
|
bitfld.long 0x00 27. "FLASH_REGF,FLASH_REGF" "0,1"
|
|
bitfld.long 0x00 26. "FLASHF,FLASHF" "0,1"
|
|
bitfld.long 0x00 25. "RCCF,RCCF" "0,1"
|
|
bitfld.long 0x00 24. "DMAMUX1F,DMAMUX1F" "0,1"
|
|
bitfld.long 0x00 23. "DMA2F,DMA2F" "0,1"
|
|
bitfld.long 0x00 22. "DMA1F,DMA1F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "SYSCFGF,SYSCFGF" "0,1"
|
|
bitfld.long 0x00 20. "PWRF,PWRF" "0,1"
|
|
bitfld.long 0x00 19. "RTCF,RTCF" "0,1"
|
|
bitfld.long 0x00 18. "OCTOSPI1_REGF,OCTOSPI1_REGF" "0,1"
|
|
bitfld.long 0x00 17. "FMC_REGF,FMC_REGF" "0,1"
|
|
bitfld.long 0x00 16. "SDMMC1F,SDMMC1F" "0,1"
|
|
bitfld.long 0x00 15. "PKAF,PKAF" "0,1"
|
|
bitfld.long 0x00 14. "RNGF,RNGF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "HASHF,HASHF" "0,1"
|
|
bitfld.long 0x00 12. "AESF,AESF" "0,1"
|
|
bitfld.long 0x00 11. "ADCF,ADCF" "0,1"
|
|
bitfld.long 0x00 10. "ICACHEF,ICACHEF" "0,1"
|
|
bitfld.long 0x00 9. "TSCF,TSCF" "0,1"
|
|
bitfld.long 0x00 8. "CRCF,CRCF" "0,1"
|
|
bitfld.long 0x00 7. "DFSDM1F,DFSDM1F" "0,1"
|
|
bitfld.long 0x00 6. "SAI2F,SAI2F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SAI1F,SAI1F" "0,1"
|
|
bitfld.long 0x00 4. "TIM17F,TIM17F" "0,1"
|
|
bitfld.long 0x00 3. "TIM16F,TIM16F" "0,1"
|
|
bitfld.long 0x00 2. "TIM15F,TIM15F" "0,1"
|
|
bitfld.long 0x00 1. "USART1F,USART1F" "0,1"
|
|
bitfld.long 0x00 0. "TIM8F,TIM8F" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SR3,TZIC interrupt status register 3"
|
|
bitfld.long 0x00 7. "MPCBB2_REGF,MPCBB2_REGF" "0,1"
|
|
bitfld.long 0x00 6. "MPCBB2F,MPCBB2F" "0,1"
|
|
bitfld.long 0x00 5. "MPCBB1_REGF,MPCBB1_REGF" "0,1"
|
|
bitfld.long 0x00 4. "MPCBB1F,MPCBB1F" "0,1"
|
|
bitfld.long 0x00 3. "MPCWM2F,MPCWM2F" "0,1"
|
|
bitfld.long 0x00 2. "MPCWM1F,MPCWM1F" "0,1"
|
|
bitfld.long 0x00 1. "TZICF,TZICF" "0,1"
|
|
bitfld.long 0x00 0. "TZSCF,TZSCF" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FCR1,TZIC interrupt clear register 1"
|
|
bitfld.long 0x00 31. "SPI1FC,SPI1FC" "0,1"
|
|
bitfld.long 0x00 30. "TIM1FC,TIM1FC" "0,1"
|
|
bitfld.long 0x00 29. "COMPFC,COMPFC" "0,1"
|
|
bitfld.long 0x00 28. "VREFBUFFC,VREFBUFFC" "0,1"
|
|
bitfld.long 0x00 27. "UCPD1FC,UCPD1FC" "0,1"
|
|
bitfld.long 0x00 26. "USBFSFC,USBFSFC" "0,1"
|
|
bitfld.long 0x00 25. "FDCAN1FC,FDCAN1FC" "0,1"
|
|
bitfld.long 0x00 24. "LPTIM3FC,LPTIM3FC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "LPTIM2FC,LPTIM2FC" "0,1"
|
|
bitfld.long 0x00 22. "I2C4FC,I2C4FC" "0,1"
|
|
bitfld.long 0x00 21. "LPUART1FC,LPUART1FC" "0,1"
|
|
bitfld.long 0x00 20. "LPTIM1FC,LPTIM1FC" "0,1"
|
|
bitfld.long 0x00 19. "OPAMPFC,OPAMPFC" "0,1"
|
|
bitfld.long 0x00 18. "DACFC,DACFC" "0,1"
|
|
bitfld.long 0x00 17. "CRSFC,CRSFC" "0,1"
|
|
bitfld.long 0x00 16. "I2C3FC,I2C3FC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "I2C2FC,I2C2FC" "0,1"
|
|
bitfld.long 0x00 14. "I2C1FC,I2C1FC" "0,1"
|
|
bitfld.long 0x00 13. "UART5FC,UART5FC" "0,1"
|
|
bitfld.long 0x00 12. "UART4FC,UART4FC" "0,1"
|
|
bitfld.long 0x00 11. "USART3FC,USART3FC" "0,1"
|
|
bitfld.long 0x00 10. "USART2FC,USART2FC" "0,1"
|
|
bitfld.long 0x00 9. "SPI3FC,SPI3FC" "0,1"
|
|
bitfld.long 0x00 8. "SPI2FC,SPI2FC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IWDGFC,IWDGFC" "0,1"
|
|
bitfld.long 0x00 6. "WWDGFC,WWDGFC" "0,1"
|
|
bitfld.long 0x00 5. "TIM7FC,TIM7FC" "0,1"
|
|
bitfld.long 0x00 4. "TIM6FC,TIM6FC" "0,1"
|
|
bitfld.long 0x00 3. "TIM5FC,TIM5FC" "0,1"
|
|
bitfld.long 0x00 2. "TIM4FC,TIM4FC" "0,1"
|
|
bitfld.long 0x00 1. "TIM3FC,TIM3FC" "0,1"
|
|
bitfld.long 0x00 0. "TIM2FC,TIM2FC" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICR2,TZIC interrupt clear register 2"
|
|
bitfld.long 0x00 29. "OTFDEC1FC,OTFDEC1FC" "0,1"
|
|
bitfld.long 0x00 28. "EXTIFC,EXTIFC" "0,1"
|
|
bitfld.long 0x00 27. "FLASH_REGFC,FLASH_REGFC" "0,1"
|
|
bitfld.long 0x00 26. "FLASHFC,FLASHFC" "0,1"
|
|
bitfld.long 0x00 25. "RCCFC,RCCFC" "0,1"
|
|
bitfld.long 0x00 24. "DMAMUX1FC,DMAMUX1FC" "0,1"
|
|
bitfld.long 0x00 23. "DMA2FC,DMA2FC" "0,1"
|
|
bitfld.long 0x00 22. "DMA1FC,DMA1FC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "SYSCFGFC,SYSCFGFC" "0,1"
|
|
bitfld.long 0x00 20. "PWRFC,PWRFC" "0,1"
|
|
bitfld.long 0x00 19. "RTCFC,RTCFC" "0,1"
|
|
bitfld.long 0x00 18. "OCTOSPI1_REGFC,OCTOSPI1_REGFC" "0,1"
|
|
bitfld.long 0x00 17. "FMC_REGFC,FMC_REGFC" "0,1"
|
|
bitfld.long 0x00 16. "SDMMC1FC,SDMMC1FC" "0,1"
|
|
bitfld.long 0x00 15. "PKAFC,PKAFC" "0,1"
|
|
bitfld.long 0x00 14. "RNGFC,RNGFC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "HASHFC,HASHFC" "0,1"
|
|
bitfld.long 0x00 12. "AESFC,AESFC" "0,1"
|
|
bitfld.long 0x00 11. "ADCFC,ADCFC" "0,1"
|
|
bitfld.long 0x00 10. "ICACHEFC,ICACHEFC" "0,1"
|
|
bitfld.long 0x00 9. "TSCFC,TSCFC" "0,1"
|
|
bitfld.long 0x00 8. "CRCFC,CRCFC" "0,1"
|
|
bitfld.long 0x00 7. "DFSDM1FC,DFSDM1FC" "0,1"
|
|
bitfld.long 0x00 6. "SAI2FC,SAI2FC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SAI1FC,SAI1FC" "0,1"
|
|
bitfld.long 0x00 4. "TIM17FC,TIM17FC" "0,1"
|
|
bitfld.long 0x00 3. "TIM16FC,TIM16FC" "0,1"
|
|
bitfld.long 0x00 2. "TIM15FC,TIM15FC" "0,1"
|
|
bitfld.long 0x00 1. "USART1FC,USART1FC" "0,1"
|
|
bitfld.long 0x00 0. "TIM8FC,TIM8FC" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FCR3,TZIC interrupt clear register 3"
|
|
bitfld.long 0x00 7. "MPCBB2_REGFC,MPCBB2_REGFC" "0,1"
|
|
bitfld.long 0x00 6. "MPCBB2FC,MPCBB2FC" "0,1"
|
|
bitfld.long 0x00 5. "MPCBB1_REGFC,MPCBB1_REGFC" "0,1"
|
|
bitfld.long 0x00 4. "MPCBB1FC,MPCBB1FC" "0,1"
|
|
bitfld.long 0x00 3. "MPCWM2FC,MPCWM2FC" "0,1"
|
|
bitfld.long 0x00 2. "MPCWM1FC,MPCWM1FC" "0,1"
|
|
bitfld.long 0x00 1. "TZICFC,TZICFC" "0,1"
|
|
bitfld.long 0x00 0. "TZSCFC,TZSCFC" "0,1"
|
|
tree.end
|
|
tree "TZSC"
|
|
base ad:0x40032400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TZSC_CR,TZSC control register"
|
|
bitfld.long 0x00 0. "LCK,LCK" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TZSC_SECCFGR1,TZSC secure configuration register 1"
|
|
bitfld.long 0x00 31. "SPI1SEC,SPI1SEC" "0,1"
|
|
bitfld.long 0x00 30. "TIM1SEC,TIM1SEC" "0,1"
|
|
bitfld.long 0x00 29. "COMPSEC,COMPSEC" "0,1"
|
|
bitfld.long 0x00 28. "VREFBUFSEC,VREFBUFSEC" "0,1"
|
|
bitfld.long 0x00 27. "UCPD1SEC,UCPD1SEC" "0,1"
|
|
bitfld.long 0x00 26. "USBFSSEC,USBFSSEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "FDCAN1SEC,FDCAN1SEC" "0,1"
|
|
bitfld.long 0x00 24. "LPTIM3SEC,LPTIM3SEC" "0,1"
|
|
bitfld.long 0x00 23. "LPTIM2SEC,LPTIM2SEC" "0,1"
|
|
bitfld.long 0x00 22. "I2C4SEC,I2C4SEC" "0,1"
|
|
bitfld.long 0x00 21. "LPUART1SEC,LPUART1SEC" "0,1"
|
|
bitfld.long 0x00 20. "LPTIM1SEC,LPTIM1SEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "OPAMPSEC,OPAMPSEC" "0,1"
|
|
bitfld.long 0x00 18. "DACSEC,DACSEC" "0,1"
|
|
bitfld.long 0x00 17. "CRSSEC,CRSSEC" "0,1"
|
|
bitfld.long 0x00 16. "I2C3SEC,I2C3SEC" "0,1"
|
|
bitfld.long 0x00 15. "I2C2SEC,I2C2SEC" "0,1"
|
|
bitfld.long 0x00 14. "I2C1SEC,I2C1SEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "UART5SEC,UART5SEC" "0,1"
|
|
bitfld.long 0x00 12. "UART4SEC,UART4SEC" "0,1"
|
|
bitfld.long 0x00 11. "USART3SEC,USART3SEC" "0,1"
|
|
bitfld.long 0x00 10. "USART2SEC,USART2SEC" "0,1"
|
|
bitfld.long 0x00 9. "SPI3SEC,SPI3SEC" "0,1"
|
|
bitfld.long 0x00 8. "SPI2SEC,SPI2SEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IWDGSEC,IWDGSEC" "0,1"
|
|
bitfld.long 0x00 6. "WWDGSEC,WWDGSEC" "0,1"
|
|
bitfld.long 0x00 5. "TIM7SEC,TIM7SEC" "0,1"
|
|
bitfld.long 0x00 4. "TIM6SEC,TIM6SEC" "0,1"
|
|
bitfld.long 0x00 3. "TIM5SEC,TIM5SEC" "0,1"
|
|
bitfld.long 0x00 2. "TIM4SEC,TIM4SEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TIM3SEC,TIM3SEC" "0,1"
|
|
bitfld.long 0x00 0. "TIM2SEC,TIM2SEC" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TZSC_SECCFGR2,TZSC secure configuration register 2"
|
|
bitfld.long 0x00 18. "OCTOSPI1_REGSEC,OCTOSPI1_REGSEC" "0,1"
|
|
bitfld.long 0x00 17. "FSMC_REGSEC,FSMC_REGSEC" "0,1"
|
|
bitfld.long 0x00 16. "SDMMC1SEC,SDMMC1SEC" "0,1"
|
|
bitfld.long 0x00 15. "PKASEC,PKASEC" "0,1"
|
|
bitfld.long 0x00 14. "RNGSEC,RNGSEC" "0,1"
|
|
bitfld.long 0x00 13. "HASHSEC,HASHSEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "AESSEC,AESSEC" "0,1"
|
|
bitfld.long 0x00 11. "ADCSEC,ADCSEC" "0,1"
|
|
bitfld.long 0x00 10. "ICACHESEC,ICACHESEC" "0,1"
|
|
bitfld.long 0x00 9. "TSCSEC,TSCSEC" "0,1"
|
|
bitfld.long 0x00 8. "CRCSEC,CRCSEC" "0,1"
|
|
bitfld.long 0x00 7. "DFSDM1SEC,DFSDM1SEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SAI2SEC,SAI2SEC" "0,1"
|
|
bitfld.long 0x00 5. "SAI1SEC,SAI1SEC" "0,1"
|
|
bitfld.long 0x00 4. "TIM17SEC,TIM17SEC" "0,1"
|
|
bitfld.long 0x00 3. "TIM16SEC,TIM16SEC" "0,1"
|
|
bitfld.long 0x00 2. "TIM15SEC,TIM15SEC" "0,1"
|
|
bitfld.long 0x00 1. "USART1SEC,USART1SEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TIM8SEC,TIM8SEC" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1"
|
|
bitfld.long 0x00 31. "SPI1PRIV,SPI1PRIV" "0,1"
|
|
bitfld.long 0x00 30. "TIM1PRIV,TIM1PRIV" "0,1"
|
|
bitfld.long 0x00 29. "COMPPRIV,COMPPRIV" "0,1"
|
|
bitfld.long 0x00 28. "VREFBUFPRIV,VREFBUFPRIV" "0,1"
|
|
bitfld.long 0x00 27. "UCPD1PRIV,UCPD1PRIV" "0,1"
|
|
bitfld.long 0x00 26. "USBFSPRIV,USBFSPRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "FDCAN1PRIV,FDCAN1PRIV" "0,1"
|
|
bitfld.long 0x00 24. "LPTIM3PRIV,LPTIM3PRIV" "0,1"
|
|
bitfld.long 0x00 23. "LPTIM2PRIV,LPTIM2PRIV" "0,1"
|
|
bitfld.long 0x00 22. "I2C4PRIV,I2C4PRIV" "0,1"
|
|
bitfld.long 0x00 21. "LPUART1PRIV,LPUART1PRIV" "0,1"
|
|
bitfld.long 0x00 20. "LPTIM1PRIV,LPTIM1PRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "OPAMPPRIV,OPAMPPRIV" "0,1"
|
|
bitfld.long 0x00 18. "DACPRIV,DACPRIV" "0,1"
|
|
bitfld.long 0x00 17. "CRSPRIV,CRSPRIV" "0,1"
|
|
bitfld.long 0x00 16. "I2C3PRIV,I2C3PRIV" "0,1"
|
|
bitfld.long 0x00 15. "I2C2PRIV,I2C2PRIV" "0,1"
|
|
bitfld.long 0x00 14. "I2C1PRIV,I2C1PRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "UART5PRIV,UART5PRIV" "0,1"
|
|
bitfld.long 0x00 12. "UART4PRIV,UART4PRIV" "0,1"
|
|
bitfld.long 0x00 11. "USART3PRIV,USART3PRIV" "0,1"
|
|
bitfld.long 0x00 10. "USART2PRIV,USART2PRIV" "0,1"
|
|
bitfld.long 0x00 9. "SPI3PRIV,SPI3PRIV" "0,1"
|
|
bitfld.long 0x00 8. "SPI2PRIV,SPI2PRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IWDGPRIV,IWDGPRIV" "0,1"
|
|
bitfld.long 0x00 6. "WWDGPRIV,WWDGPRIV" "0,1"
|
|
bitfld.long 0x00 5. "TIM7PRIV,TIM7PRIV" "0,1"
|
|
bitfld.long 0x00 4. "TIM6PRIV,TIM6PRIV" "0,1"
|
|
bitfld.long 0x00 3. "TIM5PRIV,TIM5PRIV" "0,1"
|
|
bitfld.long 0x00 2. "TIM4PRIV,TIM4PRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TIM3PRIV,TIM3PRIV" "0,1"
|
|
bitfld.long 0x00 0. "TIM2PRIV,TIM2PRIV" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2"
|
|
bitfld.long 0x00 18. "OCTOSPI1_REGPRIV,OCTOSPI1_REGRIV" "0,1"
|
|
bitfld.long 0x00 17. "FSMC_REGPRIV,FSMC_REGPRIV" "0,1"
|
|
bitfld.long 0x00 16. "SDMMC1PRIV,SDMMC1PRIV" "0,1"
|
|
bitfld.long 0x00 15. "PKAPRIV,PKAPRIV" "0,1"
|
|
bitfld.long 0x00 14. "RNGPRIV,RNGPRIV" "0,1"
|
|
bitfld.long 0x00 13. "HASHPRIV,HASHPRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "AESPRIV,AESPRIV" "0,1"
|
|
bitfld.long 0x00 11. "ADCPRIV,ADCPRIV" "0,1"
|
|
bitfld.long 0x00 10. "ICACHEPRIV,ICACHEPRIV" "0,1"
|
|
bitfld.long 0x00 9. "TSCPRIV,TSCPRIV" "0,1"
|
|
bitfld.long 0x00 8. "CRCPRIV,CRCPRIV" "0,1"
|
|
bitfld.long 0x00 7. "DFSDM1PRIV,DFSDM1PRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SAI2PRIV,SAI2PRIV" "0,1"
|
|
bitfld.long 0x00 5. "SAI1PRIV,SAI1PRIV" "0,1"
|
|
bitfld.long 0x00 4. "TIM17PRIV,TIM17PRIV" "0,1"
|
|
bitfld.long 0x00 3. "TIM16PRIV,TIM16PRIV" "0,1"
|
|
bitfld.long 0x00 2. "TIM15PRIV,TIM15PRIV" "0,1"
|
|
bitfld.long 0x00 1. "USART1PRIV,USART1PRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TIM8PRIV,TIM8PRIV" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TZSC_MPCWM1_NSWMR1,TZSC external memory non-secure watermark register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. "NSWM1LGTH,NSWM1LGTH"
|
|
hexmask.long.word 0x00 0.--10. 1. "NSWM1STRT,NSWM1STRT"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TZSC_MPCWM1_NSWMR2,TZSC external memory non-secure watermark register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. "NSWM2LGTH,NSWM2LGTH"
|
|
hexmask.long.word 0x00 0.--10. 1. "NSWM2STRT,NSWM2STRT"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TZSC_MPCWM2_NSWMR1,TZSC external memory non-secure watermark register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. "NSWM1LGTH,NSWM1LGTH"
|
|
hexmask.long.word 0x00 0.--10. 1. "NSWM1STRT,NSWM1STRT"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TZSC_MPCWM3_NSWMR1,TZSC external memory non-secure watermark register 2"
|
|
hexmask.long.word 0x00 16.--27. 1. "NSWM2LGTH,NSWM2LGTH"
|
|
hexmask.long.word 0x00 0.--10. 1. "NSWM2STRT,NSWM2STRT"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TZSC_MPCWM2_NSWMR2,TZSC external memory non-secure watermark register 2"
|
|
hexmask.long.word 0x00 16.--27. 1. "NSWM2LGTH,NSWM2LGTH"
|
|
hexmask.long.word 0x00 0.--10. 1. "NSWM2STRT,NSWM2STRT"
|
|
tree.end
|
|
tree "SEC_TZIC"
|
|
base ad:0x50032800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IER1,TZIC interrupt enable register 1"
|
|
bitfld.long 0x00 31. "SPI1IE,SPI1IE" "0,1"
|
|
bitfld.long 0x00 30. "TIM1IE,TIM1IE" "0,1"
|
|
bitfld.long 0x00 29. "COMPIE,COMPIE" "0,1"
|
|
bitfld.long 0x00 28. "VREFBUFIE,VREFBUFIE" "0,1"
|
|
bitfld.long 0x00 27. "UCPD1IE,UCPD1IE" "0,1"
|
|
bitfld.long 0x00 26. "USBFSIE,USBFSIE" "0,1"
|
|
bitfld.long 0x00 25. "FDCAN1IE,FDCAN1IE" "0,1"
|
|
bitfld.long 0x00 24. "LPTIM3IE,LPTIM3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "LPTIM2IE,LPTIM2IE" "0,1"
|
|
bitfld.long 0x00 22. "I2C4IE,I2C4IE" "0,1"
|
|
bitfld.long 0x00 21. "LPUART1IE,LPUART1IE" "0,1"
|
|
bitfld.long 0x00 20. "LPTIM1IE,LPTIM1IE" "0,1"
|
|
bitfld.long 0x00 19. "OPAMPIE,OPAMPIE" "0,1"
|
|
bitfld.long 0x00 18. "DACIE,DACIE" "0,1"
|
|
bitfld.long 0x00 17. "CRSIE,CRSIE" "0,1"
|
|
bitfld.long 0x00 16. "I2C3IE,I2C3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "I2C2IE,I2C2IE" "0,1"
|
|
bitfld.long 0x00 14. "I2C1IE,I2C1IE" "0,1"
|
|
bitfld.long 0x00 13. "UART5IE,UART5IE" "0,1"
|
|
bitfld.long 0x00 12. "UART4IE,UART4IE" "0,1"
|
|
bitfld.long 0x00 11. "USART3IE,USART3IE" "0,1"
|
|
bitfld.long 0x00 10. "USART2IE,USART2IE" "0,1"
|
|
bitfld.long 0x00 9. "SPI3IE,SPI3IE" "0,1"
|
|
bitfld.long 0x00 8. "SPI2IE,SPI2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IWDGIE,IWDGIE" "0,1"
|
|
bitfld.long 0x00 6. "WWDGIE,WWDGIE" "0,1"
|
|
bitfld.long 0x00 5. "TIM7IE,TIM7IE" "0,1"
|
|
bitfld.long 0x00 4. "TIM6IE,TIM6IE" "0,1"
|
|
bitfld.long 0x00 3. "TIM5IE,TIM5IE" "0,1"
|
|
bitfld.long 0x00 2. "TIM4IE,TIM4IE" "0,1"
|
|
bitfld.long 0x00 1. "TIM3IE,TIM3IE" "0,1"
|
|
bitfld.long 0x00 0. "TIM2IE,TIM2IE" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER2,TZIC interrupt enable register 2"
|
|
bitfld.long 0x00 29. "OTFDEC1IE,OTFDEC1IE" "0,1"
|
|
bitfld.long 0x00 28. "EXTIIE,EXTIIE" "0,1"
|
|
bitfld.long 0x00 27. "FLASH_REGIE,FLASH_REGIE" "0,1"
|
|
bitfld.long 0x00 26. "FLASHIE,FLASHIE" "0,1"
|
|
bitfld.long 0x00 25. "RCCIE,RCCIE" "0,1"
|
|
bitfld.long 0x00 24. "DMAMUX1IE,DMAMUX1IE" "0,1"
|
|
bitfld.long 0x00 23. "DMA2IE,DMA2IE" "0,1"
|
|
bitfld.long 0x00 22. "DMA1IE,DMA1IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "SYSCFGIE,SYSCFGIE" "0,1"
|
|
bitfld.long 0x00 20. "PWRIE,PWRIE" "0,1"
|
|
bitfld.long 0x00 19. "RTCIE,RTCIE" "0,1"
|
|
bitfld.long 0x00 18. "OCTOSPI1_REGIE,OCTOSPI1_REGIE" "0,1"
|
|
bitfld.long 0x00 17. "FMC_REGIE,FMC_REGIE" "0,1"
|
|
bitfld.long 0x00 16. "SDMMC1IE,SDMMC1IE" "0,1"
|
|
bitfld.long 0x00 15. "PKAIE,PKAIE" "0,1"
|
|
bitfld.long 0x00 14. "RNGIE,RNGIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "HASHIE,HASHIE" "0,1"
|
|
bitfld.long 0x00 12. "AESIE,AESIE" "0,1"
|
|
bitfld.long 0x00 11. "ADCIE,ADCIE" "0,1"
|
|
bitfld.long 0x00 10. "ICACHEIE,ICACHEIE" "0,1"
|
|
bitfld.long 0x00 9. "TSCIE,TSCIE" "0,1"
|
|
bitfld.long 0x00 8. "CRCIE,CRCIE" "0,1"
|
|
bitfld.long 0x00 7. "DFSDM1IE,DFSDM1IE" "0,1"
|
|
bitfld.long 0x00 6. "SAI2IE,SAI2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SAI1IE,SAI1IE" "0,1"
|
|
bitfld.long 0x00 4. "TIM17IE,TIM17IE" "0,1"
|
|
bitfld.long 0x00 3. "TIM16IE,TIM16IE" "0,1"
|
|
bitfld.long 0x00 2. "TIM15IE,TIM15IE" "0,1"
|
|
bitfld.long 0x00 1. "USART1IE,USART1IE" "0,1"
|
|
bitfld.long 0x00 0. "TIM8IE,TIM8IE" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IER3,TZIC interrupt enable register 3"
|
|
bitfld.long 0x00 7. "MPCBB2_REGIE,MPCBB2_REGIE" "0,1"
|
|
bitfld.long 0x00 6. "MPCBB2IE,MPCBB2IE" "0,1"
|
|
bitfld.long 0x00 5. "MPCBB1_REGIE,MPCBB1_REGIE" "0,1"
|
|
bitfld.long 0x00 4. "MPCBB1IE,MPCBB1IE" "0,1"
|
|
bitfld.long 0x00 3. "MPCWM2IE,MPCWM2IE" "0,1"
|
|
bitfld.long 0x00 2. "MPCWM1IE,MPCWM1IE" "0,1"
|
|
bitfld.long 0x00 1. "TZICIE,TZICIE" "0,1"
|
|
bitfld.long 0x00 0. "TZSCIE,TZSCIE" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SR1,TZIC interrupt status register 1"
|
|
bitfld.long 0x00 31. "SPI1F,SPI1F" "0,1"
|
|
bitfld.long 0x00 30. "TIM1F,TIM1F" "0,1"
|
|
bitfld.long 0x00 29. "COMPF,COMPF" "0,1"
|
|
bitfld.long 0x00 28. "VREFBUFF,VREFBUFF" "0,1"
|
|
bitfld.long 0x00 27. "UCPD1F,UCPD1F" "0,1"
|
|
bitfld.long 0x00 26. "USBFSF,USBFSF" "0,1"
|
|
bitfld.long 0x00 25. "FDCAN1F,FDCAN1F" "0,1"
|
|
bitfld.long 0x00 24. "LPTIM3F,LPTIM3F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "LPTIM2F,LPTIM2F" "0,1"
|
|
bitfld.long 0x00 22. "I2C4F,I2C4F" "0,1"
|
|
bitfld.long 0x00 21. "LPUART1F,LPUART1F" "0,1"
|
|
bitfld.long 0x00 20. "LPTIM1F,LPTIM1F" "0,1"
|
|
bitfld.long 0x00 19. "OPAMPF,OPAMPF" "0,1"
|
|
bitfld.long 0x00 18. "DACF,DACF" "0,1"
|
|
bitfld.long 0x00 17. "CRSF,CRSF" "0,1"
|
|
bitfld.long 0x00 16. "I2C3F,I2C3F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "I2C2F,I2C2F" "0,1"
|
|
bitfld.long 0x00 14. "I2C1F,I2C1F" "0,1"
|
|
bitfld.long 0x00 13. "UART5F,UART5F" "0,1"
|
|
bitfld.long 0x00 12. "UART4F,UART4F" "0,1"
|
|
bitfld.long 0x00 11. "USART3F,USART3F" "0,1"
|
|
bitfld.long 0x00 10. "USART2F,USART2F" "0,1"
|
|
bitfld.long 0x00 9. "SPI3F,SPI3F" "0,1"
|
|
bitfld.long 0x00 8. "SPI2F,SPI2F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IWDGF,IWDGF" "0,1"
|
|
bitfld.long 0x00 6. "WWDGF,WWDGF" "0,1"
|
|
bitfld.long 0x00 5. "TIM7F,TIM7F" "0,1"
|
|
bitfld.long 0x00 4. "TIM6F,TIM6F" "0,1"
|
|
bitfld.long 0x00 3. "TIM5F,TIM5F" "0,1"
|
|
bitfld.long 0x00 2. "TIM4F,TIM4F" "0,1"
|
|
bitfld.long 0x00 1. "TIM3F,TIM3F" "0,1"
|
|
bitfld.long 0x00 0. "TIM2F,TIM2F" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR2,TZIC interrupt status register 2"
|
|
bitfld.long 0x00 29. "OTFDEC1F,OTFDEC1F" "0,1"
|
|
bitfld.long 0x00 28. "EXTIF,EXTIF" "0,1"
|
|
bitfld.long 0x00 27. "FLASH_REGF,FLASH_REGF" "0,1"
|
|
bitfld.long 0x00 26. "FLASHF,FLASHF" "0,1"
|
|
bitfld.long 0x00 25. "RCCF,RCCF" "0,1"
|
|
bitfld.long 0x00 24. "DMAMUX1F,DMAMUX1F" "0,1"
|
|
bitfld.long 0x00 23. "DMA2F,DMA2F" "0,1"
|
|
bitfld.long 0x00 22. "DMA1F,DMA1F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "SYSCFGF,SYSCFGF" "0,1"
|
|
bitfld.long 0x00 20. "PWRF,PWRF" "0,1"
|
|
bitfld.long 0x00 19. "RTCF,RTCF" "0,1"
|
|
bitfld.long 0x00 18. "OCTOSPI1_REGF,OCTOSPI1_REGF" "0,1"
|
|
bitfld.long 0x00 17. "FMC_REGF,FMC_REGF" "0,1"
|
|
bitfld.long 0x00 16. "SDMMC1F,SDMMC1F" "0,1"
|
|
bitfld.long 0x00 15. "PKAF,PKAF" "0,1"
|
|
bitfld.long 0x00 14. "RNGF,RNGF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "HASHF,HASHF" "0,1"
|
|
bitfld.long 0x00 12. "AESF,AESF" "0,1"
|
|
bitfld.long 0x00 11. "ADCF,ADCF" "0,1"
|
|
bitfld.long 0x00 10. "ICACHEF,ICACHEF" "0,1"
|
|
bitfld.long 0x00 9. "TSCF,TSCF" "0,1"
|
|
bitfld.long 0x00 8. "CRCF,CRCF" "0,1"
|
|
bitfld.long 0x00 7. "DFSDM1F,DFSDM1F" "0,1"
|
|
bitfld.long 0x00 6. "SAI2F,SAI2F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SAI1F,SAI1F" "0,1"
|
|
bitfld.long 0x00 4. "TIM17F,TIM17F" "0,1"
|
|
bitfld.long 0x00 3. "TIM16F,TIM16F" "0,1"
|
|
bitfld.long 0x00 2. "TIM15F,TIM15F" "0,1"
|
|
bitfld.long 0x00 1. "USART1F,USART1F" "0,1"
|
|
bitfld.long 0x00 0. "TIM8F,TIM8F" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SR3,TZIC interrupt status register 3"
|
|
bitfld.long 0x00 7. "MPCBB2_REGF,MPCBB2_REGF" "0,1"
|
|
bitfld.long 0x00 6. "MPCBB2F,MPCBB2F" "0,1"
|
|
bitfld.long 0x00 5. "MPCBB1_REGF,MPCBB1_REGF" "0,1"
|
|
bitfld.long 0x00 4. "MPCBB1F,MPCBB1F" "0,1"
|
|
bitfld.long 0x00 3. "MPCWM2F,MPCWM2F" "0,1"
|
|
bitfld.long 0x00 2. "MPCWM1F,MPCWM1F" "0,1"
|
|
bitfld.long 0x00 1. "TZICF,TZICF" "0,1"
|
|
bitfld.long 0x00 0. "TZSCF,TZSCF" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "FCR1,TZIC interrupt clear register 1"
|
|
bitfld.long 0x00 31. "SPI1FC,SPI1FC" "0,1"
|
|
bitfld.long 0x00 30. "TIM1FC,TIM1FC" "0,1"
|
|
bitfld.long 0x00 29. "COMPFC,COMPFC" "0,1"
|
|
bitfld.long 0x00 28. "VREFBUFFC,VREFBUFFC" "0,1"
|
|
bitfld.long 0x00 27. "UCPD1FC,UCPD1FC" "0,1"
|
|
bitfld.long 0x00 26. "USBFSFC,USBFSFC" "0,1"
|
|
bitfld.long 0x00 25. "FDCAN1FC,FDCAN1FC" "0,1"
|
|
bitfld.long 0x00 24. "LPTIM3FC,LPTIM3FC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "LPTIM2FC,LPTIM2FC" "0,1"
|
|
bitfld.long 0x00 22. "I2C4FC,I2C4FC" "0,1"
|
|
bitfld.long 0x00 21. "LPUART1FC,LPUART1FC" "0,1"
|
|
bitfld.long 0x00 20. "LPTIM1FC,LPTIM1FC" "0,1"
|
|
bitfld.long 0x00 19. "OPAMPFC,OPAMPFC" "0,1"
|
|
bitfld.long 0x00 18. "DACFC,DACFC" "0,1"
|
|
bitfld.long 0x00 17. "CRSFC,CRSFC" "0,1"
|
|
bitfld.long 0x00 16. "I2C3FC,I2C3FC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "I2C2FC,I2C2FC" "0,1"
|
|
bitfld.long 0x00 14. "I2C1FC,I2C1FC" "0,1"
|
|
bitfld.long 0x00 13. "UART5FC,UART5FC" "0,1"
|
|
bitfld.long 0x00 12. "UART4FC,UART4FC" "0,1"
|
|
bitfld.long 0x00 11. "USART3FC,USART3FC" "0,1"
|
|
bitfld.long 0x00 10. "USART2FC,USART2FC" "0,1"
|
|
bitfld.long 0x00 9. "SPI3FC,SPI3FC" "0,1"
|
|
bitfld.long 0x00 8. "SPI2FC,SPI2FC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IWDGFC,IWDGFC" "0,1"
|
|
bitfld.long 0x00 6. "WWDGFC,WWDGFC" "0,1"
|
|
bitfld.long 0x00 5. "TIM7FC,TIM7FC" "0,1"
|
|
bitfld.long 0x00 4. "TIM6FC,TIM6FC" "0,1"
|
|
bitfld.long 0x00 3. "TIM5FC,TIM5FC" "0,1"
|
|
bitfld.long 0x00 2. "TIM4FC,TIM4FC" "0,1"
|
|
bitfld.long 0x00 1. "TIM3FC,TIM3FC" "0,1"
|
|
bitfld.long 0x00 0. "TIM2FC,TIM2FC" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICR2,TZIC interrupt clear register 2"
|
|
bitfld.long 0x00 29. "OTFDEC1FC,OTFDEC1FC" "0,1"
|
|
bitfld.long 0x00 28. "EXTIFC,EXTIFC" "0,1"
|
|
bitfld.long 0x00 27. "FLASH_REGFC,FLASH_REGFC" "0,1"
|
|
bitfld.long 0x00 26. "FLASHFC,FLASHFC" "0,1"
|
|
bitfld.long 0x00 25. "RCCFC,RCCFC" "0,1"
|
|
bitfld.long 0x00 24. "DMAMUX1FC,DMAMUX1FC" "0,1"
|
|
bitfld.long 0x00 23. "DMA2FC,DMA2FC" "0,1"
|
|
bitfld.long 0x00 22. "DMA1FC,DMA1FC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "SYSCFGFC,SYSCFGFC" "0,1"
|
|
bitfld.long 0x00 20. "PWRFC,PWRFC" "0,1"
|
|
bitfld.long 0x00 19. "RTCFC,RTCFC" "0,1"
|
|
bitfld.long 0x00 18. "OCTOSPI1_REGFC,OCTOSPI1_REGFC" "0,1"
|
|
bitfld.long 0x00 17. "FMC_REGFC,FMC_REGFC" "0,1"
|
|
bitfld.long 0x00 16. "SDMMC1FC,SDMMC1FC" "0,1"
|
|
bitfld.long 0x00 15. "PKAFC,PKAFC" "0,1"
|
|
bitfld.long 0x00 14. "RNGFC,RNGFC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "HASHFC,HASHFC" "0,1"
|
|
bitfld.long 0x00 12. "AESFC,AESFC" "0,1"
|
|
bitfld.long 0x00 11. "ADCFC,ADCFC" "0,1"
|
|
bitfld.long 0x00 10. "ICACHEFC,ICACHEFC" "0,1"
|
|
bitfld.long 0x00 9. "TSCFC,TSCFC" "0,1"
|
|
bitfld.long 0x00 8. "CRCFC,CRCFC" "0,1"
|
|
bitfld.long 0x00 7. "DFSDM1FC,DFSDM1FC" "0,1"
|
|
bitfld.long 0x00 6. "SAI2FC,SAI2FC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SAI1FC,SAI1FC" "0,1"
|
|
bitfld.long 0x00 4. "TIM17FC,TIM17FC" "0,1"
|
|
bitfld.long 0x00 3. "TIM16FC,TIM16FC" "0,1"
|
|
bitfld.long 0x00 2. "TIM15FC,TIM15FC" "0,1"
|
|
bitfld.long 0x00 1. "USART1FC,USART1FC" "0,1"
|
|
bitfld.long 0x00 0. "TIM8FC,TIM8FC" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FCR3,TZIC interrupt clear register 3"
|
|
bitfld.long 0x00 7. "MPCBB2_REGFC,MPCBB2_REGFC" "0,1"
|
|
bitfld.long 0x00 6. "MPCBB2FC,MPCBB2FC" "0,1"
|
|
bitfld.long 0x00 5. "MPCBB1_REGFC,MPCBB1_REGFC" "0,1"
|
|
bitfld.long 0x00 4. "MPCBB1FC,MPCBB1FC" "0,1"
|
|
bitfld.long 0x00 3. "MPCWM2FC,MPCWM2FC" "0,1"
|
|
bitfld.long 0x00 2. "MPCWM1FC,MPCWM1FC" "0,1"
|
|
bitfld.long 0x00 1. "TZICFC,TZICFC" "0,1"
|
|
bitfld.long 0x00 0. "TZSCFC,TZSCFC" "0,1"
|
|
tree.end
|
|
tree "SEC_TZSC"
|
|
base ad:0x50032400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TZSC_CR,TZSC control register"
|
|
bitfld.long 0x00 0. "LCK,LCK" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TZSC_SECCFGR1,TZSC secure configuration register 1"
|
|
bitfld.long 0x00 31. "SPI1SEC,SPI1SEC" "0,1"
|
|
bitfld.long 0x00 30. "TIM1SEC,TIM1SEC" "0,1"
|
|
bitfld.long 0x00 29. "COMPSEC,COMPSEC" "0,1"
|
|
bitfld.long 0x00 28. "VREFBUFSEC,VREFBUFSEC" "0,1"
|
|
bitfld.long 0x00 27. "UCPD1SEC,UCPD1SEC" "0,1"
|
|
bitfld.long 0x00 26. "USBFSSEC,USBFSSEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "FDCAN1SEC,FDCAN1SEC" "0,1"
|
|
bitfld.long 0x00 24. "LPTIM3SEC,LPTIM3SEC" "0,1"
|
|
bitfld.long 0x00 23. "LPTIM2SEC,LPTIM2SEC" "0,1"
|
|
bitfld.long 0x00 22. "I2C4SEC,I2C4SEC" "0,1"
|
|
bitfld.long 0x00 21. "LPUART1SEC,LPUART1SEC" "0,1"
|
|
bitfld.long 0x00 20. "LPTIM1SEC,LPTIM1SEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "OPAMPSEC,OPAMPSEC" "0,1"
|
|
bitfld.long 0x00 18. "DACSEC,DACSEC" "0,1"
|
|
bitfld.long 0x00 17. "CRSSEC,CRSSEC" "0,1"
|
|
bitfld.long 0x00 16. "I2C3SEC,I2C3SEC" "0,1"
|
|
bitfld.long 0x00 15. "I2C2SEC,I2C2SEC" "0,1"
|
|
bitfld.long 0x00 14. "I2C1SEC,I2C1SEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "UART5SEC,UART5SEC" "0,1"
|
|
bitfld.long 0x00 12. "UART4SEC,UART4SEC" "0,1"
|
|
bitfld.long 0x00 11. "USART3SEC,USART3SEC" "0,1"
|
|
bitfld.long 0x00 10. "USART2SEC,USART2SEC" "0,1"
|
|
bitfld.long 0x00 9. "SPI3SEC,SPI3SEC" "0,1"
|
|
bitfld.long 0x00 8. "SPI2SEC,SPI2SEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IWDGSEC,IWDGSEC" "0,1"
|
|
bitfld.long 0x00 6. "WWDGSEC,WWDGSEC" "0,1"
|
|
bitfld.long 0x00 5. "TIM7SEC,TIM7SEC" "0,1"
|
|
bitfld.long 0x00 4. "TIM6SEC,TIM6SEC" "0,1"
|
|
bitfld.long 0x00 3. "TIM5SEC,TIM5SEC" "0,1"
|
|
bitfld.long 0x00 2. "TIM4SEC,TIM4SEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TIM3SEC,TIM3SEC" "0,1"
|
|
bitfld.long 0x00 0. "TIM2SEC,TIM2SEC" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TZSC_SECCFGR2,TZSC secure configuration register 2"
|
|
bitfld.long 0x00 18. "OCTOSPI1_REGSEC,OCTOSPI1_REGSEC" "0,1"
|
|
bitfld.long 0x00 17. "FSMC_REGSEC,FSMC_REGSEC" "0,1"
|
|
bitfld.long 0x00 16. "SDMMC1SEC,SDMMC1SEC" "0,1"
|
|
bitfld.long 0x00 15. "PKASEC,PKASEC" "0,1"
|
|
bitfld.long 0x00 14. "RNGSEC,RNGSEC" "0,1"
|
|
bitfld.long 0x00 13. "HASHSEC,HASHSEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "AESSEC,AESSEC" "0,1"
|
|
bitfld.long 0x00 11. "ADCSEC,ADCSEC" "0,1"
|
|
bitfld.long 0x00 10. "ICACHESEC,ICACHESEC" "0,1"
|
|
bitfld.long 0x00 9. "TSCSEC,TSCSEC" "0,1"
|
|
bitfld.long 0x00 8. "CRCSEC,CRCSEC" "0,1"
|
|
bitfld.long 0x00 7. "DFSDM1SEC,DFSDM1SEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SAI2SEC,SAI2SEC" "0,1"
|
|
bitfld.long 0x00 5. "SAI1SEC,SAI1SEC" "0,1"
|
|
bitfld.long 0x00 4. "TIM17SEC,TIM17SEC" "0,1"
|
|
bitfld.long 0x00 3. "TIM16SEC,TIM16SEC" "0,1"
|
|
bitfld.long 0x00 2. "TIM15SEC,TIM15SEC" "0,1"
|
|
bitfld.long 0x00 1. "USART1SEC,USART1SEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TIM8SEC,TIM8SEC" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TZSC_PRIVCFGR1,TZSC privilege configuration register 1"
|
|
bitfld.long 0x00 31. "SPI1PRIV,SPI1PRIV" "0,1"
|
|
bitfld.long 0x00 30. "TIM1PRIV,TIM1PRIV" "0,1"
|
|
bitfld.long 0x00 29. "COMPPRIV,COMPPRIV" "0,1"
|
|
bitfld.long 0x00 28. "VREFBUFPRIV,VREFBUFPRIV" "0,1"
|
|
bitfld.long 0x00 27. "UCPD1PRIV,UCPD1PRIV" "0,1"
|
|
bitfld.long 0x00 26. "USBFSPRIV,USBFSPRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "FDCAN1PRIV,FDCAN1PRIV" "0,1"
|
|
bitfld.long 0x00 24. "LPTIM3PRIV,LPTIM3PRIV" "0,1"
|
|
bitfld.long 0x00 23. "LPTIM2PRIV,LPTIM2PRIV" "0,1"
|
|
bitfld.long 0x00 22. "I2C4PRIV,I2C4PRIV" "0,1"
|
|
bitfld.long 0x00 21. "LPUART1PRIV,LPUART1PRIV" "0,1"
|
|
bitfld.long 0x00 20. "LPTIM1PRIV,LPTIM1PRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "OPAMPPRIV,OPAMPPRIV" "0,1"
|
|
bitfld.long 0x00 18. "DACPRIV,DACPRIV" "0,1"
|
|
bitfld.long 0x00 17. "CRSPRIV,CRSPRIV" "0,1"
|
|
bitfld.long 0x00 16. "I2C3PRIV,I2C3PRIV" "0,1"
|
|
bitfld.long 0x00 15. "I2C2PRIV,I2C2PRIV" "0,1"
|
|
bitfld.long 0x00 14. "I2C1PRIV,I2C1PRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "UART5PRIV,UART5PRIV" "0,1"
|
|
bitfld.long 0x00 12. "UART4PRIV,UART4PRIV" "0,1"
|
|
bitfld.long 0x00 11. "USART3PRIV,USART3PRIV" "0,1"
|
|
bitfld.long 0x00 10. "USART2PRIV,USART2PRIV" "0,1"
|
|
bitfld.long 0x00 9. "SPI3PRIV,SPI3PRIV" "0,1"
|
|
bitfld.long 0x00 8. "SPI2PRIV,SPI2PRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "IWDGPRIV,IWDGPRIV" "0,1"
|
|
bitfld.long 0x00 6. "WWDGPRIV,WWDGPRIV" "0,1"
|
|
bitfld.long 0x00 5. "TIM7PRIV,TIM7PRIV" "0,1"
|
|
bitfld.long 0x00 4. "TIM6PRIV,TIM6PRIV" "0,1"
|
|
bitfld.long 0x00 3. "TIM5PRIV,TIM5PRIV" "0,1"
|
|
bitfld.long 0x00 2. "TIM4PRIV,TIM4PRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TIM3PRIV,TIM3PRIV" "0,1"
|
|
bitfld.long 0x00 0. "TIM2PRIV,TIM2PRIV" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TZSC_PRIVCFGR2,TZSC privilege configuration register 2"
|
|
bitfld.long 0x00 18. "OCTOSPI1_REGPRIV,OCTOSPI1_REGRIV" "0,1"
|
|
bitfld.long 0x00 17. "FSMC_REGPRIV,FSMC_REGPRIV" "0,1"
|
|
bitfld.long 0x00 16. "SDMMC1PRIV,SDMMC1PRIV" "0,1"
|
|
bitfld.long 0x00 15. "PKAPRIV,PKAPRIV" "0,1"
|
|
bitfld.long 0x00 14. "RNGPRIV,RNGPRIV" "0,1"
|
|
bitfld.long 0x00 13. "HASHPRIV,HASHPRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "AESPRIV,AESPRIV" "0,1"
|
|
bitfld.long 0x00 11. "ADCPRIV,ADCPRIV" "0,1"
|
|
bitfld.long 0x00 10. "ICACHEPRIV,ICACHEPRIV" "0,1"
|
|
bitfld.long 0x00 9. "TSCPRIV,TSCPRIV" "0,1"
|
|
bitfld.long 0x00 8. "CRCPRIV,CRCPRIV" "0,1"
|
|
bitfld.long 0x00 7. "DFSDM1PRIV,DFSDM1PRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SAI2PRIV,SAI2PRIV" "0,1"
|
|
bitfld.long 0x00 5. "SAI1PRIV,SAI1PRIV" "0,1"
|
|
bitfld.long 0x00 4. "TIM17PRIV,TIM17PRIV" "0,1"
|
|
bitfld.long 0x00 3. "TIM16PRIV,TIM16PRIV" "0,1"
|
|
bitfld.long 0x00 2. "TIM15PRIV,TIM15PRIV" "0,1"
|
|
bitfld.long 0x00 1. "USART1PRIV,USART1PRIV" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TIM8PRIV,TIM8PRIV" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TZSC_MPCWM1_NSWMR1,TZSC external memory non-secure watermark register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. "NSWM1LGTH,NSWM1LGTH"
|
|
hexmask.long.word 0x00 0.--10. 1. "NSWM1STRT,NSWM1STRT"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TZSC_MPCWM1_NSWMR2,TZSC external memory non-secure watermark register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. "NSWM2LGTH,NSWM2LGTH"
|
|
hexmask.long.word 0x00 0.--10. 1. "NSWM2STRT,NSWM2STRT"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TZSC_MPCWM2_NSWMR1,TZSC external memory non-secure watermark register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. "NSWM1LGTH,NSWM1LGTH"
|
|
hexmask.long.word 0x00 0.--10. 1. "NSWM1STRT,NSWM1STRT"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TZSC_MPCWM3_NSWMR1,TZSC external memory non-secure watermark register 2"
|
|
hexmask.long.word 0x00 16.--27. 1. "NSWM2LGTH,NSWM2LGTH"
|
|
hexmask.long.word 0x00 0.--10. 1. "NSWM2STRT,NSWM2STRT"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TZSC_MPCWM2_NSWMR2,TZSC external memory non-secure watermark register 2"
|
|
hexmask.long.word 0x00 16.--27. 1. "NSWM2LGTH,NSWM2LGTH"
|
|
hexmask.long.word 0x00 0.--10. 1. "NSWM2STRT,NSWM2STRT"
|
|
tree.end
|
|
tree.end
|
|
tree "HASH (Hash processor)"
|
|
tree "HASH"
|
|
base ad:0x420C0400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,control register"
|
|
bitfld.long 0x00 18. "ALGO1,Algorithm selection" "0,1"
|
|
bitfld.long 0x00 16. "LKEY,Long key selection" "0,1"
|
|
bitfld.long 0x00 13. "MDMAT,Multiple DMA Transfers" "0,1"
|
|
rbitfld.long 0x00 12. "DINNE,DIN not empty" "0,1"
|
|
rbitfld.long 0x00 8.--11. "NBW,Number of words already pushed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "ALGO0,Algorithm selection" "0,1"
|
|
bitfld.long 0x00 6. "MODE,Mode selection" "0,1"
|
|
bitfld.long 0x00 4.--5. "DATATYPE,Data type selection" "0,1,2,3"
|
|
bitfld.long 0x00 3. "DMAE,DMA enable" "0,1"
|
|
bitfld.long 0x00 2. "INIT,Initialize message digest calculation" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DIN,data input register"
|
|
hexmask.long 0x00 0.--31. 1. "DATAIN,Data input"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "STR,start register"
|
|
bitfld.long 0x00 8. "DCAL,Digest calculation" "0,1"
|
|
bitfld.long 0x00 0.--4. "NBLW,Number of valid bits in the last word of the message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "HRA0,HASH aliased digest register 0"
|
|
hexmask.long 0x00 0.--31. 1. "H0,H0"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "HRA1,HASH aliased digest register 1"
|
|
hexmask.long 0x00 0.--31. 1. "H1,H1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "HRA2,HASH aliased digest register 2"
|
|
hexmask.long 0x00 0.--31. 1. "H2,H2"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "HRA3,HASH aliased digest register 3"
|
|
hexmask.long 0x00 0.--31. 1. "H3,H3"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "HRA4,HASH aliased digest register 4"
|
|
hexmask.long 0x00 0.--31. 1. "H4,H4"
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "HR0,digest register 0"
|
|
hexmask.long 0x00 0.--31. 1. "H0,H0"
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "HR1,digest register 1"
|
|
hexmask.long 0x00 0.--31. 1. "H1,H1"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "HR2,digest register 4"
|
|
hexmask.long 0x00 0.--31. 1. "H2,H2"
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "HR3,digest register 3"
|
|
hexmask.long 0x00 0.--31. 1. "H3,H3"
|
|
rgroup.long 0x320++0x03
|
|
line.long 0x00 "HR4,digest register 4"
|
|
hexmask.long 0x00 0.--31. 1. "H4,H4"
|
|
rgroup.long 0x324++0x03
|
|
line.long 0x00 "HR5,supplementary digest register 5"
|
|
hexmask.long 0x00 0.--31. 1. "H5,H5"
|
|
rgroup.long 0x328++0x03
|
|
line.long 0x00 "HR6,supplementary digest register 6"
|
|
hexmask.long 0x00 0.--31. 1. "H6,H6"
|
|
rgroup.long 0x32C++0x03
|
|
line.long 0x00 "HR7,supplementary digest register 7"
|
|
hexmask.long 0x00 0.--31. 1. "H7,H7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IMR,interrupt enable register"
|
|
bitfld.long 0x00 1. "DCIE,Digest calculation completion interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "DINIE,Data input interrupt enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SR,status register"
|
|
rbitfld.long 0x00 3. "BUSY,Busy bit" "0,1"
|
|
rbitfld.long 0x00 2. "DMAS,DMA Status" "0,1"
|
|
bitfld.long 0x00 1. "DCIS,Digest calculation completion interrupt status" "0,1"
|
|
bitfld.long 0x00 0. "DINIS,Data input interrupt status" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CSR0,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR0,CSR0"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CSR1,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR1,CSR1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CSR2,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR2,CSR2"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "CSR3,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR3,CSR3"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CSR4,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR4,CSR4"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "CSR5,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR5,CSR5"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CSR6,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR6,CSR6"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CSR7,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR7,CSR7"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CSR8,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR8,CSR8"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CSR9,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR9,CSR9"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CSR10,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR10,CSR10"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CSR11,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR11,CSR11"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CSR12,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR12,CSR12"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CSR13,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR13,CSR13"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CSR14,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR14,CSR14"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CSR15,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR15,CSR15"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CSR16,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR16,CSR16"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "CSR17,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR17,CSR17"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CSR18,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR18,CSR18"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CSR19,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR19,CSR19"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "CSR20,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR20,CSR20"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "CSR21,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR21,CSR21"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CSR22,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR22,CSR22"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "CSR23,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR23,CSR23"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "CSR24,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR24,CSR24"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CSR25,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR25,CSR25"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "CSR26,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR26,CSR26"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CSR27,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR27,CSR27"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CSR28,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR28,CSR28"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "CSR29,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR29,CSR29"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CSR30,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR30,CSR30"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CSR31,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR31,CSR31"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "CSR32,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR32,CSR32"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "CSR33,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR33,CSR33"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CSR34,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR34,CSR34"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "CSR35,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR35,CSR35"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "CSR36,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR36,CSR36"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CSR37,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR37,CSR37"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CSR38,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR38,CSR38"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "CSR39,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR39,CSR39"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CSR40,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR40,CSR40"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "CSR41,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR41,CSR41"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CSR42,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR42,CSR42"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CSR43,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR43,CSR43"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "CSR44,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR44,CSR44"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "CSR45,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR45,CSR45"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CSR46,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR46,CSR46"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "CSR47,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR47,CSR47"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "CSR48,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR48,CSR48"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CSR49,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR49,CSR49"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CSR50,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR50,CSR50"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "CSR51,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR51,CSR51"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "CSR52,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR52,CSR52"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "CSR53,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR53,CSR53"
|
|
tree.end
|
|
tree "SEC_HASH"
|
|
base ad:0x520C0400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,control register"
|
|
bitfld.long 0x00 18. "ALGO1,Algorithm selection" "0,1"
|
|
bitfld.long 0x00 16. "LKEY,Long key selection" "0,1"
|
|
bitfld.long 0x00 13. "MDMAT,Multiple DMA Transfers" "0,1"
|
|
rbitfld.long 0x00 12. "DINNE,DIN not empty" "0,1"
|
|
rbitfld.long 0x00 8.--11. "NBW,Number of words already pushed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "ALGO0,Algorithm selection" "0,1"
|
|
bitfld.long 0x00 6. "MODE,Mode selection" "0,1"
|
|
bitfld.long 0x00 4.--5. "DATATYPE,Data type selection" "0,1,2,3"
|
|
bitfld.long 0x00 3. "DMAE,DMA enable" "0,1"
|
|
bitfld.long 0x00 2. "INIT,Initialize message digest calculation" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DIN,data input register"
|
|
hexmask.long 0x00 0.--31. 1. "DATAIN,Data input"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "STR,start register"
|
|
bitfld.long 0x00 8. "DCAL,Digest calculation" "0,1"
|
|
bitfld.long 0x00 0.--4. "NBLW,Number of valid bits in the last word of the message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "HRA0,HASH aliased digest register 0"
|
|
hexmask.long 0x00 0.--31. 1. "H0,H0"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "HRA1,HASH aliased digest register 1"
|
|
hexmask.long 0x00 0.--31. 1. "H1,H1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "HRA2,HASH aliased digest register 2"
|
|
hexmask.long 0x00 0.--31. 1. "H2,H2"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "HRA3,HASH aliased digest register 3"
|
|
hexmask.long 0x00 0.--31. 1. "H3,H3"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "HRA4,HASH aliased digest register 4"
|
|
hexmask.long 0x00 0.--31. 1. "H4,H4"
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "HR0,digest register 0"
|
|
hexmask.long 0x00 0.--31. 1. "H0,H0"
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "HR1,digest register 1"
|
|
hexmask.long 0x00 0.--31. 1. "H1,H1"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "HR2,digest register 4"
|
|
hexmask.long 0x00 0.--31. 1. "H2,H2"
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "HR3,digest register 3"
|
|
hexmask.long 0x00 0.--31. 1. "H3,H3"
|
|
rgroup.long 0x320++0x03
|
|
line.long 0x00 "HR4,digest register 4"
|
|
hexmask.long 0x00 0.--31. 1. "H4,H4"
|
|
rgroup.long 0x324++0x03
|
|
line.long 0x00 "HR5,supplementary digest register 5"
|
|
hexmask.long 0x00 0.--31. 1. "H5,H5"
|
|
rgroup.long 0x328++0x03
|
|
line.long 0x00 "HR6,supplementary digest register 6"
|
|
hexmask.long 0x00 0.--31. 1. "H6,H6"
|
|
rgroup.long 0x32C++0x03
|
|
line.long 0x00 "HR7,supplementary digest register 7"
|
|
hexmask.long 0x00 0.--31. 1. "H7,H7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IMR,interrupt enable register"
|
|
bitfld.long 0x00 1. "DCIE,Digest calculation completion interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "DINIE,Data input interrupt enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SR,status register"
|
|
rbitfld.long 0x00 3. "BUSY,Busy bit" "0,1"
|
|
rbitfld.long 0x00 2. "DMAS,DMA Status" "0,1"
|
|
bitfld.long 0x00 1. "DCIS,Digest calculation completion interrupt status" "0,1"
|
|
bitfld.long 0x00 0. "DINIS,Data input interrupt status" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CSR0,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR0,CSR0"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CSR1,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR1,CSR1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CSR2,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR2,CSR2"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "CSR3,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR3,CSR3"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CSR4,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR4,CSR4"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "CSR5,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR5,CSR5"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CSR6,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR6,CSR6"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CSR7,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR7,CSR7"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CSR8,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR8,CSR8"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CSR9,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR9,CSR9"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CSR10,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR10,CSR10"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CSR11,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR11,CSR11"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CSR12,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR12,CSR12"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CSR13,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR13,CSR13"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CSR14,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR14,CSR14"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CSR15,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR15,CSR15"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CSR16,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR16,CSR16"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "CSR17,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR17,CSR17"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CSR18,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR18,CSR18"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CSR19,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR19,CSR19"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "CSR20,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR20,CSR20"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "CSR21,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR21,CSR21"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CSR22,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR22,CSR22"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "CSR23,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR23,CSR23"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "CSR24,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR24,CSR24"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CSR25,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR25,CSR25"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "CSR26,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR26,CSR26"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CSR27,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR27,CSR27"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CSR28,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR28,CSR28"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "CSR29,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR29,CSR29"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CSR30,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR30,CSR30"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CSR31,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR31,CSR31"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "CSR32,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR32,CSR32"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "CSR33,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR33,CSR33"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CSR34,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR34,CSR34"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "CSR35,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR35,CSR35"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "CSR36,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR36,CSR36"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CSR37,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR37,CSR37"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CSR38,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR38,CSR38"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "CSR39,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR39,CSR39"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CSR40,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR40,CSR40"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "CSR41,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR41,CSR41"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CSR42,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR42,CSR42"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CSR43,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR43,CSR43"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "CSR44,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR44,CSR44"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "CSR45,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR45,CSR45"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CSR46,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR46,CSR46"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "CSR47,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR47,CSR47"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "CSR48,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR48,CSR48"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CSR49,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR49,CSR49"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CSR50,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR50,CSR50"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "CSR51,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR51,CSR51"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "CSR52,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR52,CSR52"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "CSR53,context swap registers"
|
|
hexmask.long 0x00 0.--31. 1. "CSR53,CSR53"
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
repeat 4. (list 1. 2. 3. 4.) (list ad:0x40005400 ad:0x40005800 ad:0x40005C00 ad:0x40008400)
|
|
tree "I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control register 1"
|
|
bitfld.long 0x00 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x00 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x00 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x00 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x00 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x00 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x00 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x00 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x00 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x00 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
bitfld.long 0x00 8.--11. "DNF,Digital noise filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x00 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x00 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "PE,Peripheral enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control register 2"
|
|
bitfld.long 0x00 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x00 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x00 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x00 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x00 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x00 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x00 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x00 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OAR1,Own address register 1"
|
|
bitfld.long 0x00 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x00 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "OA1,Interface address"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OAR2,Own address register 2"
|
|
bitfld.long 0x00 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0x00 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 1.--7. 1. "OA2,Interface address"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing register"
|
|
bitfld.long 0x00 28.--31. "PRESC,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "SCLDEL,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "SDADEL,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x00 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x00 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x00 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x00 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x00 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x00 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x00 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x00 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x00 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x00 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x00 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x00 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x00 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x00 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x00 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x00 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x00 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x00 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x00 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x00 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "ICR,Interrupt clear register"
|
|
bitfld.long 0x00 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x00 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x00 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x00 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x00 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x00 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x00 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x00 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x00 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PECR,PEC register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PEC,Packet error checking register"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
repeat.end
|
|
repeat 4. (list 1. 2. 3. 4.) (list ad:0x50005400 ad:0x50005800 ad:0x50005C00 ad:0x50008400)
|
|
tree "SEC_I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control register 1"
|
|
bitfld.long 0x00 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x00 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x00 21. "SMBDEN,SMBus Device Default address enable" "0,1"
|
|
bitfld.long 0x00 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x00 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x00 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x00 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x00 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x00 15. "RXDMAEN,DMA reception requests enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "TXDMAEN,DMA transmission requests enable" "0,1"
|
|
bitfld.long 0x00 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
bitfld.long 0x00 8.--11. "DNF,Digital noise filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x00 6. "TCIE,Transfer Complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "STOPIE,STOP detection Interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "NACKIE,Not acknowledge received interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "ADDRIE,Address match interrupt enable (slave only)" "0,1"
|
|
bitfld.long 0x00 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "PE,Peripheral enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control register 2"
|
|
bitfld.long 0x00 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x00 25. "AUTOEND,Automatic end mode (master mode)" "0,1"
|
|
bitfld.long 0x00 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x00 15. "NACK,NACK generation (slave mode)" "0,1"
|
|
bitfld.long 0x00 14. "STOP,Stop generation (master mode)" "0,1"
|
|
bitfld.long 0x00 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x00 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0,1"
|
|
bitfld.long 0x00 11. "ADD10,10-bit addressing mode (master mode)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "RD_WRN,Transfer direction (master mode)" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "SADD,Slave address bit (master mode)"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OAR1,Own address register 1"
|
|
bitfld.long 0x00 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x00 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "OA1,Interface address"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OAR2,Own address register 2"
|
|
bitfld.long 0x00 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0x00 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 1.--7. 1. "OA2,Interface address"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing register"
|
|
bitfld.long 0x00 28.--31. "PRESC,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "SCLDEL,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "SDADEL,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x00 31. "TEXTEN,Extended clock timeout enable" "0,1"
|
|
hexmask.long.word 0x00 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x00 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x00 12. "TIDLE,Idle clock timeout detection" "0,1"
|
|
hexmask.long.word 0x00 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x00 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x00 16. "DIR,Transfer direction (Slave mode)" "0,1"
|
|
rbitfld.long 0x00 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x00 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x00 12. "TIMEOUT,Timeout or t_low detection flag" "0,1"
|
|
rbitfld.long 0x00 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x00 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x00 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x00 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x00 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x00 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x00 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x00 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
rbitfld.long 0x00 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x00 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
bitfld.long 0x00 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "ICR,Interrupt clear register"
|
|
bitfld.long 0x00 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x00 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
bitfld.long 0x00 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x00 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
bitfld.long 0x00 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x00 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x00 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x00 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x00 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PECR,PEC register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PEC,Packet error checking register"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "ICACHE (ICache)"
|
|
tree "ICACHE"
|
|
base ad:0x40030400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ICACHE_CR,ICACHE control register"
|
|
bitfld.long 0x00 19. "MISSMRST,MISSMRST" "0,1"
|
|
bitfld.long 0x00 18. "HITMRST,HITMRST" "0,1"
|
|
bitfld.long 0x00 17. "MISSMEN,MISSMEN" "0,1"
|
|
bitfld.long 0x00 16. "HITMEN,HITMEN" "0,1"
|
|
bitfld.long 0x00 2. "WAYSEL,WAYSEL" "0,1"
|
|
bitfld.long 0x00 1. "CACHEINV,CACHEINV" "0,1"
|
|
bitfld.long 0x00 0. "EN,EN" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICACHE_SR,ICACHE status register"
|
|
bitfld.long 0x00 2. "ERRF,ERRF" "0,1"
|
|
bitfld.long 0x00 1. "BSYENDF,BSYENDF" "0,1"
|
|
bitfld.long 0x00 0. "BUSYF,BUSYF" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICACHE_IER,ICACHE interrupt enable register"
|
|
bitfld.long 0x00 2. "ERRIE,ERRIE" "0,1"
|
|
bitfld.long 0x00 1. "BSYENDIE,BSYENDIE" "0,1"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICACHE_FCR,ICACHE flag clear register"
|
|
bitfld.long 0x00 2. "CERRF,CERRF" "0,1"
|
|
bitfld.long 0x00 1. "CBSYENDF,CBSYENDF" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ICACHE_HMONR,ICACHE hit monitor register"
|
|
hexmask.long 0x00 0.--31. 1. "HITMON,HITMON"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ICACHE_MMONR,ICACHE miss monitor register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MISSMON,MISSMON"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "ICACHE_CRR$1,ICACHE region configuration register"
|
|
bitfld.long 0x00 31. "HBURST,HBURST" "0,1"
|
|
bitfld.long 0x00 28. "MSTSEL,MSTSEL" "0,1"
|
|
hexmask.long.word 0x00 16.--26. 1. "REMAPADDR,REMAPADDR"
|
|
bitfld.long 0x00 15. "REN,REN" "0,1"
|
|
bitfld.long 0x00 9.--11. "RSIZE,RSIZE" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BASEADDR,BASEADDR"
|
|
repeat.end
|
|
tree.end
|
|
tree "SEC_ICACHE"
|
|
base ad:0x50030400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ICACHE_CR,ICACHE control register"
|
|
bitfld.long 0x00 19. "MISSMRST,MISSMRST" "0,1"
|
|
bitfld.long 0x00 18. "HITMRST,HITMRST" "0,1"
|
|
bitfld.long 0x00 17. "MISSMEN,MISSMEN" "0,1"
|
|
bitfld.long 0x00 16. "HITMEN,HITMEN" "0,1"
|
|
bitfld.long 0x00 2. "WAYSEL,WAYSEL" "0,1"
|
|
bitfld.long 0x00 1. "CACHEINV,CACHEINV" "0,1"
|
|
bitfld.long 0x00 0. "EN,EN" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICACHE_SR,ICACHE status register"
|
|
bitfld.long 0x00 2. "ERRF,ERRF" "0,1"
|
|
bitfld.long 0x00 1. "BSYENDF,BSYENDF" "0,1"
|
|
bitfld.long 0x00 0. "BUSYF,BUSYF" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICACHE_IER,ICACHE interrupt enable register"
|
|
bitfld.long 0x00 2. "ERRIE,ERRIE" "0,1"
|
|
bitfld.long 0x00 1. "BSYENDIE,BSYENDIE" "0,1"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICACHE_FCR,ICACHE flag clear register"
|
|
bitfld.long 0x00 2. "CERRF,CERRF" "0,1"
|
|
bitfld.long 0x00 1. "CBSYENDF,CBSYENDF" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ICACHE_HMONR,ICACHE hit monitor register"
|
|
hexmask.long 0x00 0.--31. 1. "HITMON,HITMON"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ICACHE_MMONR,ICACHE miss monitor register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MISSMON,MISSMON"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "ICACHE_CRR$1,ICACHE region configuration register"
|
|
bitfld.long 0x00 31. "HBURST,HBURST" "0,1"
|
|
bitfld.long 0x00 28. "MSTSEL,MSTSEL" "0,1"
|
|
hexmask.long.word 0x00 16.--26. 1. "REMAPADDR,REMAPADDR"
|
|
bitfld.long 0x00 15. "REN,REN" "0,1"
|
|
bitfld.long 0x00 9.--11. "RSIZE,RSIZE" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BASEADDR,BASEADDR"
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "IWDG (Independent watchdog)"
|
|
tree "IWDG"
|
|
base ad:0x40003000
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "KR,Key register"
|
|
hexmask.long.word 0x00 0.--15. 1. "KEY,Key value (write only read 0x0000)"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PR,Prescaler register"
|
|
bitfld.long 0x00 0.--2. "PR,Prescaler divider" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLR,Reload register"
|
|
hexmask.long.word 0x00 0.--11. 1. "RL,Watchdog counter reload value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status register"
|
|
bitfld.long 0x00 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x00 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
bitfld.long 0x00 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "WINR,Window register"
|
|
hexmask.long.word 0x00 0.--11. 1. "WIN,Watchdog counter window value"
|
|
tree.end
|
|
tree "SEC_IWDG"
|
|
base ad:0x50003000
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "KR,Key register"
|
|
hexmask.long.word 0x00 0.--15. 1. "KEY,Key value (write only read 0x0000)"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PR,Prescaler register"
|
|
bitfld.long 0x00 0.--2. "PR,Prescaler divider" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLR,Reload register"
|
|
hexmask.long.word 0x00 0.--11. 1. "RL,Watchdog counter reload value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status register"
|
|
bitfld.long 0x00 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x00 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
bitfld.long 0x00 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "WINR,Window register"
|
|
hexmask.long.word 0x00 0.--11. 1. "WIN,Watchdog counter window value"
|
|
tree.end
|
|
tree.end
|
|
tree "LPTIM (Low power timer)"
|
|
repeat 3. (list 1. 2. 3.) (list ad:0x40007C00 ad:0x40009400 ad:0x40009800)
|
|
tree "LPTIM$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x00 8. "REPOK,Repetition register update Ok" "0,1"
|
|
bitfld.long 0x00 7. "UE,LPTIM update event occurred" "0,1"
|
|
bitfld.long 0x00 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x00 5. "UP,Counter direction change down to up" "0,1"
|
|
bitfld.long 0x00 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x00 3. "CMPOK,Compare register update OK" "0,1"
|
|
bitfld.long 0x00 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x00 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x00 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
|
|
bitfld.long 0x00 7. "UECF,Update event clear flag" "0,1"
|
|
bitfld.long 0x00 6. "DOWNCF,Direction change to down Clear Flag" "0,1"
|
|
bitfld.long 0x00 5. "UPCF,Direction change to UP Clear Flag" "0,1"
|
|
bitfld.long 0x00 4. "ARROKCF,Autoreload register update OK Clear Flag" "0,1"
|
|
bitfld.long 0x00 3. "CMPOKCF,Compare register update OK Clear Flag" "0,1"
|
|
bitfld.long 0x00 2. "EXTTRIGCF,External trigger valid edge Clear Flag" "0,1"
|
|
bitfld.long 0x00 1. "ARRMCF,Autoreload match Clear Flag" "0,1"
|
|
bitfld.long 0x00 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 8. "REPOKIE,REPOKIE" "0,1"
|
|
bitfld.long 0x00 7. "UEIE,Update event interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "DOWNIE,Direction change to down Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 5. "UPIE,Direction change to UP Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 1. "ARRMIE,Autoreload match Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0. "CMPMIE,Compare match Interrupt Enable" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CFGR,Configuration Register"
|
|
bitfld.long 0x00 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x00 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
bitfld.long 0x00 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x00 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
bitfld.long 0x00 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x00 19. "TIMOUT,Timeout enable" "0,1"
|
|
bitfld.long 0x00 17.--18. "TRIGEN,Trigger enable and polarity" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. "TRGFLT,Configurable digital filter for trigger" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CKFLT,Configurable digital filter for external clock" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
bitfld.long 0x00 0. "CKSEL,Clock selector" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 4. "COUNTRST,Counter reset" "0,1"
|
|
bitfld.long 0x00 3. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x00 2. "CNTSTRT,Timer start in continuous mode" "0,1"
|
|
bitfld.long 0x00 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE,LPTIM Enable" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CMP,Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMP,Compare value"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CNT,Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "OR,LPTIM option register"
|
|
bitfld.long 0x00 1. "OR_1,Option register bit 1" "0,1"
|
|
bitfld.long 0x00 0. "OR_0,Option register bit 0" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RCR,LPTIM repetition register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REP,Repetition register value"
|
|
tree.end
|
|
repeat.end
|
|
repeat 3. (list 1. 2. 3.) (list ad:0x50007C00 ad:0x50009400 ad:0x50009800)
|
|
tree "SEC_LPTIM$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x00 8. "REPOK,Repetition register update Ok" "0,1"
|
|
bitfld.long 0x00 7. "UE,LPTIM update event occurred" "0,1"
|
|
bitfld.long 0x00 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x00 5. "UP,Counter direction change down to up" "0,1"
|
|
bitfld.long 0x00 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x00 3. "CMPOK,Compare register update OK" "0,1"
|
|
bitfld.long 0x00 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x00 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x00 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
|
|
bitfld.long 0x00 7. "UECF,Update event clear flag" "0,1"
|
|
bitfld.long 0x00 6. "DOWNCF,Direction change to down Clear Flag" "0,1"
|
|
bitfld.long 0x00 5. "UPCF,Direction change to UP Clear Flag" "0,1"
|
|
bitfld.long 0x00 4. "ARROKCF,Autoreload register update OK Clear Flag" "0,1"
|
|
bitfld.long 0x00 3. "CMPOKCF,Compare register update OK Clear Flag" "0,1"
|
|
bitfld.long 0x00 2. "EXTTRIGCF,External trigger valid edge Clear Flag" "0,1"
|
|
bitfld.long 0x00 1. "ARRMCF,Autoreload match Clear Flag" "0,1"
|
|
bitfld.long 0x00 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 8. "REPOKIE,REPOKIE" "0,1"
|
|
bitfld.long 0x00 7. "UEIE,Update event interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "DOWNIE,Direction change to down Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 5. "UPIE,Direction change to UP Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 1. "ARRMIE,Autoreload match Interrupt Enable" "0,1"
|
|
bitfld.long 0x00 0. "CMPMIE,Compare match Interrupt Enable" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CFGR,Configuration Register"
|
|
bitfld.long 0x00 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x00 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
bitfld.long 0x00 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x00 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
bitfld.long 0x00 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x00 19. "TIMOUT,Timeout enable" "0,1"
|
|
bitfld.long 0x00 17.--18. "TRIGEN,Trigger enable and polarity" "0,1,2,3"
|
|
bitfld.long 0x00 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. "TRGFLT,Configurable digital filter for trigger" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CKFLT,Configurable digital filter for external clock" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
bitfld.long 0x00 0. "CKSEL,Clock selector" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 4. "COUNTRST,Counter reset" "0,1"
|
|
bitfld.long 0x00 3. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x00 2. "CNTSTRT,Timer start in continuous mode" "0,1"
|
|
bitfld.long 0x00 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE,LPTIM Enable" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CMP,Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMP,Compare value"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CNT,Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "OR,LPTIM option register"
|
|
bitfld.long 0x00 1. "OR_1,Option register bit 1" "0,1"
|
|
bitfld.long 0x00 0. "OR_0,Option register bit 0" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RCR,LPTIM repetition register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REP,Repetition register value"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "NVIC (Nested Vectored Interrupt Controller)"
|
|
tree "NVIC"
|
|
base ad:0xE000E100
|
|
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "ISER$1,Interrupt Set-Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,SETENA"
|
|
repeat.end
|
|
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "ICER$1,Interrupt Clear-Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "CLRENA,CLRENA"
|
|
repeat.end
|
|
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "ISPR$1,Interrupt Set-Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,SETPEND"
|
|
repeat.end
|
|
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "ICPR$1,Interrupt Clear-Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "CLRPEND,CLRPEND"
|
|
repeat.end
|
|
repeat 3. (strings "0" "1" "2" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x200)++0x03
|
|
line.long 0x00 "IABR$1,Interrupt Active Bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,ACTIVE"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x300)++0x03
|
|
line.long 0x00 "IPR$1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IPR_N0,IPR_N0"
|
|
repeat.end
|
|
repeat 5. (strings "16" "17" "18" "19" "20" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
group.long ($2+0x340)++0x03
|
|
line.long 0x00 "IPR$1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "IPR_N3,IPR_N3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "IPR_N2,IPR_N2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "IPR_N1,IPR_N1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IPR_N0,IPR_N0"
|
|
repeat.end
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ISER3,Interrupt Set-Enable Register"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "ICER3,Interrupt Clear-Enable Register"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "ISPR3,Interrupt Set-Pending Register"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "ICPR3,Interrupt Clear-Pending Register"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IABR3,Interrupt Active Bit Register"
|
|
repeat 9. (strings "21" "22" "23" "24" "25" "26" "27" "28" "29" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
|
|
group.long ($2+0x354)++0x03
|
|
line.long 0x00 "IPR$1,IPR $1"
|
|
repeat.end
|
|
tree.end
|
|
tree "NVIC_STIR"
|
|
base ad:0xE000EF00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "STIR,Software trigger interrupt register"
|
|
hexmask.long.word 0x00 0.--8. 1. "INTID,Software generated interrupt ID"
|
|
tree.end
|
|
tree.end
|
|
tree "OCTOSPI (OctoSPI)"
|
|
tree "OCTOSPI1"
|
|
base ad:0x44021000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,control register"
|
|
bitfld.long 0x00 28.--29. "FMODE,Functional mode" "0,1,2,3"
|
|
bitfld.long 0x00 23. "PMM,Polling match mode" "0,1"
|
|
bitfld.long 0x00 22. "APMS,Automatic poll mode stop" "0,1"
|
|
bitfld.long 0x00 20. "TOIE,TimeOut interrupt enable" "0,1"
|
|
bitfld.long 0x00 19. "SMIE,Status match interrupt enable" "0,1"
|
|
bitfld.long 0x00 18. "FTIE,FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x00 17. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 16. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 8.--12. "FTHRES,IFO threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 7. "FSEL,FLASH memory selection" "0,1"
|
|
bitfld.long 0x00 6. "DQM,Dual-quad mode" "0,1"
|
|
bitfld.long 0x00 3. "TCEN,Timeout counter enable" "0,1"
|
|
bitfld.long 0x00 2. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x00 1. "ABORT,Abort request" "0,1"
|
|
bitfld.long 0x00 0. "EN,Enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DCR1,device configuration register"
|
|
bitfld.long 0x00 24.--25. "MTYP,Memory type" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "DEVSIZE,Device size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. "CSHT,Chip-select high time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "FRCK,Free running clock" "0,1"
|
|
bitfld.long 0x00 0. "CKMODE,Mode 0 / mode 3" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DCR2,device configuration register 2"
|
|
bitfld.long 0x00 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRESCALER,Clock prescaler"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DCR3,device configuration register 3"
|
|
bitfld.long 0x00 16.--20. "CSBOUND,CS boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DCR4,DCR4"
|
|
bitfld.long 0x00 8.--13. "FLEVEL,FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 5. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x00 4. "TOF,Timeout flag" "0,1"
|
|
bitfld.long 0x00 3. "SMF,Status match flag" "0,1"
|
|
bitfld.long 0x00 2. "FTF,FIFO threshold flag" "0,1"
|
|
bitfld.long 0x00 1. "TCF,Transfer complete flag" "0,1"
|
|
bitfld.long 0x00 0. "TEF,Transfer error flag" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 4. "CTOF,Clear timeout flag" "0,1"
|
|
bitfld.long 0x00 3. "CSMF,Clear status match flag" "0,1"
|
|
bitfld.long 0x00 1. "CTCF,Clear transfer complete flag" "0,1"
|
|
bitfld.long 0x00 0. "CTEF,Clear transfer error flag" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FCR,flag clear register"
|
|
hexmask.long 0x00 0.--31. 1. "DL,Data length"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DLR,data length register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "AR,address register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DR,data register"
|
|
hexmask.long 0x00 0.--31. 1. "MASK,Status mask"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PSMKR,polling status mask register"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH,Status match"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PSMAR,polling status match register"
|
|
hexmask.long.word 0x00 0.--15. 1. "INTERVAL,Polling interval"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PIR,polling interval register"
|
|
bitfld.long 0x00 31. "SIOO,Send instruction only once mode" "0,1"
|
|
bitfld.long 0x00 29. "DQSE,DQS enable" "0,1"
|
|
bitfld.long 0x00 27. "DDTR,Alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x00 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3"
|
|
bitfld.long 0x00 19. "ABDTR,Alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x00 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--13. "ADSIZE,Address size" "0,1,2,3"
|
|
bitfld.long 0x00 11. "ADDTR,Address double transfer rate" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "ISIZE,Instruction size" "0,1,2,3"
|
|
bitfld.long 0x00 3. "IDTR,Instruction double transfer rate" "0,1"
|
|
bitfld.long 0x00 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CCR,communication configuration register"
|
|
bitfld.long 0x00 30. "SSHIFT,Sample shift" "0,1"
|
|
bitfld.long 0x00 28. "DHQC,Delay hold quarter cycle" "0,1"
|
|
bitfld.long 0x00 0.--4. "DCYC,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TCR,timing configuration register"
|
|
hexmask.long 0x00 0.--31. 1. "INSTRUCTION,INSTRUCTION"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IR,instruction register"
|
|
hexmask.long 0x00 0.--31. 1. "ALTERNATE,Alternate bytes"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ABR,alternate bytes register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMEOUT,Timeout period"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "LPTR,low-power timeout register"
|
|
bitfld.long 0x00 29. "DQSE,DQS enable" "0,1"
|
|
bitfld.long 0x00 27. "DDTR,alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x00 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3"
|
|
bitfld.long 0x00 19. "ABDTR,Alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x00 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--13. "ADSIZE,Address size" "0,1,2,3"
|
|
bitfld.long 0x00 11. "ADDTR,Address double transfer rate" "0,1"
|
|
bitfld.long 0x00 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "ISIZE,Instruction size" "0,1,2,3"
|
|
bitfld.long 0x00 3. "IDTR,Instruction double transfer rate" "0,1"
|
|
bitfld.long 0x00 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "WPCCR,write communication configuration register"
|
|
bitfld.long 0x00 30. "SSHIFT,Sample shift" "0,1"
|
|
bitfld.long 0x00 28. "DHQC,Delay hold quarter cycle" "0,1"
|
|
bitfld.long 0x00 0.--4. "DCYC,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "WPTCR,write timing configuration register"
|
|
hexmask.long 0x00 0.--31. 1. "INSTRUCTION,INSTRUCTION"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "WPIR,write instruction register"
|
|
hexmask.long 0x00 0.--31. 1. "ALTERNATE,Alternate bytes"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "WPABR,write alternate bytes register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TRWR,Read write recovery time"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TACC,Access time"
|
|
bitfld.long 0x00 1. "WZL,Write zero latency" "0,1"
|
|
bitfld.long 0x00 0. "LM,Latency mode" "0,1"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "WCCR,WCCR"
|
|
hexmask.long.word 0x00 0.--15. 1. "REFRESH,REFRESH"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "WTCR,WTCR"
|
|
bitfld.long 0x00 29. "DQSE,DQSE" "0,1"
|
|
bitfld.long 0x00 27. "DDTR,DDTR" "0,1"
|
|
bitfld.long 0x00 24.--26. "DMODE,DMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--21. "ABSIZE,ABSIZE" "0,1,2,3"
|
|
bitfld.long 0x00 19. "ABDTR,ABDTR" "0,1"
|
|
bitfld.long 0x00 16.--18. "ABMODE,ABMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--13. "ADSIZE,ADSIZE" "0,1,2,3"
|
|
bitfld.long 0x00 11. "ADDTR,ADDTR" "0,1"
|
|
bitfld.long 0x00 8.--10. "ADMODE,ADMODE" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "ISIZE,ISIZE" "0,1,2,3"
|
|
bitfld.long 0x00 3. "IDTR,IDTR" "0,1"
|
|
bitfld.long 0x00 0.--2. "IMODE,IMODE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "WIR,WIR"
|
|
bitfld.long 0x00 0.--4. "DCYC,DCYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "WABR,WABR"
|
|
hexmask.long 0x00 0.--31. 1. "INSTRUCTION,INSTRUCTION"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "HLCR,HyperBusTM latency configuration register"
|
|
hexmask.long 0x00 0.--31. 1. "ALTERNATE,Alternate bytes"
|
|
tree.end
|
|
tree "SEC_OCTOSPI1"
|
|
base ad:0x54021000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,control register"
|
|
bitfld.long 0x00 28.--29. "FMODE,Functional mode" "0,1,2,3"
|
|
bitfld.long 0x00 23. "PMM,Polling match mode" "0,1"
|
|
bitfld.long 0x00 22. "APMS,Automatic poll mode stop" "0,1"
|
|
bitfld.long 0x00 20. "TOIE,TimeOut interrupt enable" "0,1"
|
|
bitfld.long 0x00 19. "SMIE,Status match interrupt enable" "0,1"
|
|
bitfld.long 0x00 18. "FTIE,FIFO threshold interrupt enable" "0,1"
|
|
bitfld.long 0x00 17. "TCIE,Transfer complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 16. "TEIE,Transfer error interrupt enable" "0,1"
|
|
bitfld.long 0x00 8.--12. "FTHRES,IFO threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 7. "FSEL,FLASH memory selection" "0,1"
|
|
bitfld.long 0x00 6. "DQM,Dual-quad mode" "0,1"
|
|
bitfld.long 0x00 3. "TCEN,Timeout counter enable" "0,1"
|
|
bitfld.long 0x00 2. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x00 1. "ABORT,Abort request" "0,1"
|
|
bitfld.long 0x00 0. "EN,Enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DCR1,device configuration register"
|
|
bitfld.long 0x00 24.--25. "MTYP,Memory type" "0,1,2,3"
|
|
bitfld.long 0x00 16.--20. "DEVSIZE,Device size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. "CSHT,Chip-select high time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "FRCK,Free running clock" "0,1"
|
|
bitfld.long 0x00 0. "CKMODE,Mode 0 / mode 3" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DCR2,device configuration register 2"
|
|
bitfld.long 0x00 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRESCALER,Clock prescaler"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DCR3,device configuration register 3"
|
|
bitfld.long 0x00 16.--20. "CSBOUND,CS boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DCR4,DCR4"
|
|
bitfld.long 0x00 8.--13. "FLEVEL,FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 5. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x00 4. "TOF,Timeout flag" "0,1"
|
|
bitfld.long 0x00 3. "SMF,Status match flag" "0,1"
|
|
bitfld.long 0x00 2. "FTF,FIFO threshold flag" "0,1"
|
|
bitfld.long 0x00 1. "TCF,Transfer complete flag" "0,1"
|
|
bitfld.long 0x00 0. "TEF,Transfer error flag" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 4. "CTOF,Clear timeout flag" "0,1"
|
|
bitfld.long 0x00 3. "CSMF,Clear status match flag" "0,1"
|
|
bitfld.long 0x00 1. "CTCF,Clear transfer complete flag" "0,1"
|
|
bitfld.long 0x00 0. "CTEF,Clear transfer error flag" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FCR,flag clear register"
|
|
hexmask.long 0x00 0.--31. 1. "DL,Data length"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DLR,data length register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "AR,address register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DR,data register"
|
|
hexmask.long 0x00 0.--31. 1. "MASK,Status mask"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PSMKR,polling status mask register"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH,Status match"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PSMAR,polling status match register"
|
|
hexmask.long.word 0x00 0.--15. 1. "INTERVAL,Polling interval"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PIR,polling interval register"
|
|
bitfld.long 0x00 31. "SIOO,Send instruction only once mode" "0,1"
|
|
bitfld.long 0x00 29. "DQSE,DQS enable" "0,1"
|
|
bitfld.long 0x00 27. "DDTR,Alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x00 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3"
|
|
bitfld.long 0x00 19. "ABDTR,Alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x00 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--13. "ADSIZE,Address size" "0,1,2,3"
|
|
bitfld.long 0x00 11. "ADDTR,Address double transfer rate" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--5. "ISIZE,Instruction size" "0,1,2,3"
|
|
bitfld.long 0x00 3. "IDTR,Instruction double transfer rate" "0,1"
|
|
bitfld.long 0x00 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CCR,communication configuration register"
|
|
bitfld.long 0x00 30. "SSHIFT,Sample shift" "0,1"
|
|
bitfld.long 0x00 28. "DHQC,Delay hold quarter cycle" "0,1"
|
|
bitfld.long 0x00 0.--4. "DCYC,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TCR,timing configuration register"
|
|
hexmask.long 0x00 0.--31. 1. "INSTRUCTION,INSTRUCTION"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IR,instruction register"
|
|
hexmask.long 0x00 0.--31. 1. "ALTERNATE,Alternate bytes"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ABR,alternate bytes register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMEOUT,Timeout period"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "LPTR,low-power timeout register"
|
|
bitfld.long 0x00 29. "DQSE,DQS enable" "0,1"
|
|
bitfld.long 0x00 27. "DDTR,alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x00 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3"
|
|
bitfld.long 0x00 19. "ABDTR,Alternate bytes double transfer rate" "0,1"
|
|
bitfld.long 0x00 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--13. "ADSIZE,Address size" "0,1,2,3"
|
|
bitfld.long 0x00 11. "ADDTR,Address double transfer rate" "0,1"
|
|
bitfld.long 0x00 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "ISIZE,Instruction size" "0,1,2,3"
|
|
bitfld.long 0x00 3. "IDTR,Instruction double transfer rate" "0,1"
|
|
bitfld.long 0x00 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "WPCCR,write communication configuration register"
|
|
bitfld.long 0x00 30. "SSHIFT,Sample shift" "0,1"
|
|
bitfld.long 0x00 28. "DHQC,Delay hold quarter cycle" "0,1"
|
|
bitfld.long 0x00 0.--4. "DCYC,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "WPTCR,write timing configuration register"
|
|
hexmask.long 0x00 0.--31. 1. "INSTRUCTION,INSTRUCTION"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "WPIR,write instruction register"
|
|
hexmask.long 0x00 0.--31. 1. "ALTERNATE,Alternate bytes"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "WPABR,write alternate bytes register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TRWR,Read write recovery time"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TACC,Access time"
|
|
bitfld.long 0x00 1. "WZL,Write zero latency" "0,1"
|
|
bitfld.long 0x00 0. "LM,Latency mode" "0,1"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "WCCR,WCCR"
|
|
hexmask.long.word 0x00 0.--15. 1. "REFRESH,REFRESH"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "WTCR,WTCR"
|
|
bitfld.long 0x00 29. "DQSE,DQSE" "0,1"
|
|
bitfld.long 0x00 27. "DDTR,DDTR" "0,1"
|
|
bitfld.long 0x00 24.--26. "DMODE,DMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--21. "ABSIZE,ABSIZE" "0,1,2,3"
|
|
bitfld.long 0x00 19. "ABDTR,ABDTR" "0,1"
|
|
bitfld.long 0x00 16.--18. "ABMODE,ABMODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--13. "ADSIZE,ADSIZE" "0,1,2,3"
|
|
bitfld.long 0x00 11. "ADDTR,ADDTR" "0,1"
|
|
bitfld.long 0x00 8.--10. "ADMODE,ADMODE" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "ISIZE,ISIZE" "0,1,2,3"
|
|
bitfld.long 0x00 3. "IDTR,IDTR" "0,1"
|
|
bitfld.long 0x00 0.--2. "IMODE,IMODE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "WIR,WIR"
|
|
bitfld.long 0x00 0.--4. "DCYC,DCYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "WABR,WABR"
|
|
hexmask.long 0x00 0.--31. 1. "INSTRUCTION,INSTRUCTION"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "HLCR,HyperBusTM latency configuration register"
|
|
hexmask.long 0x00 0.--31. 1. "ALTERNATE,Alternate bytes"
|
|
tree.end
|
|
tree.end
|
|
tree "OPAMP (Operational amplifiers)"
|
|
tree "OPAMP"
|
|
base ad:0x40007800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "OPAMP1_CSR,OPAMP1 control/status register"
|
|
bitfld.long 0x00 31. "OPA_RANGE,Operational amplifier power supply range for stability" "0,1"
|
|
bitfld.long 0x00 15. "CALOUT,Operational amplifier calibration output" "0,1"
|
|
bitfld.long 0x00 14. "USERTRIM,User trimming enable" "0,1"
|
|
bitfld.long 0x00 13. "CALSEL,calibration selection" "0,1"
|
|
bitfld.long 0x00 12. "CALON,calibration mode enable" "0,1"
|
|
bitfld.long 0x00 10. "VP_SEL,non inverted input selection" "0,1"
|
|
bitfld.long 0x00 8.--9. "VM_SEL,inverting input selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PGA_GAIN,Operational amplifier Programmable amplifier gain value" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "OPAMODE,Operational amplifier PGA mode" "0,1,2,3"
|
|
bitfld.long 0x00 1. "OPALPM,Operational amplifier Low Power Mode" "0,1"
|
|
bitfld.long 0x00 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OPAMP1_OTR,OPAMP1 offset trimming register in normal mode"
|
|
bitfld.long 0x00 8.--12. "TRIMOFFSETP,Trim for PMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TRIMOFFSETN,Trim for NMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OPAMP1_LPOTR,OPAMP1 offset trimming register in low-powe mode"
|
|
bitfld.long 0x00 8.--12. "TRIMLPOFFSETP,Trim for PMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TRIMLPOFFSETN,Trim for NMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "OPAMP2_CRS,OPAMP2 control/status register"
|
|
bitfld.long 0x00 15. "CALOUT,Operational amplifier calibration output" "0,1"
|
|
bitfld.long 0x00 14. "USERTRIM,User trimming enable" "0,1"
|
|
bitfld.long 0x00 13. "CALSEL,calibration selection" "0,1"
|
|
bitfld.long 0x00 12. "CALON,calibration mode enable" "0,1"
|
|
bitfld.long 0x00 10. "VP_SEL,non inverted input selection" "0,1"
|
|
bitfld.long 0x00 8.--9. "VM_SEL,inverting input selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PGA_GAIN,Operational amplifier Programmable amplifier gain value" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OPAMODE,Operational amplifier PGA mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "OPALPM,Operational amplifier Low Power Mode" "0,1"
|
|
bitfld.long 0x00 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "OPAMP2_OTR,OPAMP2 offset trimming register in normal mode"
|
|
bitfld.long 0x00 8.--12. "TRIMOFFSETP,Trim for PMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TRIMOFFSETN,Trim for NMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OPAMP2_LPOTR,OPAMP2 offset trimming register in low-power mode"
|
|
bitfld.long 0x00 8.--12. "TRIMLPOFFSETP,Trim for PMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TRIMLPOFFSETN,Trim for NMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "SEC_OPAMP"
|
|
base ad:0x50007800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "OPAMP1_CSR,OPAMP1 control/status register"
|
|
bitfld.long 0x00 31. "OPA_RANGE,Operational amplifier power supply range for stability" "0,1"
|
|
bitfld.long 0x00 15. "CALOUT,Operational amplifier calibration output" "0,1"
|
|
bitfld.long 0x00 14. "USERTRIM,User trimming enable" "0,1"
|
|
bitfld.long 0x00 13. "CALSEL,calibration selection" "0,1"
|
|
bitfld.long 0x00 12. "CALON,calibration mode enable" "0,1"
|
|
bitfld.long 0x00 10. "VP_SEL,non inverted input selection" "0,1"
|
|
bitfld.long 0x00 8.--9. "VM_SEL,inverting input selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PGA_GAIN,Operational amplifier Programmable amplifier gain value" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "OPAMODE,Operational amplifier PGA mode" "0,1,2,3"
|
|
bitfld.long 0x00 1. "OPALPM,Operational amplifier Low Power Mode" "0,1"
|
|
bitfld.long 0x00 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OPAMP1_OTR,OPAMP1 offset trimming register in normal mode"
|
|
bitfld.long 0x00 8.--12. "TRIMOFFSETP,Trim for PMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TRIMOFFSETN,Trim for NMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OPAMP1_LPOTR,OPAMP1 offset trimming register in low-powe mode"
|
|
bitfld.long 0x00 8.--12. "TRIMLPOFFSETP,Trim for PMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TRIMLPOFFSETN,Trim for NMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "OPAMP2_CRS,OPAMP2 control/status register"
|
|
bitfld.long 0x00 15. "CALOUT,Operational amplifier calibration output" "0,1"
|
|
bitfld.long 0x00 14. "USERTRIM,User trimming enable" "0,1"
|
|
bitfld.long 0x00 13. "CALSEL,calibration selection" "0,1"
|
|
bitfld.long 0x00 12. "CALON,calibration mode enable" "0,1"
|
|
bitfld.long 0x00 10. "VP_SEL,non inverted input selection" "0,1"
|
|
bitfld.long 0x00 8.--9. "VM_SEL,inverting input selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "PGA_GAIN,Operational amplifier Programmable amplifier gain value" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "OPAMODE,Operational amplifier PGA mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "OPALPM,Operational amplifier Low Power Mode" "0,1"
|
|
bitfld.long 0x00 0. "OPAEN,Operational amplifier Enable" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "OPAMP2_OTR,OPAMP2 offset trimming register in normal mode"
|
|
bitfld.long 0x00 8.--12. "TRIMOFFSETP,Trim for PMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TRIMOFFSETN,Trim for NMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OPAMP2_LPOTR,OPAMP2 offset trimming register in low-power mode"
|
|
bitfld.long 0x00 8.--12. "TRIMLPOFFSETP,Trim for PMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TRIMLPOFFSETN,Trim for NMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("STM32L562*")
|
|
tree "OTFDEC (On-The-Fly Decryption engine)"
|
|
tree "OTFDEC1"
|
|
base ad:0x420C5000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,OTFDEC control register"
|
|
bitfld.long 0x00 0. "ENC,Encryption mode bit" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "R1CFGR,OTFDEC region x configuration register"
|
|
hexmask.long.word 0x00 16.--31. 1. "REGx_VERSION,region firmware version"
|
|
hexmask.long.byte 0x00 8.--15. 1. "KEYCRC,region key 8-bit CRC"
|
|
bitfld.long 0x00 4.--5. "MODE,operating mode" "0,1,2,3"
|
|
bitfld.long 0x00 2. "KEYLOCK,region key lock" "0,1"
|
|
bitfld.long 0x00 1. "CONFIGLOCK,region config lock" "0,1"
|
|
bitfld.long 0x00 0. "REG_EN,region on-the-fly decryption enable" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "R2CFGR,OTFDEC region x configuration register"
|
|
hexmask.long.word 0x00 16.--31. 1. "REGx_VERSION,region firmware version"
|
|
hexmask.long.byte 0x00 8.--15. 1. "KEYCRC,region key 8-bit CRC"
|
|
bitfld.long 0x00 4.--5. "MODE,operating mode" "0,1,2,3"
|
|
bitfld.long 0x00 2. "KEYLOCK,region key lock" "0,1"
|
|
bitfld.long 0x00 1. "CONFIGLOCK,region config lock" "0,1"
|
|
bitfld.long 0x00 0. "REG_EN,region on-the-fly decryption enable" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "R3CFGR,OTFDEC region x configuration register"
|
|
hexmask.long.word 0x00 16.--31. 1. "REGx_VERSION,region firmware version"
|
|
hexmask.long.byte 0x00 8.--15. 1. "KEYCRC,region key 8-bit CRC"
|
|
bitfld.long 0x00 4.--5. "MODE,operating mode" "0,1,2,3"
|
|
bitfld.long 0x00 2. "KEYLOCK,region key lock" "0,1"
|
|
bitfld.long 0x00 1. "CONFIGLOCK,region config lock" "0,1"
|
|
bitfld.long 0x00 0. "REG_EN,region on-the-fly decryption enable" "0,1"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "R4CFGR,OTFDEC region x configuration register"
|
|
hexmask.long.word 0x00 16.--31. 1. "REGx_VERSION,region firmware version"
|
|
hexmask.long.byte 0x00 8.--15. 1. "KEYCRC,region key 8-bit CRC"
|
|
bitfld.long 0x00 4.--5. "MODE,operating mode" "0,1,2,3"
|
|
bitfld.long 0x00 2. "KEYLOCK,region key lock" "0,1"
|
|
bitfld.long 0x00 1. "CONFIGLOCK,region config lock" "0,1"
|
|
bitfld.long 0x00 0. "REG_EN,region on-the-fly decryption enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "R1STARTADDR,OTFDEC region x start address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_START_ADDR,Region AXI start address"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "R2STARTADDR,OTFDEC region x start address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_START_ADDR,Region AXI start address"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "R3STARTADDR,OTFDEC region x start address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_START_ADDR,Region AXI start address"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "R4STARTADDR,OTFDEC region x start address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_START_ADDR,Region AXI start address"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "R1ENDADDR,OTFDEC region x end address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_END_ADDR,Region AXI end address"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "R2ENDADDR,OTFDEC region x end address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_END_ADDR,Region AXI end address"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "R3ENDADDR,OTFDEC region x end address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_END_ADDR,Region AXI end address"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "R4ENDADDR,OTFDEC region x end address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_END_ADDR,Region AXI end address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "R1NONCER0,OTFDEC region x nonce register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,REGx_NONCE"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "R2NONCER0,OTFDEC region x nonce register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,REGx_NONCE"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "R3NONCER0,OTFDEC region x nonce register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,REGx_NONCE"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "R4NONCER0,OTFDEC region x nonce register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,REGx_NONCE"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "R1NONCER1,OTFDEC region x nonce register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,Region nonce"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "R2NONCER1,OTFDEC region x nonce register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,Region nonce bits [63:32]REGx_NONCE[63:32]"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "R3NONCER1,OTFDEC region x nonce register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,REGx_NONCE"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "R4NONCER1,OTFDEC region x nonce register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,REGx_NONCE"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "R1KEYR0,OTFDEC region x key register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "R2KEYR0,OTFDEC region x key register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x94++0x03
|
|
line.long 0x00 "R3KEYR0,OTFDEC region x key register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0xC4++0x03
|
|
line.long 0x00 "R4KEYR0,OTFDEC region x key register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x38++0x03
|
|
line.long 0x00 "R1KEYR1,OTFDEC region x key register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x68++0x03
|
|
line.long 0x00 "R2KEYR1,OTFDEC region x key register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x98++0x03
|
|
line.long 0x00 "R3KEYR1,OTFDEC region x key register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0xC8++0x03
|
|
line.long 0x00 "R4KEYR1,OTFDEC region x key register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "R1KEYR2,OTFDEC region x key register 2"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x6C++0x03
|
|
line.long 0x00 "R2KEYR2,OTFDEC region x key register 2"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY_,REGx_KEY"
|
|
wgroup.long 0x9C++0x03
|
|
line.long 0x00 "R3KEYR2,OTFDEC region x key register 2"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "R4KEYR2,OTFDEC region x key register 2"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "R1KEYR3,OTFDEC region x key register 3"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x70++0x03
|
|
line.long 0x00 "R2KEYR3,OTFDEC region x key register 3"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0xA0++0x03
|
|
line.long 0x00 "R3KEYR3,OTFDEC region x key register 3"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0xD0++0x03
|
|
line.long 0x00 "R4KEYR3,OTFDEC region x key register 3"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ISR,OTFDEC interrupt status register"
|
|
bitfld.long 0x00 2. "KEIF,Key Error Interrupt Flag status" "0,1"
|
|
bitfld.long 0x00 1. "XONEIF,Execute-only execute-Never Error Interrupt Flag status" "0,1"
|
|
bitfld.long 0x00 0. "SEIF,Security Error Interrupt Flag status" "0,1"
|
|
wgroup.long 0x304++0x03
|
|
line.long 0x00 "ICR,OTFDEC interrupt clear register"
|
|
bitfld.long 0x00 2. "KEIF,KEIF" "0,1"
|
|
bitfld.long 0x00 1. "XONEIF,Execute-only execute-Never Error Interrupt Flag clear" "0,1"
|
|
bitfld.long 0x00 0. "SEIF,SEIF" "0,1"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "IER,OTFDEC interrupt enable register"
|
|
bitfld.long 0x00 2. "KEIE,KEIE" "0,1"
|
|
bitfld.long 0x00 1. "XONEIE,XONEIE" "0,1"
|
|
bitfld.long 0x00 0. "SEIE,Security Error Interrupt Enable" "0,1"
|
|
tree.end
|
|
tree "SEC_OTFDEC1"
|
|
base ad:0x520C5000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,OTFDEC control register"
|
|
bitfld.long 0x00 0. "ENC,Encryption mode bit" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "R1CFGR,OTFDEC region x configuration register"
|
|
hexmask.long.word 0x00 16.--31. 1. "REGx_VERSION,region firmware version"
|
|
hexmask.long.byte 0x00 8.--15. 1. "KEYCRC,region key 8-bit CRC"
|
|
bitfld.long 0x00 4.--5. "MODE,operating mode" "0,1,2,3"
|
|
bitfld.long 0x00 2. "KEYLOCK,region key lock" "0,1"
|
|
bitfld.long 0x00 1. "CONFIGLOCK,region config lock" "0,1"
|
|
bitfld.long 0x00 0. "REG_EN,region on-the-fly decryption enable" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "R2CFGR,OTFDEC region x configuration register"
|
|
hexmask.long.word 0x00 16.--31. 1. "REGx_VERSION,region firmware version"
|
|
hexmask.long.byte 0x00 8.--15. 1. "KEYCRC,region key 8-bit CRC"
|
|
bitfld.long 0x00 4.--5. "MODE,operating mode" "0,1,2,3"
|
|
bitfld.long 0x00 2. "KEYLOCK,region key lock" "0,1"
|
|
bitfld.long 0x00 1. "CONFIGLOCK,region config lock" "0,1"
|
|
bitfld.long 0x00 0. "REG_EN,region on-the-fly decryption enable" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "R3CFGR,OTFDEC region x configuration register"
|
|
hexmask.long.word 0x00 16.--31. 1. "REGx_VERSION,region firmware version"
|
|
hexmask.long.byte 0x00 8.--15. 1. "KEYCRC,region key 8-bit CRC"
|
|
bitfld.long 0x00 4.--5. "MODE,operating mode" "0,1,2,3"
|
|
bitfld.long 0x00 2. "KEYLOCK,region key lock" "0,1"
|
|
bitfld.long 0x00 1. "CONFIGLOCK,region config lock" "0,1"
|
|
bitfld.long 0x00 0. "REG_EN,region on-the-fly decryption enable" "0,1"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "R4CFGR,OTFDEC region x configuration register"
|
|
hexmask.long.word 0x00 16.--31. 1. "REGx_VERSION,region firmware version"
|
|
hexmask.long.byte 0x00 8.--15. 1. "KEYCRC,region key 8-bit CRC"
|
|
bitfld.long 0x00 4.--5. "MODE,operating mode" "0,1,2,3"
|
|
bitfld.long 0x00 2. "KEYLOCK,region key lock" "0,1"
|
|
bitfld.long 0x00 1. "CONFIGLOCK,region config lock" "0,1"
|
|
bitfld.long 0x00 0. "REG_EN,region on-the-fly decryption enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "R1STARTADDR,OTFDEC region x start address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_START_ADDR,Region AXI start address"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "R2STARTADDR,OTFDEC region x start address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_START_ADDR,Region AXI start address"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "R3STARTADDR,OTFDEC region x start address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_START_ADDR,Region AXI start address"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "R4STARTADDR,OTFDEC region x start address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_START_ADDR,Region AXI start address"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "R1ENDADDR,OTFDEC region x end address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_END_ADDR,Region AXI end address"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "R2ENDADDR,OTFDEC region x end address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_END_ADDR,Region AXI end address"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "R3ENDADDR,OTFDEC region x end address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_END_ADDR,Region AXI end address"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "R4ENDADDR,OTFDEC region x end address register"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_END_ADDR,Region AXI end address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "R1NONCER0,OTFDEC region x nonce register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,REGx_NONCE"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "R2NONCER0,OTFDEC region x nonce register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,REGx_NONCE"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "R3NONCER0,OTFDEC region x nonce register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,REGx_NONCE"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "R4NONCER0,OTFDEC region x nonce register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,REGx_NONCE"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "R1NONCER1,OTFDEC region x nonce register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,Region nonce"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "R2NONCER1,OTFDEC region x nonce register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,Region nonce bits [63:32]REGx_NONCE[63:32]"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "R3NONCER1,OTFDEC region x nonce register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,REGx_NONCE"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "R4NONCER1,OTFDEC region x nonce register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_NONCE,REGx_NONCE"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "R1KEYR0,OTFDEC region x key register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "R2KEYR0,OTFDEC region x key register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x94++0x03
|
|
line.long 0x00 "R3KEYR0,OTFDEC region x key register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0xC4++0x03
|
|
line.long 0x00 "R4KEYR0,OTFDEC region x key register 0"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x38++0x03
|
|
line.long 0x00 "R1KEYR1,OTFDEC region x key register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x68++0x03
|
|
line.long 0x00 "R2KEYR1,OTFDEC region x key register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x98++0x03
|
|
line.long 0x00 "R3KEYR1,OTFDEC region x key register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0xC8++0x03
|
|
line.long 0x00 "R4KEYR1,OTFDEC region x key register 1"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "R1KEYR2,OTFDEC region x key register 2"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x6C++0x03
|
|
line.long 0x00 "R2KEYR2,OTFDEC region x key register 2"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY_,REGx_KEY"
|
|
wgroup.long 0x9C++0x03
|
|
line.long 0x00 "R3KEYR2,OTFDEC region x key register 2"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0xCC++0x03
|
|
line.long 0x00 "R4KEYR2,OTFDEC region x key register 2"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "R1KEYR3,OTFDEC region x key register 3"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0x70++0x03
|
|
line.long 0x00 "R2KEYR3,OTFDEC region x key register 3"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0xA0++0x03
|
|
line.long 0x00 "R3KEYR3,OTFDEC region x key register 3"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
wgroup.long 0xD0++0x03
|
|
line.long 0x00 "R4KEYR3,OTFDEC region x key register 3"
|
|
hexmask.long 0x00 0.--31. 1. "REGx_KEY,REGx_KEY"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ISR,OTFDEC interrupt status register"
|
|
bitfld.long 0x00 2. "KEIF,Key Error Interrupt Flag status" "0,1"
|
|
bitfld.long 0x00 1. "XONEIF,Execute-only execute-Never Error Interrupt Flag status" "0,1"
|
|
bitfld.long 0x00 0. "SEIF,Security Error Interrupt Flag status" "0,1"
|
|
wgroup.long 0x304++0x03
|
|
line.long 0x00 "ICR,OTFDEC interrupt clear register"
|
|
bitfld.long 0x00 2. "KEIF,KEIF" "0,1"
|
|
bitfld.long 0x00 1. "XONEIF,Execute-only execute-Never Error Interrupt Flag clear" "0,1"
|
|
bitfld.long 0x00 0. "SEIF,SEIF" "0,1"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "IER,OTFDEC interrupt enable register"
|
|
bitfld.long 0x00 2. "KEIE,KEIE" "0,1"
|
|
bitfld.long 0x00 1. "XONEIE,XONEIE" "0,1"
|
|
bitfld.long 0x00 0. "SEIE,Security Error Interrupt Enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "PKA"
|
|
tree "PKA"
|
|
base ad:0x420C2000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PKA_CR,PKA control register"
|
|
bitfld.long 0x00 20. "ADDRERRIE,Address error interrupt enable" "0,1"
|
|
bitfld.long 0x00 19. "RAMERRIE,RAM error interrupt enable" "0,1"
|
|
bitfld.long 0x00 17. "PROCENDIE,End of operation interrupt enable" "0,1"
|
|
bitfld.long 0x00 8.--13. "MODE,PKA operation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 1. "START,Start the operation" "0,1"
|
|
bitfld.long 0x00 0. "EN,PKA Enable" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PKA_SR,PKA status register"
|
|
bitfld.long 0x00 20. "ADDRERRF,address er flag" "0,1"
|
|
bitfld.long 0x00 19. "RAMERRF,PKA ram error flag" "0,1"
|
|
bitfld.long 0x00 17. "PROCENDF,PKA end of operation flag" "0,1"
|
|
bitfld.long 0x00 16. "BUSY,PKA operation in progress" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "PKA_CLRFR,PKA clear flag register"
|
|
bitfld.long 0x00 20. "ADDRERRFC,clear address error flag" "0,1"
|
|
bitfld.long 0x00 19. "RAMERRFC,CLEAR PKA RAM ERROR FLAG" "0,1"
|
|
bitfld.long 0x00 17. "PROCENDFC,clear PKA end of operation flag" "0,1"
|
|
tree.end
|
|
tree "SEC_PKA"
|
|
base ad:0x520C2000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PKA_CR,PKA control register"
|
|
bitfld.long 0x00 20. "ADDRERRIE,Address error interrupt enable" "0,1"
|
|
bitfld.long 0x00 19. "RAMERRIE,RAM error interrupt enable" "0,1"
|
|
bitfld.long 0x00 17. "PROCENDIE,End of operation interrupt enable" "0,1"
|
|
bitfld.long 0x00 8.--13. "MODE,PKA operation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 1. "START,Start the operation" "0,1"
|
|
bitfld.long 0x00 0. "EN,PKA Enable" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PKA_SR,PKA status register"
|
|
bitfld.long 0x00 20. "ADDRERRF,address er flag" "0,1"
|
|
bitfld.long 0x00 19. "RAMERRF,PKA ram error flag" "0,1"
|
|
bitfld.long 0x00 17. "PROCENDF,PKA end of operation flag" "0,1"
|
|
bitfld.long 0x00 16. "BUSY,PKA operation in progress" "0,1"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "PKA_CLRFR,PKA clear flag register"
|
|
bitfld.long 0x00 20. "ADDRERRFC,clear address error flag" "0,1"
|
|
bitfld.long 0x00 19. "RAMERRFC,CLEAR PKA RAM ERROR FLAG" "0,1"
|
|
bitfld.long 0x00 17. "PROCENDFC,clear PKA end of operation flag" "0,1"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "PWR (Power control)"
|
|
tree "PWR"
|
|
base ad:0x40007000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Power control register 1"
|
|
bitfld.long 0x00 14. "LPR,Low-power run" "0,1"
|
|
bitfld.long 0x00 9.--10. "VOS,Voltage scaling range selection" "0,1,2,3"
|
|
bitfld.long 0x00 8. "DBP,Disable backup domain write protection" "0,1"
|
|
bitfld.long 0x00 0.--2. "LPMS,Low-power mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Power control register 2"
|
|
bitfld.long 0x00 10. "USV,VDDUSB USB supply valid" "0,1"
|
|
bitfld.long 0x00 9. "IOSV,VDDIO2 Independent I/Os supply valid" "0,1"
|
|
bitfld.long 0x00 7. "PVME4,Peripheral voltage monitoring 4 enable: VDDA vs" "0,1"
|
|
bitfld.long 0x00 6. "PVME3,Peripheral voltage monitoring 3 enable: VDDA vs" "0,1"
|
|
bitfld.long 0x00 5. "PVME2,Peripheral voltage monitoring 2 enable: VDDIO2 vs" "0,1"
|
|
bitfld.long 0x00 4. "PVME1,Peripheral voltage monitoring 1 enable: VDDUSB vs" "0,1"
|
|
bitfld.long 0x00 1.--3. "PLS,Power voltage detector level selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "PVDE,Power voltage detector enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Power control register 3"
|
|
bitfld.long 0x00 14. "UCPD_DBDIS,UCPD_DBDIS" "0,1"
|
|
bitfld.long 0x00 13. "UCPD_STDBY,UCPD_STDBY" "0,1"
|
|
bitfld.long 0x00 11. "ULPMEN,ULPMEN" "0,1"
|
|
bitfld.long 0x00 10. "APC,Apply pull-up and pull-down configuration" "0,1"
|
|
bitfld.long 0x00 8.--9. "RRS,SRAM2 retention in Standby mode" "0,1,2,3"
|
|
bitfld.long 0x00 4. "EWUP5,Enable Wakeup pin WKUP5" "0,1"
|
|
bitfld.long 0x00 3. "EWUP4,Enable Wakeup pin WKUP4" "0,1"
|
|
bitfld.long 0x00 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
bitfld.long 0x00 1. "EWUP2,Enable Wakeup pin WKUP2" "0,1"
|
|
bitfld.long 0x00 0. "EWUP1,Enable Wakeup pin WKUP1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR4,Power control register 4"
|
|
bitfld.long 0x00 15. "SMPSLPEN,SMPSLPEN" "0,1"
|
|
bitfld.long 0x00 14. "SMPSFSTEN,SMPSFSTEN" "0,1"
|
|
bitfld.long 0x00 13. "EXTSMPSEN,EXTSMPSEN" "0,1"
|
|
bitfld.long 0x00 12. "SMPSBYP,SMPSBYP" "0,1"
|
|
bitfld.long 0x00 9. "VBRS,VBAT battery charging resistor selection" "0,1"
|
|
bitfld.long 0x00 8. "VBE,VBAT battery charging enable" "0,1"
|
|
bitfld.long 0x00 4. "WUPP5,Wakeup pin WKUP5 polarity" "0,1"
|
|
bitfld.long 0x00 3. "WUPP4,Wakeup pin WKUP4 polarity" "0,1"
|
|
bitfld.long 0x00 2. "WUPP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
bitfld.long 0x00 1. "WUPP2,Wakeup pin WKUP2 polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WUPP1,Wakeup pin WKUP1 polarity" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SR1,Power status register 1"
|
|
bitfld.long 0x00 15. "SMPSHPRDY,SMPSHPRDY" "0,1"
|
|
bitfld.long 0x00 13. "EXTSMPSRDY,EXTSMPSRDY" "0,1"
|
|
bitfld.long 0x00 12. "SMPSBYPRDY,SMPSBYPRDY" "0,1"
|
|
bitfld.long 0x00 8. "SBF,Standby flag" "0,1"
|
|
bitfld.long 0x00 4. "WUF5,Wakeup flag 5" "0,1"
|
|
bitfld.long 0x00 3. "WUF4,Wakeup flag 4" "0,1"
|
|
bitfld.long 0x00 2. "WUF3,Wakeup flag 3" "0,1"
|
|
bitfld.long 0x00 1. "WUF2,Wakeup flag 2" "0,1"
|
|
bitfld.long 0x00 0. "WUF1,Wakeup flag 1" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SR2,Power status register 2"
|
|
bitfld.long 0x00 15. "PVMO4,Peripheral voltage monitoring output: VDDA vs" "0,1"
|
|
bitfld.long 0x00 14. "PVMO3,Peripheral voltage monitoring output: VDDA vs" "0,1"
|
|
bitfld.long 0x00 13. "PVMO2,Peripheral voltage monitoring output: VDDIO2 vs" "0,1"
|
|
bitfld.long 0x00 12. "PVMO1,Peripheral voltage monitoring output: VDDUSB vs" "0,1"
|
|
bitfld.long 0x00 11. "PVDO,Power voltage detector output" "0,1"
|
|
bitfld.long 0x00 10. "VOSF,Voltage scaling flag" "0,1"
|
|
bitfld.long 0x00 9. "REGLPF,Low-power regulator flag" "0,1"
|
|
bitfld.long 0x00 8. "REGLPS,Low-power regulator started" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "SCR,Power status clear register"
|
|
bitfld.long 0x00 8. "CSBF,Clear standby flag" "0,1"
|
|
bitfld.long 0x00 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
bitfld.long 0x00 3. "CWUF4,Clear wakeup flag 4" "0,1"
|
|
bitfld.long 0x00 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
bitfld.long 0x00 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
bitfld.long 0x00 0. "CWUF1,Clear wakeup flag 1" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PUCRA,Power Port A pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port A pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port A pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PDCRA,Power Port A pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port A pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port A pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PUCRB,Power Port B pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port B pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port B pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PDCRB,Power Port B pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port B pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port B pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PUCRC,Power Port C pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port C pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PDCRC,Power Port C pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port C pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PUCRD,Power Port D pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port D pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PDCRD,Power Port D pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port D pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PUCRE,Power Port E pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port E pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port E pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PDCRE,Power Port E pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port E pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port E pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PUCRF,Power Port F pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port F pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port F pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PDCRF,Power Port F pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port F pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port F pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PUCRG,Power Port G pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port G pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port G pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PDCRG,Power Port G pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port G pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port G pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PUCRH,Power Port H pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port G pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port G pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PDCRH,Power Port H pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port G pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port G pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "SECCFGR,Power secure configuration register"
|
|
bitfld.long 0x00 11. "APCSEC,APCSEC" "0,1"
|
|
bitfld.long 0x00 10. "VBSEC,VBSEC" "0,1"
|
|
bitfld.long 0x00 9. "VDMSEC,VDMSEC" "0,1"
|
|
bitfld.long 0x00 8. "LPMSEC,LPMSEC" "0,1"
|
|
bitfld.long 0x00 4. "WUP5SEC,WKUP5 pin security" "0,1"
|
|
bitfld.long 0x00 3. "WUP4SEC,WKUP4 pin security" "0,1"
|
|
bitfld.long 0x00 2. "WUP3SEC,WKUP3 pin security" "0,1"
|
|
bitfld.long 0x00 1. "WUP2SEC,WKUP2 pin security" "0,1"
|
|
bitfld.long 0x00 0. "WUP1SEC,WKUP1 pin security" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PRIVCFGR,Power privilege configuration register"
|
|
bitfld.long 0x00 0. "PRIV,PRIV" "0,1"
|
|
tree.end
|
|
tree "SEC_PWR"
|
|
base ad:0x50007000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Power control register 1"
|
|
bitfld.long 0x00 14. "LPR,Low-power run" "0,1"
|
|
bitfld.long 0x00 9.--10. "VOS,Voltage scaling range selection" "0,1,2,3"
|
|
bitfld.long 0x00 8. "DBP,Disable backup domain write protection" "0,1"
|
|
bitfld.long 0x00 0.--2. "LPMS,Low-power mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Power control register 2"
|
|
bitfld.long 0x00 10. "USV,VDDUSB USB supply valid" "0,1"
|
|
bitfld.long 0x00 9. "IOSV,VDDIO2 Independent I/Os supply valid" "0,1"
|
|
bitfld.long 0x00 7. "PVME4,Peripheral voltage monitoring 4 enable: VDDA vs" "0,1"
|
|
bitfld.long 0x00 6. "PVME3,Peripheral voltage monitoring 3 enable: VDDA vs" "0,1"
|
|
bitfld.long 0x00 5. "PVME2,Peripheral voltage monitoring 2 enable: VDDIO2 vs" "0,1"
|
|
bitfld.long 0x00 4. "PVME1,Peripheral voltage monitoring 1 enable: VDDUSB vs" "0,1"
|
|
bitfld.long 0x00 1.--3. "PLS,Power voltage detector level selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "PVDE,Power voltage detector enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Power control register 3"
|
|
bitfld.long 0x00 14. "UCPD_DBDIS,UCPD_DBDIS" "0,1"
|
|
bitfld.long 0x00 13. "UCPD_STDBY,UCPD_STDBY" "0,1"
|
|
bitfld.long 0x00 11. "ULPMEN,ULPMEN" "0,1"
|
|
bitfld.long 0x00 10. "APC,Apply pull-up and pull-down configuration" "0,1"
|
|
bitfld.long 0x00 8.--9. "RRS,SRAM2 retention in Standby mode" "0,1,2,3"
|
|
bitfld.long 0x00 4. "EWUP5,Enable Wakeup pin WKUP5" "0,1"
|
|
bitfld.long 0x00 3. "EWUP4,Enable Wakeup pin WKUP4" "0,1"
|
|
bitfld.long 0x00 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
bitfld.long 0x00 1. "EWUP2,Enable Wakeup pin WKUP2" "0,1"
|
|
bitfld.long 0x00 0. "EWUP1,Enable Wakeup pin WKUP1" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR4,Power control register 4"
|
|
bitfld.long 0x00 15. "SMPSLPEN,SMPSLPEN" "0,1"
|
|
bitfld.long 0x00 14. "SMPSFSTEN,SMPSFSTEN" "0,1"
|
|
bitfld.long 0x00 13. "EXTSMPSEN,EXTSMPSEN" "0,1"
|
|
bitfld.long 0x00 12. "SMPSBYP,SMPSBYP" "0,1"
|
|
bitfld.long 0x00 9. "VBRS,VBAT battery charging resistor selection" "0,1"
|
|
bitfld.long 0x00 8. "VBE,VBAT battery charging enable" "0,1"
|
|
bitfld.long 0x00 4. "WUPP5,Wakeup pin WKUP5 polarity" "0,1"
|
|
bitfld.long 0x00 3. "WUPP4,Wakeup pin WKUP4 polarity" "0,1"
|
|
bitfld.long 0x00 2. "WUPP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
bitfld.long 0x00 1. "WUPP2,Wakeup pin WKUP2 polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WUPP1,Wakeup pin WKUP1 polarity" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SR1,Power status register 1"
|
|
bitfld.long 0x00 15. "SMPSHPRDY,SMPSHPRDY" "0,1"
|
|
bitfld.long 0x00 13. "EXTSMPSRDY,EXTSMPSRDY" "0,1"
|
|
bitfld.long 0x00 12. "SMPSBYPRDY,SMPSBYPRDY" "0,1"
|
|
bitfld.long 0x00 8. "SBF,Standby flag" "0,1"
|
|
bitfld.long 0x00 4. "WUF5,Wakeup flag 5" "0,1"
|
|
bitfld.long 0x00 3. "WUF4,Wakeup flag 4" "0,1"
|
|
bitfld.long 0x00 2. "WUF3,Wakeup flag 3" "0,1"
|
|
bitfld.long 0x00 1. "WUF2,Wakeup flag 2" "0,1"
|
|
bitfld.long 0x00 0. "WUF1,Wakeup flag 1" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SR2,Power status register 2"
|
|
bitfld.long 0x00 15. "PVMO4,Peripheral voltage monitoring output: VDDA vs" "0,1"
|
|
bitfld.long 0x00 14. "PVMO3,Peripheral voltage monitoring output: VDDA vs" "0,1"
|
|
bitfld.long 0x00 13. "PVMO2,Peripheral voltage monitoring output: VDDIO2 vs" "0,1"
|
|
bitfld.long 0x00 12. "PVMO1,Peripheral voltage monitoring output: VDDUSB vs" "0,1"
|
|
bitfld.long 0x00 11. "PVDO,Power voltage detector output" "0,1"
|
|
bitfld.long 0x00 10. "VOSF,Voltage scaling flag" "0,1"
|
|
bitfld.long 0x00 9. "REGLPF,Low-power regulator flag" "0,1"
|
|
bitfld.long 0x00 8. "REGLPS,Low-power regulator started" "0,1"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "SCR,Power status clear register"
|
|
bitfld.long 0x00 8. "CSBF,Clear standby flag" "0,1"
|
|
bitfld.long 0x00 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
bitfld.long 0x00 3. "CWUF4,Clear wakeup flag 4" "0,1"
|
|
bitfld.long 0x00 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
bitfld.long 0x00 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
bitfld.long 0x00 0. "CWUF1,Clear wakeup flag 1" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PUCRA,Power Port A pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port A pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port A pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port A pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PDCRA,Power Port A pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port A pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port A pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port A pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PUCRB,Power Port B pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port B pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port B pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port B pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PDCRB,Power Port B pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port B pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port B pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port B pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PUCRC,Power Port C pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port C pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port C pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port C pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PDCRC,Power Port C pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port C pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port C pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port C pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PUCRD,Power Port D pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port D pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port D pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port D pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PDCRD,Power Port D pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port D pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port D pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port D pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PUCRE,Power Port E pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port E pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port E pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port E pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PDCRE,Power Port E pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port E pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port E pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port E pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PUCRF,Power Port F pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port F pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port F pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port F pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PDCRF,Power Port F pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port F pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port F pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port F pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PUCRG,Power Port G pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port G pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port G pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PDCRG,Power Port G pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port G pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port G pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PUCRH,Power Port H pull-up control register"
|
|
bitfld.long 0x00 15. "PU15,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PU14,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PU13,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PU12,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PU11,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PU10,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PU9,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PU8,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PU7,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PU6,Port G pull-up bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PU5,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PU4,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PU3,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PU2,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PU1,Port G pull-up bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PU0,Port G pull-up bit y (y=0..15)" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PDCRH,Power Port H pull-down control register"
|
|
bitfld.long 0x00 15. "PD15,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 14. "PD14,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 13. "PD13,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 12. "PD12,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 11. "PD11,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 10. "PD10,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 9. "PD9,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 8. "PD8,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 7. "PD7,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 6. "PD6,Port G pull-down bit y (y=0..15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD5,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 4. "PD4,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 3. "PD3,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 2. "PD2,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 1. "PD1,Port G pull-down bit y (y=0..15)" "0,1"
|
|
bitfld.long 0x00 0. "PD0,Port G pull-down bit y (y=0..15)" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "SECCFGR,Power secure configuration register"
|
|
bitfld.long 0x00 11. "APCSEC,APCSEC" "0,1"
|
|
bitfld.long 0x00 10. "VBSEC,VBSEC" "0,1"
|
|
bitfld.long 0x00 9. "VDMSEC,VDMSEC" "0,1"
|
|
bitfld.long 0x00 8. "LPMSEC,LPMSEC" "0,1"
|
|
bitfld.long 0x00 4. "WUP5SEC,WKUP5 pin security" "0,1"
|
|
bitfld.long 0x00 3. "WUP4SEC,WKUP4 pin security" "0,1"
|
|
bitfld.long 0x00 2. "WUP3SEC,WKUP3 pin security" "0,1"
|
|
bitfld.long 0x00 1. "WUP2SEC,WKUP2 pin security" "0,1"
|
|
bitfld.long 0x00 0. "WUP1SEC,WKUP1 pin security" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PRIVCFGR,Power privilege configuration register"
|
|
bitfld.long 0x00 0. "PRIV,PRIV" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "RCC (Reset and clock control)"
|
|
tree "RCC"
|
|
base ad:0x40021000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Clock control register"
|
|
bitfld.long 0x00 31. "PRIV,PRIV" "0,1"
|
|
rbitfld.long 0x00 29. "PLLSAI2RDY,SAI2 PLL clock ready flag" "0,1"
|
|
bitfld.long 0x00 28. "PLLSAI2ON,SAI2 PLL enable" "0,1"
|
|
rbitfld.long 0x00 27. "PLLSAI1RDY,SAI1 PLL clock ready flag" "0,1"
|
|
bitfld.long 0x00 26. "PLLSAI1ON,SAI1 PLL enable" "0,1"
|
|
rbitfld.long 0x00 25. "PLLRDY,Main PLL clock ready flag" "0,1"
|
|
bitfld.long 0x00 24. "PLLON,Main PLL enable" "0,1"
|
|
bitfld.long 0x00 19. "CSSON,Clock security system enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "HSEBYP,HSE crystal oscillator bypass" "0,1"
|
|
rbitfld.long 0x00 17. "HSERDY,HSE clock ready flag" "0,1"
|
|
bitfld.long 0x00 16. "HSEON,HSE clock enable" "0,1"
|
|
bitfld.long 0x00 11. "HSIASFS,HSI automatic start from Stop" "0,1"
|
|
rbitfld.long 0x00 10. "HSIRDY,HSI clock ready flag" "0,1"
|
|
bitfld.long 0x00 9. "HSIKERON,HSI always enable for peripheral kernels" "0,1"
|
|
bitfld.long 0x00 8. "HSION,HSI clock enable" "0,1"
|
|
bitfld.long 0x00 4.--7. "MSIRANGE,MSI clock ranges" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "MSIRGSEL,MSI clock range selection" "0,1"
|
|
bitfld.long 0x00 2. "MSIPLLEN,MSI clock PLL enable" "0,1"
|
|
rbitfld.long 0x00 1. "MSIRDY,MSI clock ready flag" "0,1"
|
|
bitfld.long 0x00 0. "MSION,MSI clock enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICSCR,Internal clock sources calibration register"
|
|
hexmask.long.byte 0x00 24.--30. 1. "HSITRIM,HSI clock trimming"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HSICAL,HSI clock calibration"
|
|
hexmask.long.byte 0x00 8.--15. 1. "MSITRIM,MSI clock trimming"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MSICAL,MSI clock calibration"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CFGR,Clock configuration register"
|
|
rbitfld.long 0x00 28.--30. "MCOPRE,Microcontroller clock output prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--27. "MCOSEL,Microcontroller clock output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "STOPWUCK,Wakeup from Stop and CSS backup clock selection" "0,1"
|
|
bitfld.long 0x00 11.--13. "PPRE2,APB high-speed prescaler (APB2)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PPRE1,PB low-speed prescaler (APB1)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--7. "HPRE,AHB prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 2.--3. "SWS,System clock switch status" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SW,System clock switch" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PLLCFGR,PLL configuration register"
|
|
bitfld.long 0x00 27.--31. "PLLPDIV,Main PLL division factor for PLLSAI2CLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 25.--26. "PLLR,Main PLL division factor for PLLCLK (system clock)" "0,1,2,3"
|
|
bitfld.long 0x00 24. "PLLREN,Main PLL PLLCLK output enable" "0,1"
|
|
bitfld.long 0x00 21.--22. "PLLQ,Main PLL division factor for PLLUSB1CLK(48 MHz clock)" "0,1,2,3"
|
|
bitfld.long 0x00 20. "PLLQEN,Main PLL PLLUSB1CLK output enable" "0,1"
|
|
bitfld.long 0x00 17. "PLLP,Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)" "0,1"
|
|
bitfld.long 0x00 16. "PLLPEN,Main PLL PLLSAI3CLK output enable" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "PLLN,Main PLL multiplication factor for VCO"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PLLM,Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "PLLSRC,Main PLL PLLSAI1 and PLLSAI2 entry clock source" "0,1,2,3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PLLSAI1CFGR,PLLSAI1 configuration register"
|
|
bitfld.long 0x00 27.--31. "PLLSAI1PDIV,PLLSAI1 division factor for PLLSAI1CLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 25.--26. "PLLSAI1R,PLLSAI1 division factor for PLLADC1CLK (ADC clock)" "0,1,2,3"
|
|
bitfld.long 0x00 24. "PLLSAI1REN,PLLSAI1 PLLADC1CLK output enable" "0,1"
|
|
bitfld.long 0x00 21.--22. "PLLSAI1Q,SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)" "0,1,2,3"
|
|
bitfld.long 0x00 20. "PLLSAI1QEN,SAI1PLL PLLUSB2CLK output enable" "0,1"
|
|
bitfld.long 0x00 17. "PLLSAI1P,SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)" "0,1"
|
|
bitfld.long 0x00 16. "PLLSAI1PEN,SAI1PLL PLLSAI1CLK output enable" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "PLLSAI1N,SAI1PLL multiplication factor for VCO"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PLLSAI1M,Division factor for PLLSAI1 input clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "PLLSAI1SRC,PLLSAI1SRC" "0,1,2,3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PLLSAI2CFGR,PLLSAI2 configuration register"
|
|
bitfld.long 0x00 27.--31. "PLLSAI2PDIV,PLLSAI2 division factor for PLLSAI2CLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17. "PLLSAI2P,SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)" "0,1"
|
|
bitfld.long 0x00 16. "PLLSAI2PEN,SAI2PLL PLLSAI2CLK output enable" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "PLLSAI2N,SAI2PLL multiplication factor for VCO"
|
|
bitfld.long 0x00 4.--7. "PLLSAI2M,Division factor for PLLSAI2 input clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "PLLSAI2SRC,PLLSAI2SRC" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CIER,Clock interrupt enable register"
|
|
bitfld.long 0x00 10. "HSI48RDYIE,HSI48 ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 9. "LSECSSIE,LSE clock security system interrupt enable" "0,1"
|
|
bitfld.long 0x00 7. "PLLSAI2RDYIE,PLLSAI2 ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "PLLSAI1RDYIE,PLLSAI1 ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "PLLRDYIE,PLL ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "HSERDYIE,HSE ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "HSIRDYIE,HSI ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "MSIRDYIE,MSI ready interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LSERDYIE,LSE ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "LSIRDYIE,LSI ready interrupt enable" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CIFR,Clock interrupt flag register"
|
|
bitfld.long 0x00 10. "HSI48RDYF,HSI48 ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 9. "LSECSSF,LSE Clock security system interrupt flag" "0,1"
|
|
bitfld.long 0x00 8. "CSSF,Clock security system interrupt flag" "0,1"
|
|
bitfld.long 0x00 7. "PLLSAI2RDYF,PLLSAI2 ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 6. "PLLSAI1RDYF,PLLSAI1 ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "PLLRDYF,PLL ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "HSERDYF,HSE ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "HSIRDYF,HSI ready interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "MSIRDYF,MSI ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "LSERDYF,LSE ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "LSIRDYF,LSI ready interrupt flag" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "CICR,Clock interrupt clear register"
|
|
bitfld.long 0x00 10. "HSI48RDYC,HSI48 oscillator ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 9. "LSECSSC,LSE Clock security system interrupt clear" "0,1"
|
|
bitfld.long 0x00 8. "CSSC,Clock security system interrupt clear" "0,1"
|
|
bitfld.long 0x00 7. "PLLSAI2RDYC,PLLSAI2 ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 6. "PLLSAI1RDYC,PLLSAI1 ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 5. "PLLRDYC,PLL ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 4. "HSERDYC,HSE ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 3. "HSIRDYC,HSI ready interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "MSIRDYC,MSI ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 1. "LSERDYC,LSE ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 0. "LSIRDYC,LSI ready interrupt clear" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "AHB1RSTR,AHB1 peripheral reset register"
|
|
bitfld.long 0x00 22. "GTZCRST,GTZC reset" "0,1"
|
|
bitfld.long 0x00 16. "TSCRST,Touch Sensing Controller reset" "0,1"
|
|
bitfld.long 0x00 12. "CRCRST,CRC reset" "0,1"
|
|
bitfld.long 0x00 8. "FLASHRST,Flash memory interface reset" "0,1"
|
|
bitfld.long 0x00 2. "DMAMUX1RST,DMAMUXRST" "0,1"
|
|
bitfld.long 0x00 1. "DMA2RST,DMA2 reset" "0,1"
|
|
bitfld.long 0x00 0. "DMA1RST,DMA1 reset" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "AHB2RSTR,AHB2 peripheral reset register"
|
|
bitfld.long 0x00 22. "SDMMC1RST,SDMMC1 reset" "0,1"
|
|
bitfld.long 0x00 21. "OTFDEC1RST,OTFDEC1RST" "0,1"
|
|
bitfld.long 0x00 19. "PKARST,PKARST" "0,1"
|
|
bitfld.long 0x00 18. "RNGRST,Random number generator reset" "0,1"
|
|
bitfld.long 0x00 17. "HASHRST,Hash reset" "0,1"
|
|
bitfld.long 0x00 16. "AESRST,AES hardware accelerator reset" "0,1"
|
|
bitfld.long 0x00 13. "ADCRST,ADC reset" "0,1"
|
|
bitfld.long 0x00 7. "GPIOHRST,IO port H reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "GPIOGRST,IO port G reset" "0,1"
|
|
bitfld.long 0x00 5. "GPIOFRST,IO port F reset" "0,1"
|
|
bitfld.long 0x00 4. "GPIOERST,IO port E reset" "0,1"
|
|
bitfld.long 0x00 3. "GPIODRST,IO port D reset" "0,1"
|
|
bitfld.long 0x00 2. "GPIOCRST,IO port C reset" "0,1"
|
|
bitfld.long 0x00 1. "GPIOBRST,IO port B reset" "0,1"
|
|
bitfld.long 0x00 0. "GPIOARST,IO port A reset" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "AHB3RSTR,AHB3 peripheral reset register"
|
|
bitfld.long 0x00 8. "OSPI1RST,OSPI1RST" "0,1"
|
|
bitfld.long 0x00 0. "FMCRST,Flexible memory controller reset" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "APB1RSTR1,APB1 peripheral reset register 1"
|
|
bitfld.long 0x00 31. "LPTIM1RST,Low Power Timer 1 reset" "0,1"
|
|
bitfld.long 0x00 30. "OPAMPRST,OPAMP interface reset" "0,1"
|
|
bitfld.long 0x00 29. "DAC1RST,DAC1 interface reset" "0,1"
|
|
bitfld.long 0x00 28. "PWRRST,Power interface reset" "0,1"
|
|
bitfld.long 0x00 24. "CRSRST,CRS reset" "0,1"
|
|
bitfld.long 0x00 23. "I2C3RST,I2C3 reset" "0,1"
|
|
bitfld.long 0x00 22. "I2C2RST,I2C2 reset" "0,1"
|
|
bitfld.long 0x00 21. "I2C1RST,I2C1 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "UART5RST,UART5 reset" "0,1"
|
|
bitfld.long 0x00 19. "UART4RST,UART4 reset" "0,1"
|
|
bitfld.long 0x00 18. "USART3RST,USART3 reset" "0,1"
|
|
bitfld.long 0x00 17. "USART2RST,USART2 reset" "0,1"
|
|
bitfld.long 0x00 15. "SPI3RST,SPI3 reset" "0,1"
|
|
bitfld.long 0x00 14. "SPI2RST,SPI2 reset" "0,1"
|
|
bitfld.long 0x00 5. "TIM7RST,TIM7 timer reset" "0,1"
|
|
bitfld.long 0x00 4. "TIM6RST,TIM6 timer reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TIM5RST,TIM5 timer reset" "0,1"
|
|
bitfld.long 0x00 2. "TIM4RST,TIM3 timer reset" "0,1"
|
|
bitfld.long 0x00 1. "TIM3RST,TIM3 timer reset" "0,1"
|
|
bitfld.long 0x00 0. "TIM2RST,TIM2 timer reset" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "APB1RSTR2,APB1 peripheral reset register 2"
|
|
bitfld.long 0x00 23. "UCPD1RST,UCPD1RST" "0,1"
|
|
bitfld.long 0x00 21. "USBFSRST,USBFSRST" "0,1"
|
|
bitfld.long 0x00 9. "FDCAN1RST,FDCAN1RST" "0,1"
|
|
bitfld.long 0x00 6. "LPTIM3RST,LPTIM3RST" "0,1"
|
|
bitfld.long 0x00 5. "LPTIM2RST,Low-power timer 2 reset" "0,1"
|
|
bitfld.long 0x00 1. "I2C4RST,I2C4 reset" "0,1"
|
|
bitfld.long 0x00 0. "LPUART1RST,Low-power UART 1 reset" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "APB2RSTR,APB2 peripheral reset register"
|
|
bitfld.long 0x00 24. "DFSDM1RST,Digital filters for sigma-delata modulators (DFSDM) reset" "0,1"
|
|
bitfld.long 0x00 22. "SAI2RST,Serial audio interface 2 (SAI2) reset" "0,1"
|
|
bitfld.long 0x00 21. "SAI1RST,Serial audio interface 1 (SAI1) reset" "0,1"
|
|
bitfld.long 0x00 18. "TIM17RST,TIM17 timer reset" "0,1"
|
|
bitfld.long 0x00 17. "TIM16RST,TIM16 timer reset" "0,1"
|
|
bitfld.long 0x00 16. "TIM15RST,TIM15 timer reset" "0,1"
|
|
bitfld.long 0x00 14. "USART1RST,USART1 reset" "0,1"
|
|
bitfld.long 0x00 13. "TIM8RST,TIM8 timer reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "SPI1RST,SPI1 reset" "0,1"
|
|
bitfld.long 0x00 11. "TIM1RST,TIM1 timer reset" "0,1"
|
|
bitfld.long 0x00 0. "SYSCFGRST,System configuration (SYSCFG) reset" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "AHB1ENR,AHB1 peripheral clock enable register"
|
|
bitfld.long 0x00 22. "GTZCEN,GTZCEN" "0,1"
|
|
bitfld.long 0x00 16. "TSCEN,Touch Sensing Controller clock enable" "0,1"
|
|
bitfld.long 0x00 12. "CRCEN,CRC clock enable" "0,1"
|
|
bitfld.long 0x00 8. "FLASHEN,Flash memory interface clock enable" "0,1"
|
|
bitfld.long 0x00 2. "DMAMUX1EN,DMAMUX clock enable" "0,1"
|
|
bitfld.long 0x00 1. "DMA2EN,DMA2 clock enable" "0,1"
|
|
bitfld.long 0x00 0. "DMA1EN,DMA1 clock enable" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "AHB2ENR,AHB2 peripheral clock enable register"
|
|
bitfld.long 0x00 22. "SDMMC1EN,SDMMC1 clock enable" "0,1"
|
|
bitfld.long 0x00 21. "OTFDEC1EN,OTFDEC1EN" "0,1"
|
|
bitfld.long 0x00 19. "PKAEN,PKAEN" "0,1"
|
|
bitfld.long 0x00 18. "RNGEN,Random Number Generator clock enable" "0,1"
|
|
bitfld.long 0x00 17. "HASHEN,HASH clock enable" "0,1"
|
|
bitfld.long 0x00 16. "AESEN,AES accelerator clock enable" "0,1"
|
|
bitfld.long 0x00 13. "ADCEN,ADC clock enable" "0,1"
|
|
bitfld.long 0x00 7. "GPIOHEN,IO port H clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "GPIOGEN,IO port G clock enable" "0,1"
|
|
bitfld.long 0x00 5. "GPIOFEN,IO port F clock enable" "0,1"
|
|
bitfld.long 0x00 4. "GPIOEEN,IO port E clock enable" "0,1"
|
|
bitfld.long 0x00 3. "GPIODEN,IO port D clock enable" "0,1"
|
|
bitfld.long 0x00 2. "GPIOCEN,IO port C clock enable" "0,1"
|
|
bitfld.long 0x00 1. "GPIOBEN,IO port B clock enable" "0,1"
|
|
bitfld.long 0x00 0. "GPIOAEN,IO port A clock enable" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "AHB3ENR,AHB3 peripheral clock enable register"
|
|
bitfld.long 0x00 8. "OSPI1EN,OSPI1EN" "0,1"
|
|
bitfld.long 0x00 0. "FMCEN,Flexible memory controller clock enable" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "APB1ENR1,APB1ENR1"
|
|
bitfld.long 0x00 31. "LPTIM1EN,Low power timer 1 clock enable" "0,1"
|
|
bitfld.long 0x00 30. "OPAMPEN,OPAMP interface clock enable" "0,1"
|
|
bitfld.long 0x00 29. "DAC1EN,DAC1 interface clock enable" "0,1"
|
|
bitfld.long 0x00 28. "PWREN,Power interface clock enable" "0,1"
|
|
bitfld.long 0x00 24. "CRSEN,Clock Recovery System clock enable" "0,1"
|
|
bitfld.long 0x00 23. "I2C3EN,I2C3 clock enable" "0,1"
|
|
bitfld.long 0x00 22. "I2C2EN,I2C2 clock enable" "0,1"
|
|
bitfld.long 0x00 21. "I2C1EN,I2C1 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "UART5EN,UART5 clock enable" "0,1"
|
|
bitfld.long 0x00 19. "UART4EN,UART4 clock enable" "0,1"
|
|
bitfld.long 0x00 18. "USART3EN,USART3 clock enable" "0,1"
|
|
bitfld.long 0x00 17. "USART2EN,USART2 clock enable" "0,1"
|
|
bitfld.long 0x00 15. "SP3EN,SPI3 clock enable" "0,1"
|
|
bitfld.long 0x00 14. "SPI2EN,SPI2 clock enable" "0,1"
|
|
bitfld.long 0x00 11. "WWDGEN,Window watchdog clock enable" "0,1"
|
|
bitfld.long 0x00 10. "RTCAPBEN,RTC APB clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TIM7EN,TIM7 timer clock enable" "0,1"
|
|
bitfld.long 0x00 4. "TIM6EN,TIM6 timer clock enable" "0,1"
|
|
bitfld.long 0x00 3. "TIM5EN,TIM5 timer clock enable" "0,1"
|
|
bitfld.long 0x00 2. "TIM4EN,TIM4 timer clock enable" "0,1"
|
|
bitfld.long 0x00 1. "TIM3EN,TIM3 timer clock enable" "0,1"
|
|
bitfld.long 0x00 0. "TIM2EN,TIM2 timer clock enable" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "APB1ENR2,APB1 peripheral clock enable register 2"
|
|
bitfld.long 0x00 23. "UCPD1EN,UCPD1EN" "0,1"
|
|
bitfld.long 0x00 21. "USBFSEN,USBFSEN" "0,1"
|
|
bitfld.long 0x00 9. "FDCAN1EN,FDCAN1EN" "0,1"
|
|
bitfld.long 0x00 6. "LPTIM3EN,LPTIM3EN" "0,1"
|
|
bitfld.long 0x00 5. "LPTIM2EN,LPTIM2EN" "0,1"
|
|
bitfld.long 0x00 1. "I2C4EN,I2C4 clock enable" "0,1"
|
|
bitfld.long 0x00 0. "LPUART1EN,Low power UART 1 clock enable" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "APB2ENR,APB2ENR"
|
|
bitfld.long 0x00 24. "DFSDM1EN,DFSDM timer clock enable" "0,1"
|
|
bitfld.long 0x00 22. "SAI2EN,SAI2 clock enable" "0,1"
|
|
bitfld.long 0x00 21. "SAI1EN,SAI1 clock enable" "0,1"
|
|
bitfld.long 0x00 18. "TIM17EN,TIM17 timer clock enable" "0,1"
|
|
bitfld.long 0x00 17. "TIM16EN,TIM16 timer clock enable" "0,1"
|
|
bitfld.long 0x00 16. "TIM15EN,TIM15 timer clock enable" "0,1"
|
|
bitfld.long 0x00 14. "USART1EN,USART1clock enable" "0,1"
|
|
bitfld.long 0x00 13. "TIM8EN,TIM8 timer clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "SPI1EN,SPI1 clock enable" "0,1"
|
|
bitfld.long 0x00 11. "TIM1EN,TIM1 timer clock enable" "0,1"
|
|
bitfld.long 0x00 0. "SYSCFGEN,SYSCFG clock enable" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "AHB1SMENR,AHB1 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x00 23. "ICACHESMEN,ICACHESMEN" "0,1"
|
|
bitfld.long 0x00 22. "GTZCSMEN,GTZCSMEN" "0,1"
|
|
bitfld.long 0x00 16. "TSCSMEN,Touch Sensing Controller clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 12. "CRCSMEN,CRCSMEN" "0,1"
|
|
bitfld.long 0x00 9. "SRAM1SMEN,SRAM1 interface clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 8. "FLASHSMEN,Flash memory interface clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 2. "DMAMUX1SMEN,DMAMUX clock enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 1. "DMA2SMEN,DMA2 clocks enable during Sleep and Stop modes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA1SMEN,DMA1 clocks enable during Sleep and Stop modes" "0,1"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "AHB2SMENR,AHB2 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x00 22. "SDMMC1SMEN,SDMMC1 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 21. "OTFDEC1SMEN,OTFDEC1SMEN" "0,1"
|
|
bitfld.long 0x00 19. "PKASMEN,PKASMEN" "0,1"
|
|
bitfld.long 0x00 18. "RNGSMEN,Random Number Generator clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 17. "HASHSMEN,HASH clock enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 16. "AESSMEN,AES accelerator clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 13. "ADCFSSMEN,ADC clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 9. "SRAM2SMEN,SRAM2 interface clocks enable during Sleep and Stop modes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "GPIOHSMEN,IO port H clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 6. "GPIOGSMEN,IO port G clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 5. "GPIOFSMEN,IO port F clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 4. "GPIOESMEN,IO port E clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 3. "GPIODSMEN,IO port D clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 2. "GPIOCSMEN,IO port C clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 1. "GPIOBSMEN,IO port B clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 0. "GPIOASMEN,IO port A clocks enable during Sleep and Stop modes" "0,1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "AHB3SMENR,AHB3 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x00 8. "OSPI1SMEN,OSPI1SMEN" "0,1"
|
|
bitfld.long 0x00 0. "FMCSMEN,Flexible memory controller clocks enable during Sleep and Stop modes" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "APB1SMENR1,APB1SMENR1"
|
|
bitfld.long 0x00 31. "LPTIM1SMEN,Low power timer 1 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 30. "OPAMPSMEN,OPAMP interface clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 29. "DAC1SMEN,DAC1 interface clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 28. "PWRSMEN,Power interface clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 24. "CRSSMEN,CRS clock enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 23. "I2C3SMEN,I2C3 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 22. "I2C2SMEN,I2C2 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 21. "I2C1SMEN,I2C1 clocks enable during Sleep and Stop modes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "UART5SMEN,UART5 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 19. "UART4SMEN,UART4 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 18. "USART3SMEN,USART3 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 17. "USART2SMEN,USART2 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 15. "SP3SMEN,SPI3 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 14. "SPI2SMEN,SPI2 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 11. "WWDGSMEN,Window watchdog clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 10. "RTCAPBSMEN,RTC APB clock enable during Sleep and Stop modes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TIM7SMEN,TIM7 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 4. "TIM6SMEN,TIM6 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 3. "TIM5SMEN,TIM5 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 2. "TIM4SMEN,TIM4 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 1. "TIM3SMEN,TIM3 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 0. "TIM2SMEN,TIM2 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "APB1SMENR2,APB1 peripheral clocks enable in Sleep and Stop modes register 2"
|
|
bitfld.long 0x00 23. "UCPD1SMEN,UCPD1SMEN" "0,1"
|
|
bitfld.long 0x00 21. "USBFSSMEN,USBFSSMEN" "0,1"
|
|
bitfld.long 0x00 9. "FDCAN1SMEN,FDCAN1SMEN" "0,1"
|
|
bitfld.long 0x00 6. "LPTIM3SMEN,LPTIM3SMEN" "0,1"
|
|
bitfld.long 0x00 5. "LPTIM2SMEN,LPTIM2SMEN" "0,1"
|
|
bitfld.long 0x00 1. "I2C4SMEN,I2C4 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 0. "LPUART1SMEN,Low power UART 1 clocks enable during Sleep and Stop modes" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "APB2SMENR,APB2SMENR"
|
|
bitfld.long 0x00 24. "DFSDM1SMEN,DFSDM timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 22. "SAI2SMEN,SAI2 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 21. "SAI1SMEN,SAI1 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 18. "TIM17SMEN,TIM17 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 17. "TIM16SMEN,TIM16 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 16. "TIM15SMEN,TIM15 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 14. "USART1SMEN,USART1clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 13. "TIM8SMEN,TIM8 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "SPI1SMEN,SPI1 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 11. "TIM1SMEN,TIM1 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 0. "SYSCFGSMEN,SYSCFG clocks enable during Sleep and Stop modes" "0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CCIPR1,CCIPR1"
|
|
bitfld.long 0x00 28.--29. "ADCSEL,ADCs clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "CLK48MSEL,48 MHz clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "FDCANSEL,FDCAN clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "LPTIM3SEL,Low-power timer 3 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "LPTIM2SEL,Low power timer 2 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "LPTIM1SEL,Low power timer 1 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "I2C3SEL,I2C3 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "I2C2SEL,I2C2 clock source selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "I2C1SEL,I2C1 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "LPUART1SEL,LPUART1 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "UART5SEL,UART5 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "UART4SEL,UART4 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "USART3SEL,USART3 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "USART2SEL,USART2 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "USART1SEL,USART1 clock source selection" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "BDCR,BDCR"
|
|
bitfld.long 0x00 25. "LSCOSEL,Low speed clock output selection" "0,1"
|
|
bitfld.long 0x00 24. "LSCOEN,Low speed clock output enable" "0,1"
|
|
bitfld.long 0x00 16. "BDRST,Backup domain software reset" "0,1"
|
|
bitfld.long 0x00 15. "RTCEN,RTC clock enable" "0,1"
|
|
bitfld.long 0x00 11. "LSESYSRDY,LSESYSRDY" "0,1"
|
|
bitfld.long 0x00 8.--9. "RTCSEL,RTC clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "LSESYSEN,LSESYSEN" "0,1"
|
|
rbitfld.long 0x00 6. "LSECSSD,LSECSSD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "LSECSSON,LSECSSON" "0,1"
|
|
bitfld.long 0x00 3.--4. "LSEDRV,SE oscillator drive capability" "0,1,2,3"
|
|
bitfld.long 0x00 2. "LSEBYP,LSE oscillator bypass" "0,1"
|
|
rbitfld.long 0x00 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
bitfld.long 0x00 0. "LSEON,LSE oscillator enable" "0,1"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CSR,CSR"
|
|
rbitfld.long 0x00 31. "LPWRSTF,Low-power reset flag" "0,1"
|
|
rbitfld.long 0x00 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
rbitfld.long 0x00 29. "IWWDGRSTF,Independent window watchdog reset flag" "0,1"
|
|
rbitfld.long 0x00 28. "SFTRSTF,Software reset flag" "0,1"
|
|
rbitfld.long 0x00 27. "BORRSTF,BOR flag" "0,1"
|
|
rbitfld.long 0x00 26. "PINRSTF,Pin reset flag" "0,1"
|
|
rbitfld.long 0x00 25. "OBLRSTF,Option byte loader reset flag" "0,1"
|
|
bitfld.long 0x00 23. "RMVF,Remove reset flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "MSISRANGE,SI range after Standby mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. "LSIPREDIV,LSIPREDIV" "0,1"
|
|
rbitfld.long 0x00 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
bitfld.long 0x00 0. "LSION,LSI oscillator enable" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CRRCR,Clock recovery RC register"
|
|
hexmask.long.word 0x00 7.--15. 1. "HSI48CAL,HSI48 clock calibration"
|
|
rbitfld.long 0x00 1. "HSI48RDY,HSI48 clock ready flag" "0,1"
|
|
bitfld.long 0x00 0. "HSI48ON,HSI48 clock enable" "0,1"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CCIPR2,Peripherals independent clock configuration register"
|
|
bitfld.long 0x00 20.--21. "OSPISEL,Octospi clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 14. "SDMMCSEL,SDMMC clock selection" "0,1"
|
|
bitfld.long 0x00 8.--10. "SAI2SEL,SAI2 clock source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. "SAI1SEL,SAI1 clock source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. "ADFSDMSEL,Digital filter for sigma delta modulator audio clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 2. "DFSDMSEL,Digital filter for sigma delta modulator kernel clock source selection" "0,1"
|
|
bitfld.long 0x00 0.--1. "I2C4SEL,I2C4 clock source selection" "0,1,2,3"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "SECCFGR,RCC secure configuration register"
|
|
bitfld.long 0x00 12. "RMVFSEC,RMVFSEC" "0,1"
|
|
bitfld.long 0x00 11. "HSI48SEC,HSI48SEC" "0,1"
|
|
bitfld.long 0x00 10. "CLK48MSEC,CLK48MSEC" "0,1"
|
|
bitfld.long 0x00 9. "PLLSAI2SEC,PLLSAI2SEC" "0,1"
|
|
bitfld.long 0x00 8. "PLLSAI1SEC,PLLSAI1SEC" "0,1"
|
|
bitfld.long 0x00 7. "PLLSEC,PLLSEC" "0,1"
|
|
bitfld.long 0x00 6. "PRESCSEC,PRESCSEC" "0,1"
|
|
bitfld.long 0x00 5. "SYSCLKSEC,SYSCLKSEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LSESEC,LSESEC" "0,1"
|
|
bitfld.long 0x00 3. "LSISEC,LSISEC" "0,1"
|
|
bitfld.long 0x00 2. "MSISEC,MSISEC" "0,1"
|
|
bitfld.long 0x00 1. "HSESEC,HSESEC" "0,1"
|
|
bitfld.long 0x00 0. "HSISEC,HSISEC" "0,1"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "SECSR,RCC secure status register"
|
|
bitfld.long 0x00 12. "RMVFSECF,RMVFSECF" "0,1"
|
|
bitfld.long 0x00 11. "HSI48SECF,HSI48SECF" "0,1"
|
|
bitfld.long 0x00 10. "CLK48MSECF,CLK48MSECF" "0,1"
|
|
bitfld.long 0x00 9. "PLLSAI2SECF,PLLSAI2SECF" "0,1"
|
|
bitfld.long 0x00 8. "PLLSAI1SECF,PLLSAI1SECF" "0,1"
|
|
bitfld.long 0x00 7. "PLLSECF,PLLSECF" "0,1"
|
|
bitfld.long 0x00 6. "PRESCSECF,PRESCSECF" "0,1"
|
|
bitfld.long 0x00 5. "SYSCLKSECF,SYSCLKSECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LSESECF,LSESECF" "0,1"
|
|
bitfld.long 0x00 3. "LSISECF,LSISECF" "0,1"
|
|
bitfld.long 0x00 2. "MSISECF,MSISECF" "0,1"
|
|
bitfld.long 0x00 1. "HSESECF,HSESECF" "0,1"
|
|
bitfld.long 0x00 0. "HSISECF,HSISECF" "0,1"
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "AHB1SECSR,RCC AHB1 security status register"
|
|
bitfld.long 0x00 23. "ICACHESECF,ICACHESECF" "0,1"
|
|
bitfld.long 0x00 22. "GTZCSECF,GTZCSECF" "0,1"
|
|
bitfld.long 0x00 16. "TSCSECF,TSCSECF" "0,1"
|
|
bitfld.long 0x00 12. "CRCSECF,CRCSECF" "0,1"
|
|
bitfld.long 0x00 9. "SRAM1SECF,SRAM1SECF" "0,1"
|
|
bitfld.long 0x00 8. "FLASHSECF,FLASHSECF" "0,1"
|
|
bitfld.long 0x00 2. "DMAMUX1SECF,DMAMUX1SECF" "0,1"
|
|
bitfld.long 0x00 1. "DMA2SECF,DMA2SECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA1SECF,DMA1SECF" "0,1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "AHB2SECSR,RCC AHB2 security status register"
|
|
bitfld.long 0x00 22. "SDMMC1SECF,SDMMC1SECF" "0,1"
|
|
bitfld.long 0x00 21. "OTFDEC1SECF,OTFDEC1SECF" "0,1"
|
|
bitfld.long 0x00 9. "SRAM2SECF,SRAM2SECF" "0,1"
|
|
bitfld.long 0x00 7. "GPIOHSECF,GPIOHSECF" "0,1"
|
|
bitfld.long 0x00 6. "GPIOGSECF,GPIOGSECF" "0,1"
|
|
bitfld.long 0x00 5. "GPIOFSECF,GPIOFSECF" "0,1"
|
|
bitfld.long 0x00 4. "GPIOESECF,GPIOESECF" "0,1"
|
|
bitfld.long 0x00 3. "GPIODSECF,GPIODSECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GPIOCSECF,GPIOCSECF" "0,1"
|
|
bitfld.long 0x00 1. "GPIOBSECF,GPIOBSECF" "0,1"
|
|
bitfld.long 0x00 0. "GPIOASECF,GPIOASECF" "0,1"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "AHB3SECSR,RCC AHB3 security status register"
|
|
bitfld.long 0x00 8. "OSPI1SECF,OSPI1SECF" "0,1"
|
|
bitfld.long 0x00 0. "FSMCSECF,FSMCSECF" "0,1"
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "APB1SECSR1,RCC APB1 security status register 1"
|
|
bitfld.long 0x00 31. "LPTIM1SECF,LPTIM1SECF" "0,1"
|
|
bitfld.long 0x00 30. "OPAMPSECF,OPAMPSECF" "0,1"
|
|
bitfld.long 0x00 29. "DACSECF,DACSECF" "0,1"
|
|
bitfld.long 0x00 28. "PWRSECF,PWRSECF" "0,1"
|
|
bitfld.long 0x00 24. "CRSSECF,CRSSECF" "0,1"
|
|
bitfld.long 0x00 23. "I2C3SECF,I2C3SECF" "0,1"
|
|
bitfld.long 0x00 22. "I2C2SECF,I2C2SECF" "0,1"
|
|
bitfld.long 0x00 21. "I2C1SECF,I2C1SECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "UART5SECF,UART5SECF" "0,1"
|
|
bitfld.long 0x00 19. "UART4SECF,UART4SECF" "0,1"
|
|
bitfld.long 0x00 18. "UART3SECF,UART3SECF" "0,1"
|
|
bitfld.long 0x00 17. "UART2SECF,UART2SECF" "0,1"
|
|
bitfld.long 0x00 15. "SPI3SECF,SPI3SECF" "0,1"
|
|
bitfld.long 0x00 14. "SPI2SECF,SPI2SECF" "0,1"
|
|
bitfld.long 0x00 11. "WWDGSECF,WWDGSECF" "0,1"
|
|
bitfld.long 0x00 10. "RTCAPBSECF,RTCAPBSECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TIM7SECF,TIM7SECF" "0,1"
|
|
bitfld.long 0x00 4. "TIM6SECF,TIM6SECF" "0,1"
|
|
bitfld.long 0x00 3. "TIM5SECF,TIM5SECF" "0,1"
|
|
bitfld.long 0x00 2. "TIM4SECF,TIM4SECF" "0,1"
|
|
bitfld.long 0x00 1. "TIM3SECF,TIM3SECF" "0,1"
|
|
bitfld.long 0x00 0. "TIM2SECF,TIM2SECF" "0,1"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "APB1SECSR2,RCC APB1 security status register 2"
|
|
bitfld.long 0x00 23. "UCPD1SECF,UCPD1SECF" "0,1"
|
|
bitfld.long 0x00 21. "USBFSSECF,USBFSSECF" "0,1"
|
|
bitfld.long 0x00 9. "FDCAN1SECF,FDCAN1SECF" "0,1"
|
|
bitfld.long 0x00 6. "LPTIM3SECF,LPTIM3SECF" "0,1"
|
|
bitfld.long 0x00 5. "LPTIM2SECF,LPTIM2SECF" "0,1"
|
|
bitfld.long 0x00 1. "I2C4SECF,I2C4SECF" "0,1"
|
|
bitfld.long 0x00 0. "LPUART1SECF,LPUART1SECF" "0,1"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "APB2SECSR,RCC APB2 security status register"
|
|
bitfld.long 0x00 24. "DFSDM1SECF,DFSDM1SECF" "0,1"
|
|
bitfld.long 0x00 22. "SAI2SECF,SAI2SECF" "0,1"
|
|
bitfld.long 0x00 21. "SAI1SECF,SAI1SECF" "0,1"
|
|
bitfld.long 0x00 18. "TIM17SECF,TIM17SECF" "0,1"
|
|
bitfld.long 0x00 17. "TIM16SECF,TIM16SECF" "0,1"
|
|
bitfld.long 0x00 16. "TIM15SECF,TIM15SECF" "0,1"
|
|
bitfld.long 0x00 14. "USART1SECF,USART1SECF" "0,1"
|
|
bitfld.long 0x00 13. "TIM8SECF,TIM8SECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "SPI1SECF,SPI1SECF" "0,1"
|
|
bitfld.long 0x00 11. "TIM1SECF,TIM1SECF" "0,1"
|
|
bitfld.long 0x00 0. "SYSCFGSECF,SYSCFGSECF" "0,1"
|
|
tree.end
|
|
tree "SEC_RCC"
|
|
base ad:0x50021000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Clock control register"
|
|
bitfld.long 0x00 31. "PRIV,PRIV" "0,1"
|
|
rbitfld.long 0x00 29. "PLLSAI2RDY,SAI2 PLL clock ready flag" "0,1"
|
|
bitfld.long 0x00 28. "PLLSAI2ON,SAI2 PLL enable" "0,1"
|
|
rbitfld.long 0x00 27. "PLLSAI1RDY,SAI1 PLL clock ready flag" "0,1"
|
|
bitfld.long 0x00 26. "PLLSAI1ON,SAI1 PLL enable" "0,1"
|
|
rbitfld.long 0x00 25. "PLLRDY,Main PLL clock ready flag" "0,1"
|
|
bitfld.long 0x00 24. "PLLON,Main PLL enable" "0,1"
|
|
bitfld.long 0x00 19. "CSSON,Clock security system enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "HSEBYP,HSE crystal oscillator bypass" "0,1"
|
|
rbitfld.long 0x00 17. "HSERDY,HSE clock ready flag" "0,1"
|
|
bitfld.long 0x00 16. "HSEON,HSE clock enable" "0,1"
|
|
bitfld.long 0x00 11. "HSIASFS,HSI automatic start from Stop" "0,1"
|
|
rbitfld.long 0x00 10. "HSIRDY,HSI clock ready flag" "0,1"
|
|
bitfld.long 0x00 9. "HSIKERON,HSI always enable for peripheral kernels" "0,1"
|
|
bitfld.long 0x00 8. "HSION,HSI clock enable" "0,1"
|
|
bitfld.long 0x00 4.--7. "MSIRANGE,MSI clock ranges" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "MSIRGSEL,MSI clock range selection" "0,1"
|
|
bitfld.long 0x00 2. "MSIPLLEN,MSI clock PLL enable" "0,1"
|
|
rbitfld.long 0x00 1. "MSIRDY,MSI clock ready flag" "0,1"
|
|
bitfld.long 0x00 0. "MSION,MSI clock enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICSCR,Internal clock sources calibration register"
|
|
hexmask.long.byte 0x00 24.--30. 1. "HSITRIM,HSI clock trimming"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HSICAL,HSI clock calibration"
|
|
hexmask.long.byte 0x00 8.--15. 1. "MSITRIM,MSI clock trimming"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MSICAL,MSI clock calibration"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CFGR,Clock configuration register"
|
|
rbitfld.long 0x00 28.--30. "MCOPRE,Microcontroller clock output prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--27. "MCOSEL,Microcontroller clock output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "STOPWUCK,Wakeup from Stop and CSS backup clock selection" "0,1"
|
|
bitfld.long 0x00 11.--13. "PPRE2,APB high-speed prescaler (APB2)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "PPRE1,PB low-speed prescaler (APB1)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--7. "HPRE,AHB prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 2.--3. "SWS,System clock switch status" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SW,System clock switch" "0,1,2,3"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PLLCFGR,PLL configuration register"
|
|
bitfld.long 0x00 27.--31. "PLLPDIV,Main PLL division factor for PLLSAI2CLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 25.--26. "PLLR,Main PLL division factor for PLLCLK (system clock)" "0,1,2,3"
|
|
bitfld.long 0x00 24. "PLLREN,Main PLL PLLCLK output enable" "0,1"
|
|
bitfld.long 0x00 21.--22. "PLLQ,Main PLL division factor for PLLUSB1CLK(48 MHz clock)" "0,1,2,3"
|
|
bitfld.long 0x00 20. "PLLQEN,Main PLL PLLUSB1CLK output enable" "0,1"
|
|
bitfld.long 0x00 17. "PLLP,Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)" "0,1"
|
|
bitfld.long 0x00 16. "PLLPEN,Main PLL PLLSAI3CLK output enable" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "PLLN,Main PLL multiplication factor for VCO"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PLLM,Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "PLLSRC,Main PLL PLLSAI1 and PLLSAI2 entry clock source" "0,1,2,3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PLLSAI1CFGR,PLLSAI1 configuration register"
|
|
bitfld.long 0x00 27.--31. "PLLSAI1PDIV,PLLSAI1 division factor for PLLSAI1CLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 25.--26. "PLLSAI1R,PLLSAI1 division factor for PLLADC1CLK (ADC clock)" "0,1,2,3"
|
|
bitfld.long 0x00 24. "PLLSAI1REN,PLLSAI1 PLLADC1CLK output enable" "0,1"
|
|
bitfld.long 0x00 21.--22. "PLLSAI1Q,SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)" "0,1,2,3"
|
|
bitfld.long 0x00 20. "PLLSAI1QEN,SAI1PLL PLLUSB2CLK output enable" "0,1"
|
|
bitfld.long 0x00 17. "PLLSAI1P,SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)" "0,1"
|
|
bitfld.long 0x00 16. "PLLSAI1PEN,SAI1PLL PLLSAI1CLK output enable" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "PLLSAI1N,SAI1PLL multiplication factor for VCO"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PLLSAI1M,Division factor for PLLSAI1 input clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "PLLSAI1SRC,PLLSAI1SRC" "0,1,2,3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PLLSAI2CFGR,PLLSAI2 configuration register"
|
|
bitfld.long 0x00 27.--31. "PLLSAI2PDIV,PLLSAI2 division factor for PLLSAI2CLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 17. "PLLSAI2P,SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)" "0,1"
|
|
bitfld.long 0x00 16. "PLLSAI2PEN,SAI2PLL PLLSAI2CLK output enable" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "PLLSAI2N,SAI2PLL multiplication factor for VCO"
|
|
bitfld.long 0x00 4.--7. "PLLSAI2M,Division factor for PLLSAI2 input clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "PLLSAI2SRC,PLLSAI2SRC" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CIER,Clock interrupt enable register"
|
|
bitfld.long 0x00 10. "HSI48RDYIE,HSI48 ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 9. "LSECSSIE,LSE clock security system interrupt enable" "0,1"
|
|
bitfld.long 0x00 7. "PLLSAI2RDYIE,PLLSAI2 ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "PLLSAI1RDYIE,PLLSAI1 ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "PLLRDYIE,PLL ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "HSERDYIE,HSE ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "HSIRDYIE,HSI ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "MSIRDYIE,MSI ready interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LSERDYIE,LSE ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "LSIRDYIE,LSI ready interrupt enable" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CIFR,Clock interrupt flag register"
|
|
bitfld.long 0x00 10. "HSI48RDYF,HSI48 ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 9. "LSECSSF,LSE Clock security system interrupt flag" "0,1"
|
|
bitfld.long 0x00 8. "CSSF,Clock security system interrupt flag" "0,1"
|
|
bitfld.long 0x00 7. "PLLSAI2RDYF,PLLSAI2 ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 6. "PLLSAI1RDYF,PLLSAI1 ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "PLLRDYF,PLL ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "HSERDYF,HSE ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "HSIRDYF,HSI ready interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "MSIRDYF,MSI ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "LSERDYF,LSE ready interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "LSIRDYF,LSI ready interrupt flag" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "CICR,Clock interrupt clear register"
|
|
bitfld.long 0x00 10. "HSI48RDYC,HSI48 oscillator ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 9. "LSECSSC,LSE Clock security system interrupt clear" "0,1"
|
|
bitfld.long 0x00 8. "CSSC,Clock security system interrupt clear" "0,1"
|
|
bitfld.long 0x00 7. "PLLSAI2RDYC,PLLSAI2 ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 6. "PLLSAI1RDYC,PLLSAI1 ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 5. "PLLRDYC,PLL ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 4. "HSERDYC,HSE ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 3. "HSIRDYC,HSI ready interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "MSIRDYC,MSI ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 1. "LSERDYC,LSE ready interrupt clear" "0,1"
|
|
bitfld.long 0x00 0. "LSIRDYC,LSI ready interrupt clear" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "AHB1RSTR,AHB1 peripheral reset register"
|
|
bitfld.long 0x00 22. "GTZCRST,GTZC reset" "0,1"
|
|
bitfld.long 0x00 16. "TSCRST,Touch Sensing Controller reset" "0,1"
|
|
bitfld.long 0x00 12. "CRCRST,CRC reset" "0,1"
|
|
bitfld.long 0x00 8. "FLASHRST,Flash memory interface reset" "0,1"
|
|
bitfld.long 0x00 2. "DMAMUX1RST,DMAMUXRST" "0,1"
|
|
bitfld.long 0x00 1. "DMA2RST,DMA2 reset" "0,1"
|
|
bitfld.long 0x00 0. "DMA1RST,DMA1 reset" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "AHB2RSTR,AHB2 peripheral reset register"
|
|
bitfld.long 0x00 22. "SDMMC1RST,SDMMC1 reset" "0,1"
|
|
bitfld.long 0x00 21. "OTFDEC1RST,OTFDEC1RST" "0,1"
|
|
bitfld.long 0x00 19. "PKARST,PKARST" "0,1"
|
|
bitfld.long 0x00 18. "RNGRST,Random number generator reset" "0,1"
|
|
bitfld.long 0x00 17. "HASHRST,Hash reset" "0,1"
|
|
bitfld.long 0x00 16. "AESRST,AES hardware accelerator reset" "0,1"
|
|
bitfld.long 0x00 13. "ADCRST,ADC reset" "0,1"
|
|
bitfld.long 0x00 7. "GPIOHRST,IO port H reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "GPIOGRST,IO port G reset" "0,1"
|
|
bitfld.long 0x00 5. "GPIOFRST,IO port F reset" "0,1"
|
|
bitfld.long 0x00 4. "GPIOERST,IO port E reset" "0,1"
|
|
bitfld.long 0x00 3. "GPIODRST,IO port D reset" "0,1"
|
|
bitfld.long 0x00 2. "GPIOCRST,IO port C reset" "0,1"
|
|
bitfld.long 0x00 1. "GPIOBRST,IO port B reset" "0,1"
|
|
bitfld.long 0x00 0. "GPIOARST,IO port A reset" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "AHB3RSTR,AHB3 peripheral reset register"
|
|
bitfld.long 0x00 8. "OSPI1RST,OSPI1RST" "0,1"
|
|
bitfld.long 0x00 0. "FMCRST,Flexible memory controller reset" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "APB1RSTR1,APB1 peripheral reset register 1"
|
|
bitfld.long 0x00 31. "LPTIM1RST,Low Power Timer 1 reset" "0,1"
|
|
bitfld.long 0x00 30. "OPAMPRST,OPAMP interface reset" "0,1"
|
|
bitfld.long 0x00 29. "DAC1RST,DAC1 interface reset" "0,1"
|
|
bitfld.long 0x00 28. "PWRRST,Power interface reset" "0,1"
|
|
bitfld.long 0x00 24. "CRSRST,CRS reset" "0,1"
|
|
bitfld.long 0x00 23. "I2C3RST,I2C3 reset" "0,1"
|
|
bitfld.long 0x00 22. "I2C2RST,I2C2 reset" "0,1"
|
|
bitfld.long 0x00 21. "I2C1RST,I2C1 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "UART5RST,UART5 reset" "0,1"
|
|
bitfld.long 0x00 19. "UART4RST,UART4 reset" "0,1"
|
|
bitfld.long 0x00 18. "USART3RST,USART3 reset" "0,1"
|
|
bitfld.long 0x00 17. "USART2RST,USART2 reset" "0,1"
|
|
bitfld.long 0x00 15. "SPI3RST,SPI3 reset" "0,1"
|
|
bitfld.long 0x00 14. "SPI2RST,SPI2 reset" "0,1"
|
|
bitfld.long 0x00 5. "TIM7RST,TIM7 timer reset" "0,1"
|
|
bitfld.long 0x00 4. "TIM6RST,TIM6 timer reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TIM5RST,TIM5 timer reset" "0,1"
|
|
bitfld.long 0x00 2. "TIM4RST,TIM3 timer reset" "0,1"
|
|
bitfld.long 0x00 1. "TIM3RST,TIM3 timer reset" "0,1"
|
|
bitfld.long 0x00 0. "TIM2RST,TIM2 timer reset" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "APB1RSTR2,APB1 peripheral reset register 2"
|
|
bitfld.long 0x00 23. "UCPD1RST,UCPD1RST" "0,1"
|
|
bitfld.long 0x00 21. "USBFSRST,USBFSRST" "0,1"
|
|
bitfld.long 0x00 9. "FDCAN1RST,FDCAN1RST" "0,1"
|
|
bitfld.long 0x00 6. "LPTIM3RST,LPTIM3RST" "0,1"
|
|
bitfld.long 0x00 5. "LPTIM2RST,Low-power timer 2 reset" "0,1"
|
|
bitfld.long 0x00 1. "I2C4RST,I2C4 reset" "0,1"
|
|
bitfld.long 0x00 0. "LPUART1RST,Low-power UART 1 reset" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "APB2RSTR,APB2 peripheral reset register"
|
|
bitfld.long 0x00 24. "DFSDM1RST,Digital filters for sigma-delata modulators (DFSDM) reset" "0,1"
|
|
bitfld.long 0x00 22. "SAI2RST,Serial audio interface 2 (SAI2) reset" "0,1"
|
|
bitfld.long 0x00 21. "SAI1RST,Serial audio interface 1 (SAI1) reset" "0,1"
|
|
bitfld.long 0x00 18. "TIM17RST,TIM17 timer reset" "0,1"
|
|
bitfld.long 0x00 17. "TIM16RST,TIM16 timer reset" "0,1"
|
|
bitfld.long 0x00 16. "TIM15RST,TIM15 timer reset" "0,1"
|
|
bitfld.long 0x00 14. "USART1RST,USART1 reset" "0,1"
|
|
bitfld.long 0x00 13. "TIM8RST,TIM8 timer reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "SPI1RST,SPI1 reset" "0,1"
|
|
bitfld.long 0x00 11. "TIM1RST,TIM1 timer reset" "0,1"
|
|
bitfld.long 0x00 0. "SYSCFGRST,System configuration (SYSCFG) reset" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "AHB1ENR,AHB1 peripheral clock enable register"
|
|
bitfld.long 0x00 22. "GTZCEN,GTZCEN" "0,1"
|
|
bitfld.long 0x00 16. "TSCEN,Touch Sensing Controller clock enable" "0,1"
|
|
bitfld.long 0x00 12. "CRCEN,CRC clock enable" "0,1"
|
|
bitfld.long 0x00 8. "FLASHEN,Flash memory interface clock enable" "0,1"
|
|
bitfld.long 0x00 2. "DMAMUX1EN,DMAMUX clock enable" "0,1"
|
|
bitfld.long 0x00 1. "DMA2EN,DMA2 clock enable" "0,1"
|
|
bitfld.long 0x00 0. "DMA1EN,DMA1 clock enable" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "AHB2ENR,AHB2 peripheral clock enable register"
|
|
bitfld.long 0x00 22. "SDMMC1EN,SDMMC1 clock enable" "0,1"
|
|
bitfld.long 0x00 21. "OTFDEC1EN,OTFDEC1EN" "0,1"
|
|
bitfld.long 0x00 19. "PKAEN,PKAEN" "0,1"
|
|
bitfld.long 0x00 18. "RNGEN,Random Number Generator clock enable" "0,1"
|
|
bitfld.long 0x00 17. "HASHEN,HASH clock enable" "0,1"
|
|
bitfld.long 0x00 16. "AESEN,AES accelerator clock enable" "0,1"
|
|
bitfld.long 0x00 13. "ADCEN,ADC clock enable" "0,1"
|
|
bitfld.long 0x00 7. "GPIOHEN,IO port H clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "GPIOGEN,IO port G clock enable" "0,1"
|
|
bitfld.long 0x00 5. "GPIOFEN,IO port F clock enable" "0,1"
|
|
bitfld.long 0x00 4. "GPIOEEN,IO port E clock enable" "0,1"
|
|
bitfld.long 0x00 3. "GPIODEN,IO port D clock enable" "0,1"
|
|
bitfld.long 0x00 2. "GPIOCEN,IO port C clock enable" "0,1"
|
|
bitfld.long 0x00 1. "GPIOBEN,IO port B clock enable" "0,1"
|
|
bitfld.long 0x00 0. "GPIOAEN,IO port A clock enable" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "AHB3ENR,AHB3 peripheral clock enable register"
|
|
bitfld.long 0x00 8. "OSPI1EN,OSPI1EN" "0,1"
|
|
bitfld.long 0x00 0. "FMCEN,Flexible memory controller clock enable" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "APB1ENR1,APB1ENR1"
|
|
bitfld.long 0x00 31. "LPTIM1EN,Low power timer 1 clock enable" "0,1"
|
|
bitfld.long 0x00 30. "OPAMPEN,OPAMP interface clock enable" "0,1"
|
|
bitfld.long 0x00 29. "DAC1EN,DAC1 interface clock enable" "0,1"
|
|
bitfld.long 0x00 28. "PWREN,Power interface clock enable" "0,1"
|
|
bitfld.long 0x00 24. "CRSEN,Clock Recovery System clock enable" "0,1"
|
|
bitfld.long 0x00 23. "I2C3EN,I2C3 clock enable" "0,1"
|
|
bitfld.long 0x00 22. "I2C2EN,I2C2 clock enable" "0,1"
|
|
bitfld.long 0x00 21. "I2C1EN,I2C1 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "UART5EN,UART5 clock enable" "0,1"
|
|
bitfld.long 0x00 19. "UART4EN,UART4 clock enable" "0,1"
|
|
bitfld.long 0x00 18. "USART3EN,USART3 clock enable" "0,1"
|
|
bitfld.long 0x00 17. "USART2EN,USART2 clock enable" "0,1"
|
|
bitfld.long 0x00 15. "SP3EN,SPI3 clock enable" "0,1"
|
|
bitfld.long 0x00 14. "SPI2EN,SPI2 clock enable" "0,1"
|
|
bitfld.long 0x00 11. "WWDGEN,Window watchdog clock enable" "0,1"
|
|
bitfld.long 0x00 10. "RTCAPBEN,RTC APB clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TIM7EN,TIM7 timer clock enable" "0,1"
|
|
bitfld.long 0x00 4. "TIM6EN,TIM6 timer clock enable" "0,1"
|
|
bitfld.long 0x00 3. "TIM5EN,TIM5 timer clock enable" "0,1"
|
|
bitfld.long 0x00 2. "TIM4EN,TIM4 timer clock enable" "0,1"
|
|
bitfld.long 0x00 1. "TIM3EN,TIM3 timer clock enable" "0,1"
|
|
bitfld.long 0x00 0. "TIM2EN,TIM2 timer clock enable" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "APB1ENR2,APB1 peripheral clock enable register 2"
|
|
bitfld.long 0x00 23. "UCPD1EN,UCPD1EN" "0,1"
|
|
bitfld.long 0x00 21. "USBFSEN,USBFSEN" "0,1"
|
|
bitfld.long 0x00 9. "FDCAN1EN,FDCAN1EN" "0,1"
|
|
bitfld.long 0x00 6. "LPTIM3EN,LPTIM3EN" "0,1"
|
|
bitfld.long 0x00 5. "LPTIM2EN,LPTIM2EN" "0,1"
|
|
bitfld.long 0x00 1. "I2C4EN,I2C4 clock enable" "0,1"
|
|
bitfld.long 0x00 0. "LPUART1EN,Low power UART 1 clock enable" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "APB2ENR,APB2ENR"
|
|
bitfld.long 0x00 24. "DFSDM1EN,DFSDM timer clock enable" "0,1"
|
|
bitfld.long 0x00 22. "SAI2EN,SAI2 clock enable" "0,1"
|
|
bitfld.long 0x00 21. "SAI1EN,SAI1 clock enable" "0,1"
|
|
bitfld.long 0x00 18. "TIM17EN,TIM17 timer clock enable" "0,1"
|
|
bitfld.long 0x00 17. "TIM16EN,TIM16 timer clock enable" "0,1"
|
|
bitfld.long 0x00 16. "TIM15EN,TIM15 timer clock enable" "0,1"
|
|
bitfld.long 0x00 14. "USART1EN,USART1clock enable" "0,1"
|
|
bitfld.long 0x00 13. "TIM8EN,TIM8 timer clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "SPI1EN,SPI1 clock enable" "0,1"
|
|
bitfld.long 0x00 11. "TIM1EN,TIM1 timer clock enable" "0,1"
|
|
bitfld.long 0x00 0. "SYSCFGEN,SYSCFG clock enable" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "AHB1SMENR,AHB1 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x00 23. "ICACHESMEN,ICACHESMEN" "0,1"
|
|
bitfld.long 0x00 22. "GTZCSMEN,GTZCSMEN" "0,1"
|
|
bitfld.long 0x00 16. "TSCSMEN,Touch Sensing Controller clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 12. "CRCSMEN,CRCSMEN" "0,1"
|
|
bitfld.long 0x00 9. "SRAM1SMEN,SRAM1 interface clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 8. "FLASHSMEN,Flash memory interface clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 2. "DMAMUX1SMEN,DMAMUX clock enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 1. "DMA2SMEN,DMA2 clocks enable during Sleep and Stop modes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA1SMEN,DMA1 clocks enable during Sleep and Stop modes" "0,1"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "AHB2SMENR,AHB2 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x00 22. "SDMMC1SMEN,SDMMC1 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 21. "OTFDEC1SMEN,OTFDEC1SMEN" "0,1"
|
|
bitfld.long 0x00 19. "PKASMEN,PKASMEN" "0,1"
|
|
bitfld.long 0x00 18. "RNGSMEN,Random Number Generator clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 17. "HASHSMEN,HASH clock enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 16. "AESSMEN,AES accelerator clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 13. "ADCFSSMEN,ADC clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 9. "SRAM2SMEN,SRAM2 interface clocks enable during Sleep and Stop modes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "GPIOHSMEN,IO port H clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 6. "GPIOGSMEN,IO port G clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 5. "GPIOFSMEN,IO port F clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 4. "GPIOESMEN,IO port E clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 3. "GPIODSMEN,IO port D clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 2. "GPIOCSMEN,IO port C clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 1. "GPIOBSMEN,IO port B clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 0. "GPIOASMEN,IO port A clocks enable during Sleep and Stop modes" "0,1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "AHB3SMENR,AHB3 peripheral clocks enable in Sleep and Stop modes register"
|
|
bitfld.long 0x00 8. "OSPI1SMEN,OSPI1SMEN" "0,1"
|
|
bitfld.long 0x00 0. "FMCSMEN,Flexible memory controller clocks enable during Sleep and Stop modes" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "APB1SMENR1,APB1SMENR1"
|
|
bitfld.long 0x00 31. "LPTIM1SMEN,Low power timer 1 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 30. "OPAMPSMEN,OPAMP interface clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 29. "DAC1SMEN,DAC1 interface clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 28. "PWRSMEN,Power interface clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 24. "CRSSMEN,CRS clock enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 23. "I2C3SMEN,I2C3 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 22. "I2C2SMEN,I2C2 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 21. "I2C1SMEN,I2C1 clocks enable during Sleep and Stop modes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "UART5SMEN,UART5 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 19. "UART4SMEN,UART4 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 18. "USART3SMEN,USART3 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 17. "USART2SMEN,USART2 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 15. "SP3SMEN,SPI3 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 14. "SPI2SMEN,SPI2 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 11. "WWDGSMEN,Window watchdog clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 10. "RTCAPBSMEN,RTC APB clock enable during Sleep and Stop modes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TIM7SMEN,TIM7 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 4. "TIM6SMEN,TIM6 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 3. "TIM5SMEN,TIM5 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 2. "TIM4SMEN,TIM4 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 1. "TIM3SMEN,TIM3 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 0. "TIM2SMEN,TIM2 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "APB1SMENR2,APB1 peripheral clocks enable in Sleep and Stop modes register 2"
|
|
bitfld.long 0x00 23. "UCPD1SMEN,UCPD1SMEN" "0,1"
|
|
bitfld.long 0x00 21. "USBFSSMEN,USBFSSMEN" "0,1"
|
|
bitfld.long 0x00 9. "FDCAN1SMEN,FDCAN1SMEN" "0,1"
|
|
bitfld.long 0x00 6. "LPTIM3SMEN,LPTIM3SMEN" "0,1"
|
|
bitfld.long 0x00 5. "LPTIM2SMEN,LPTIM2SMEN" "0,1"
|
|
bitfld.long 0x00 1. "I2C4SMEN,I2C4 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 0. "LPUART1SMEN,Low power UART 1 clocks enable during Sleep and Stop modes" "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "APB2SMENR,APB2SMENR"
|
|
bitfld.long 0x00 24. "DFSDM1SMEN,DFSDM timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 22. "SAI2SMEN,SAI2 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 21. "SAI1SMEN,SAI1 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 18. "TIM17SMEN,TIM17 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 17. "TIM16SMEN,TIM16 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 16. "TIM15SMEN,TIM15 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 14. "USART1SMEN,USART1clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 13. "TIM8SMEN,TIM8 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "SPI1SMEN,SPI1 clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 11. "TIM1SMEN,TIM1 timer clocks enable during Sleep and Stop modes" "0,1"
|
|
bitfld.long 0x00 0. "SYSCFGSMEN,SYSCFG clocks enable during Sleep and Stop modes" "0,1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CCIPR1,CCIPR1"
|
|
bitfld.long 0x00 28.--29. "ADCSEL,ADCs clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 26.--27. "CLK48MSEL,48 MHz clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "FDCANSEL,FDCAN clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "LPTIM3SEL,Low-power timer 3 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. "LPTIM2SEL,Low power timer 2 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "LPTIM1SEL,Low power timer 1 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "I2C3SEL,I2C3 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "I2C2SEL,I2C2 clock source selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "I2C1SEL,I2C1 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "LPUART1SEL,LPUART1 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "UART5SEL,UART5 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "UART4SEL,UART4 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "USART3SEL,USART3 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "USART2SEL,USART2 clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "USART1SEL,USART1 clock source selection" "0,1,2,3"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "BDCR,BDCR"
|
|
bitfld.long 0x00 25. "LSCOSEL,Low speed clock output selection" "0,1"
|
|
bitfld.long 0x00 24. "LSCOEN,Low speed clock output enable" "0,1"
|
|
bitfld.long 0x00 16. "BDRST,Backup domain software reset" "0,1"
|
|
bitfld.long 0x00 15. "RTCEN,RTC clock enable" "0,1"
|
|
bitfld.long 0x00 11. "LSESYSRDY,LSESYSRDY" "0,1"
|
|
bitfld.long 0x00 8.--9. "RTCSEL,RTC clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "LSESYSEN,LSESYSEN" "0,1"
|
|
rbitfld.long 0x00 6. "LSECSSD,LSECSSD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "LSECSSON,LSECSSON" "0,1"
|
|
bitfld.long 0x00 3.--4. "LSEDRV,SE oscillator drive capability" "0,1,2,3"
|
|
bitfld.long 0x00 2. "LSEBYP,LSE oscillator bypass" "0,1"
|
|
rbitfld.long 0x00 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
bitfld.long 0x00 0. "LSEON,LSE oscillator enable" "0,1"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CSR,CSR"
|
|
rbitfld.long 0x00 31. "LPWRSTF,Low-power reset flag" "0,1"
|
|
rbitfld.long 0x00 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
rbitfld.long 0x00 29. "IWWDGRSTF,Independent window watchdog reset flag" "0,1"
|
|
rbitfld.long 0x00 28. "SFTRSTF,Software reset flag" "0,1"
|
|
rbitfld.long 0x00 27. "BORRSTF,BOR flag" "0,1"
|
|
rbitfld.long 0x00 26. "PINRSTF,Pin reset flag" "0,1"
|
|
rbitfld.long 0x00 25. "OBLRSTF,Option byte loader reset flag" "0,1"
|
|
bitfld.long 0x00 23. "RMVF,Remove reset flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "MSISRANGE,SI range after Standby mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. "LSIPREDIV,LSIPREDIV" "0,1"
|
|
rbitfld.long 0x00 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
bitfld.long 0x00 0. "LSION,LSI oscillator enable" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CRRCR,Clock recovery RC register"
|
|
hexmask.long.word 0x00 7.--15. 1. "HSI48CAL,HSI48 clock calibration"
|
|
rbitfld.long 0x00 1. "HSI48RDY,HSI48 clock ready flag" "0,1"
|
|
bitfld.long 0x00 0. "HSI48ON,HSI48 clock enable" "0,1"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CCIPR2,Peripherals independent clock configuration register"
|
|
bitfld.long 0x00 20.--21. "OSPISEL,Octospi clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 14. "SDMMCSEL,SDMMC clock selection" "0,1"
|
|
bitfld.long 0x00 8.--10. "SAI2SEL,SAI2 clock source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. "SAI1SEL,SAI1 clock source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. "ADFSDMSEL,Digital filter for sigma delta modulator audio clock source selection" "0,1,2,3"
|
|
bitfld.long 0x00 2. "DFSDMSEL,Digital filter for sigma delta modulator kernel clock source selection" "0,1"
|
|
bitfld.long 0x00 0.--1. "I2C4SEL,I2C4 clock source selection" "0,1,2,3"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "SECCFGR,RCC secure configuration register"
|
|
bitfld.long 0x00 12. "RMVFSEC,RMVFSEC" "0,1"
|
|
bitfld.long 0x00 11. "HSI48SEC,HSI48SEC" "0,1"
|
|
bitfld.long 0x00 10. "CLK48MSEC,CLK48MSEC" "0,1"
|
|
bitfld.long 0x00 9. "PLLSAI2SEC,PLLSAI2SEC" "0,1"
|
|
bitfld.long 0x00 8. "PLLSAI1SEC,PLLSAI1SEC" "0,1"
|
|
bitfld.long 0x00 7. "PLLSEC,PLLSEC" "0,1"
|
|
bitfld.long 0x00 6. "PRESCSEC,PRESCSEC" "0,1"
|
|
bitfld.long 0x00 5. "SYSCLKSEC,SYSCLKSEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LSESEC,LSESEC" "0,1"
|
|
bitfld.long 0x00 3. "LSISEC,LSISEC" "0,1"
|
|
bitfld.long 0x00 2. "MSISEC,MSISEC" "0,1"
|
|
bitfld.long 0x00 1. "HSESEC,HSESEC" "0,1"
|
|
bitfld.long 0x00 0. "HSISEC,HSISEC" "0,1"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "SECSR,RCC secure status register"
|
|
bitfld.long 0x00 12. "RMVFSECF,RMVFSECF" "0,1"
|
|
bitfld.long 0x00 11. "HSI48SECF,HSI48SECF" "0,1"
|
|
bitfld.long 0x00 10. "CLK48MSECF,CLK48MSECF" "0,1"
|
|
bitfld.long 0x00 9. "PLLSAI2SECF,PLLSAI2SECF" "0,1"
|
|
bitfld.long 0x00 8. "PLLSAI1SECF,PLLSAI1SECF" "0,1"
|
|
bitfld.long 0x00 7. "PLLSECF,PLLSECF" "0,1"
|
|
bitfld.long 0x00 6. "PRESCSECF,PRESCSECF" "0,1"
|
|
bitfld.long 0x00 5. "SYSCLKSECF,SYSCLKSECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LSESECF,LSESECF" "0,1"
|
|
bitfld.long 0x00 3. "LSISECF,LSISECF" "0,1"
|
|
bitfld.long 0x00 2. "MSISECF,MSISECF" "0,1"
|
|
bitfld.long 0x00 1. "HSESECF,HSESECF" "0,1"
|
|
bitfld.long 0x00 0. "HSISECF,HSISECF" "0,1"
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "AHB1SECSR,RCC AHB1 security status register"
|
|
bitfld.long 0x00 23. "ICACHESECF,ICACHESECF" "0,1"
|
|
bitfld.long 0x00 22. "GTZCSECF,GTZCSECF" "0,1"
|
|
bitfld.long 0x00 16. "TSCSECF,TSCSECF" "0,1"
|
|
bitfld.long 0x00 12. "CRCSECF,CRCSECF" "0,1"
|
|
bitfld.long 0x00 9. "SRAM1SECF,SRAM1SECF" "0,1"
|
|
bitfld.long 0x00 8. "FLASHSECF,FLASHSECF" "0,1"
|
|
bitfld.long 0x00 2. "DMAMUX1SECF,DMAMUX1SECF" "0,1"
|
|
bitfld.long 0x00 1. "DMA2SECF,DMA2SECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA1SECF,DMA1SECF" "0,1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "AHB2SECSR,RCC AHB2 security status register"
|
|
bitfld.long 0x00 22. "SDMMC1SECF,SDMMC1SECF" "0,1"
|
|
bitfld.long 0x00 21. "OTFDEC1SECF,OTFDEC1SECF" "0,1"
|
|
bitfld.long 0x00 9. "SRAM2SECF,SRAM2SECF" "0,1"
|
|
bitfld.long 0x00 7. "GPIOHSECF,GPIOHSECF" "0,1"
|
|
bitfld.long 0x00 6. "GPIOGSECF,GPIOGSECF" "0,1"
|
|
bitfld.long 0x00 5. "GPIOFSECF,GPIOFSECF" "0,1"
|
|
bitfld.long 0x00 4. "GPIOESECF,GPIOESECF" "0,1"
|
|
bitfld.long 0x00 3. "GPIODSECF,GPIODSECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GPIOCSECF,GPIOCSECF" "0,1"
|
|
bitfld.long 0x00 1. "GPIOBSECF,GPIOBSECF" "0,1"
|
|
bitfld.long 0x00 0. "GPIOASECF,GPIOASECF" "0,1"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "AHB3SECSR,RCC AHB3 security status register"
|
|
bitfld.long 0x00 8. "OSPI1SECF,OSPI1SECF" "0,1"
|
|
bitfld.long 0x00 0. "FSMCSECF,FSMCSECF" "0,1"
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "APB1SECSR1,RCC APB1 security status register 1"
|
|
bitfld.long 0x00 31. "LPTIM1SECF,LPTIM1SECF" "0,1"
|
|
bitfld.long 0x00 30. "OPAMPSECF,OPAMPSECF" "0,1"
|
|
bitfld.long 0x00 29. "DACSECF,DACSECF" "0,1"
|
|
bitfld.long 0x00 28. "PWRSECF,PWRSECF" "0,1"
|
|
bitfld.long 0x00 24. "CRSSECF,CRSSECF" "0,1"
|
|
bitfld.long 0x00 23. "I2C3SECF,I2C3SECF" "0,1"
|
|
bitfld.long 0x00 22. "I2C2SECF,I2C2SECF" "0,1"
|
|
bitfld.long 0x00 21. "I2C1SECF,I2C1SECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "UART5SECF,UART5SECF" "0,1"
|
|
bitfld.long 0x00 19. "UART4SECF,UART4SECF" "0,1"
|
|
bitfld.long 0x00 18. "UART3SECF,UART3SECF" "0,1"
|
|
bitfld.long 0x00 17. "UART2SECF,UART2SECF" "0,1"
|
|
bitfld.long 0x00 15. "SPI3SECF,SPI3SECF" "0,1"
|
|
bitfld.long 0x00 14. "SPI2SECF,SPI2SECF" "0,1"
|
|
bitfld.long 0x00 11. "WWDGSECF,WWDGSECF" "0,1"
|
|
bitfld.long 0x00 10. "RTCAPBSECF,RTCAPBSECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TIM7SECF,TIM7SECF" "0,1"
|
|
bitfld.long 0x00 4. "TIM6SECF,TIM6SECF" "0,1"
|
|
bitfld.long 0x00 3. "TIM5SECF,TIM5SECF" "0,1"
|
|
bitfld.long 0x00 2. "TIM4SECF,TIM4SECF" "0,1"
|
|
bitfld.long 0x00 1. "TIM3SECF,TIM3SECF" "0,1"
|
|
bitfld.long 0x00 0. "TIM2SECF,TIM2SECF" "0,1"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "APB1SECSR2,RCC APB1 security status register 2"
|
|
bitfld.long 0x00 23. "UCPD1SECF,UCPD1SECF" "0,1"
|
|
bitfld.long 0x00 21. "USBFSSECF,USBFSSECF" "0,1"
|
|
bitfld.long 0x00 9. "FDCAN1SECF,FDCAN1SECF" "0,1"
|
|
bitfld.long 0x00 6. "LPTIM3SECF,LPTIM3SECF" "0,1"
|
|
bitfld.long 0x00 5. "LPTIM2SECF,LPTIM2SECF" "0,1"
|
|
bitfld.long 0x00 1. "I2C4SECF,I2C4SECF" "0,1"
|
|
bitfld.long 0x00 0. "LPUART1SECF,LPUART1SECF" "0,1"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "APB2SECSR,RCC APB2 security status register"
|
|
bitfld.long 0x00 24. "DFSDM1SECF,DFSDM1SECF" "0,1"
|
|
bitfld.long 0x00 22. "SAI2SECF,SAI2SECF" "0,1"
|
|
bitfld.long 0x00 21. "SAI1SECF,SAI1SECF" "0,1"
|
|
bitfld.long 0x00 18. "TIM17SECF,TIM17SECF" "0,1"
|
|
bitfld.long 0x00 17. "TIM16SECF,TIM16SECF" "0,1"
|
|
bitfld.long 0x00 16. "TIM15SECF,TIM15SECF" "0,1"
|
|
bitfld.long 0x00 14. "USART1SECF,USART1SECF" "0,1"
|
|
bitfld.long 0x00 13. "TIM8SECF,TIM8SECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "SPI1SECF,SPI1SECF" "0,1"
|
|
bitfld.long 0x00 11. "TIM1SECF,TIM1SECF" "0,1"
|
|
bitfld.long 0x00 0. "SYSCFGSECF,SYSCFGSECF" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "RNG (Random Number Generator)"
|
|
tree "RNG"
|
|
base ad:0x420C0800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RNG_CR,RNG control register"
|
|
bitfld.long 0x00 31. "CONFIGLOCK,RNG Config Lock" "0,1"
|
|
bitfld.long 0x00 30. "CONDRST,Conditioning soft reset" "0,1"
|
|
bitfld.long 0x00 20.--25. "RNG_CONFIG1,RNG configuration 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--19. "CLKDIV,Clock divider factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 13.--15. "RNG_CONFIG2,RNG configuration 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "NISTC,Non NIST compliant" "0,1"
|
|
bitfld.long 0x00 8.--11. "RNG_CONFIG3,RNG configuration 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. "CED,Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise CED bit must be equal to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IE,Interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "RNGEN,Random number generator enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RNG_SR,RNG status register"
|
|
bitfld.long 0x00 6. "SEIS,Seed error interrupt status This bit is set at the same time as SECS" "0,1"
|
|
bitfld.long 0x00 5. "CEIS,Clock error interrupt status This bit is set at the same time as CECS" "0,1"
|
|
rbitfld.long 0x00 2. "SECS,Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01)" "0,1"
|
|
rbitfld.long 0x00 1. "CECS,Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1" "0,1"
|
|
rbitfld.long 0x00 0. "DRDY,Data ready Note: If IE=1 in RNG_CR an interrupt is generated when DRDY=1" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RNG_DR,The RNG_DR register is a read-only register that delivers a 32-bit random value when"
|
|
hexmask.long 0x00 0.--31. 1. "RNDATA,Random data 32-bit random data which are valid when DRDY=1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RNG_HTCR,The RNG_DR register is a read-only register that delivers a 32-bit random value when"
|
|
hexmask.long 0x00 0.--31. 1. "HTCFG,health test configuration"
|
|
tree.end
|
|
tree "SEC_RNG"
|
|
base ad:0x520C0800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RNG_CR,RNG control register"
|
|
bitfld.long 0x00 31. "CONFIGLOCK,RNG Config Lock" "0,1"
|
|
bitfld.long 0x00 30. "CONDRST,Conditioning soft reset" "0,1"
|
|
bitfld.long 0x00 20.--25. "RNG_CONFIG1,RNG configuration 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--19. "CLKDIV,Clock divider factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 13.--15. "RNG_CONFIG2,RNG configuration 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "NISTC,Non NIST compliant" "0,1"
|
|
bitfld.long 0x00 8.--11. "RNG_CONFIG3,RNG configuration 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. "CED,Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise CED bit must be equal to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IE,Interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "RNGEN,Random number generator enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RNG_SR,RNG status register"
|
|
bitfld.long 0x00 6. "SEIS,Seed error interrupt status This bit is set at the same time as SECS" "0,1"
|
|
bitfld.long 0x00 5. "CEIS,Clock error interrupt status This bit is set at the same time as CECS" "0,1"
|
|
rbitfld.long 0x00 2. "SECS,Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01)" "0,1"
|
|
rbitfld.long 0x00 1. "CECS,Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1" "0,1"
|
|
rbitfld.long 0x00 0. "DRDY,Data ready Note: If IE=1 in RNG_CR an interrupt is generated when DRDY=1" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RNG_DR,The RNG_DR register is a read-only register that delivers a 32-bit random value when"
|
|
hexmask.long 0x00 0.--31. 1. "RNDATA,Random data 32-bit random data which are valid when DRDY=1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RNG_HTCR,The RNG_DR register is a read-only register that delivers a 32-bit random value when"
|
|
hexmask.long 0x00 0.--31. 1. "HTCFG,health test configuration"
|
|
tree.end
|
|
tree.end
|
|
tree "RTC (Real-time Counter)"
|
|
tree "RTC"
|
|
base ad:0x40002800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TR,time register"
|
|
bitfld.long 0x00 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x00 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "HU,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "MNU,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SU,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,date register"
|
|
bitfld.long 0x00 20.--23. "YT,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "YU,Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "MT,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. "MU,Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "DU,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SSR,RTC sub second register"
|
|
hexmask.long.word 0x00 0.--15. 1. "SS,SS"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ICSR,RTC initialization control and status register"
|
|
rbitfld.long 0x00 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x00 7. "INIT,Initialization mode" "0,1"
|
|
rbitfld.long 0x00 6. "INITF,Initialization flag" "0,1"
|
|
bitfld.long 0x00 5. "RSF,Registers synchronization flag" "0,1"
|
|
rbitfld.long 0x00 4. "INITS,Initialization status flag" "0,1"
|
|
bitfld.long 0x00 3. "SHPF,Shift operation pending" "0,1"
|
|
rbitfld.long 0x00 2. "WUTWF,Wakeup timer write flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "ALRBWF,Alarm B write flag" "0,1"
|
|
rbitfld.long 0x00 0. "ALRAWF,Alarm A write flag" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRER,prescaler register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x00 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "WUTR,wakeup timer register"
|
|
hexmask.long.word 0x00 16.--31. 1. "WUTOCLR,WUTOCLR"
|
|
hexmask.long.word 0x00 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CR,RTC control register"
|
|
bitfld.long 0x00 31. "OUT2EN,OUT2EN" "0,1"
|
|
bitfld.long 0x00 30. "TAMPALRM_TYPE,TAMPALRM_TYPE" "0,1"
|
|
bitfld.long 0x00 29. "TAMPALRM_PU,TAMPALRM_PU" "0,1"
|
|
bitfld.long 0x00 26. "TAMPOE,TAMPOE" "0,1"
|
|
bitfld.long 0x00 25. "TAMPTS,TAMPTS" "0,1"
|
|
bitfld.long 0x00 24. "ITSE,ITSE" "0,1"
|
|
bitfld.long 0x00 23. "COE,COE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "OSEL,OSEL" "0,1,2,3"
|
|
bitfld.long 0x00 20. "POL,POL" "0,1"
|
|
bitfld.long 0x00 19. "COSEL,COSEL" "0,1"
|
|
bitfld.long 0x00 18. "BKP,BKP" "0,1"
|
|
bitfld.long 0x00 17. "SUB1H,SUB1H" "0,1"
|
|
bitfld.long 0x00 16. "ADD1H,ADD1H" "0,1"
|
|
bitfld.long 0x00 15. "TSIE,TSIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "WUTIE,WUTIE" "0,1"
|
|
bitfld.long 0x00 13. "ALRBIE,ALRBIE" "0,1"
|
|
bitfld.long 0x00 12. "ALRAIE,ALRAIE" "0,1"
|
|
bitfld.long 0x00 11. "TSE,TSE" "0,1"
|
|
bitfld.long 0x00 10. "WUTE,WUTE" "0,1"
|
|
bitfld.long 0x00 9. "ALRBE,ALRBE" "0,1"
|
|
bitfld.long 0x00 8. "ALRAE,ALRAE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "FMT,FMT" "0,1"
|
|
bitfld.long 0x00 5. "BYPSHAD,BYPSHAD" "0,1"
|
|
bitfld.long 0x00 4. "REFCKON,REFCKON" "0,1"
|
|
bitfld.long 0x00 3. "TSEDGE,TSEDGE" "0,1"
|
|
bitfld.long 0x00 0.--2. "WUCKSEL,WUCKSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PRIVCR,RTC privilege mode control register"
|
|
bitfld.long 0x00 15. "PRIV,PRIV" "0,1"
|
|
bitfld.long 0x00 14. "INITPRIV,INITPRIV" "0,1"
|
|
bitfld.long 0x00 13. "CALPRIV,CALPRIV" "0,1"
|
|
bitfld.long 0x00 3. "TSPRIV,TSPRIV" "0,1"
|
|
bitfld.long 0x00 2. "WUTPRIV,WUTPRIV" "0,1"
|
|
bitfld.long 0x00 1. "ALRBPRIV,ALRBPRIV" "0,1"
|
|
bitfld.long 0x00 0. "ALRAPRIV,ALRAPRIV" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SMCR,RTC secure mode control register"
|
|
bitfld.long 0x00 15. "DECPROT,DECPROT" "0,1"
|
|
bitfld.long 0x00 14. "INITDPROT,INITDPROT" "0,1"
|
|
bitfld.long 0x00 13. "CALDPROT,CALDPROT" "0,1"
|
|
bitfld.long 0x00 3. "TSDPROT,TSDPROT" "0,1"
|
|
bitfld.long 0x00 2. "WUTDPROT,WUTDPROT" "0,1"
|
|
bitfld.long 0x00 1. "ALRBDPROT,ALRBDPROT" "0,1"
|
|
bitfld.long 0x00 0. "ALRADPROT,ALRADPROT" "0,1"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "WPR,write protection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CALR,calibration register"
|
|
bitfld.long 0x00 15. "CALP,Increase frequency of RTC by 488.5 ppm" "0,1"
|
|
bitfld.long 0x00 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
bitfld.long 0x00 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
bitfld.long 0x00 12. "LPCAL,LPCAL" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "SHIFTR,shift control register"
|
|
bitfld.long 0x00 31. "ADD1S,Add one second" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TSTR,time stamp time register"
|
|
bitfld.long 0x00 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x00 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "HU,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "MNU,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SU,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TSDR,time stamp date register"
|
|
bitfld.long 0x00 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "MT,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. "MU,Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "DU,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TSSSR,timestamp sub second register"
|
|
hexmask.long.word 0x00 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ALRMAR,alarm A register"
|
|
bitfld.long 0x00 31. "MSK4,Alarm A date mask" "0,1"
|
|
bitfld.long 0x00 30. "WDSEL,Week day selection" "0,1"
|
|
bitfld.long 0x00 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DU,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "MSK3,Alarm A hours mask" "0,1"
|
|
bitfld.long 0x00 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x00 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "HU,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "MSK2,Alarm A minutes mask" "0,1"
|
|
bitfld.long 0x00 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "MNU,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSK1,Alarm A seconds mask" "0,1"
|
|
bitfld.long 0x00 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SU,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ALRMASSR,alarm A sub second register"
|
|
bitfld.long 0x00 24.--27. "MASKSS,Mask the most-significant bits starting at this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--14. 1. "SS,Sub seconds value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ALRMBR,alarm B register"
|
|
bitfld.long 0x00 31. "MSK4,Alarm B date mask" "0,1"
|
|
bitfld.long 0x00 30. "WDSEL,Week day selection" "0,1"
|
|
bitfld.long 0x00 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DU,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "MSK3,Alarm B hours mask" "0,1"
|
|
bitfld.long 0x00 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x00 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "HU,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "MSK2,Alarm B minutes mask" "0,1"
|
|
bitfld.long 0x00 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "MNU,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSK1,Alarm B seconds mask" "0,1"
|
|
bitfld.long 0x00 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SU,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ALRMBSSR,alarm B sub second register"
|
|
bitfld.long 0x00 24.--27. "MASKSS,Mask the most-significant bits starting at this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "SR,RTC status register"
|
|
bitfld.long 0x00 5. "ITSF,ITSF" "0,1"
|
|
bitfld.long 0x00 4. "TSOVF,TSOVF" "0,1"
|
|
bitfld.long 0x00 3. "TSF,TSF" "0,1"
|
|
bitfld.long 0x00 2. "WUTF,WUTF" "0,1"
|
|
bitfld.long 0x00 1. "ALRBF,ALRBF" "0,1"
|
|
bitfld.long 0x00 0. "ALRAF,ALRAF" "0,1"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "MISR,RTC non-secure masked interrupt status register"
|
|
bitfld.long 0x00 5. "ITSMF,ITSMF" "0,1"
|
|
bitfld.long 0x00 4. "TSOVMF,TSOVMF" "0,1"
|
|
bitfld.long 0x00 3. "TSMF,TSMF" "0,1"
|
|
bitfld.long 0x00 2. "WUTMF,WUTMF" "0,1"
|
|
bitfld.long 0x00 1. "ALRBMF,ALRBMF" "0,1"
|
|
bitfld.long 0x00 0. "ALRAMF,ALRAMF" "0,1"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "SMISR,RTC secure masked interrupt status register"
|
|
bitfld.long 0x00 5. "ITSMF,ITSMF" "0,1"
|
|
bitfld.long 0x00 4. "TSOVMF,TSOVMF" "0,1"
|
|
bitfld.long 0x00 3. "TSMF,TSMF" "0,1"
|
|
bitfld.long 0x00 2. "WUTMF,WUTMF" "0,1"
|
|
bitfld.long 0x00 1. "ALRBMF,ALRBMF" "0,1"
|
|
bitfld.long 0x00 0. "ALRAMF,ALRAMF" "0,1"
|
|
wgroup.long 0x5C++0x03
|
|
line.long 0x00 "SCR,RTC status clear register"
|
|
bitfld.long 0x00 5. "CITSF,CITSF" "0,1"
|
|
bitfld.long 0x00 4. "CTSOVF,CTSOVF" "0,1"
|
|
bitfld.long 0x00 3. "CTSF,CTSF" "0,1"
|
|
bitfld.long 0x00 2. "CWUTF,CWUTF" "0,1"
|
|
bitfld.long 0x00 1. "CALRBF,CALRBF" "0,1"
|
|
bitfld.long 0x00 0. "CALRAF,CALRAF" "0,1"
|
|
tree.end
|
|
tree "SEC_RTC"
|
|
base ad:0x50002800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TR,time register"
|
|
bitfld.long 0x00 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x00 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "HU,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "MNU,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SU,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,date register"
|
|
bitfld.long 0x00 20.--23. "YT,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "YU,Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "MT,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. "MU,Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "DU,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SSR,RTC sub second register"
|
|
hexmask.long.word 0x00 0.--15. 1. "SS,SS"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ICSR,RTC initialization control and status register"
|
|
rbitfld.long 0x00 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x00 7. "INIT,Initialization mode" "0,1"
|
|
rbitfld.long 0x00 6. "INITF,Initialization flag" "0,1"
|
|
bitfld.long 0x00 5. "RSF,Registers synchronization flag" "0,1"
|
|
rbitfld.long 0x00 4. "INITS,Initialization status flag" "0,1"
|
|
bitfld.long 0x00 3. "SHPF,Shift operation pending" "0,1"
|
|
rbitfld.long 0x00 2. "WUTWF,Wakeup timer write flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "ALRBWF,Alarm B write flag" "0,1"
|
|
rbitfld.long 0x00 0. "ALRAWF,Alarm A write flag" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRER,prescaler register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x00 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "WUTR,wakeup timer register"
|
|
hexmask.long.word 0x00 16.--31. 1. "WUTOCLR,WUTOCLR"
|
|
hexmask.long.word 0x00 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CR,RTC control register"
|
|
bitfld.long 0x00 31. "OUT2EN,OUT2EN" "0,1"
|
|
bitfld.long 0x00 30. "TAMPALRM_TYPE,TAMPALRM_TYPE" "0,1"
|
|
bitfld.long 0x00 29. "TAMPALRM_PU,TAMPALRM_PU" "0,1"
|
|
bitfld.long 0x00 26. "TAMPOE,TAMPOE" "0,1"
|
|
bitfld.long 0x00 25. "TAMPTS,TAMPTS" "0,1"
|
|
bitfld.long 0x00 24. "ITSE,ITSE" "0,1"
|
|
bitfld.long 0x00 23. "COE,COE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "OSEL,OSEL" "0,1,2,3"
|
|
bitfld.long 0x00 20. "POL,POL" "0,1"
|
|
bitfld.long 0x00 19. "COSEL,COSEL" "0,1"
|
|
bitfld.long 0x00 18. "BKP,BKP" "0,1"
|
|
bitfld.long 0x00 17. "SUB1H,SUB1H" "0,1"
|
|
bitfld.long 0x00 16. "ADD1H,ADD1H" "0,1"
|
|
bitfld.long 0x00 15. "TSIE,TSIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "WUTIE,WUTIE" "0,1"
|
|
bitfld.long 0x00 13. "ALRBIE,ALRBIE" "0,1"
|
|
bitfld.long 0x00 12. "ALRAIE,ALRAIE" "0,1"
|
|
bitfld.long 0x00 11. "TSE,TSE" "0,1"
|
|
bitfld.long 0x00 10. "WUTE,WUTE" "0,1"
|
|
bitfld.long 0x00 9. "ALRBE,ALRBE" "0,1"
|
|
bitfld.long 0x00 8. "ALRAE,ALRAE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "FMT,FMT" "0,1"
|
|
bitfld.long 0x00 5. "BYPSHAD,BYPSHAD" "0,1"
|
|
bitfld.long 0x00 4. "REFCKON,REFCKON" "0,1"
|
|
bitfld.long 0x00 3. "TSEDGE,TSEDGE" "0,1"
|
|
bitfld.long 0x00 0.--2. "WUCKSEL,WUCKSEL" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PRIVCR,RTC privilege mode control register"
|
|
bitfld.long 0x00 15. "PRIV,PRIV" "0,1"
|
|
bitfld.long 0x00 14. "INITPRIV,INITPRIV" "0,1"
|
|
bitfld.long 0x00 13. "CALPRIV,CALPRIV" "0,1"
|
|
bitfld.long 0x00 3. "TSPRIV,TSPRIV" "0,1"
|
|
bitfld.long 0x00 2. "WUTPRIV,WUTPRIV" "0,1"
|
|
bitfld.long 0x00 1. "ALRBPRIV,ALRBPRIV" "0,1"
|
|
bitfld.long 0x00 0. "ALRAPRIV,ALRAPRIV" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SMCR,RTC secure mode control register"
|
|
bitfld.long 0x00 15. "DECPROT,DECPROT" "0,1"
|
|
bitfld.long 0x00 14. "INITDPROT,INITDPROT" "0,1"
|
|
bitfld.long 0x00 13. "CALDPROT,CALDPROT" "0,1"
|
|
bitfld.long 0x00 3. "TSDPROT,TSDPROT" "0,1"
|
|
bitfld.long 0x00 2. "WUTDPROT,WUTDPROT" "0,1"
|
|
bitfld.long 0x00 1. "ALRBDPROT,ALRBDPROT" "0,1"
|
|
bitfld.long 0x00 0. "ALRADPROT,ALRADPROT" "0,1"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "WPR,write protection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CALR,calibration register"
|
|
bitfld.long 0x00 15. "CALP,Increase frequency of RTC by 488.5 ppm" "0,1"
|
|
bitfld.long 0x00 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
bitfld.long 0x00 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
bitfld.long 0x00 12. "LPCAL,LPCAL" "0,1"
|
|
hexmask.long.word 0x00 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "SHIFTR,shift control register"
|
|
bitfld.long 0x00 31. "ADD1S,Add one second" "0,1"
|
|
hexmask.long.word 0x00 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TSTR,time stamp time register"
|
|
bitfld.long 0x00 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x00 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "HU,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "MNU,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SU,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TSDR,time stamp date register"
|
|
bitfld.long 0x00 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "MT,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. "MU,Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "DU,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TSSSR,timestamp sub second register"
|
|
hexmask.long.word 0x00 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ALRMAR,alarm A register"
|
|
bitfld.long 0x00 31. "MSK4,Alarm A date mask" "0,1"
|
|
bitfld.long 0x00 30. "WDSEL,Week day selection" "0,1"
|
|
bitfld.long 0x00 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DU,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "MSK3,Alarm A hours mask" "0,1"
|
|
bitfld.long 0x00 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x00 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "HU,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "MSK2,Alarm A minutes mask" "0,1"
|
|
bitfld.long 0x00 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "MNU,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSK1,Alarm A seconds mask" "0,1"
|
|
bitfld.long 0x00 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SU,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ALRMASSR,alarm A sub second register"
|
|
bitfld.long 0x00 24.--27. "MASKSS,Mask the most-significant bits starting at this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--14. 1. "SS,Sub seconds value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ALRMBR,alarm B register"
|
|
bitfld.long 0x00 31. "MSK4,Alarm B date mask" "0,1"
|
|
bitfld.long 0x00 30. "WDSEL,Week day selection" "0,1"
|
|
bitfld.long 0x00 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DU,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "MSK3,Alarm B hours mask" "0,1"
|
|
bitfld.long 0x00 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x00 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "HU,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "MSK2,Alarm B minutes mask" "0,1"
|
|
bitfld.long 0x00 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "MNU,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSK1,Alarm B seconds mask" "0,1"
|
|
bitfld.long 0x00 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SU,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ALRMBSSR,alarm B sub second register"
|
|
bitfld.long 0x00 24.--27. "MASKSS,Mask the most-significant bits starting at this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "SR,RTC status register"
|
|
bitfld.long 0x00 5. "ITSF,ITSF" "0,1"
|
|
bitfld.long 0x00 4. "TSOVF,TSOVF" "0,1"
|
|
bitfld.long 0x00 3. "TSF,TSF" "0,1"
|
|
bitfld.long 0x00 2. "WUTF,WUTF" "0,1"
|
|
bitfld.long 0x00 1. "ALRBF,ALRBF" "0,1"
|
|
bitfld.long 0x00 0. "ALRAF,ALRAF" "0,1"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "MISR,RTC non-secure masked interrupt status register"
|
|
bitfld.long 0x00 5. "ITSMF,ITSMF" "0,1"
|
|
bitfld.long 0x00 4. "TSOVMF,TSOVMF" "0,1"
|
|
bitfld.long 0x00 3. "TSMF,TSMF" "0,1"
|
|
bitfld.long 0x00 2. "WUTMF,WUTMF" "0,1"
|
|
bitfld.long 0x00 1. "ALRBMF,ALRBMF" "0,1"
|
|
bitfld.long 0x00 0. "ALRAMF,ALRAMF" "0,1"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "SMISR,RTC secure masked interrupt status register"
|
|
bitfld.long 0x00 5. "ITSMF,ITSMF" "0,1"
|
|
bitfld.long 0x00 4. "TSOVMF,TSOVMF" "0,1"
|
|
bitfld.long 0x00 3. "TSMF,TSMF" "0,1"
|
|
bitfld.long 0x00 2. "WUTMF,WUTMF" "0,1"
|
|
bitfld.long 0x00 1. "ALRBMF,ALRBMF" "0,1"
|
|
bitfld.long 0x00 0. "ALRAMF,ALRAMF" "0,1"
|
|
wgroup.long 0x5C++0x03
|
|
line.long 0x00 "SCR,RTC status clear register"
|
|
bitfld.long 0x00 5. "CITSF,CITSF" "0,1"
|
|
bitfld.long 0x00 4. "CTSOVF,CTSOVF" "0,1"
|
|
bitfld.long 0x00 3. "CTSF,CTSF" "0,1"
|
|
bitfld.long 0x00 2. "CWUTF,CWUTF" "0,1"
|
|
bitfld.long 0x00 1. "CALRBF,CALRBF" "0,1"
|
|
bitfld.long 0x00 0. "CALRAF,CALRAF" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "SAI (Serial audio interface)"
|
|
repeat 2. (list 1. 2.) (list ad:0x40015400 ad:0x40015800)
|
|
tree "SAI$1"
|
|
base $2
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR1,BConfiguration register 1"
|
|
bitfld.long 0x00 26. "OSR,Oversampling ratio for master clock" "0,1"
|
|
bitfld.long 0x00 20.--23. "MCJDIV,Master clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "NODIV,No divider" "0,1"
|
|
bitfld.long 0x00 17. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x00 16. "SAIBEN,Audio block B enable" "0,1"
|
|
bitfld.long 0x00 13. "OutDri,Output drive" "0,1"
|
|
bitfld.long 0x00 12. "MONO,Mono mode" "0,1"
|
|
bitfld.long 0x00 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3"
|
|
bitfld.long 0x00 9. "CKSTR,Clock strobing edge" "0,1"
|
|
bitfld.long 0x00 8. "LSBFIRST,Least significant bit first" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODE,Audio block mode" "0,1,2,3"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "BCR2,BConfiguration register 2"
|
|
bitfld.long 0x00 14.--15. "COMP,Companding mode" "0,1,2,3"
|
|
bitfld.long 0x00 13. "CPL,Complement bit" "0,1"
|
|
bitfld.long 0x00 7.--12. "MUTECN,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6. "MUTEVAL,Mute value" "0,1"
|
|
bitfld.long 0x00 5. "MUTE,Mute" "0,1"
|
|
bitfld.long 0x00 4. "TRIS,Tristate management on data line" "0,1"
|
|
bitfld.long 0x00 3. "FFLUS,FIFO flush" "0,1"
|
|
bitfld.long 0x00 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "BFRCR,BFRCR"
|
|
bitfld.long 0x00 18. "FSOFF,Frame synchronization offset" "0,1"
|
|
bitfld.long 0x00 17. "FSPOL,Frame synchronization polarity" "0,1"
|
|
bitfld.long 0x00 16. "FSDEF,Frame synchronization definition" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "FSALL,Frame synchronization active level length"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FRL,Frame length"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "BSLOTR,BSlot register"
|
|
hexmask.long.word 0x00 16.--31. 1. "SLOTEN,Slot enable"
|
|
bitfld.long 0x00 8.--11. "NBSLOT,Number of slots in an audio frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "SLOTSZ,Slot size" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "FBOFF,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "BIM,BInterrupt mask register2"
|
|
bitfld.long 0x00 6. "LFSDETIE,Late frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CNRDYIE,Codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "FREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "WCKCFG,Wrong clock configuration interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "MUTEDET,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "OVRUDRIE,Overrun/underrun interrupt enable" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "BSR,BStatus register"
|
|
bitfld.long 0x00 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6. "LFSDET,Late frame synchronization detection" "0,1"
|
|
bitfld.long 0x00 5. "AFSDET,Anticipated frame synchronization detection" "0,1"
|
|
bitfld.long 0x00 4. "CNRDY,Codec not ready" "0,1"
|
|
bitfld.long 0x00 3. "FREQ,FIFO request" "0,1"
|
|
bitfld.long 0x00 2. "WCKCFG,Wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x00 1. "MUTEDET,Mute detection" "0,1"
|
|
bitfld.long 0x00 0. "OVRUDR,Overrun / underrun" "0,1"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "BCLRFR,BClear flag register"
|
|
bitfld.long 0x00 6. "LFSDET,Clear late frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x00 5. "CAFSDET,Clear anticipated frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x00 4. "CNRDY,Clear codec not ready flag" "0,1"
|
|
bitfld.long 0x00 2. "WCKCFG,Clear wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x00 1. "MUTEDET,Mute detection flag" "0,1"
|
|
bitfld.long 0x00 0. "OVRUDR,Clear overrun / underrun" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "BDR,BData register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Data"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ACR1,AConfiguration register 1"
|
|
bitfld.long 0x00 26. "OSR,OSR" "0,1"
|
|
bitfld.long 0x00 20.--23. "MCJDIV,Master clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "NODIV,No divider" "0,1"
|
|
bitfld.long 0x00 17. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x00 16. "SAIAEN,Audio block A enable" "0,1"
|
|
bitfld.long 0x00 13. "OutDri,Output drive" "0,1"
|
|
bitfld.long 0x00 12. "MONO,Mono mode" "0,1"
|
|
bitfld.long 0x00 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3"
|
|
bitfld.long 0x00 9. "CKSTR,Clock strobing edge" "0,1"
|
|
bitfld.long 0x00 8. "LSBFIRST,Least significant bit first" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODE,Audio block mode" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACR2,AConfiguration register 2"
|
|
bitfld.long 0x00 14.--15. "COMP,Companding mode" "0,1,2,3"
|
|
bitfld.long 0x00 13. "CPL,Complement bit" "0,1"
|
|
bitfld.long 0x00 7.--12. "MUTECN,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6. "MUTEVAL,Mute value" "0,1"
|
|
bitfld.long 0x00 5. "MUTE,Mute" "0,1"
|
|
bitfld.long 0x00 4. "TRIS,Tristate management on data line" "0,1"
|
|
bitfld.long 0x00 3. "FFLUS,FIFO flush" "0,1"
|
|
bitfld.long 0x00 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "AFRCR,AFRCR"
|
|
bitfld.long 0x00 18. "FSOFF,Frame synchronization offset" "0,1"
|
|
bitfld.long 0x00 17. "FSPOL,Frame synchronization polarity" "0,1"
|
|
bitfld.long 0x00 16. "FSDEF,Frame synchronization definition" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "FSALL,Frame synchronization active level length"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FRL,Frame length"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ASLOTR,ASlot register"
|
|
hexmask.long.word 0x00 16.--31. 1. "SLOTEN,Slot enable"
|
|
bitfld.long 0x00 8.--11. "NBSLOT,Number of slots in an audio frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "SLOTSZ,Slot size" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "FBOFF,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "AIM,AInterrupt mask register2"
|
|
bitfld.long 0x00 6. "LFSDET,Late frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CNRDYIE,Codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "FREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "WCKCFG,Wrong clock configuration interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "MUTEDET,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "OVRUDRIE,Overrun/underrun interrupt enable" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ASR,AStatus register"
|
|
bitfld.long 0x00 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6. "LFSDET,Late frame synchronization detection" "0,1"
|
|
bitfld.long 0x00 5. "AFSDET,Anticipated frame synchronization detection" "0,1"
|
|
bitfld.long 0x00 4. "CNRDY,Codec not ready" "0,1"
|
|
bitfld.long 0x00 3. "FREQ,FIFO request" "0,1"
|
|
bitfld.long 0x00 2. "WCKCFG,Wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x00 1. "MUTEDET,Mute detection" "0,1"
|
|
bitfld.long 0x00 0. "OVRUDR,Overrun / underrun" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ACLRFR,AClear flag register"
|
|
bitfld.long 0x00 6. "LFSDET,Clear late frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x00 5. "CAFSDET,Clear anticipated frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x00 4. "CNRDY,Clear codec not ready flag" "0,1"
|
|
bitfld.long 0x00 2. "WCKCFG,Clear wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x00 1. "MUTEDET,Mute detection flag" "0,1"
|
|
bitfld.long 0x00 0. "OVRUDR,Clear overrun / underrun" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADR,AData register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Data"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,Global configuration register"
|
|
bitfld.long 0x00 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PDMCR,PDM control register"
|
|
bitfld.long 0x00 9. "CKEN2,CKEN2" "0,1"
|
|
bitfld.long 0x00 8. "CKEN1,Clock enable of bitstream clock number 1" "0,1"
|
|
bitfld.long 0x00 4.--5. "MICNBR,MICNBR" "0,1,2,3"
|
|
bitfld.long 0x00 0. "PDMEN,PDM enable" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PDMDLY,PDM delay register"
|
|
bitfld.long 0x00 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "DLYM2R,Delay line for second microphone of pair 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "DLYM2L,Delay line for first microphone of pair 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "DLYM1R,Delay line adjust for second microphone of pair 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "DLYM1L,Delay line adjust for first microphone of pair 1" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
repeat.end
|
|
repeat 2. (list 1. 2.) (list ad:0x50015400 ad:0x50015800)
|
|
tree "SEC_SAI$1"
|
|
base $2
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR1,BConfiguration register 1"
|
|
bitfld.long 0x00 26. "OSR,Oversampling ratio for master clock" "0,1"
|
|
bitfld.long 0x00 20.--23. "MCJDIV,Master clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "NODIV,No divider" "0,1"
|
|
bitfld.long 0x00 17. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x00 16. "SAIBEN,Audio block B enable" "0,1"
|
|
bitfld.long 0x00 13. "OutDri,Output drive" "0,1"
|
|
bitfld.long 0x00 12. "MONO,Mono mode" "0,1"
|
|
bitfld.long 0x00 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3"
|
|
bitfld.long 0x00 9. "CKSTR,Clock strobing edge" "0,1"
|
|
bitfld.long 0x00 8. "LSBFIRST,Least significant bit first" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODE,Audio block mode" "0,1,2,3"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "BCR2,BConfiguration register 2"
|
|
bitfld.long 0x00 14.--15. "COMP,Companding mode" "0,1,2,3"
|
|
bitfld.long 0x00 13. "CPL,Complement bit" "0,1"
|
|
bitfld.long 0x00 7.--12. "MUTECN,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6. "MUTEVAL,Mute value" "0,1"
|
|
bitfld.long 0x00 5. "MUTE,Mute" "0,1"
|
|
bitfld.long 0x00 4. "TRIS,Tristate management on data line" "0,1"
|
|
bitfld.long 0x00 3. "FFLUS,FIFO flush" "0,1"
|
|
bitfld.long 0x00 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "BFRCR,BFRCR"
|
|
bitfld.long 0x00 18. "FSOFF,Frame synchronization offset" "0,1"
|
|
bitfld.long 0x00 17. "FSPOL,Frame synchronization polarity" "0,1"
|
|
bitfld.long 0x00 16. "FSDEF,Frame synchronization definition" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "FSALL,Frame synchronization active level length"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FRL,Frame length"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "BSLOTR,BSlot register"
|
|
hexmask.long.word 0x00 16.--31. 1. "SLOTEN,Slot enable"
|
|
bitfld.long 0x00 8.--11. "NBSLOT,Number of slots in an audio frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "SLOTSZ,Slot size" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "FBOFF,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "BIM,BInterrupt mask register2"
|
|
bitfld.long 0x00 6. "LFSDETIE,Late frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CNRDYIE,Codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "FREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "WCKCFG,Wrong clock configuration interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "MUTEDET,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "OVRUDRIE,Overrun/underrun interrupt enable" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "BSR,BStatus register"
|
|
bitfld.long 0x00 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6. "LFSDET,Late frame synchronization detection" "0,1"
|
|
bitfld.long 0x00 5. "AFSDET,Anticipated frame synchronization detection" "0,1"
|
|
bitfld.long 0x00 4. "CNRDY,Codec not ready" "0,1"
|
|
bitfld.long 0x00 3. "FREQ,FIFO request" "0,1"
|
|
bitfld.long 0x00 2. "WCKCFG,Wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x00 1. "MUTEDET,Mute detection" "0,1"
|
|
bitfld.long 0x00 0. "OVRUDR,Overrun / underrun" "0,1"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "BCLRFR,BClear flag register"
|
|
bitfld.long 0x00 6. "LFSDET,Clear late frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x00 5. "CAFSDET,Clear anticipated frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x00 4. "CNRDY,Clear codec not ready flag" "0,1"
|
|
bitfld.long 0x00 2. "WCKCFG,Clear wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x00 1. "MUTEDET,Mute detection flag" "0,1"
|
|
bitfld.long 0x00 0. "OVRUDR,Clear overrun / underrun" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "BDR,BData register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Data"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ACR1,AConfiguration register 1"
|
|
bitfld.long 0x00 26. "OSR,OSR" "0,1"
|
|
bitfld.long 0x00 20.--23. "MCJDIV,Master clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "NODIV,No divider" "0,1"
|
|
bitfld.long 0x00 17. "DMAEN,DMA enable" "0,1"
|
|
bitfld.long 0x00 16. "SAIAEN,Audio block A enable" "0,1"
|
|
bitfld.long 0x00 13. "OutDri,Output drive" "0,1"
|
|
bitfld.long 0x00 12. "MONO,Mono mode" "0,1"
|
|
bitfld.long 0x00 10.--11. "SYNCEN,Synchronization enable" "0,1,2,3"
|
|
bitfld.long 0x00 9. "CKSTR,Clock strobing edge" "0,1"
|
|
bitfld.long 0x00 8. "LSBFIRST,Least significant bit first" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "DS,Data size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2.--3. "PRTCFG,Protocol configuration" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "MODE,Audio block mode" "0,1,2,3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACR2,AConfiguration register 2"
|
|
bitfld.long 0x00 14.--15. "COMP,Companding mode" "0,1,2,3"
|
|
bitfld.long 0x00 13. "CPL,Complement bit" "0,1"
|
|
bitfld.long 0x00 7.--12. "MUTECN,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6. "MUTEVAL,Mute value" "0,1"
|
|
bitfld.long 0x00 5. "MUTE,Mute" "0,1"
|
|
bitfld.long 0x00 4. "TRIS,Tristate management on data line" "0,1"
|
|
bitfld.long 0x00 3. "FFLUS,FIFO flush" "0,1"
|
|
bitfld.long 0x00 0.--2. "FTH,FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "AFRCR,AFRCR"
|
|
bitfld.long 0x00 18. "FSOFF,Frame synchronization offset" "0,1"
|
|
bitfld.long 0x00 17. "FSPOL,Frame synchronization polarity" "0,1"
|
|
bitfld.long 0x00 16. "FSDEF,Frame synchronization definition" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "FSALL,Frame synchronization active level length"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FRL,Frame length"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ASLOTR,ASlot register"
|
|
hexmask.long.word 0x00 16.--31. 1. "SLOTEN,Slot enable"
|
|
bitfld.long 0x00 8.--11. "NBSLOT,Number of slots in an audio frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "SLOTSZ,Slot size" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. "FBOFF,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "AIM,AInterrupt mask register2"
|
|
bitfld.long 0x00 6. "LFSDET,Late frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "AFSDETIE,Anticipated frame synchronization detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CNRDYIE,Codec not ready interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "FREQIE,FIFO request interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "WCKCFG,Wrong clock configuration interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "MUTEDET,Mute detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "OVRUDRIE,Overrun/underrun interrupt enable" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ASR,AStatus register"
|
|
bitfld.long 0x00 16.--18. "FLVL,FIFO level threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6. "LFSDET,Late frame synchronization detection" "0,1"
|
|
bitfld.long 0x00 5. "AFSDET,Anticipated frame synchronization detection" "0,1"
|
|
bitfld.long 0x00 4. "CNRDY,Codec not ready" "0,1"
|
|
bitfld.long 0x00 3. "FREQ,FIFO request" "0,1"
|
|
bitfld.long 0x00 2. "WCKCFG,Wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x00 1. "MUTEDET,Mute detection" "0,1"
|
|
bitfld.long 0x00 0. "OVRUDR,Overrun / underrun" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ACLRFR,AClear flag register"
|
|
bitfld.long 0x00 6. "LFSDET,Clear late frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x00 5. "CAFSDET,Clear anticipated frame synchronization detection flag" "0,1"
|
|
bitfld.long 0x00 4. "CNRDY,Clear codec not ready flag" "0,1"
|
|
bitfld.long 0x00 2. "WCKCFG,Clear wrong clock configuration flag" "0,1"
|
|
bitfld.long 0x00 1. "MUTEDET,Mute detection flag" "0,1"
|
|
bitfld.long 0x00 0. "OVRUDR,Clear overrun / underrun" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADR,AData register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Data"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,Global configuration register"
|
|
bitfld.long 0x00 4.--5. "SYNCOUT,Synchronization outputs" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PDMCR,PDM control register"
|
|
bitfld.long 0x00 9. "CKEN2,CKEN2" "0,1"
|
|
bitfld.long 0x00 8. "CKEN1,Clock enable of bitstream clock number 1" "0,1"
|
|
bitfld.long 0x00 4.--5. "MICNBR,MICNBR" "0,1,2,3"
|
|
bitfld.long 0x00 0. "PDMEN,PDM enable" "0,1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PDMDLY,PDM delay register"
|
|
bitfld.long 0x00 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "DLYM2R,Delay line for second microphone of pair 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "DLYM2L,Delay line for first microphone of pair 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "DLYM1R,Delay line adjust for second microphone of pair 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "DLYM1L,Delay line adjust for first microphone of pair 1" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SDMMC (SDMMC1)"
|
|
tree "SDMMC1"
|
|
base ad:0x420C8000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SDMMC_POWER,SDMMC power control register"
|
|
bitfld.long 0x00 4. "DIRPOL,Data and command direction signals polarity selection" "0,1"
|
|
bitfld.long 0x00 3. "VSWITCHEN,Voltage switch procedure enable" "0,1"
|
|
bitfld.long 0x00 2. "VSWITCH,Voltage switch sequence start" "0,1"
|
|
bitfld.long 0x00 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the SDMMC_CK output clock the SDMMC_RX_CLK receive clock and the bus width"
|
|
bitfld.long 0x00 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3"
|
|
bitfld.long 0x00 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1"
|
|
bitfld.long 0x00 18. "DDR,Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode" "0,1"
|
|
bitfld.long 0x00 17. "HWFC_EN,Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled the meaning of the TXFIFOE and RXFIFOF flags change please see SDMMC status.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "NEGEDGE,SDMMC_CK dephasing selection bit for data and Command" "0: - SDMMC_CK edge occurs on SDMMCCLK rising edge,1: - Data changed on the SDMMCCLK falling edge"
|
|
bitfld.long 0x00 14.--15. "WIDBUS,Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)" "0,1,2,3"
|
|
bitfld.long 0x00 12. "PWRSAV,Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit command argument which is sent to a card as part of a command message"
|
|
hexmask.long 0x00 0.--31. 1. "CMDARG,Command argument"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SDMMC_CMDR,The SDMMC_CMDR register contains the command index and command type bits"
|
|
bitfld.long 0x00 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1"
|
|
bitfld.long 0x00 15. "BOOTEN,Enable boot mode procedure" "0,1"
|
|
bitfld.long 0x00 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1"
|
|
bitfld.long 0x00 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "CPSMEN,Command path state machine (CPSM) Enable bit This bit is written 1 by firmware and cleared by hardware when the CPSM enters the Idle state" "0,1"
|
|
bitfld.long 0x00 11. "WAITPEND,CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM" "0,1"
|
|
bitfld.long 0x00 10. "WAITINT,CPSM waits for interrupt request" "0,1"
|
|
bitfld.long 0x00 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1"
|
|
bitfld.long 0x00 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)" "0,1"
|
|
bitfld.long 0x00 0.--5. "CMDINDEX,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the status of a card which is part of the received response"
|
|
hexmask.long 0x00 0.--31. 1. "CARDSTATUS1,see Table 432"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the status of a card which is part of the received response"
|
|
hexmask.long 0x00 0.--31. 1. "CARDSTATUS2,see Table404"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the status of a card which is part of the received response"
|
|
hexmask.long 0x00 0.--31. 1. "CARDSTATUS3,see Table404"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the status of a card which is part of the received response"
|
|
hexmask.long 0x00 0.--31. 1. "CARDSTATUS4,see Table404"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data timeout period in card bus clock periods"
|
|
hexmask.long 0x00 0.--31. 1. "DATATIME,Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SDMMC_DLENR,The SDMMC_DLENR register contains the number of data bytes to be transferred"
|
|
hexmask.long 0x00 0.--24. 1. "DATALENGTH,Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0)"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data path state machine (DPSM)"
|
|
bitfld.long 0x00 13. "FIFORST,FIFO reset will flush any remaining data" "0,1"
|
|
bitfld.long 0x00 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1"
|
|
bitfld.long 0x00 11. "SDIOEN,SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)" "0,1"
|
|
bitfld.long 0x00 10. "RWMOD,Read wait mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "RWSTOP,Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state" "0,1"
|
|
bitfld.long 0x00 8. "RWSTART,Read wait start" "0,1"
|
|
bitfld.long 0x00 4.--7. "DBLOCKSIZE,Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "DTDIR,Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)" "0,1"
|
|
bitfld.long 0x00 0. "DTEN,Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)" "0,1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state"
|
|
hexmask.long 0x00 0.--24. 1. "DATACOUNT,Data count value When read the number of remaining data bytes to be transferred is returned"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SDMMC_STAR,The SDMMC_STAR register is a read-only register"
|
|
bitfld.long 0x00 28. "IDMABTC,IDMA buffer transfer complete" "0,1"
|
|
bitfld.long 0x00 27. "IDMATE,IDMA transfer error" "0,1"
|
|
bitfld.long 0x00 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1"
|
|
bitfld.long 0x00 25. "VSWEND,Voltage switch critical timing section completion" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1"
|
|
bitfld.long 0x00 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1"
|
|
bitfld.long 0x00 22. "SDIOIT,SDIO interrupt received" "0,1"
|
|
bitfld.long 0x00 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1"
|
|
bitfld.long 0x00 19. "RXFIFOE,Receive FIFO empty This is a hardware status flag only does not generate an interrupt" "0,1"
|
|
bitfld.long 0x00 18. "TXFIFOE,Transmit FIFO empty This bit is cleared when one FIFO location becomes full" "0,1"
|
|
bitfld.long 0x00 17. "RXFIFOF,Receive FIFO full This bit is cleared when one FIFO location becomes empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "TXFIFOF,Transmit FIFO full This is a hardware status flag only does not generate an interrupt" "0,1"
|
|
bitfld.long 0x00 15. "RXFIFOHF,Receive FIFO half full There are at least half the number of words in the FIFO" "0,1"
|
|
bitfld.long 0x00 14. "TXFIFOHE,Transmit FIFO half empty At least half the number of words can be written into the FIFO" "0,1"
|
|
bitfld.long 0x00 13. "CPSMACT,Command path state machine active i.e" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "DPSMACT,Data path state machine active i.e" "0,1"
|
|
bitfld.long 0x00 11. "DABORT,Data transfer aborted by CMD12" "0,1"
|
|
bitfld.long 0x00 10. "DBCKEND,Data block sent/received" "0,1"
|
|
bitfld.long 0x00 9. "DHOLD,Data transfer Hold" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DATAEND,Data transfer ended correctly" "0,1"
|
|
bitfld.long 0x00 7. "CMDSENT,Command sent (no response required)" "0,1"
|
|
bitfld.long 0x00 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1"
|
|
bitfld.long 0x00 5. "RXOVERR,Received FIFO overrun error or IDMA write transfer error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TXUNDERR,Transmit FIFO underrun error or IDMA read transfer error" "0,1"
|
|
bitfld.long 0x00 3. "DTIMEOUT,Data timeout" "0,1"
|
|
bitfld.long 0x00 2. "CTIMEOUT,Command response timeout" "0,1"
|
|
bitfld.long 0x00 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SDMMC_ICR,The SDMMC_ICR register is a write-only register"
|
|
bitfld.long 0x00 28. "IDMABTCC,IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag" "0,1"
|
|
bitfld.long 0x00 27. "IDMATEC,IDMA transfer error clear bit Set by software to clear the IDMATE flag" "0,1"
|
|
bitfld.long 0x00 26. "CKSTOPC,CKSTOP flag clear bit Set by software to clear the CKSTOP flag" "0,1"
|
|
bitfld.long 0x00 25. "VSWENDC,VSWEND flag clear bit Set by software to clear the VSWEND flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag" "0,1"
|
|
bitfld.long 0x00 23. "ACKFAILC,ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag" "0,1"
|
|
bitfld.long 0x00 22. "SDIOITC,SDIOIT flag clear bit Set by software to clear the SDIOIT flag" "0,1"
|
|
bitfld.long 0x00 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "DABORTC,DABORT flag clear bit Set by software to clear the DABORT flag" "0,1"
|
|
bitfld.long 0x00 10. "DBCKENDC,DBCKEND flag clear bit Set by software to clear the DBCKEND flag" "0,1"
|
|
bitfld.long 0x00 9. "DHOLDC,DHOLD flag clear bit Set by software to clear the DHOLD flag" "0,1"
|
|
bitfld.long 0x00 8. "DATAENDC,DATAEND flag clear bit Set by software to clear the DATAEND flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CMDSENTC,CMDSENT flag clear bit Set by software to clear the CMDSENT flag" "0,1"
|
|
bitfld.long 0x00 6. "CMDRENDC,CMDREND flag clear bit Set by software to clear the CMDREND flag" "0,1"
|
|
bitfld.long 0x00 5. "RXOVERRC,RXOVERR flag clear bit Set by software to clear the RXOVERR flag" "0,1"
|
|
bitfld.long 0x00 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software to clear TXUNDERR flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag" "0,1"
|
|
bitfld.long 0x00 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag" "0,1"
|
|
bitfld.long 0x00 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag" "0,1"
|
|
bitfld.long 0x00 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SDMMC_MASKR,The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1"
|
|
bitfld.long 0x00 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer" "0,1"
|
|
bitfld.long 0x00 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped" "0,1"
|
|
bitfld.long 0x00 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion" "0,1"
|
|
bitfld.long 0x00 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail" "0,1"
|
|
bitfld.long 0x00 22. "SDIOITIE,SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt" "0,1"
|
|
bitfld.long 0x00 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response" "0,1"
|
|
bitfld.long 0x00 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full" "0,1"
|
|
bitfld.long 0x00 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full" "0,1"
|
|
bitfld.long 0x00 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty" "0,1"
|
|
bitfld.long 0x00 11. "DABORTIE,Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "DBCKENDIE,Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end" "0,1"
|
|
bitfld.long 0x00 9. "DHOLDIE,Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state" "0,1"
|
|
bitfld.long 0x00 8. "DATAENDIE,Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end" "0,1"
|
|
bitfld.long 0x00 7. "CMDSENTIE,Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CMDRENDIE,Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response" "0,1"
|
|
bitfld.long 0x00 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error" "0,1"
|
|
bitfld.long 0x00 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error" "0,1"
|
|
bitfld.long 0x00 3. "DTIMEOUTIE,Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CTIMEOUTIE,Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout" "0,1"
|
|
bitfld.long 0x00 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure" "0,1"
|
|
bitfld.long 0x00 0. "CCRCFAILIE,Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the acknowledgment timeout period in SDMMC_CK bus clock periods"
|
|
hexmask.long 0x00 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read or written as 32-bit wide registers"
|
|
bitfld.long 0x00 2. "IDMABACT,Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)" "0,1"
|
|
bitfld.long 0x00 1. "IDMABMODE,Buffer mode selection" "0,1"
|
|
bitfld.long 0x00 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration"
|
|
hexmask.long.byte 0x00 5.--12. 1. "IDMABNDT,Number of transfers per buffer"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SDMMC_IDMABASE0R,The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration"
|
|
hexmask.long 0x00 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SDMMC_IDMABASE1R,The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address"
|
|
hexmask.long 0x00 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be word aligned (bit [1:0] are always 0 and read only)"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SDMMC_FIFOR,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers"
|
|
hexmask.long 0x00 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1)"
|
|
rgroup.long 0x3F4++0x03
|
|
line.long 0x00 "SDMMC_VER,SDMMC IP version register"
|
|
bitfld.long 0x00 4.--7. "MAJREV,IP major revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MINREV,IP minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x3F8++0x03
|
|
line.long 0x00 "SDMMC_ID,SDMMC IP identification register"
|
|
hexmask.long 0x00 0.--31. 1. "IP_ID,SDMMC IP identification"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SDMMC_RESPCMDR,SDMMC command response register"
|
|
bitfld.long 0x00 0.--5. "RESPCMD,Response command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree "SEC_SDMMC1"
|
|
base ad:0x520C8000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SDMMC_POWER,SDMMC power control register"
|
|
bitfld.long 0x00 4. "DIRPOL,Data and command direction signals polarity selection" "0,1"
|
|
bitfld.long 0x00 3. "VSWITCHEN,Voltage switch procedure enable" "0,1"
|
|
bitfld.long 0x00 2. "VSWITCH,Voltage switch sequence start" "0,1"
|
|
bitfld.long 0x00 0.--1. "PWRCTRL,SDMMC state control bits" "0,1,2,3"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the SDMMC_CK output clock the SDMMC_RX_CLK receive clock and the bus width"
|
|
bitfld.long 0x00 20.--21. "SELCLKRX,Receive clock selection" "0,1,2,3"
|
|
bitfld.long 0x00 19. "BUSSPEED,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "0,1"
|
|
bitfld.long 0x00 18. "DDR,Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode" "0,1"
|
|
bitfld.long 0x00 17. "HWFC_EN,Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled the meaning of the TXFIFOE and RXFIFOF flags change please see SDMMC status.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "NEGEDGE,SDMMC_CK dephasing selection bit for data and Command" "0: - SDMMC_CK edge occurs on SDMMCCLK rising edge,1: - Data changed on the SDMMCCLK falling edge"
|
|
bitfld.long 0x00 14.--15. "WIDBUS,Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)" "0,1,2,3"
|
|
bitfld.long 0x00 12. "PWRSAV,Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit command argument which is sent to a card as part of a command message"
|
|
hexmask.long 0x00 0.--31. 1. "CMDARG,Command argument"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SDMMC_CMDR,The SDMMC_CMDR register contains the command index and command type bits"
|
|
bitfld.long 0x00 16. "CMDSUSPEND,The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end" "0,1"
|
|
bitfld.long 0x00 15. "BOOTEN,Enable boot mode procedure" "0,1"
|
|
bitfld.long 0x00 14. "BOOTMODE,Select the boot mode procedure to be used" "0,1"
|
|
bitfld.long 0x00 13. "DTHOLD,Hold new data block transmission and reception in the DPSM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "CPSMEN,Command path state machine (CPSM) Enable bit This bit is written 1 by firmware and cleared by hardware when the CPSM enters the Idle state" "0,1"
|
|
bitfld.long 0x00 11. "WAITPEND,CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM" "0,1"
|
|
bitfld.long 0x00 10. "WAITINT,CPSM waits for interrupt request" "0,1"
|
|
bitfld.long 0x00 8.--9. "WAITRESP,Wait for response bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "CMDSTOP,The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM" "0,1"
|
|
bitfld.long 0x00 6. "CMDTRANS,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)" "0,1"
|
|
bitfld.long 0x00 0.--5. "CMDINDEX,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the status of a card which is part of the received response"
|
|
hexmask.long 0x00 0.--31. 1. "CARDSTATUS1,see Table 432"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the status of a card which is part of the received response"
|
|
hexmask.long 0x00 0.--31. 1. "CARDSTATUS2,see Table404"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the status of a card which is part of the received response"
|
|
hexmask.long 0x00 0.--31. 1. "CARDSTATUS3,see Table404"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the status of a card which is part of the received response"
|
|
hexmask.long 0x00 0.--31. 1. "CARDSTATUS4,see Table404"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data timeout period in card bus clock periods"
|
|
hexmask.long 0x00 0.--31. 1. "DATATIME,Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SDMMC_DLENR,The SDMMC_DLENR register contains the number of data bytes to be transferred"
|
|
hexmask.long 0x00 0.--24. 1. "DATALENGTH,Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0)"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data path state machine (DPSM)"
|
|
bitfld.long 0x00 13. "FIFORST,FIFO reset will flush any remaining data" "0,1"
|
|
bitfld.long 0x00 12. "BOOTACKEN,Enable the reception of the boot acknowledgment" "0,1"
|
|
bitfld.long 0x00 11. "SDIOEN,SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)" "0,1"
|
|
bitfld.long 0x00 10. "RWMOD,Read wait mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "RWSTOP,Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state" "0,1"
|
|
bitfld.long 0x00 8. "RWSTART,Read wait start" "0,1"
|
|
bitfld.long 0x00 4.--7. "DBLOCKSIZE,Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "DTMODE,Data transfer mode selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "DTDIR,Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)" "0,1"
|
|
bitfld.long 0x00 0. "DTEN,Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)" "0,1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state"
|
|
hexmask.long 0x00 0.--24. 1. "DATACOUNT,Data count value When read the number of remaining data bytes to be transferred is returned"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SDMMC_STAR,The SDMMC_STAR register is a read-only register"
|
|
bitfld.long 0x00 28. "IDMABTC,IDMA buffer transfer complete" "0,1"
|
|
bitfld.long 0x00 27. "IDMATE,IDMA transfer error" "0,1"
|
|
bitfld.long 0x00 26. "CKSTOP,SDMMC_CK stopped in Voltage switch procedure" "0,1"
|
|
bitfld.long 0x00 25. "VSWEND,Voltage switch critical timing section completion" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "ACKTIMEOUT,Boot acknowledgment timeout" "0,1"
|
|
bitfld.long 0x00 23. "ACKFAIL,Boot acknowledgment received (boot acknowledgment check fail)" "0,1"
|
|
bitfld.long 0x00 22. "SDIOIT,SDIO interrupt received" "0,1"
|
|
bitfld.long 0x00 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD response detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response" "0,1"
|
|
bitfld.long 0x00 19. "RXFIFOE,Receive FIFO empty This is a hardware status flag only does not generate an interrupt" "0,1"
|
|
bitfld.long 0x00 18. "TXFIFOE,Transmit FIFO empty This bit is cleared when one FIFO location becomes full" "0,1"
|
|
bitfld.long 0x00 17. "RXFIFOF,Receive FIFO full This bit is cleared when one FIFO location becomes empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "TXFIFOF,Transmit FIFO full This is a hardware status flag only does not generate an interrupt" "0,1"
|
|
bitfld.long 0x00 15. "RXFIFOHF,Receive FIFO half full There are at least half the number of words in the FIFO" "0,1"
|
|
bitfld.long 0x00 14. "TXFIFOHE,Transmit FIFO half empty At least half the number of words can be written into the FIFO" "0,1"
|
|
bitfld.long 0x00 13. "CPSMACT,Command path state machine active i.e" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "DPSMACT,Data path state machine active i.e" "0,1"
|
|
bitfld.long 0x00 11. "DABORT,Data transfer aborted by CMD12" "0,1"
|
|
bitfld.long 0x00 10. "DBCKEND,Data block sent/received" "0,1"
|
|
bitfld.long 0x00 9. "DHOLD,Data transfer Hold" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DATAEND,Data transfer ended correctly" "0,1"
|
|
bitfld.long 0x00 7. "CMDSENT,Command sent (no response required)" "0,1"
|
|
bitfld.long 0x00 6. "CMDREND,Command response received (CRC check passed or no CRC)" "0,1"
|
|
bitfld.long 0x00 5. "RXOVERR,Received FIFO overrun error or IDMA write transfer error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TXUNDERR,Transmit FIFO underrun error or IDMA read transfer error" "0,1"
|
|
bitfld.long 0x00 3. "DTIMEOUT,Data timeout" "0,1"
|
|
bitfld.long 0x00 2. "CTIMEOUT,Command response timeout" "0,1"
|
|
bitfld.long 0x00 1. "DCRCFAIL,Data block sent/received (CRC check failed)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CCRCFAIL,Command response received (CRC check failed)" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SDMMC_ICR,The SDMMC_ICR register is a write-only register"
|
|
bitfld.long 0x00 28. "IDMABTCC,IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag" "0,1"
|
|
bitfld.long 0x00 27. "IDMATEC,IDMA transfer error clear bit Set by software to clear the IDMATE flag" "0,1"
|
|
bitfld.long 0x00 26. "CKSTOPC,CKSTOP flag clear bit Set by software to clear the CKSTOP flag" "0,1"
|
|
bitfld.long 0x00 25. "VSWENDC,VSWEND flag clear bit Set by software to clear the VSWEND flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag" "0,1"
|
|
bitfld.long 0x00 23. "ACKFAILC,ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag" "0,1"
|
|
bitfld.long 0x00 22. "SDIOITC,SDIOIT flag clear bit Set by software to clear the SDIOIT flag" "0,1"
|
|
bitfld.long 0x00 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "DABORTC,DABORT flag clear bit Set by software to clear the DABORT flag" "0,1"
|
|
bitfld.long 0x00 10. "DBCKENDC,DBCKEND flag clear bit Set by software to clear the DBCKEND flag" "0,1"
|
|
bitfld.long 0x00 9. "DHOLDC,DHOLD flag clear bit Set by software to clear the DHOLD flag" "0,1"
|
|
bitfld.long 0x00 8. "DATAENDC,DATAEND flag clear bit Set by software to clear the DATAEND flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CMDSENTC,CMDSENT flag clear bit Set by software to clear the CMDSENT flag" "0,1"
|
|
bitfld.long 0x00 6. "CMDRENDC,CMDREND flag clear bit Set by software to clear the CMDREND flag" "0,1"
|
|
bitfld.long 0x00 5. "RXOVERRC,RXOVERR flag clear bit Set by software to clear the RXOVERR flag" "0,1"
|
|
bitfld.long 0x00 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software to clear TXUNDERR flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag" "0,1"
|
|
bitfld.long 0x00 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag" "0,1"
|
|
bitfld.long 0x00 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag" "0,1"
|
|
bitfld.long 0x00 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SDMMC_MASKR,The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1"
|
|
bitfld.long 0x00 28. "IDMABTCIE,IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer" "0,1"
|
|
bitfld.long 0x00 26. "CKSTOPIE,Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped" "0,1"
|
|
bitfld.long 0x00 25. "VSWENDIE,Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion" "0,1"
|
|
bitfld.long 0x00 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail" "0,1"
|
|
bitfld.long 0x00 22. "SDIOITIE,SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt" "0,1"
|
|
bitfld.long 0x00 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response" "0,1"
|
|
bitfld.long 0x00 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full" "0,1"
|
|
bitfld.long 0x00 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full" "0,1"
|
|
bitfld.long 0x00 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty" "0,1"
|
|
bitfld.long 0x00 11. "DABORTIE,Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "DBCKENDIE,Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end" "0,1"
|
|
bitfld.long 0x00 9. "DHOLDIE,Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state" "0,1"
|
|
bitfld.long 0x00 8. "DATAENDIE,Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end" "0,1"
|
|
bitfld.long 0x00 7. "CMDSENTIE,Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CMDRENDIE,Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response" "0,1"
|
|
bitfld.long 0x00 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error" "0,1"
|
|
bitfld.long 0x00 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error" "0,1"
|
|
bitfld.long 0x00 3. "DTIMEOUTIE,Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CTIMEOUTIE,Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout" "0,1"
|
|
bitfld.long 0x00 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure" "0,1"
|
|
bitfld.long 0x00 0. "CCRCFAILIE,Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the acknowledgment timeout period in SDMMC_CK bus clock periods"
|
|
hexmask.long 0x00 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read or written as 32-bit wide registers"
|
|
bitfld.long 0x00 2. "IDMABACT,Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)" "0,1"
|
|
bitfld.long 0x00 1. "IDMABMODE,Buffer mode selection" "0,1"
|
|
bitfld.long 0x00 0. "IDMAEN,IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration"
|
|
hexmask.long.byte 0x00 5.--12. 1. "IDMABNDT,Number of transfers per buffer"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SDMMC_IDMABASE0R,The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration"
|
|
hexmask.long 0x00 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits [31:2] shall be word aligned (bit [1:0] are always 0 and read only)"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SDMMC_IDMABASE1R,The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address"
|
|
hexmask.long 0x00 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be word aligned (bit [1:0] are always 0 and read only)"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SDMMC_FIFOR,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers"
|
|
hexmask.long 0x00 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1)"
|
|
rgroup.long 0x3F4++0x03
|
|
line.long 0x00 "SDMMC_VER,SDMMC IP version register"
|
|
bitfld.long 0x00 4.--7. "MAJREV,IP major revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MINREV,IP minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x3F8++0x03
|
|
line.long 0x00 "SDMMC_ID,SDMMC IP identification register"
|
|
hexmask.long 0x00 0.--31. 1. "IP_ID,SDMMC IP identification"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SDMMC_RESPCMDR,SDMMC command response register"
|
|
bitfld.long 0x00 0.--5. "RESPCMD,Response command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree.end
|
|
tree "SEC_GTZC (SEC_MPCBB1)"
|
|
tree "SEC_MPCBB1"
|
|
base ad:0x50032C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MPCBB1_CR,MPCBB control register"
|
|
bitfld.long 0x00 31. "SRWILADIS,SRWILADIS" "0,1"
|
|
bitfld.long 0x00 30. "INVSECSTATE,INVSECSTATE" "0,1"
|
|
bitfld.long 0x00 0. "LCK,LCK" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MPCBB1_LCKVTR1,MPCBB control register"
|
|
bitfld.long 0x00 31. "LCKSB31,LCKSB31" "0,1"
|
|
bitfld.long 0x00 30. "LCKSB30,LCKSB30" "0,1"
|
|
bitfld.long 0x00 29. "LCKSB29,LCKSB29" "0,1"
|
|
bitfld.long 0x00 28. "LCKSB28,LCKSB28" "0,1"
|
|
bitfld.long 0x00 27. "LCKSB27,LCKSB27" "0,1"
|
|
bitfld.long 0x00 26. "LCKSB26,LCKSB26" "0,1"
|
|
bitfld.long 0x00 25. "LCKSB25,LCKSB25" "0,1"
|
|
bitfld.long 0x00 24. "LCKSB24,LCKSB24" "0,1"
|
|
bitfld.long 0x00 23. "LCKSB23,LCKSB23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "LCKSB22,LCKSB22" "0,1"
|
|
bitfld.long 0x00 21. "LCKSB21,LCKSB21" "0,1"
|
|
bitfld.long 0x00 20. "LCKSB20,LCKSB20" "0,1"
|
|
bitfld.long 0x00 19. "LCKSB19,LCKSB19" "0,1"
|
|
bitfld.long 0x00 18. "LCKSB18,LCKSB18" "0,1"
|
|
bitfld.long 0x00 17. "LCKSB17,LCKSB17" "0,1"
|
|
bitfld.long 0x00 16. "LCKSB16,LCKSB16" "0,1"
|
|
bitfld.long 0x00 15. "LCKSB15,LCKSB15" "0,1"
|
|
bitfld.long 0x00 14. "LCKSB14,LCKSB14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "LCKSB13,LCKSB13" "0,1"
|
|
bitfld.long 0x00 12. "LCKSB12,LCKSB12" "0,1"
|
|
bitfld.long 0x00 11. "LCKSB11,LCKSB11" "0,1"
|
|
bitfld.long 0x00 10. "LCKSB10,LCKSB10" "0,1"
|
|
bitfld.long 0x00 9. "LCKSB9,LCKSB9" "0,1"
|
|
bitfld.long 0x00 8. "LCKSB8,LCKSB8" "0,1"
|
|
bitfld.long 0x00 7. "LCKSB7,LCKSB7" "0,1"
|
|
bitfld.long 0x00 6. "LCKSB6,LCKSB6" "0,1"
|
|
bitfld.long 0x00 5. "LCKSB5,LCKSB5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LCKSB4,LCKSB4" "0,1"
|
|
bitfld.long 0x00 3. "LCKSB3,LCKSB3" "0,1"
|
|
bitfld.long 0x00 2. "LCKSB2,LCKSB2" "0,1"
|
|
bitfld.long 0x00 1. "LCKSB1,LCKSB1" "0,1"
|
|
bitfld.long 0x00 0. "LCKSB0,LCKSB0" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MPCBB1_LCKVTR2,MPCBB control register"
|
|
bitfld.long 0x00 31. "LCKSB63,LCKSB63" "0,1"
|
|
bitfld.long 0x00 30. "LCKSB62,LCKSB62" "0,1"
|
|
bitfld.long 0x00 29. "LCKSB61,LCKSB61" "0,1"
|
|
bitfld.long 0x00 28. "LCKSB60,LCKSB60" "0,1"
|
|
bitfld.long 0x00 27. "LCKSB59,LCKSB59" "0,1"
|
|
bitfld.long 0x00 26. "LCKSB58,LCKSB58" "0,1"
|
|
bitfld.long 0x00 25. "LCKSB57,LCKSB57" "0,1"
|
|
bitfld.long 0x00 24. "LCKSB56,LCKSB56" "0,1"
|
|
bitfld.long 0x00 23. "LCKSB55,LCKSB55" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "LCKSB54,LCKSB54" "0,1"
|
|
bitfld.long 0x00 21. "LCKSB53,LCKSB53" "0,1"
|
|
bitfld.long 0x00 20. "LCKSB52,LCKSB52" "0,1"
|
|
bitfld.long 0x00 19. "LCKSB51,LCKSB51" "0,1"
|
|
bitfld.long 0x00 18. "LCKSB50,LCKSB50" "0,1"
|
|
bitfld.long 0x00 17. "LCKSB49,LCKSB49" "0,1"
|
|
bitfld.long 0x00 16. "LCKSB48,LCKSB48" "0,1"
|
|
bitfld.long 0x00 15. "LCKSB47,LCKSB47" "0,1"
|
|
bitfld.long 0x00 14. "LCKSB46,LCKSB46" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "LCKSB45,LCKSB45" "0,1"
|
|
bitfld.long 0x00 12. "LCKSB44,LCKSB44" "0,1"
|
|
bitfld.long 0x00 11. "LCKSB43,LCKSB43" "0,1"
|
|
bitfld.long 0x00 10. "LCKSB42,LCKSB42" "0,1"
|
|
bitfld.long 0x00 9. "LCKSB41,LCKSB41" "0,1"
|
|
bitfld.long 0x00 8. "LCKSB40,LCKSB40" "0,1"
|
|
bitfld.long 0x00 7. "LCKSB39,LCKSB39" "0,1"
|
|
bitfld.long 0x00 6. "LCKSB38,LCKSB38" "0,1"
|
|
bitfld.long 0x00 5. "LCKSB37,LCKSB37" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LCKSB36,LCKSB36" "0,1"
|
|
bitfld.long 0x00 3. "LCKSB35,LCKSB35" "0,1"
|
|
bitfld.long 0x00 2. "LCKSB34,LCKSB34" "0,1"
|
|
bitfld.long 0x00 1. "LCKSB33,LCKSB33" "0,1"
|
|
bitfld.long 0x00 0. "LCKSB32,LCKSB32" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MPCBB1_VCTR0,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B31,B31" "0,1"
|
|
bitfld.long 0x00 30. "B30,B30" "0,1"
|
|
bitfld.long 0x00 29. "B29,B29" "0,1"
|
|
bitfld.long 0x00 28. "B28,B28" "0,1"
|
|
bitfld.long 0x00 27. "B27,B27" "0,1"
|
|
bitfld.long 0x00 26. "B26,B26" "0,1"
|
|
bitfld.long 0x00 25. "B25,B25" "0,1"
|
|
bitfld.long 0x00 24. "B24,B24" "0,1"
|
|
bitfld.long 0x00 23. "B23,B23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B22,B22" "0,1"
|
|
bitfld.long 0x00 21. "B21,B21" "0,1"
|
|
bitfld.long 0x00 20. "B20,B20" "0,1"
|
|
bitfld.long 0x00 19. "B19,B19" "0,1"
|
|
bitfld.long 0x00 18. "B18,B18" "0,1"
|
|
bitfld.long 0x00 17. "B17,B17" "0,1"
|
|
bitfld.long 0x00 16. "B16,B16" "0,1"
|
|
bitfld.long 0x00 15. "B15,B15" "0,1"
|
|
bitfld.long 0x00 14. "B14,B14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B13,B13" "0,1"
|
|
bitfld.long 0x00 12. "B12,B12" "0,1"
|
|
bitfld.long 0x00 11. "B11,B11" "0,1"
|
|
bitfld.long 0x00 10. "B10,B10" "0,1"
|
|
bitfld.long 0x00 9. "B9,B9" "0,1"
|
|
bitfld.long 0x00 8. "B8,B8" "0,1"
|
|
bitfld.long 0x00 7. "B7,B7" "0,1"
|
|
bitfld.long 0x00 6. "B6,B6" "0,1"
|
|
bitfld.long 0x00 5. "B5,B5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B4,B4" "0,1"
|
|
bitfld.long 0x00 3. "B3,B3" "0,1"
|
|
bitfld.long 0x00 2. "B2,B2" "0,1"
|
|
bitfld.long 0x00 1. "B1,B1" "0,1"
|
|
bitfld.long 0x00 0. "B0,B0" "0,1"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "MPCBB1_VCTR1,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B63,B63" "0,1"
|
|
bitfld.long 0x00 30. "B62,B62" "0,1"
|
|
bitfld.long 0x00 29. "B61,B61" "0,1"
|
|
bitfld.long 0x00 28. "B60,B60" "0,1"
|
|
bitfld.long 0x00 27. "B59,B59" "0,1"
|
|
bitfld.long 0x00 26. "B58,B58" "0,1"
|
|
bitfld.long 0x00 25. "B57,B57" "0,1"
|
|
bitfld.long 0x00 24. "B56,B56" "0,1"
|
|
bitfld.long 0x00 23. "B55,B55" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B54,B54" "0,1"
|
|
bitfld.long 0x00 21. "B53,B53" "0,1"
|
|
bitfld.long 0x00 20. "B52,B52" "0,1"
|
|
bitfld.long 0x00 19. "B51,B51" "0,1"
|
|
bitfld.long 0x00 18. "B50,B50" "0,1"
|
|
bitfld.long 0x00 17. "B49,B49" "0,1"
|
|
bitfld.long 0x00 16. "B48,B48" "0,1"
|
|
bitfld.long 0x00 15. "B47,B47" "0,1"
|
|
bitfld.long 0x00 14. "B46,B46" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B45,B45" "0,1"
|
|
bitfld.long 0x00 12. "B44,B44" "0,1"
|
|
bitfld.long 0x00 11. "B43,B43" "0,1"
|
|
bitfld.long 0x00 10. "B42,B42" "0,1"
|
|
bitfld.long 0x00 9. "B41,B41" "0,1"
|
|
bitfld.long 0x00 8. "B40,B40" "0,1"
|
|
bitfld.long 0x00 7. "B39,B39" "0,1"
|
|
bitfld.long 0x00 6. "B38,B38" "0,1"
|
|
bitfld.long 0x00 5. "B37,B37" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B36,B36" "0,1"
|
|
bitfld.long 0x00 3. "B35,B35" "0,1"
|
|
bitfld.long 0x00 2. "B34,B34" "0,1"
|
|
bitfld.long 0x00 1. "B33,B33" "0,1"
|
|
bitfld.long 0x00 0. "B32,B32" "0,1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "MPCBB1_VCTR2,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B95,B95" "0,1"
|
|
bitfld.long 0x00 30. "B94,B94" "0,1"
|
|
bitfld.long 0x00 29. "B93,B93" "0,1"
|
|
bitfld.long 0x00 28. "B92,B92" "0,1"
|
|
bitfld.long 0x00 27. "B91,B91" "0,1"
|
|
bitfld.long 0x00 26. "B90,B90" "0,1"
|
|
bitfld.long 0x00 25. "B89,B89" "0,1"
|
|
bitfld.long 0x00 24. "B88,B88" "0,1"
|
|
bitfld.long 0x00 23. "B87,B87" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B86,B86" "0,1"
|
|
bitfld.long 0x00 21. "B85,B85" "0,1"
|
|
bitfld.long 0x00 20. "B84,B84" "0,1"
|
|
bitfld.long 0x00 19. "B83,B83" "0,1"
|
|
bitfld.long 0x00 18. "B82,B82" "0,1"
|
|
bitfld.long 0x00 17. "B81,B81" "0,1"
|
|
bitfld.long 0x00 16. "B80,B80" "0,1"
|
|
bitfld.long 0x00 15. "B79,B79" "0,1"
|
|
bitfld.long 0x00 14. "B78,B78" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B77,B77" "0,1"
|
|
bitfld.long 0x00 12. "B76,B76" "0,1"
|
|
bitfld.long 0x00 11. "B75,B75" "0,1"
|
|
bitfld.long 0x00 10. "B74,B74" "0,1"
|
|
bitfld.long 0x00 9. "B73,B73" "0,1"
|
|
bitfld.long 0x00 8. "B72,B72" "0,1"
|
|
bitfld.long 0x00 7. "B71,B71" "0,1"
|
|
bitfld.long 0x00 6. "B70,B70" "0,1"
|
|
bitfld.long 0x00 5. "B69,B69" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B68,B68" "0,1"
|
|
bitfld.long 0x00 3. "B67,B67" "0,1"
|
|
bitfld.long 0x00 2. "B66,B66" "0,1"
|
|
bitfld.long 0x00 1. "B65,B65" "0,1"
|
|
bitfld.long 0x00 0. "B64,B64" "0,1"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR3,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B127,B127" "0,1"
|
|
bitfld.long 0x00 30. "B126,B126" "0,1"
|
|
bitfld.long 0x00 29. "B125,B125" "0,1"
|
|
bitfld.long 0x00 28. "B124,B124" "0,1"
|
|
bitfld.long 0x00 27. "B123,B123" "0,1"
|
|
bitfld.long 0x00 26. "B122,B122" "0,1"
|
|
bitfld.long 0x00 25. "B121,B121" "0,1"
|
|
bitfld.long 0x00 24. "B120,B120" "0,1"
|
|
bitfld.long 0x00 23. "B119,B119" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B118,B118" "0,1"
|
|
bitfld.long 0x00 21. "B117,B117" "0,1"
|
|
bitfld.long 0x00 20. "B116,B116" "0,1"
|
|
bitfld.long 0x00 19. "B115,B115" "0,1"
|
|
bitfld.long 0x00 18. "B114,B114" "0,1"
|
|
bitfld.long 0x00 17. "B113,B113" "0,1"
|
|
bitfld.long 0x00 16. "B112,B112" "0,1"
|
|
bitfld.long 0x00 15. "B111,B111" "0,1"
|
|
bitfld.long 0x00 14. "B110,B110" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B109,B109" "0,1"
|
|
bitfld.long 0x00 12. "B108,B108" "0,1"
|
|
bitfld.long 0x00 11. "B107,B107" "0,1"
|
|
bitfld.long 0x00 10. "B106,B106" "0,1"
|
|
bitfld.long 0x00 9. "B105,B105" "0,1"
|
|
bitfld.long 0x00 8. "B104,B104" "0,1"
|
|
bitfld.long 0x00 7. "B103,B103" "0,1"
|
|
bitfld.long 0x00 6. "B102,B102" "0,1"
|
|
bitfld.long 0x00 5. "B101,B101" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B100,B100" "0,1"
|
|
bitfld.long 0x00 3. "B99,B99" "0,1"
|
|
bitfld.long 0x00 2. "B98,B98" "0,1"
|
|
bitfld.long 0x00 1. "B97,B97" "0,1"
|
|
bitfld.long 0x00 0. "B96,B96" "0,1"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MPCBB1_VCTR4,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B159,B159" "0,1"
|
|
bitfld.long 0x00 30. "B158,B158" "0,1"
|
|
bitfld.long 0x00 29. "B157,B157" "0,1"
|
|
bitfld.long 0x00 28. "B156,B156" "0,1"
|
|
bitfld.long 0x00 27. "B155,B155" "0,1"
|
|
bitfld.long 0x00 26. "B154,B154" "0,1"
|
|
bitfld.long 0x00 25. "B153,B153" "0,1"
|
|
bitfld.long 0x00 24. "B152,B152" "0,1"
|
|
bitfld.long 0x00 23. "B151,B151" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B150,B150" "0,1"
|
|
bitfld.long 0x00 21. "B149,B149" "0,1"
|
|
bitfld.long 0x00 20. "B148,B148" "0,1"
|
|
bitfld.long 0x00 19. "B147,B147" "0,1"
|
|
bitfld.long 0x00 18. "B146,B146" "0,1"
|
|
bitfld.long 0x00 17. "B145,B145" "0,1"
|
|
bitfld.long 0x00 16. "B144,B144" "0,1"
|
|
bitfld.long 0x00 15. "B143,B143" "0,1"
|
|
bitfld.long 0x00 14. "B142,B142" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B141,B141" "0,1"
|
|
bitfld.long 0x00 12. "B140,B140" "0,1"
|
|
bitfld.long 0x00 11. "B139,B139" "0,1"
|
|
bitfld.long 0x00 10. "B138,B138" "0,1"
|
|
bitfld.long 0x00 9. "B137,B137" "0,1"
|
|
bitfld.long 0x00 8. "B136,B136" "0,1"
|
|
bitfld.long 0x00 7. "B135,B135" "0,1"
|
|
bitfld.long 0x00 6. "B134,B134" "0,1"
|
|
bitfld.long 0x00 5. "B133,B133" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B132,B132" "0,1"
|
|
bitfld.long 0x00 3. "B131,B131" "0,1"
|
|
bitfld.long 0x00 2. "B130,B130" "0,1"
|
|
bitfld.long 0x00 1. "B129,B129" "0,1"
|
|
bitfld.long 0x00 0. "B128,B128" "0,1"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MPCBB1_VCTR5,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B191,B191" "0,1"
|
|
bitfld.long 0x00 30. "B190,B190" "0,1"
|
|
bitfld.long 0x00 29. "B189,B189" "0,1"
|
|
bitfld.long 0x00 28. "B188,B188" "0,1"
|
|
bitfld.long 0x00 27. "B187,B187" "0,1"
|
|
bitfld.long 0x00 26. "B186,B186" "0,1"
|
|
bitfld.long 0x00 25. "B185,B185" "0,1"
|
|
bitfld.long 0x00 24. "B184,B184" "0,1"
|
|
bitfld.long 0x00 23. "B183,B183" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B182,B182" "0,1"
|
|
bitfld.long 0x00 21. "B181,B181" "0,1"
|
|
bitfld.long 0x00 20. "B180,B180" "0,1"
|
|
bitfld.long 0x00 19. "B179,B179" "0,1"
|
|
bitfld.long 0x00 18. "B178,B178" "0,1"
|
|
bitfld.long 0x00 17. "B177,B177" "0,1"
|
|
bitfld.long 0x00 16. "B176,B176" "0,1"
|
|
bitfld.long 0x00 15. "B175,B175" "0,1"
|
|
bitfld.long 0x00 14. "B174,B174" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B173,B173" "0,1"
|
|
bitfld.long 0x00 12. "B172,B172" "0,1"
|
|
bitfld.long 0x00 11. "B171,B171" "0,1"
|
|
bitfld.long 0x00 10. "B170,B170" "0,1"
|
|
bitfld.long 0x00 9. "B169,B169" "0,1"
|
|
bitfld.long 0x00 8. "B168,B168" "0,1"
|
|
bitfld.long 0x00 7. "B167,B167" "0,1"
|
|
bitfld.long 0x00 6. "B166,B166" "0,1"
|
|
bitfld.long 0x00 5. "B165,B165" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B164,B164" "0,1"
|
|
bitfld.long 0x00 3. "B163,B163" "0,1"
|
|
bitfld.long 0x00 2. "B162,B162" "0,1"
|
|
bitfld.long 0x00 1. "B161,B161" "0,1"
|
|
bitfld.long 0x00 0. "B160,B160" "0,1"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MPCBB1_VCTR6,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B223,B223" "0,1"
|
|
bitfld.long 0x00 30. "B222,B222" "0,1"
|
|
bitfld.long 0x00 29. "B221,B221" "0,1"
|
|
bitfld.long 0x00 28. "B220,B220" "0,1"
|
|
bitfld.long 0x00 27. "B219,B219" "0,1"
|
|
bitfld.long 0x00 26. "B218,B218" "0,1"
|
|
bitfld.long 0x00 25. "B217,B217" "0,1"
|
|
bitfld.long 0x00 24. "B216,B216" "0,1"
|
|
bitfld.long 0x00 23. "B215,B215" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B214,B214" "0,1"
|
|
bitfld.long 0x00 21. "B213,B213" "0,1"
|
|
bitfld.long 0x00 20. "B212,B212" "0,1"
|
|
bitfld.long 0x00 19. "B211,B211" "0,1"
|
|
bitfld.long 0x00 18. "B210,B210" "0,1"
|
|
bitfld.long 0x00 17. "B209,B209" "0,1"
|
|
bitfld.long 0x00 16. "B208,B208" "0,1"
|
|
bitfld.long 0x00 15. "B207,B207" "0,1"
|
|
bitfld.long 0x00 14. "B206,B206" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B205,B205" "0,1"
|
|
bitfld.long 0x00 12. "B204,B204" "0,1"
|
|
bitfld.long 0x00 11. "B203,B203" "0,1"
|
|
bitfld.long 0x00 10. "B202,B202" "0,1"
|
|
bitfld.long 0x00 9. "B201,B201" "0,1"
|
|
bitfld.long 0x00 8. "B200,B200" "0,1"
|
|
bitfld.long 0x00 7. "B199,B199" "0,1"
|
|
bitfld.long 0x00 6. "B198,B198" "0,1"
|
|
bitfld.long 0x00 5. "B197,B197" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B196,B196" "0,1"
|
|
bitfld.long 0x00 3. "B195,B195" "0,1"
|
|
bitfld.long 0x00 2. "B194,B194" "0,1"
|
|
bitfld.long 0x00 1. "B193,B193" "0,1"
|
|
bitfld.long 0x00 0. "B192,B192" "0,1"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR7,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B255,B255" "0,1"
|
|
bitfld.long 0x00 30. "B254,B254" "0,1"
|
|
bitfld.long 0x00 29. "B253,B253" "0,1"
|
|
bitfld.long 0x00 28. "B252,B252" "0,1"
|
|
bitfld.long 0x00 27. "B251,B251" "0,1"
|
|
bitfld.long 0x00 26. "B250,B250" "0,1"
|
|
bitfld.long 0x00 25. "B249,B249" "0,1"
|
|
bitfld.long 0x00 24. "B248,B248" "0,1"
|
|
bitfld.long 0x00 23. "B247,B247" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B246,B246" "0,1"
|
|
bitfld.long 0x00 21. "B245,B245" "0,1"
|
|
bitfld.long 0x00 20. "B244,B244" "0,1"
|
|
bitfld.long 0x00 19. "B243,B243" "0,1"
|
|
bitfld.long 0x00 18. "B242,B242" "0,1"
|
|
bitfld.long 0x00 17. "B241,B241" "0,1"
|
|
bitfld.long 0x00 16. "B240,B240" "0,1"
|
|
bitfld.long 0x00 15. "B239,B239" "0,1"
|
|
bitfld.long 0x00 14. "B238,B238" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B237,B237" "0,1"
|
|
bitfld.long 0x00 12. "B236,B236" "0,1"
|
|
bitfld.long 0x00 11. "B235,B235" "0,1"
|
|
bitfld.long 0x00 10. "B234,B234" "0,1"
|
|
bitfld.long 0x00 9. "B233,B233" "0,1"
|
|
bitfld.long 0x00 8. "B232,B232" "0,1"
|
|
bitfld.long 0x00 7. "B231,B231" "0,1"
|
|
bitfld.long 0x00 6. "B230,B230" "0,1"
|
|
bitfld.long 0x00 5. "B229,B229" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B228,B228" "0,1"
|
|
bitfld.long 0x00 3. "B227,B227" "0,1"
|
|
bitfld.long 0x00 2. "B226,B226" "0,1"
|
|
bitfld.long 0x00 1. "B225,B225" "0,1"
|
|
bitfld.long 0x00 0. "B224,B224" "0,1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "MPCBB1_VCTR8,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B287,B287" "0,1"
|
|
bitfld.long 0x00 30. "B286,B286" "0,1"
|
|
bitfld.long 0x00 29. "B285,B285" "0,1"
|
|
bitfld.long 0x00 28. "B284,B284" "0,1"
|
|
bitfld.long 0x00 27. "B283,B283" "0,1"
|
|
bitfld.long 0x00 26. "B282,B282" "0,1"
|
|
bitfld.long 0x00 25. "B281,B281" "0,1"
|
|
bitfld.long 0x00 24. "B280,B280" "0,1"
|
|
bitfld.long 0x00 23. "B279,B279" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B278,B278" "0,1"
|
|
bitfld.long 0x00 21. "B277,B277" "0,1"
|
|
bitfld.long 0x00 20. "B276,B276" "0,1"
|
|
bitfld.long 0x00 19. "B275,B275" "0,1"
|
|
bitfld.long 0x00 18. "B274,B274" "0,1"
|
|
bitfld.long 0x00 17. "B273,B273" "0,1"
|
|
bitfld.long 0x00 16. "B272,B272" "0,1"
|
|
bitfld.long 0x00 15. "B271,B271" "0,1"
|
|
bitfld.long 0x00 14. "B270,B270" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B269,B269" "0,1"
|
|
bitfld.long 0x00 12. "B268,B268" "0,1"
|
|
bitfld.long 0x00 11. "B267,B267" "0,1"
|
|
bitfld.long 0x00 10. "B266,B266" "0,1"
|
|
bitfld.long 0x00 9. "B265,B265" "0,1"
|
|
bitfld.long 0x00 8. "B264,B264" "0,1"
|
|
bitfld.long 0x00 7. "B263,B263" "0,1"
|
|
bitfld.long 0x00 6. "B262,B262" "0,1"
|
|
bitfld.long 0x00 5. "B261,B261" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B260,B260" "0,1"
|
|
bitfld.long 0x00 3. "B259,B259" "0,1"
|
|
bitfld.long 0x00 2. "B258,B258" "0,1"
|
|
bitfld.long 0x00 1. "B257,B257" "0,1"
|
|
bitfld.long 0x00 0. "B256,B256" "0,1"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MPCBB1_VCTR9,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B319,B319" "0,1"
|
|
bitfld.long 0x00 30. "B318,B318" "0,1"
|
|
bitfld.long 0x00 29. "B317,B317" "0,1"
|
|
bitfld.long 0x00 28. "B316,B316" "0,1"
|
|
bitfld.long 0x00 27. "B315,B315" "0,1"
|
|
bitfld.long 0x00 26. "B314,B314" "0,1"
|
|
bitfld.long 0x00 25. "B313,B313" "0,1"
|
|
bitfld.long 0x00 24. "B312,B312" "0,1"
|
|
bitfld.long 0x00 23. "B311,B311" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B310,B310" "0,1"
|
|
bitfld.long 0x00 21. "B309,B309" "0,1"
|
|
bitfld.long 0x00 20. "B308,B308" "0,1"
|
|
bitfld.long 0x00 19. "B307,B307" "0,1"
|
|
bitfld.long 0x00 18. "B306,B306" "0,1"
|
|
bitfld.long 0x00 17. "B305,B305" "0,1"
|
|
bitfld.long 0x00 16. "B304,B304" "0,1"
|
|
bitfld.long 0x00 15. "B303,B303" "0,1"
|
|
bitfld.long 0x00 14. "B302,B302" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B301,B301" "0,1"
|
|
bitfld.long 0x00 12. "B300,B300" "0,1"
|
|
bitfld.long 0x00 11. "B299,B299" "0,1"
|
|
bitfld.long 0x00 10. "B298,B298" "0,1"
|
|
bitfld.long 0x00 9. "B297,B297" "0,1"
|
|
bitfld.long 0x00 8. "B296,B296" "0,1"
|
|
bitfld.long 0x00 7. "B295,B295" "0,1"
|
|
bitfld.long 0x00 6. "B294,B294" "0,1"
|
|
bitfld.long 0x00 5. "B293,B293" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B292,B292" "0,1"
|
|
bitfld.long 0x00 3. "B291,B291" "0,1"
|
|
bitfld.long 0x00 2. "B290,B290" "0,1"
|
|
bitfld.long 0x00 1. "B289,B289" "0,1"
|
|
bitfld.long 0x00 0. "B288,B288" "0,1"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "MPCBB1_VCTR10,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B351,B351" "0,1"
|
|
bitfld.long 0x00 30. "B350,B350" "0,1"
|
|
bitfld.long 0x00 29. "B349,B349" "0,1"
|
|
bitfld.long 0x00 28. "B348,B348" "0,1"
|
|
bitfld.long 0x00 27. "B347,B347" "0,1"
|
|
bitfld.long 0x00 26. "B346,B346" "0,1"
|
|
bitfld.long 0x00 25. "B345,B345" "0,1"
|
|
bitfld.long 0x00 24. "B344,B344" "0,1"
|
|
bitfld.long 0x00 23. "B343,B343" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B342,B342" "0,1"
|
|
bitfld.long 0x00 21. "B341,B341" "0,1"
|
|
bitfld.long 0x00 20. "B340,B340" "0,1"
|
|
bitfld.long 0x00 19. "B339,B339" "0,1"
|
|
bitfld.long 0x00 18. "B338,B338" "0,1"
|
|
bitfld.long 0x00 17. "B337,B337" "0,1"
|
|
bitfld.long 0x00 16. "B336,B336" "0,1"
|
|
bitfld.long 0x00 15. "B335,B335" "0,1"
|
|
bitfld.long 0x00 14. "B334,B334" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B333,B333" "0,1"
|
|
bitfld.long 0x00 12. "B332,B332" "0,1"
|
|
bitfld.long 0x00 11. "B331,B331" "0,1"
|
|
bitfld.long 0x00 10. "B330,B330" "0,1"
|
|
bitfld.long 0x00 9. "B329,B329" "0,1"
|
|
bitfld.long 0x00 8. "B328,B328" "0,1"
|
|
bitfld.long 0x00 7. "B327,B327" "0,1"
|
|
bitfld.long 0x00 6. "B326,B326" "0,1"
|
|
bitfld.long 0x00 5. "B325,B325" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B324,B324" "0,1"
|
|
bitfld.long 0x00 3. "B323,B323" "0,1"
|
|
bitfld.long 0x00 2. "B322,B322" "0,1"
|
|
bitfld.long 0x00 1. "B321,B321" "0,1"
|
|
bitfld.long 0x00 0. "B320,B320" "0,1"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR11,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B383,B383" "0,1"
|
|
bitfld.long 0x00 30. "B382,B382" "0,1"
|
|
bitfld.long 0x00 29. "B381,B381" "0,1"
|
|
bitfld.long 0x00 28. "B380,B380" "0,1"
|
|
bitfld.long 0x00 27. "B379,B379" "0,1"
|
|
bitfld.long 0x00 26. "B378,B378" "0,1"
|
|
bitfld.long 0x00 25. "B377,B377" "0,1"
|
|
bitfld.long 0x00 24. "B376,B376" "0,1"
|
|
bitfld.long 0x00 23. "B375,B375" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B374,B374" "0,1"
|
|
bitfld.long 0x00 21. "B373,B373" "0,1"
|
|
bitfld.long 0x00 20. "B372,B372" "0,1"
|
|
bitfld.long 0x00 19. "B371,B371" "0,1"
|
|
bitfld.long 0x00 18. "B370,B370" "0,1"
|
|
bitfld.long 0x00 17. "B369,B369" "0,1"
|
|
bitfld.long 0x00 16. "B368,B368" "0,1"
|
|
bitfld.long 0x00 15. "B367,B367" "0,1"
|
|
bitfld.long 0x00 14. "B366,B366" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B365,B365" "0,1"
|
|
bitfld.long 0x00 12. "B364,B364" "0,1"
|
|
bitfld.long 0x00 11. "B363,B363" "0,1"
|
|
bitfld.long 0x00 10. "B362,B362" "0,1"
|
|
bitfld.long 0x00 9. "B361,B361" "0,1"
|
|
bitfld.long 0x00 8. "B360,B360" "0,1"
|
|
bitfld.long 0x00 7. "B359,B359" "0,1"
|
|
bitfld.long 0x00 6. "B358,B358" "0,1"
|
|
bitfld.long 0x00 5. "B357,B357" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B356,B356" "0,1"
|
|
bitfld.long 0x00 3. "B355,B355" "0,1"
|
|
bitfld.long 0x00 2. "B354,B354" "0,1"
|
|
bitfld.long 0x00 1. "B353,B353" "0,1"
|
|
bitfld.long 0x00 0. "B352,B352" "0,1"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "MPCBB1_VCTR12,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B415,B415" "0,1"
|
|
bitfld.long 0x00 30. "B414,B414" "0,1"
|
|
bitfld.long 0x00 29. "B413,B413" "0,1"
|
|
bitfld.long 0x00 28. "B412,B412" "0,1"
|
|
bitfld.long 0x00 27. "B411,B411" "0,1"
|
|
bitfld.long 0x00 26. "B410,B410" "0,1"
|
|
bitfld.long 0x00 25. "B409,B409" "0,1"
|
|
bitfld.long 0x00 24. "B408,B408" "0,1"
|
|
bitfld.long 0x00 23. "B407,B407" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B406,B406" "0,1"
|
|
bitfld.long 0x00 21. "B405,B405" "0,1"
|
|
bitfld.long 0x00 20. "B404,B404" "0,1"
|
|
bitfld.long 0x00 19. "B403,B403" "0,1"
|
|
bitfld.long 0x00 18. "B402,B402" "0,1"
|
|
bitfld.long 0x00 17. "B401,B401" "0,1"
|
|
bitfld.long 0x00 16. "B400,B400" "0,1"
|
|
bitfld.long 0x00 15. "B399,B399" "0,1"
|
|
bitfld.long 0x00 14. "B398,B398" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B397,B397" "0,1"
|
|
bitfld.long 0x00 12. "B396,B396" "0,1"
|
|
bitfld.long 0x00 11. "B395,B395" "0,1"
|
|
bitfld.long 0x00 10. "B394,B394" "0,1"
|
|
bitfld.long 0x00 9. "B393,B393" "0,1"
|
|
bitfld.long 0x00 8. "B392,B392" "0,1"
|
|
bitfld.long 0x00 7. "B391,B391" "0,1"
|
|
bitfld.long 0x00 6. "B390,B390" "0,1"
|
|
bitfld.long 0x00 5. "B389,B389" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B388,B388" "0,1"
|
|
bitfld.long 0x00 3. "B387,B387" "0,1"
|
|
bitfld.long 0x00 2. "B386,B386" "0,1"
|
|
bitfld.long 0x00 1. "B385,B385" "0,1"
|
|
bitfld.long 0x00 0. "B384,B384" "0,1"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "MPCBB1_VCTR13,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B447,B447" "0,1"
|
|
bitfld.long 0x00 30. "B446,B446" "0,1"
|
|
bitfld.long 0x00 29. "B445,B445" "0,1"
|
|
bitfld.long 0x00 28. "B444,B444" "0,1"
|
|
bitfld.long 0x00 27. "B443,B443" "0,1"
|
|
bitfld.long 0x00 26. "B442,B442" "0,1"
|
|
bitfld.long 0x00 25. "B441,B441" "0,1"
|
|
bitfld.long 0x00 24. "B440,B440" "0,1"
|
|
bitfld.long 0x00 23. "B439,B439" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B438,B438" "0,1"
|
|
bitfld.long 0x00 21. "B437,B437" "0,1"
|
|
bitfld.long 0x00 20. "B436,B436" "0,1"
|
|
bitfld.long 0x00 19. "B435,B435" "0,1"
|
|
bitfld.long 0x00 18. "B434,B434" "0,1"
|
|
bitfld.long 0x00 17. "B433,B433" "0,1"
|
|
bitfld.long 0x00 16. "B432,B432" "0,1"
|
|
bitfld.long 0x00 15. "B431,B431" "0,1"
|
|
bitfld.long 0x00 14. "B430,B430" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B429,B429" "0,1"
|
|
bitfld.long 0x00 12. "B428,B428" "0,1"
|
|
bitfld.long 0x00 11. "B427,B427" "0,1"
|
|
bitfld.long 0x00 10. "B426,B426" "0,1"
|
|
bitfld.long 0x00 9. "B425,B425" "0,1"
|
|
bitfld.long 0x00 8. "B424,B424" "0,1"
|
|
bitfld.long 0x00 7. "B423,B423" "0,1"
|
|
bitfld.long 0x00 6. "B422,B422" "0,1"
|
|
bitfld.long 0x00 5. "B421,B421" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B420,B420" "0,1"
|
|
bitfld.long 0x00 3. "B419,B419" "0,1"
|
|
bitfld.long 0x00 2. "B418,B418" "0,1"
|
|
bitfld.long 0x00 1. "B417,B417" "0,1"
|
|
bitfld.long 0x00 0. "B416,B416" "0,1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "MPCBB1_VCTR14,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B479,B479" "0,1"
|
|
bitfld.long 0x00 30. "B478,B478" "0,1"
|
|
bitfld.long 0x00 29. "B477,B477" "0,1"
|
|
bitfld.long 0x00 28. "B476,B476" "0,1"
|
|
bitfld.long 0x00 27. "B475,B475" "0,1"
|
|
bitfld.long 0x00 26. "B474,B474" "0,1"
|
|
bitfld.long 0x00 25. "B473,B473" "0,1"
|
|
bitfld.long 0x00 24. "B472,B472" "0,1"
|
|
bitfld.long 0x00 23. "B471,B471" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B470,B470" "0,1"
|
|
bitfld.long 0x00 21. "B469,B469" "0,1"
|
|
bitfld.long 0x00 20. "B468,B468" "0,1"
|
|
bitfld.long 0x00 19. "B467,B467" "0,1"
|
|
bitfld.long 0x00 18. "B466,B466" "0,1"
|
|
bitfld.long 0x00 17. "B465,B465" "0,1"
|
|
bitfld.long 0x00 16. "B464,B464" "0,1"
|
|
bitfld.long 0x00 15. "B463,B463" "0,1"
|
|
bitfld.long 0x00 14. "B462,B462" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B461,B461" "0,1"
|
|
bitfld.long 0x00 12. "B460,B460" "0,1"
|
|
bitfld.long 0x00 11. "B459,B459" "0,1"
|
|
bitfld.long 0x00 10. "B458,B458" "0,1"
|
|
bitfld.long 0x00 9. "B457,B457" "0,1"
|
|
bitfld.long 0x00 8. "B456,B456" "0,1"
|
|
bitfld.long 0x00 7. "B455,B455" "0,1"
|
|
bitfld.long 0x00 6. "B454,B454" "0,1"
|
|
bitfld.long 0x00 5. "B453,B453" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B452,B452" "0,1"
|
|
bitfld.long 0x00 3. "B451,B451" "0,1"
|
|
bitfld.long 0x00 2. "B450,B450" "0,1"
|
|
bitfld.long 0x00 1. "B449,B449" "0,1"
|
|
bitfld.long 0x00 0. "B448,B448" "0,1"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR15,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B511,B511" "0,1"
|
|
bitfld.long 0x00 30. "B510,B510" "0,1"
|
|
bitfld.long 0x00 29. "B509,B509" "0,1"
|
|
bitfld.long 0x00 28. "B508,B508" "0,1"
|
|
bitfld.long 0x00 27. "B507,B507" "0,1"
|
|
bitfld.long 0x00 26. "B506,B506" "0,1"
|
|
bitfld.long 0x00 25. "B505,B505" "0,1"
|
|
bitfld.long 0x00 24. "B504,B504" "0,1"
|
|
bitfld.long 0x00 23. "B503,B503" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B502,B502" "0,1"
|
|
bitfld.long 0x00 21. "B501,B501" "0,1"
|
|
bitfld.long 0x00 20. "B500,B500" "0,1"
|
|
bitfld.long 0x00 19. "B499,B499" "0,1"
|
|
bitfld.long 0x00 18. "B498,B498" "0,1"
|
|
bitfld.long 0x00 17. "B497,B497" "0,1"
|
|
bitfld.long 0x00 16. "B496,B496" "0,1"
|
|
bitfld.long 0x00 15. "B495,B495" "0,1"
|
|
bitfld.long 0x00 14. "B494,B494" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B493,B493" "0,1"
|
|
bitfld.long 0x00 12. "B492,B492" "0,1"
|
|
bitfld.long 0x00 11. "B491,B491" "0,1"
|
|
bitfld.long 0x00 10. "B490,B490" "0,1"
|
|
bitfld.long 0x00 9. "B489,B489" "0,1"
|
|
bitfld.long 0x00 8. "B488,B488" "0,1"
|
|
bitfld.long 0x00 7. "B487,B487" "0,1"
|
|
bitfld.long 0x00 6. "B486,B486" "0,1"
|
|
bitfld.long 0x00 5. "B485,B485" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B484,B484" "0,1"
|
|
bitfld.long 0x00 3. "B483,B483" "0,1"
|
|
bitfld.long 0x00 2. "B482,B482" "0,1"
|
|
bitfld.long 0x00 1. "B481,B481" "0,1"
|
|
bitfld.long 0x00 0. "B480,B480" "0,1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "MPCBB1_VCTR16,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B543,B543" "0,1"
|
|
bitfld.long 0x00 30. "B542,B542" "0,1"
|
|
bitfld.long 0x00 29. "B541,B541" "0,1"
|
|
bitfld.long 0x00 28. "B540,B540" "0,1"
|
|
bitfld.long 0x00 27. "B539,B539" "0,1"
|
|
bitfld.long 0x00 26. "B538,B538" "0,1"
|
|
bitfld.long 0x00 25. "B537,B537" "0,1"
|
|
bitfld.long 0x00 24. "B536,B536" "0,1"
|
|
bitfld.long 0x00 23. "B535,B535" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B534,B534" "0,1"
|
|
bitfld.long 0x00 21. "B533,B533" "0,1"
|
|
bitfld.long 0x00 20. "B532,B532" "0,1"
|
|
bitfld.long 0x00 19. "B531,B531" "0,1"
|
|
bitfld.long 0x00 18. "B530,B530" "0,1"
|
|
bitfld.long 0x00 17. "B529,B529" "0,1"
|
|
bitfld.long 0x00 16. "B528,B528" "0,1"
|
|
bitfld.long 0x00 15. "B527,B527" "0,1"
|
|
bitfld.long 0x00 14. "B526,B526" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B525,B525" "0,1"
|
|
bitfld.long 0x00 12. "B524,B524" "0,1"
|
|
bitfld.long 0x00 11. "B523,B523" "0,1"
|
|
bitfld.long 0x00 10. "B522,B522" "0,1"
|
|
bitfld.long 0x00 9. "B521,B521" "0,1"
|
|
bitfld.long 0x00 8. "B520,B520" "0,1"
|
|
bitfld.long 0x00 7. "B519,B519" "0,1"
|
|
bitfld.long 0x00 6. "B518,B518" "0,1"
|
|
bitfld.long 0x00 5. "B517,B517" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B516,B516" "0,1"
|
|
bitfld.long 0x00 3. "B515,B515" "0,1"
|
|
bitfld.long 0x00 2. "B514,B514" "0,1"
|
|
bitfld.long 0x00 1. "B513,B513" "0,1"
|
|
bitfld.long 0x00 0. "B512,B512" "0,1"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "MPCBB1_VCTR17,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B575,B575" "0,1"
|
|
bitfld.long 0x00 30. "B574,B574" "0,1"
|
|
bitfld.long 0x00 29. "B573,B573" "0,1"
|
|
bitfld.long 0x00 28. "B572,B572" "0,1"
|
|
bitfld.long 0x00 27. "B571,B571" "0,1"
|
|
bitfld.long 0x00 26. "B570,B570" "0,1"
|
|
bitfld.long 0x00 25. "B569,B569" "0,1"
|
|
bitfld.long 0x00 24. "B568,B568" "0,1"
|
|
bitfld.long 0x00 23. "B567,B567" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B566,B566" "0,1"
|
|
bitfld.long 0x00 21. "B565,B565" "0,1"
|
|
bitfld.long 0x00 20. "B564,B564" "0,1"
|
|
bitfld.long 0x00 19. "B563,B563" "0,1"
|
|
bitfld.long 0x00 18. "B562,B562" "0,1"
|
|
bitfld.long 0x00 17. "B561,B561" "0,1"
|
|
bitfld.long 0x00 16. "B560,B560" "0,1"
|
|
bitfld.long 0x00 15. "B559,B559" "0,1"
|
|
bitfld.long 0x00 14. "B558,B558" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B557,B557" "0,1"
|
|
bitfld.long 0x00 12. "B556,B556" "0,1"
|
|
bitfld.long 0x00 11. "B555,B555" "0,1"
|
|
bitfld.long 0x00 10. "B554,B554" "0,1"
|
|
bitfld.long 0x00 9. "B553,B553" "0,1"
|
|
bitfld.long 0x00 8. "B552,B552" "0,1"
|
|
bitfld.long 0x00 7. "B551,B551" "0,1"
|
|
bitfld.long 0x00 6. "B550,B550" "0,1"
|
|
bitfld.long 0x00 5. "B549,B549" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B548,B548" "0,1"
|
|
bitfld.long 0x00 3. "B547,B547" "0,1"
|
|
bitfld.long 0x00 2. "B546,B546" "0,1"
|
|
bitfld.long 0x00 1. "B545,B545" "0,1"
|
|
bitfld.long 0x00 0. "B544,B544" "0,1"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "MPCBB1_VCTR18,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B607,B607" "0,1"
|
|
bitfld.long 0x00 30. "B606,B606" "0,1"
|
|
bitfld.long 0x00 29. "B605,B605" "0,1"
|
|
bitfld.long 0x00 28. "B604,B604" "0,1"
|
|
bitfld.long 0x00 27. "B603,B603" "0,1"
|
|
bitfld.long 0x00 26. "B602,B602" "0,1"
|
|
bitfld.long 0x00 25. "B601,B601" "0,1"
|
|
bitfld.long 0x00 24. "B600,B600" "0,1"
|
|
bitfld.long 0x00 23. "B599,B599" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B598,B598" "0,1"
|
|
bitfld.long 0x00 21. "B597,B597" "0,1"
|
|
bitfld.long 0x00 20. "B596,B596" "0,1"
|
|
bitfld.long 0x00 19. "B595,B595" "0,1"
|
|
bitfld.long 0x00 18. "B594,B594" "0,1"
|
|
bitfld.long 0x00 17. "B593,B593" "0,1"
|
|
bitfld.long 0x00 16. "B592,B592" "0,1"
|
|
bitfld.long 0x00 15. "B591,B591" "0,1"
|
|
bitfld.long 0x00 14. "B590,B590" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B589,B589" "0,1"
|
|
bitfld.long 0x00 12. "B588,B588" "0,1"
|
|
bitfld.long 0x00 11. "B587,B587" "0,1"
|
|
bitfld.long 0x00 10. "B586,B586" "0,1"
|
|
bitfld.long 0x00 9. "B585,B585" "0,1"
|
|
bitfld.long 0x00 8. "B584,B584" "0,1"
|
|
bitfld.long 0x00 7. "B583,B583" "0,1"
|
|
bitfld.long 0x00 6. "B582,B582" "0,1"
|
|
bitfld.long 0x00 5. "B581,B581" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B580,B580" "0,1"
|
|
bitfld.long 0x00 3. "B579,B579" "0,1"
|
|
bitfld.long 0x00 2. "B578,B578" "0,1"
|
|
bitfld.long 0x00 1. "B577,B577" "0,1"
|
|
bitfld.long 0x00 0. "B576,B576" "0,1"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR19,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B639,B639" "0,1"
|
|
bitfld.long 0x00 30. "B638,B638" "0,1"
|
|
bitfld.long 0x00 29. "B637,B637" "0,1"
|
|
bitfld.long 0x00 28. "B636,B636" "0,1"
|
|
bitfld.long 0x00 27. "B635,B635" "0,1"
|
|
bitfld.long 0x00 26. "B634,B634" "0,1"
|
|
bitfld.long 0x00 25. "B633,B633" "0,1"
|
|
bitfld.long 0x00 24. "B632,B632" "0,1"
|
|
bitfld.long 0x00 23. "B631,B631" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B630,B630" "0,1"
|
|
bitfld.long 0x00 21. "B629,B629" "0,1"
|
|
bitfld.long 0x00 20. "B628,B628" "0,1"
|
|
bitfld.long 0x00 19. "B627,B627" "0,1"
|
|
bitfld.long 0x00 18. "B626,B626" "0,1"
|
|
bitfld.long 0x00 17. "B625,B625" "0,1"
|
|
bitfld.long 0x00 16. "B624,B624" "0,1"
|
|
bitfld.long 0x00 15. "B623,B623" "0,1"
|
|
bitfld.long 0x00 14. "B622,B622" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B621,B621" "0,1"
|
|
bitfld.long 0x00 12. "B620,B620" "0,1"
|
|
bitfld.long 0x00 11. "B619,B619" "0,1"
|
|
bitfld.long 0x00 10. "B618,B618" "0,1"
|
|
bitfld.long 0x00 9. "B617,B617" "0,1"
|
|
bitfld.long 0x00 8. "B616,B616" "0,1"
|
|
bitfld.long 0x00 7. "B615,B615" "0,1"
|
|
bitfld.long 0x00 6. "B614,B614" "0,1"
|
|
bitfld.long 0x00 5. "B613,B613" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B612,B612" "0,1"
|
|
bitfld.long 0x00 3. "B611,B611" "0,1"
|
|
bitfld.long 0x00 2. "B610,B610" "0,1"
|
|
bitfld.long 0x00 1. "B609,B609" "0,1"
|
|
bitfld.long 0x00 0. "B608,B608" "0,1"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "MPCBB1_VCTR20,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B671,B671" "0,1"
|
|
bitfld.long 0x00 30. "B670,B670" "0,1"
|
|
bitfld.long 0x00 29. "B669,B669" "0,1"
|
|
bitfld.long 0x00 28. "B668,B668" "0,1"
|
|
bitfld.long 0x00 27. "B667,B667" "0,1"
|
|
bitfld.long 0x00 26. "B666,B666" "0,1"
|
|
bitfld.long 0x00 25. "B665,B665" "0,1"
|
|
bitfld.long 0x00 24. "B664,B664" "0,1"
|
|
bitfld.long 0x00 23. "B663,B663" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B662,B662" "0,1"
|
|
bitfld.long 0x00 21. "B661,B661" "0,1"
|
|
bitfld.long 0x00 20. "B660,B660" "0,1"
|
|
bitfld.long 0x00 19. "B659,B659" "0,1"
|
|
bitfld.long 0x00 18. "B658,B658" "0,1"
|
|
bitfld.long 0x00 17. "B657,B657" "0,1"
|
|
bitfld.long 0x00 16. "B656,B656" "0,1"
|
|
bitfld.long 0x00 15. "B655,B655" "0,1"
|
|
bitfld.long 0x00 14. "B654,B654" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B653,B653" "0,1"
|
|
bitfld.long 0x00 12. "B652,B652" "0,1"
|
|
bitfld.long 0x00 11. "B651,B651" "0,1"
|
|
bitfld.long 0x00 10. "B650,B650" "0,1"
|
|
bitfld.long 0x00 9. "B649,B649" "0,1"
|
|
bitfld.long 0x00 8. "B648,B648" "0,1"
|
|
bitfld.long 0x00 7. "B647,B647" "0,1"
|
|
bitfld.long 0x00 6. "B646,B646" "0,1"
|
|
bitfld.long 0x00 5. "B645,B645" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B644,B644" "0,1"
|
|
bitfld.long 0x00 3. "B643,B643" "0,1"
|
|
bitfld.long 0x00 2. "B642,B642" "0,1"
|
|
bitfld.long 0x00 1. "B641,B641" "0,1"
|
|
bitfld.long 0x00 0. "B640,B640" "0,1"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "MPCBB1_VCTR21,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B703,B703" "0,1"
|
|
bitfld.long 0x00 30. "B702,B702" "0,1"
|
|
bitfld.long 0x00 29. "B701,B701" "0,1"
|
|
bitfld.long 0x00 28. "B700,B700" "0,1"
|
|
bitfld.long 0x00 27. "B699,B699" "0,1"
|
|
bitfld.long 0x00 26. "B698,B698" "0,1"
|
|
bitfld.long 0x00 25. "B697,B697" "0,1"
|
|
bitfld.long 0x00 24. "B696,B696" "0,1"
|
|
bitfld.long 0x00 23. "B695,B695" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B694,B694" "0,1"
|
|
bitfld.long 0x00 21. "B693,B693" "0,1"
|
|
bitfld.long 0x00 20. "B692,B692" "0,1"
|
|
bitfld.long 0x00 19. "B691,B691" "0,1"
|
|
bitfld.long 0x00 18. "B690,B690" "0,1"
|
|
bitfld.long 0x00 17. "B689,B689" "0,1"
|
|
bitfld.long 0x00 16. "B688,B688" "0,1"
|
|
bitfld.long 0x00 15. "B687,B687" "0,1"
|
|
bitfld.long 0x00 14. "B686,B686" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B685,B685" "0,1"
|
|
bitfld.long 0x00 12. "B684,B684" "0,1"
|
|
bitfld.long 0x00 11. "B683,B683" "0,1"
|
|
bitfld.long 0x00 10. "B682,B682" "0,1"
|
|
bitfld.long 0x00 9. "B681,B681" "0,1"
|
|
bitfld.long 0x00 8. "B680,B680" "0,1"
|
|
bitfld.long 0x00 7. "B679,B679" "0,1"
|
|
bitfld.long 0x00 6. "B678,B678" "0,1"
|
|
bitfld.long 0x00 5. "B677,B677" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B676,B676" "0,1"
|
|
bitfld.long 0x00 3. "B675,B675" "0,1"
|
|
bitfld.long 0x00 2. "B674,B674" "0,1"
|
|
bitfld.long 0x00 1. "B673,B673" "0,1"
|
|
bitfld.long 0x00 0. "B672,B672" "0,1"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "MPCBB1_VCTR22,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B735,B735" "0,1"
|
|
bitfld.long 0x00 30. "B734,B734" "0,1"
|
|
bitfld.long 0x00 29. "B733,B733" "0,1"
|
|
bitfld.long 0x00 28. "B732,B732" "0,1"
|
|
bitfld.long 0x00 27. "B731,B731" "0,1"
|
|
bitfld.long 0x00 26. "B730,B730" "0,1"
|
|
bitfld.long 0x00 25. "B729,B729" "0,1"
|
|
bitfld.long 0x00 24. "B728,B728" "0,1"
|
|
bitfld.long 0x00 23. "B727,B727" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B726,B726" "0,1"
|
|
bitfld.long 0x00 21. "B725,B725" "0,1"
|
|
bitfld.long 0x00 20. "B724,B724" "0,1"
|
|
bitfld.long 0x00 19. "B723,B723" "0,1"
|
|
bitfld.long 0x00 18. "B722,B722" "0,1"
|
|
bitfld.long 0x00 17. "B721,B721" "0,1"
|
|
bitfld.long 0x00 16. "B720,B720" "0,1"
|
|
bitfld.long 0x00 15. "B719,B719" "0,1"
|
|
bitfld.long 0x00 14. "B718,B718" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B717,B717" "0,1"
|
|
bitfld.long 0x00 12. "B716,B716" "0,1"
|
|
bitfld.long 0x00 11. "B715,B715" "0,1"
|
|
bitfld.long 0x00 10. "B714,B714" "0,1"
|
|
bitfld.long 0x00 9. "B713,B713" "0,1"
|
|
bitfld.long 0x00 8. "B712,B712" "0,1"
|
|
bitfld.long 0x00 7. "B711,B711" "0,1"
|
|
bitfld.long 0x00 6. "B710,B710" "0,1"
|
|
bitfld.long 0x00 5. "B709,B709" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B708,B708" "0,1"
|
|
bitfld.long 0x00 3. "B707,B707" "0,1"
|
|
bitfld.long 0x00 2. "B706,B706" "0,1"
|
|
bitfld.long 0x00 1. "B705,B705" "0,1"
|
|
bitfld.long 0x00 0. "B704,B704" "0,1"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR23,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B767,B767" "0,1"
|
|
bitfld.long 0x00 30. "B766,B766" "0,1"
|
|
bitfld.long 0x00 29. "B765,B765" "0,1"
|
|
bitfld.long 0x00 28. "B764,B764" "0,1"
|
|
bitfld.long 0x00 27. "B763,B763" "0,1"
|
|
bitfld.long 0x00 26. "B762,B762" "0,1"
|
|
bitfld.long 0x00 25. "B761,B761" "0,1"
|
|
bitfld.long 0x00 24. "B760,B760" "0,1"
|
|
bitfld.long 0x00 23. "B759,B759" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B758,B758" "0,1"
|
|
bitfld.long 0x00 21. "B757,B757" "0,1"
|
|
bitfld.long 0x00 20. "B756,B756" "0,1"
|
|
bitfld.long 0x00 19. "B755,B755" "0,1"
|
|
bitfld.long 0x00 18. "B754,B754" "0,1"
|
|
bitfld.long 0x00 17. "B753,B753" "0,1"
|
|
bitfld.long 0x00 16. "B752,B752" "0,1"
|
|
bitfld.long 0x00 15. "B751,B751" "0,1"
|
|
bitfld.long 0x00 14. "B750,B750" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B749,B749" "0,1"
|
|
bitfld.long 0x00 12. "B748,B748" "0,1"
|
|
bitfld.long 0x00 11. "B747,B747" "0,1"
|
|
bitfld.long 0x00 10. "B746,B746" "0,1"
|
|
bitfld.long 0x00 9. "B745,B745" "0,1"
|
|
bitfld.long 0x00 8. "B744,B744" "0,1"
|
|
bitfld.long 0x00 7. "B743,B743" "0,1"
|
|
bitfld.long 0x00 6. "B742,B742" "0,1"
|
|
bitfld.long 0x00 5. "B741,B741" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B740,B740" "0,1"
|
|
bitfld.long 0x00 3. "B739,B739" "0,1"
|
|
bitfld.long 0x00 2. "B738,B738" "0,1"
|
|
bitfld.long 0x00 1. "B737,B737" "0,1"
|
|
bitfld.long 0x00 0. "B736,B736" "0,1"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "MPCBB1_VCTR24,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B799,B799" "0,1"
|
|
bitfld.long 0x00 30. "B798,B798" "0,1"
|
|
bitfld.long 0x00 29. "B797,B797" "0,1"
|
|
bitfld.long 0x00 28. "B796,B796" "0,1"
|
|
bitfld.long 0x00 27. "B795,B795" "0,1"
|
|
bitfld.long 0x00 26. "B794,B794" "0,1"
|
|
bitfld.long 0x00 25. "B793,B793" "0,1"
|
|
bitfld.long 0x00 24. "B792,B792" "0,1"
|
|
bitfld.long 0x00 23. "B791,B791" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B790,B790" "0,1"
|
|
bitfld.long 0x00 21. "B789,B789" "0,1"
|
|
bitfld.long 0x00 20. "B788,B788" "0,1"
|
|
bitfld.long 0x00 19. "B787,B787" "0,1"
|
|
bitfld.long 0x00 18. "B786,B786" "0,1"
|
|
bitfld.long 0x00 17. "B785,B785" "0,1"
|
|
bitfld.long 0x00 16. "B784,B784" "0,1"
|
|
bitfld.long 0x00 15. "B783,B783" "0,1"
|
|
bitfld.long 0x00 14. "B782,B782" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B781,B781" "0,1"
|
|
bitfld.long 0x00 12. "B780,B780" "0,1"
|
|
bitfld.long 0x00 11. "B779,B779" "0,1"
|
|
bitfld.long 0x00 10. "B778,B778" "0,1"
|
|
bitfld.long 0x00 9. "B777,B777" "0,1"
|
|
bitfld.long 0x00 8. "B776,B776" "0,1"
|
|
bitfld.long 0x00 7. "B775,B775" "0,1"
|
|
bitfld.long 0x00 6. "B774,B774" "0,1"
|
|
bitfld.long 0x00 5. "B773,B773" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B772,B772" "0,1"
|
|
bitfld.long 0x00 3. "B771,B771" "0,1"
|
|
bitfld.long 0x00 2. "B770,B770" "0,1"
|
|
bitfld.long 0x00 1. "B769,B769" "0,1"
|
|
bitfld.long 0x00 0. "B768,B768" "0,1"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "MPCBB1_VCTR25,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B831,B831" "0,1"
|
|
bitfld.long 0x00 30. "B830,B830" "0,1"
|
|
bitfld.long 0x00 29. "B829,B829" "0,1"
|
|
bitfld.long 0x00 28. "B828,B828" "0,1"
|
|
bitfld.long 0x00 27. "B827,B827" "0,1"
|
|
bitfld.long 0x00 26. "B826,B826" "0,1"
|
|
bitfld.long 0x00 25. "B825,B825" "0,1"
|
|
bitfld.long 0x00 24. "B824,B824" "0,1"
|
|
bitfld.long 0x00 23. "B823,B823" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B822,B822" "0,1"
|
|
bitfld.long 0x00 21. "B821,B821" "0,1"
|
|
bitfld.long 0x00 20. "B820,B820" "0,1"
|
|
bitfld.long 0x00 19. "B819,B819" "0,1"
|
|
bitfld.long 0x00 18. "B818,B818" "0,1"
|
|
bitfld.long 0x00 17. "B817,B817" "0,1"
|
|
bitfld.long 0x00 16. "B816,B816" "0,1"
|
|
bitfld.long 0x00 15. "B815,B815" "0,1"
|
|
bitfld.long 0x00 14. "B814,B814" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B813,B813" "0,1"
|
|
bitfld.long 0x00 12. "B812,B812" "0,1"
|
|
bitfld.long 0x00 11. "B811,B811" "0,1"
|
|
bitfld.long 0x00 10. "B810,B810" "0,1"
|
|
bitfld.long 0x00 9. "B809,B809" "0,1"
|
|
bitfld.long 0x00 8. "B808,B808" "0,1"
|
|
bitfld.long 0x00 7. "B807,B807" "0,1"
|
|
bitfld.long 0x00 6. "B806,B806" "0,1"
|
|
bitfld.long 0x00 5. "B805,B805" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B804,B804" "0,1"
|
|
bitfld.long 0x00 3. "B803,B803" "0,1"
|
|
bitfld.long 0x00 2. "B802,B802" "0,1"
|
|
bitfld.long 0x00 1. "B801,B801" "0,1"
|
|
bitfld.long 0x00 0. "B800,B800" "0,1"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "MPCBB1_VCTR26,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B863,B863" "0,1"
|
|
bitfld.long 0x00 30. "B862,B862" "0,1"
|
|
bitfld.long 0x00 29. "B861,B861" "0,1"
|
|
bitfld.long 0x00 28. "B860,B860" "0,1"
|
|
bitfld.long 0x00 27. "B859,B859" "0,1"
|
|
bitfld.long 0x00 26. "B858,B858" "0,1"
|
|
bitfld.long 0x00 25. "B857,B857" "0,1"
|
|
bitfld.long 0x00 24. "B856,B856" "0,1"
|
|
bitfld.long 0x00 23. "B855,B855" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B854,B854" "0,1"
|
|
bitfld.long 0x00 21. "B853,B853" "0,1"
|
|
bitfld.long 0x00 20. "B852,B852" "0,1"
|
|
bitfld.long 0x00 19. "B851,B851" "0,1"
|
|
bitfld.long 0x00 18. "B850,B850" "0,1"
|
|
bitfld.long 0x00 17. "B849,B849" "0,1"
|
|
bitfld.long 0x00 16. "B848,B848" "0,1"
|
|
bitfld.long 0x00 15. "B847,B847" "0,1"
|
|
bitfld.long 0x00 14. "B846,B846" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B845,B845" "0,1"
|
|
bitfld.long 0x00 12. "B844,B844" "0,1"
|
|
bitfld.long 0x00 11. "B843,B843" "0,1"
|
|
bitfld.long 0x00 10. "B842,B842" "0,1"
|
|
bitfld.long 0x00 9. "B841,B841" "0,1"
|
|
bitfld.long 0x00 8. "B840,B840" "0,1"
|
|
bitfld.long 0x00 7. "B839,B839" "0,1"
|
|
bitfld.long 0x00 6. "B838,B838" "0,1"
|
|
bitfld.long 0x00 5. "B837,B837" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B836,B836" "0,1"
|
|
bitfld.long 0x00 3. "B835,B835" "0,1"
|
|
bitfld.long 0x00 2. "B834,B834" "0,1"
|
|
bitfld.long 0x00 1. "B833,B833" "0,1"
|
|
bitfld.long 0x00 0. "B832,B832" "0,1"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR27,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B895,B895" "0,1"
|
|
bitfld.long 0x00 30. "B894,B894" "0,1"
|
|
bitfld.long 0x00 29. "B893,B893" "0,1"
|
|
bitfld.long 0x00 28. "B892,B892" "0,1"
|
|
bitfld.long 0x00 27. "B891,B891" "0,1"
|
|
bitfld.long 0x00 26. "B890,B890" "0,1"
|
|
bitfld.long 0x00 25. "B889,B889" "0,1"
|
|
bitfld.long 0x00 24. "B888,B888" "0,1"
|
|
bitfld.long 0x00 23. "B887,B887" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B886,B886" "0,1"
|
|
bitfld.long 0x00 21. "B885,B885" "0,1"
|
|
bitfld.long 0x00 20. "B884,B884" "0,1"
|
|
bitfld.long 0x00 19. "B883,B883" "0,1"
|
|
bitfld.long 0x00 18. "B882,B882" "0,1"
|
|
bitfld.long 0x00 17. "B881,B881" "0,1"
|
|
bitfld.long 0x00 16. "B880,B880" "0,1"
|
|
bitfld.long 0x00 15. "B879,B879" "0,1"
|
|
bitfld.long 0x00 14. "B878,B878" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B877,B877" "0,1"
|
|
bitfld.long 0x00 12. "B876,B876" "0,1"
|
|
bitfld.long 0x00 11. "B875,B875" "0,1"
|
|
bitfld.long 0x00 10. "B874,B874" "0,1"
|
|
bitfld.long 0x00 9. "B873,B873" "0,1"
|
|
bitfld.long 0x00 8. "B872,B872" "0,1"
|
|
bitfld.long 0x00 7. "B871,B871" "0,1"
|
|
bitfld.long 0x00 6. "B870,B870" "0,1"
|
|
bitfld.long 0x00 5. "B869,B869" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B868,B868" "0,1"
|
|
bitfld.long 0x00 3. "B867,B867" "0,1"
|
|
bitfld.long 0x00 2. "B866,B866" "0,1"
|
|
bitfld.long 0x00 1. "B865,B865" "0,1"
|
|
bitfld.long 0x00 0. "B864,B864" "0,1"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "MPCBB1_VCTR28,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B927,B927" "0,1"
|
|
bitfld.long 0x00 30. "B926,B926" "0,1"
|
|
bitfld.long 0x00 29. "B925,B925" "0,1"
|
|
bitfld.long 0x00 28. "B924,B924" "0,1"
|
|
bitfld.long 0x00 27. "B923,B923" "0,1"
|
|
bitfld.long 0x00 26. "B922,B922" "0,1"
|
|
bitfld.long 0x00 25. "B921,B921" "0,1"
|
|
bitfld.long 0x00 24. "B920,B920" "0,1"
|
|
bitfld.long 0x00 23. "B919,B919" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B918,B918" "0,1"
|
|
bitfld.long 0x00 21. "B917,B917" "0,1"
|
|
bitfld.long 0x00 20. "B916,B916" "0,1"
|
|
bitfld.long 0x00 19. "B915,B915" "0,1"
|
|
bitfld.long 0x00 18. "B914,B914" "0,1"
|
|
bitfld.long 0x00 17. "B913,B913" "0,1"
|
|
bitfld.long 0x00 16. "B912,B912" "0,1"
|
|
bitfld.long 0x00 15. "B911,B911" "0,1"
|
|
bitfld.long 0x00 14. "B910,B910" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B909,B909" "0,1"
|
|
bitfld.long 0x00 12. "B908,B908" "0,1"
|
|
bitfld.long 0x00 11. "B907,B907" "0,1"
|
|
bitfld.long 0x00 10. "B906,B906" "0,1"
|
|
bitfld.long 0x00 9. "B905,B905" "0,1"
|
|
bitfld.long 0x00 8. "B904,B904" "0,1"
|
|
bitfld.long 0x00 7. "B903,B903" "0,1"
|
|
bitfld.long 0x00 6. "B902,B902" "0,1"
|
|
bitfld.long 0x00 5. "B901,B901" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B900,B900" "0,1"
|
|
bitfld.long 0x00 3. "B899,B899" "0,1"
|
|
bitfld.long 0x00 2. "B898,B898" "0,1"
|
|
bitfld.long 0x00 1. "B897,B897" "0,1"
|
|
bitfld.long 0x00 0. "B896,B896" "0,1"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "MPCBB1_VCTR29,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B959,B959" "0,1"
|
|
bitfld.long 0x00 30. "B958,B958" "0,1"
|
|
bitfld.long 0x00 29. "B957,B957" "0,1"
|
|
bitfld.long 0x00 28. "B956,B956" "0,1"
|
|
bitfld.long 0x00 27. "B955,B955" "0,1"
|
|
bitfld.long 0x00 26. "B954,B954" "0,1"
|
|
bitfld.long 0x00 25. "B953,B953" "0,1"
|
|
bitfld.long 0x00 24. "B952,B952" "0,1"
|
|
bitfld.long 0x00 23. "B951,B951" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B950,B950" "0,1"
|
|
bitfld.long 0x00 21. "B949,B949" "0,1"
|
|
bitfld.long 0x00 20. "B948,B948" "0,1"
|
|
bitfld.long 0x00 19. "B947,B947" "0,1"
|
|
bitfld.long 0x00 18. "B946,B946" "0,1"
|
|
bitfld.long 0x00 17. "B945,B945" "0,1"
|
|
bitfld.long 0x00 16. "B944,B944" "0,1"
|
|
bitfld.long 0x00 15. "B943,B943" "0,1"
|
|
bitfld.long 0x00 14. "B942,B942" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B941,B941" "0,1"
|
|
bitfld.long 0x00 12. "B940,B940" "0,1"
|
|
bitfld.long 0x00 11. "B939,B939" "0,1"
|
|
bitfld.long 0x00 10. "B938,B938" "0,1"
|
|
bitfld.long 0x00 9. "B937,B937" "0,1"
|
|
bitfld.long 0x00 8. "B936,B936" "0,1"
|
|
bitfld.long 0x00 7. "B935,B935" "0,1"
|
|
bitfld.long 0x00 6. "B934,B934" "0,1"
|
|
bitfld.long 0x00 5. "B933,B933" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B932,B932" "0,1"
|
|
bitfld.long 0x00 3. "B931,B931" "0,1"
|
|
bitfld.long 0x00 2. "B930,B930" "0,1"
|
|
bitfld.long 0x00 1. "B929,B929" "0,1"
|
|
bitfld.long 0x00 0. "B928,B928" "0,1"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "MPCBB1_VCTR30,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B991,B991" "0,1"
|
|
bitfld.long 0x00 30. "B990,B990" "0,1"
|
|
bitfld.long 0x00 29. "B989,B989" "0,1"
|
|
bitfld.long 0x00 28. "B988,B988" "0,1"
|
|
bitfld.long 0x00 27. "B987,B987" "0,1"
|
|
bitfld.long 0x00 26. "B986,B986" "0,1"
|
|
bitfld.long 0x00 25. "B985,B985" "0,1"
|
|
bitfld.long 0x00 24. "B984,B984" "0,1"
|
|
bitfld.long 0x00 23. "B983,B983" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B982,B982" "0,1"
|
|
bitfld.long 0x00 21. "B981,B981" "0,1"
|
|
bitfld.long 0x00 20. "B980,B980" "0,1"
|
|
bitfld.long 0x00 19. "B979,B979" "0,1"
|
|
bitfld.long 0x00 18. "B978,B978" "0,1"
|
|
bitfld.long 0x00 17. "B977,B977" "0,1"
|
|
bitfld.long 0x00 16. "B976,B976" "0,1"
|
|
bitfld.long 0x00 15. "B975,B975" "0,1"
|
|
bitfld.long 0x00 14. "B974,B974" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B973,B973" "0,1"
|
|
bitfld.long 0x00 12. "B972,B972" "0,1"
|
|
bitfld.long 0x00 11. "B971,B971" "0,1"
|
|
bitfld.long 0x00 10. "B970,B970" "0,1"
|
|
bitfld.long 0x00 9. "B969,B969" "0,1"
|
|
bitfld.long 0x00 8. "B968,B968" "0,1"
|
|
bitfld.long 0x00 7. "B967,B967" "0,1"
|
|
bitfld.long 0x00 6. "B966,B966" "0,1"
|
|
bitfld.long 0x00 5. "B965,B965" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B964,B964" "0,1"
|
|
bitfld.long 0x00 3. "B963,B963" "0,1"
|
|
bitfld.long 0x00 2. "B962,B962" "0,1"
|
|
bitfld.long 0x00 1. "B961,B961" "0,1"
|
|
bitfld.long 0x00 0. "B960,B960" "0,1"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR31,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1023,B1023" "0,1"
|
|
bitfld.long 0x00 30. "B1022,B1022" "0,1"
|
|
bitfld.long 0x00 29. "B1021,B1021" "0,1"
|
|
bitfld.long 0x00 28. "B1020,B1020" "0,1"
|
|
bitfld.long 0x00 27. "B1019,B1019" "0,1"
|
|
bitfld.long 0x00 26. "B1018,B1018" "0,1"
|
|
bitfld.long 0x00 25. "B1017,B1017" "0,1"
|
|
bitfld.long 0x00 24. "B1016,B1016" "0,1"
|
|
bitfld.long 0x00 23. "B1015,B1015" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1014,B1014" "0,1"
|
|
bitfld.long 0x00 21. "B1013,B1013" "0,1"
|
|
bitfld.long 0x00 20. "B1012,B1012" "0,1"
|
|
bitfld.long 0x00 19. "B1011,B1011" "0,1"
|
|
bitfld.long 0x00 18. "B1010,B1010" "0,1"
|
|
bitfld.long 0x00 17. "B1009,B1009" "0,1"
|
|
bitfld.long 0x00 16. "B1008,B1008" "0,1"
|
|
bitfld.long 0x00 15. "B1007,B1007" "0,1"
|
|
bitfld.long 0x00 14. "B1006,B1006" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1005,B1005" "0,1"
|
|
bitfld.long 0x00 12. "B1004,B1004" "0,1"
|
|
bitfld.long 0x00 11. "B1003,B1003" "0,1"
|
|
bitfld.long 0x00 10. "B1002,B1002" "0,1"
|
|
bitfld.long 0x00 9. "B1001,B1001" "0,1"
|
|
bitfld.long 0x00 8. "B1000,B1000" "0,1"
|
|
bitfld.long 0x00 7. "B999,B999" "0,1"
|
|
bitfld.long 0x00 6. "B998,B998" "0,1"
|
|
bitfld.long 0x00 5. "B997,B997" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B996,B996" "0,1"
|
|
bitfld.long 0x00 3. "B995,B995" "0,1"
|
|
bitfld.long 0x00 2. "B994,B994" "0,1"
|
|
bitfld.long 0x00 1. "B993,B993" "0,1"
|
|
bitfld.long 0x00 0. "B992,B992" "0,1"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "MPCBB1_VCTR32,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1055,B1055" "0,1"
|
|
bitfld.long 0x00 30. "B1054,B1054" "0,1"
|
|
bitfld.long 0x00 29. "B1053,B1053" "0,1"
|
|
bitfld.long 0x00 28. "B1052,B1052" "0,1"
|
|
bitfld.long 0x00 27. "B1051,B1051" "0,1"
|
|
bitfld.long 0x00 26. "B1050,B1050" "0,1"
|
|
bitfld.long 0x00 25. "B1049,B1049" "0,1"
|
|
bitfld.long 0x00 24. "B1048,B1048" "0,1"
|
|
bitfld.long 0x00 23. "B1047,B1047" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1046,B1046" "0,1"
|
|
bitfld.long 0x00 21. "B1045,B1045" "0,1"
|
|
bitfld.long 0x00 20. "B1044,B1044" "0,1"
|
|
bitfld.long 0x00 19. "B1043,B1043" "0,1"
|
|
bitfld.long 0x00 18. "B1042,B1042" "0,1"
|
|
bitfld.long 0x00 17. "B1041,B1041" "0,1"
|
|
bitfld.long 0x00 16. "B1040,B1040" "0,1"
|
|
bitfld.long 0x00 15. "B1039,B1039" "0,1"
|
|
bitfld.long 0x00 14. "B1038,B1038" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1037,B1037" "0,1"
|
|
bitfld.long 0x00 12. "B1036,B1036" "0,1"
|
|
bitfld.long 0x00 11. "B1035,B1035" "0,1"
|
|
bitfld.long 0x00 10. "B1034,B1034" "0,1"
|
|
bitfld.long 0x00 9. "B1033,B1033" "0,1"
|
|
bitfld.long 0x00 8. "B1032,B1032" "0,1"
|
|
bitfld.long 0x00 7. "B1031,B1031" "0,1"
|
|
bitfld.long 0x00 6. "B1030,B1030" "0,1"
|
|
bitfld.long 0x00 5. "B1029,B1029" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1028,B1028" "0,1"
|
|
bitfld.long 0x00 3. "B1027,B1027" "0,1"
|
|
bitfld.long 0x00 2. "B1026,B1026" "0,1"
|
|
bitfld.long 0x00 1. "B1025,B1025" "0,1"
|
|
bitfld.long 0x00 0. "B1024,B1024" "0,1"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "MPCBB1_VCTR33,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1087,B1087" "0,1"
|
|
bitfld.long 0x00 30. "B1086,B1086" "0,1"
|
|
bitfld.long 0x00 29. "B1085,B1085" "0,1"
|
|
bitfld.long 0x00 28. "B1084,B1084" "0,1"
|
|
bitfld.long 0x00 27. "B1083,B1083" "0,1"
|
|
bitfld.long 0x00 26. "B1082,B1082" "0,1"
|
|
bitfld.long 0x00 25. "B1081,B1081" "0,1"
|
|
bitfld.long 0x00 24. "B1080,B1080" "0,1"
|
|
bitfld.long 0x00 23. "B1079,B1079" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1078,B1078" "0,1"
|
|
bitfld.long 0x00 21. "B1077,B1077" "0,1"
|
|
bitfld.long 0x00 20. "B1076,B1076" "0,1"
|
|
bitfld.long 0x00 19. "B1075,B1075" "0,1"
|
|
bitfld.long 0x00 18. "B1074,B1074" "0,1"
|
|
bitfld.long 0x00 17. "B1073,B1073" "0,1"
|
|
bitfld.long 0x00 16. "B1072,B1072" "0,1"
|
|
bitfld.long 0x00 15. "B1071,B1071" "0,1"
|
|
bitfld.long 0x00 14. "B1070,B1070" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1069,B1069" "0,1"
|
|
bitfld.long 0x00 12. "B1068,B1068" "0,1"
|
|
bitfld.long 0x00 11. "B1067,B1067" "0,1"
|
|
bitfld.long 0x00 10. "B1066,B1066" "0,1"
|
|
bitfld.long 0x00 9. "B1065,B1065" "0,1"
|
|
bitfld.long 0x00 8. "B1064,B1064" "0,1"
|
|
bitfld.long 0x00 7. "B1063,B1063" "0,1"
|
|
bitfld.long 0x00 6. "B1062,B1062" "0,1"
|
|
bitfld.long 0x00 5. "B1061,B1061" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1060,B1060" "0,1"
|
|
bitfld.long 0x00 3. "B1059,B1059" "0,1"
|
|
bitfld.long 0x00 2. "B1058,B1058" "0,1"
|
|
bitfld.long 0x00 1. "B1057,B1057" "0,1"
|
|
bitfld.long 0x00 0. "B1056,B1056" "0,1"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "MPCBB1_VCTR34,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1119,B1119" "0,1"
|
|
bitfld.long 0x00 30. "B1118,B1118" "0,1"
|
|
bitfld.long 0x00 29. "B1117,B1117" "0,1"
|
|
bitfld.long 0x00 28. "B1116,B1116" "0,1"
|
|
bitfld.long 0x00 27. "B1115,B1115" "0,1"
|
|
bitfld.long 0x00 26. "B1114,B1114" "0,1"
|
|
bitfld.long 0x00 25. "B1113,B1113" "0,1"
|
|
bitfld.long 0x00 24. "B1112,B1112" "0,1"
|
|
bitfld.long 0x00 23. "B1111,B1111" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1110,B1110" "0,1"
|
|
bitfld.long 0x00 21. "B1109,B1109" "0,1"
|
|
bitfld.long 0x00 20. "B1108,B1108" "0,1"
|
|
bitfld.long 0x00 19. "B1107,B1107" "0,1"
|
|
bitfld.long 0x00 18. "B1106,B1106" "0,1"
|
|
bitfld.long 0x00 17. "B1105,B1105" "0,1"
|
|
bitfld.long 0x00 16. "B1104,B1104" "0,1"
|
|
bitfld.long 0x00 15. "B1103,B1103" "0,1"
|
|
bitfld.long 0x00 14. "B1102,B1102" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1101,B1101" "0,1"
|
|
bitfld.long 0x00 12. "B1100,B1100" "0,1"
|
|
bitfld.long 0x00 11. "B1099,B1099" "0,1"
|
|
bitfld.long 0x00 10. "B1098,B1098" "0,1"
|
|
bitfld.long 0x00 9. "B1097,B1097" "0,1"
|
|
bitfld.long 0x00 8. "B1096,B1096" "0,1"
|
|
bitfld.long 0x00 7. "B1095,B1095" "0,1"
|
|
bitfld.long 0x00 6. "B1094,B1094" "0,1"
|
|
bitfld.long 0x00 5. "B1093,B1093" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1092,B1092" "0,1"
|
|
bitfld.long 0x00 3. "B1091,B1091" "0,1"
|
|
bitfld.long 0x00 2. "B1090,B1090" "0,1"
|
|
bitfld.long 0x00 1. "B1089,B1089" "0,1"
|
|
bitfld.long 0x00 0. "B1088,B1088" "0,1"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR35,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1151,B1151" "0,1"
|
|
bitfld.long 0x00 30. "B1150,B1150" "0,1"
|
|
bitfld.long 0x00 29. "B1149,B1149" "0,1"
|
|
bitfld.long 0x00 28. "B1148,B1148" "0,1"
|
|
bitfld.long 0x00 27. "B1147,B1147" "0,1"
|
|
bitfld.long 0x00 26. "B1146,B1146" "0,1"
|
|
bitfld.long 0x00 25. "B1145,B1145" "0,1"
|
|
bitfld.long 0x00 24. "B1144,B1144" "0,1"
|
|
bitfld.long 0x00 23. "B1143,B1143" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1142,B1142" "0,1"
|
|
bitfld.long 0x00 21. "B1141,B1141" "0,1"
|
|
bitfld.long 0x00 20. "B1140,B1140" "0,1"
|
|
bitfld.long 0x00 19. "B1139,B1139" "0,1"
|
|
bitfld.long 0x00 18. "B1138,B1138" "0,1"
|
|
bitfld.long 0x00 17. "B1137,B1137" "0,1"
|
|
bitfld.long 0x00 16. "B1136,B1136" "0,1"
|
|
bitfld.long 0x00 15. "B1135,B1135" "0,1"
|
|
bitfld.long 0x00 14. "B1134,B1134" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1133,B1133" "0,1"
|
|
bitfld.long 0x00 12. "B1132,B1132" "0,1"
|
|
bitfld.long 0x00 11. "B1131,B1131" "0,1"
|
|
bitfld.long 0x00 10. "B1130,B1130" "0,1"
|
|
bitfld.long 0x00 9. "B1129,B1129" "0,1"
|
|
bitfld.long 0x00 8. "B1128,B1128" "0,1"
|
|
bitfld.long 0x00 7. "B1127,B1127" "0,1"
|
|
bitfld.long 0x00 6. "B1126,B1126" "0,1"
|
|
bitfld.long 0x00 5. "B1125,B1125" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1124,B1124" "0,1"
|
|
bitfld.long 0x00 3. "B1123,B1123" "0,1"
|
|
bitfld.long 0x00 2. "B1122,B1122" "0,1"
|
|
bitfld.long 0x00 1. "B1121,B1121" "0,1"
|
|
bitfld.long 0x00 0. "B1120,B1120" "0,1"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "MPCBB1_VCTR36,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1183,B1183" "0,1"
|
|
bitfld.long 0x00 30. "B1182,B1182" "0,1"
|
|
bitfld.long 0x00 29. "B1181,B1181" "0,1"
|
|
bitfld.long 0x00 28. "B1180,B1180" "0,1"
|
|
bitfld.long 0x00 27. "B1179,B1179" "0,1"
|
|
bitfld.long 0x00 26. "B1178,B1178" "0,1"
|
|
bitfld.long 0x00 25. "B1177,B1177" "0,1"
|
|
bitfld.long 0x00 24. "B1176,B1176" "0,1"
|
|
bitfld.long 0x00 23. "B1175,B1175" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1174,B1174" "0,1"
|
|
bitfld.long 0x00 21. "B1173,B1173" "0,1"
|
|
bitfld.long 0x00 20. "B1172,B1172" "0,1"
|
|
bitfld.long 0x00 19. "B1171,B1171" "0,1"
|
|
bitfld.long 0x00 18. "B1170,B1170" "0,1"
|
|
bitfld.long 0x00 17. "B1169,B1169" "0,1"
|
|
bitfld.long 0x00 16. "B1168,B1168" "0,1"
|
|
bitfld.long 0x00 15. "B1167,B1167" "0,1"
|
|
bitfld.long 0x00 14. "B1166,B1166" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1165,B1165" "0,1"
|
|
bitfld.long 0x00 12. "B1164,B1164" "0,1"
|
|
bitfld.long 0x00 11. "B1163,B1163" "0,1"
|
|
bitfld.long 0x00 10. "B1162,B1162" "0,1"
|
|
bitfld.long 0x00 9. "B1161,B1161" "0,1"
|
|
bitfld.long 0x00 8. "B1160,B1160" "0,1"
|
|
bitfld.long 0x00 7. "B1159,B1159" "0,1"
|
|
bitfld.long 0x00 6. "B1158,B1158" "0,1"
|
|
bitfld.long 0x00 5. "B1157,B1157" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1156,B1156" "0,1"
|
|
bitfld.long 0x00 3. "B1155,B1155" "0,1"
|
|
bitfld.long 0x00 2. "B1154,B1154" "0,1"
|
|
bitfld.long 0x00 1. "B1153,B1153" "0,1"
|
|
bitfld.long 0x00 0. "B1152,B1152" "0,1"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "MPCBB1_VCTR37,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1215,B1215" "0,1"
|
|
bitfld.long 0x00 30. "B1214,B1214" "0,1"
|
|
bitfld.long 0x00 29. "B1213,B1213" "0,1"
|
|
bitfld.long 0x00 28. "B1212,B1212" "0,1"
|
|
bitfld.long 0x00 27. "B1211,B1211" "0,1"
|
|
bitfld.long 0x00 26. "B1210,B1210" "0,1"
|
|
bitfld.long 0x00 25. "B1209,B1209" "0,1"
|
|
bitfld.long 0x00 24. "B1208,B1208" "0,1"
|
|
bitfld.long 0x00 23. "B1207,B1207" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1206,B1206" "0,1"
|
|
bitfld.long 0x00 21. "B1205,B1205" "0,1"
|
|
bitfld.long 0x00 20. "B1204,B1204" "0,1"
|
|
bitfld.long 0x00 19. "B1203,B1203" "0,1"
|
|
bitfld.long 0x00 18. "B1202,B1202" "0,1"
|
|
bitfld.long 0x00 17. "B1201,B1201" "0,1"
|
|
bitfld.long 0x00 16. "B1200,B1200" "0,1"
|
|
bitfld.long 0x00 15. "B1199,B1199" "0,1"
|
|
bitfld.long 0x00 14. "B1198,B1198" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1197,B1197" "0,1"
|
|
bitfld.long 0x00 12. "B1196,B1196" "0,1"
|
|
bitfld.long 0x00 11. "B1195,B1195" "0,1"
|
|
bitfld.long 0x00 10. "B1194,B1194" "0,1"
|
|
bitfld.long 0x00 9. "B1193,B1193" "0,1"
|
|
bitfld.long 0x00 8. "B1192,B1192" "0,1"
|
|
bitfld.long 0x00 7. "B1191,B1191" "0,1"
|
|
bitfld.long 0x00 6. "B1190,B1190" "0,1"
|
|
bitfld.long 0x00 5. "B1189,B1189" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1188,B1188" "0,1"
|
|
bitfld.long 0x00 3. "B1187,B1187" "0,1"
|
|
bitfld.long 0x00 2. "B1186,B1186" "0,1"
|
|
bitfld.long 0x00 1. "B1185,B1185" "0,1"
|
|
bitfld.long 0x00 0. "B1184,B1184" "0,1"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "MPCBB1_VCTR38,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1247,B1247" "0,1"
|
|
bitfld.long 0x00 30. "B1246,B1246" "0,1"
|
|
bitfld.long 0x00 29. "B1245,B1245" "0,1"
|
|
bitfld.long 0x00 28. "B1244,B1244" "0,1"
|
|
bitfld.long 0x00 27. "B1243,B1243" "0,1"
|
|
bitfld.long 0x00 26. "B1242,B1242" "0,1"
|
|
bitfld.long 0x00 25. "B1241,B1241" "0,1"
|
|
bitfld.long 0x00 24. "B1240,B1240" "0,1"
|
|
bitfld.long 0x00 23. "B1239,B1239" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1238,B1238" "0,1"
|
|
bitfld.long 0x00 21. "B1237,B1237" "0,1"
|
|
bitfld.long 0x00 20. "B1236,B1236" "0,1"
|
|
bitfld.long 0x00 19. "B1235,B1235" "0,1"
|
|
bitfld.long 0x00 18. "B1234,B1234" "0,1"
|
|
bitfld.long 0x00 17. "B1233,B1233" "0,1"
|
|
bitfld.long 0x00 16. "B1232,B1232" "0,1"
|
|
bitfld.long 0x00 15. "B1231,B1231" "0,1"
|
|
bitfld.long 0x00 14. "B1230,B1230" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1229,B1229" "0,1"
|
|
bitfld.long 0x00 12. "B1228,B1228" "0,1"
|
|
bitfld.long 0x00 11. "B1227,B1227" "0,1"
|
|
bitfld.long 0x00 10. "B1226,B1226" "0,1"
|
|
bitfld.long 0x00 9. "B1225,B1225" "0,1"
|
|
bitfld.long 0x00 8. "B1224,B1224" "0,1"
|
|
bitfld.long 0x00 7. "B1223,B1223" "0,1"
|
|
bitfld.long 0x00 6. "B1222,B1222" "0,1"
|
|
bitfld.long 0x00 5. "B1221,B1221" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1220,B1220" "0,1"
|
|
bitfld.long 0x00 3. "B1219,B1219" "0,1"
|
|
bitfld.long 0x00 2. "B1218,B1218" "0,1"
|
|
bitfld.long 0x00 1. "B1217,B1217" "0,1"
|
|
bitfld.long 0x00 0. "B1216,B1216" "0,1"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "MPCBB1_VCTR39,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1279,B1279" "0,1"
|
|
bitfld.long 0x00 30. "B1278,B1278" "0,1"
|
|
bitfld.long 0x00 29. "B1277,B1277" "0,1"
|
|
bitfld.long 0x00 28. "B1276,B1276" "0,1"
|
|
bitfld.long 0x00 27. "B1275,B1275" "0,1"
|
|
bitfld.long 0x00 26. "B1274,B1274" "0,1"
|
|
bitfld.long 0x00 25. "B1273,B1273" "0,1"
|
|
bitfld.long 0x00 24. "B1272,B1272" "0,1"
|
|
bitfld.long 0x00 23. "B1271,B1271" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1270,B1270" "0,1"
|
|
bitfld.long 0x00 21. "B1269,B1269" "0,1"
|
|
bitfld.long 0x00 20. "B1268,B1268" "0,1"
|
|
bitfld.long 0x00 19. "B1267,B1267" "0,1"
|
|
bitfld.long 0x00 18. "B1266,B1266" "0,1"
|
|
bitfld.long 0x00 17. "B1265,B1265" "0,1"
|
|
bitfld.long 0x00 16. "B1264,B1264" "0,1"
|
|
bitfld.long 0x00 15. "B1263,B1263" "0,1"
|
|
bitfld.long 0x00 14. "B1262,B1262" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1261,B1261" "0,1"
|
|
bitfld.long 0x00 12. "B1260,B1260" "0,1"
|
|
bitfld.long 0x00 11. "B1259,B1259" "0,1"
|
|
bitfld.long 0x00 10. "B1258,B1258" "0,1"
|
|
bitfld.long 0x00 9. "B1257,B1257" "0,1"
|
|
bitfld.long 0x00 8. "B1256,B1256" "0,1"
|
|
bitfld.long 0x00 7. "B1255,B1255" "0,1"
|
|
bitfld.long 0x00 6. "B1254,B1254" "0,1"
|
|
bitfld.long 0x00 5. "B1253,B1253" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1252,B1252" "0,1"
|
|
bitfld.long 0x00 3. "B1251,B1251" "0,1"
|
|
bitfld.long 0x00 2. "B1250,B1250" "0,1"
|
|
bitfld.long 0x00 1. "B1249,B1249" "0,1"
|
|
bitfld.long 0x00 0. "B1248,B1248" "0,1"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "MPCBB1_VCTR40,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1311,B1311" "0,1"
|
|
bitfld.long 0x00 30. "B1310,B1310" "0,1"
|
|
bitfld.long 0x00 29. "B1309,B1309" "0,1"
|
|
bitfld.long 0x00 28. "B1308,B1308" "0,1"
|
|
bitfld.long 0x00 27. "B1307,B1307" "0,1"
|
|
bitfld.long 0x00 26. "B1306,B1306" "0,1"
|
|
bitfld.long 0x00 25. "B1305,B1305" "0,1"
|
|
bitfld.long 0x00 24. "B1304,B1304" "0,1"
|
|
bitfld.long 0x00 23. "B1303,B1303" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1302,B1302" "0,1"
|
|
bitfld.long 0x00 21. "B1301,B1301" "0,1"
|
|
bitfld.long 0x00 20. "B1300,B1300" "0,1"
|
|
bitfld.long 0x00 19. "B1299,B1299" "0,1"
|
|
bitfld.long 0x00 18. "B1298,B1298" "0,1"
|
|
bitfld.long 0x00 17. "B1297,B1297" "0,1"
|
|
bitfld.long 0x00 16. "B1296,B1296" "0,1"
|
|
bitfld.long 0x00 15. "B1295,B1295" "0,1"
|
|
bitfld.long 0x00 14. "B1294,B1294" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1293,B1293" "0,1"
|
|
bitfld.long 0x00 12. "B1292,B1292" "0,1"
|
|
bitfld.long 0x00 11. "B1291,B1291" "0,1"
|
|
bitfld.long 0x00 10. "B1290,B1290" "0,1"
|
|
bitfld.long 0x00 9. "B1289,B1289" "0,1"
|
|
bitfld.long 0x00 8. "B1288,B1288" "0,1"
|
|
bitfld.long 0x00 7. "B1287,B1287" "0,1"
|
|
bitfld.long 0x00 6. "B1286,B1286" "0,1"
|
|
bitfld.long 0x00 5. "B1285,B1285" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1284,B1284" "0,1"
|
|
bitfld.long 0x00 3. "B1283,B1283" "0,1"
|
|
bitfld.long 0x00 2. "B1282,B1282" "0,1"
|
|
bitfld.long 0x00 1. "B1281,B1281" "0,1"
|
|
bitfld.long 0x00 0. "B1280,B1280" "0,1"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "MPCBB1_VCTR41,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1343,B1343" "0,1"
|
|
bitfld.long 0x00 30. "B1342,B1342" "0,1"
|
|
bitfld.long 0x00 29. "B1341,B1341" "0,1"
|
|
bitfld.long 0x00 28. "B1340,B1340" "0,1"
|
|
bitfld.long 0x00 27. "B1339,B1339" "0,1"
|
|
bitfld.long 0x00 26. "B1338,B1338" "0,1"
|
|
bitfld.long 0x00 25. "B1337,B1337" "0,1"
|
|
bitfld.long 0x00 24. "B1336,B1336" "0,1"
|
|
bitfld.long 0x00 23. "B1335,B1335" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1334,B1334" "0,1"
|
|
bitfld.long 0x00 21. "B1333,B1333" "0,1"
|
|
bitfld.long 0x00 20. "B1332,B1332" "0,1"
|
|
bitfld.long 0x00 19. "B1331,B1331" "0,1"
|
|
bitfld.long 0x00 18. "B1330,B1330" "0,1"
|
|
bitfld.long 0x00 17. "B1329,B1329" "0,1"
|
|
bitfld.long 0x00 16. "B1328,B1328" "0,1"
|
|
bitfld.long 0x00 15. "B1327,B1327" "0,1"
|
|
bitfld.long 0x00 14. "B1326,B1326" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1325,B1325" "0,1"
|
|
bitfld.long 0x00 12. "B1324,B1324" "0,1"
|
|
bitfld.long 0x00 11. "B1323,B1323" "0,1"
|
|
bitfld.long 0x00 10. "B1322,B1322" "0,1"
|
|
bitfld.long 0x00 9. "B1321,B1321" "0,1"
|
|
bitfld.long 0x00 8. "B1320,B1320" "0,1"
|
|
bitfld.long 0x00 7. "B1319,B1319" "0,1"
|
|
bitfld.long 0x00 6. "B1318,B1318" "0,1"
|
|
bitfld.long 0x00 5. "B1317,B1317" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1316,B1316" "0,1"
|
|
bitfld.long 0x00 3. "B1315,B1315" "0,1"
|
|
bitfld.long 0x00 2. "B1314,B1314" "0,1"
|
|
bitfld.long 0x00 1. "B1313,B1313" "0,1"
|
|
bitfld.long 0x00 0. "B1312,B1312" "0,1"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "MPCBB1_VCTR42,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1375,B1375" "0,1"
|
|
bitfld.long 0x00 30. "B1374,B1374" "0,1"
|
|
bitfld.long 0x00 29. "B1373,B1373" "0,1"
|
|
bitfld.long 0x00 28. "B1372,B1372" "0,1"
|
|
bitfld.long 0x00 27. "B1371,B1371" "0,1"
|
|
bitfld.long 0x00 26. "B1370,B1370" "0,1"
|
|
bitfld.long 0x00 25. "B1369,B1369" "0,1"
|
|
bitfld.long 0x00 24. "B1368,B1368" "0,1"
|
|
bitfld.long 0x00 23. "B1367,B1367" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1366,B1366" "0,1"
|
|
bitfld.long 0x00 21. "B1365,B1365" "0,1"
|
|
bitfld.long 0x00 20. "B1364,B1364" "0,1"
|
|
bitfld.long 0x00 19. "B1363,B1363" "0,1"
|
|
bitfld.long 0x00 18. "B1362,B1362" "0,1"
|
|
bitfld.long 0x00 17. "B1361,B1361" "0,1"
|
|
bitfld.long 0x00 16. "B1360,B1360" "0,1"
|
|
bitfld.long 0x00 15. "B1359,B1359" "0,1"
|
|
bitfld.long 0x00 14. "B1358,B1358" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1357,B1357" "0,1"
|
|
bitfld.long 0x00 12. "B1356,B1356" "0,1"
|
|
bitfld.long 0x00 11. "B1355,B1355" "0,1"
|
|
bitfld.long 0x00 10. "B1354,B1354" "0,1"
|
|
bitfld.long 0x00 9. "B1353,B1353" "0,1"
|
|
bitfld.long 0x00 8. "B1352,B1352" "0,1"
|
|
bitfld.long 0x00 7. "B1351,B1351" "0,1"
|
|
bitfld.long 0x00 6. "B1350,B1350" "0,1"
|
|
bitfld.long 0x00 5. "B1349,B1349" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1348,B1348" "0,1"
|
|
bitfld.long 0x00 3. "B1347,B1347" "0,1"
|
|
bitfld.long 0x00 2. "B1346,B1346" "0,1"
|
|
bitfld.long 0x00 1. "B1345,B1345" "0,1"
|
|
bitfld.long 0x00 0. "B1344,B1344" "0,1"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "MPCBB1_VCTR43,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1407,B1407" "0,1"
|
|
bitfld.long 0x00 30. "B1406,B1406" "0,1"
|
|
bitfld.long 0x00 29. "B1405,B1405" "0,1"
|
|
bitfld.long 0x00 28. "B1404,B1404" "0,1"
|
|
bitfld.long 0x00 27. "B1403,B1403" "0,1"
|
|
bitfld.long 0x00 26. "B1402,B1402" "0,1"
|
|
bitfld.long 0x00 25. "B1401,B1401" "0,1"
|
|
bitfld.long 0x00 24. "B1400,B1400" "0,1"
|
|
bitfld.long 0x00 23. "B1399,B1399" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1398,B1398" "0,1"
|
|
bitfld.long 0x00 21. "B1397,B1397" "0,1"
|
|
bitfld.long 0x00 20. "B1396,B1396" "0,1"
|
|
bitfld.long 0x00 19. "B1395,B1395" "0,1"
|
|
bitfld.long 0x00 18. "B1394,B1394" "0,1"
|
|
bitfld.long 0x00 17. "B1393,B1393" "0,1"
|
|
bitfld.long 0x00 16. "B1392,B1392" "0,1"
|
|
bitfld.long 0x00 15. "B1391,B1391" "0,1"
|
|
bitfld.long 0x00 14. "B1390,B1390" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1389,B1389" "0,1"
|
|
bitfld.long 0x00 12. "B1388,B1388" "0,1"
|
|
bitfld.long 0x00 11. "B1387,B1387" "0,1"
|
|
bitfld.long 0x00 10. "B1386,B1386" "0,1"
|
|
bitfld.long 0x00 9. "B1385,B1385" "0,1"
|
|
bitfld.long 0x00 8. "B1384,B1384" "0,1"
|
|
bitfld.long 0x00 7. "B1383,B1383" "0,1"
|
|
bitfld.long 0x00 6. "B1382,B1382" "0,1"
|
|
bitfld.long 0x00 5. "B1381,B1381" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1380,B1380" "0,1"
|
|
bitfld.long 0x00 3. "B1379,B1379" "0,1"
|
|
bitfld.long 0x00 2. "B1378,B1378" "0,1"
|
|
bitfld.long 0x00 1. "B1377,B1377" "0,1"
|
|
bitfld.long 0x00 0. "B1376,B1376" "0,1"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "MPCBB1_VCTR44,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1439,B1439" "0,1"
|
|
bitfld.long 0x00 30. "B1438,B1438" "0,1"
|
|
bitfld.long 0x00 29. "B1437,B1437" "0,1"
|
|
bitfld.long 0x00 28. "B1436,B1436" "0,1"
|
|
bitfld.long 0x00 27. "B1435,B1435" "0,1"
|
|
bitfld.long 0x00 26. "B1434,B1434" "0,1"
|
|
bitfld.long 0x00 25. "B1433,B1433" "0,1"
|
|
bitfld.long 0x00 24. "B1432,B1432" "0,1"
|
|
bitfld.long 0x00 23. "B1431,B1431" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1430,B1430" "0,1"
|
|
bitfld.long 0x00 21. "B1429,B1429" "0,1"
|
|
bitfld.long 0x00 20. "B1428,B1428" "0,1"
|
|
bitfld.long 0x00 19. "B1427,B1427" "0,1"
|
|
bitfld.long 0x00 18. "B1426,B1426" "0,1"
|
|
bitfld.long 0x00 17. "B1425,B1425" "0,1"
|
|
bitfld.long 0x00 16. "B1424,B1424" "0,1"
|
|
bitfld.long 0x00 15. "B1423,B1423" "0,1"
|
|
bitfld.long 0x00 14. "B1422,B1422" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1421,B1421" "0,1"
|
|
bitfld.long 0x00 12. "B1420,B1420" "0,1"
|
|
bitfld.long 0x00 11. "B1419,B1419" "0,1"
|
|
bitfld.long 0x00 10. "B1418,B1418" "0,1"
|
|
bitfld.long 0x00 9. "B1417,B1417" "0,1"
|
|
bitfld.long 0x00 8. "B1416,B1416" "0,1"
|
|
bitfld.long 0x00 7. "B1415,B1415" "0,1"
|
|
bitfld.long 0x00 6. "B1414,B1414" "0,1"
|
|
bitfld.long 0x00 5. "B1413,B1413" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1412,B1412" "0,1"
|
|
bitfld.long 0x00 3. "B1411,B1411" "0,1"
|
|
bitfld.long 0x00 2. "B1410,B1410" "0,1"
|
|
bitfld.long 0x00 1. "B1409,B1409" "0,1"
|
|
bitfld.long 0x00 0. "B1408,B1408" "0,1"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "MPCBB1_VCTR45,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1471,B1471" "0,1"
|
|
bitfld.long 0x00 30. "B1470,B1470" "0,1"
|
|
bitfld.long 0x00 29. "B1469,B1469" "0,1"
|
|
bitfld.long 0x00 28. "B1468,B1468" "0,1"
|
|
bitfld.long 0x00 27. "B1467,B1467" "0,1"
|
|
bitfld.long 0x00 26. "B1466,B1466" "0,1"
|
|
bitfld.long 0x00 25. "B1465,B1465" "0,1"
|
|
bitfld.long 0x00 24. "B1464,B1464" "0,1"
|
|
bitfld.long 0x00 23. "B1463,B1463" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1462,B1462" "0,1"
|
|
bitfld.long 0x00 21. "B1461,B1461" "0,1"
|
|
bitfld.long 0x00 20. "B1460,B1460" "0,1"
|
|
bitfld.long 0x00 19. "B1459,B1459" "0,1"
|
|
bitfld.long 0x00 18. "B1458,B1458" "0,1"
|
|
bitfld.long 0x00 17. "B1457,B1457" "0,1"
|
|
bitfld.long 0x00 16. "B1456,B1456" "0,1"
|
|
bitfld.long 0x00 15. "B1455,B1455" "0,1"
|
|
bitfld.long 0x00 14. "B1454,B1454" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1453,B1453" "0,1"
|
|
bitfld.long 0x00 12. "B1452,B1452" "0,1"
|
|
bitfld.long 0x00 11. "B1451,B1451" "0,1"
|
|
bitfld.long 0x00 10. "B1450,B1450" "0,1"
|
|
bitfld.long 0x00 9. "B1449,B1449" "0,1"
|
|
bitfld.long 0x00 8. "B1448,B1448" "0,1"
|
|
bitfld.long 0x00 7. "B1447,B1447" "0,1"
|
|
bitfld.long 0x00 6. "B1446,B1446" "0,1"
|
|
bitfld.long 0x00 5. "B1445,B1445" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1444,B1444" "0,1"
|
|
bitfld.long 0x00 3. "B1443,B1443" "0,1"
|
|
bitfld.long 0x00 2. "B1442,B1442" "0,1"
|
|
bitfld.long 0x00 1. "B1441,B1441" "0,1"
|
|
bitfld.long 0x00 0. "B1440,B1440" "0,1"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "MPCBB1_VCTR46,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1503,B1503" "0,1"
|
|
bitfld.long 0x00 30. "B1502,B1502" "0,1"
|
|
bitfld.long 0x00 29. "B1501,B1501" "0,1"
|
|
bitfld.long 0x00 28. "B1500,B1500" "0,1"
|
|
bitfld.long 0x00 27. "B1499,B1499" "0,1"
|
|
bitfld.long 0x00 26. "B1498,B1498" "0,1"
|
|
bitfld.long 0x00 25. "B1497,B1497" "0,1"
|
|
bitfld.long 0x00 24. "B1496,B1496" "0,1"
|
|
bitfld.long 0x00 23. "B1495,B1495" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1494,B1494" "0,1"
|
|
bitfld.long 0x00 21. "B1493,B1493" "0,1"
|
|
bitfld.long 0x00 20. "B1492,B1492" "0,1"
|
|
bitfld.long 0x00 19. "B1491,B1491" "0,1"
|
|
bitfld.long 0x00 18. "B1490,B1490" "0,1"
|
|
bitfld.long 0x00 17. "B1489,B1489" "0,1"
|
|
bitfld.long 0x00 16. "B1488,B1488" "0,1"
|
|
bitfld.long 0x00 15. "B1487,B1487" "0,1"
|
|
bitfld.long 0x00 14. "B1486,B1486" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1485,B1485" "0,1"
|
|
bitfld.long 0x00 12. "B1484,B1484" "0,1"
|
|
bitfld.long 0x00 11. "B1483,B1483" "0,1"
|
|
bitfld.long 0x00 10. "B1482,B1482" "0,1"
|
|
bitfld.long 0x00 9. "B1481,B1481" "0,1"
|
|
bitfld.long 0x00 8. "B1480,B1480" "0,1"
|
|
bitfld.long 0x00 7. "B1479,B1479" "0,1"
|
|
bitfld.long 0x00 6. "B1478,B1478" "0,1"
|
|
bitfld.long 0x00 5. "B1477,B1477" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1476,B1476" "0,1"
|
|
bitfld.long 0x00 3. "B1475,B1475" "0,1"
|
|
bitfld.long 0x00 2. "B1474,B1474" "0,1"
|
|
bitfld.long 0x00 1. "B1473,B1473" "0,1"
|
|
bitfld.long 0x00 0. "B1472,B1472" "0,1"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "MPCBB1_VCTR47,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1535,B1535" "0,1"
|
|
bitfld.long 0x00 30. "B1534,B1534" "0,1"
|
|
bitfld.long 0x00 29. "B1533,B1533" "0,1"
|
|
bitfld.long 0x00 28. "B1532,B1532" "0,1"
|
|
bitfld.long 0x00 27. "B1531,B1531" "0,1"
|
|
bitfld.long 0x00 26. "B1530,B1530" "0,1"
|
|
bitfld.long 0x00 25. "B1529,B1529" "0,1"
|
|
bitfld.long 0x00 24. "B1528,B1528" "0,1"
|
|
bitfld.long 0x00 23. "B1527,B1527" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1526,B1526" "0,1"
|
|
bitfld.long 0x00 21. "B1525,B1525" "0,1"
|
|
bitfld.long 0x00 20. "B1524,B1524" "0,1"
|
|
bitfld.long 0x00 19. "B1523,B1523" "0,1"
|
|
bitfld.long 0x00 18. "B1522,B1522" "0,1"
|
|
bitfld.long 0x00 17. "B1521,B1521" "0,1"
|
|
bitfld.long 0x00 16. "B1520,B1520" "0,1"
|
|
bitfld.long 0x00 15. "B1519,B1519" "0,1"
|
|
bitfld.long 0x00 14. "B1518,B1518" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1517,B1517" "0,1"
|
|
bitfld.long 0x00 12. "B1516,B1516" "0,1"
|
|
bitfld.long 0x00 11. "B1515,B1515" "0,1"
|
|
bitfld.long 0x00 10. "B1514,B1514" "0,1"
|
|
bitfld.long 0x00 9. "B1513,B1513" "0,1"
|
|
bitfld.long 0x00 8. "B1512,B1512" "0,1"
|
|
bitfld.long 0x00 7. "B1511,B1511" "0,1"
|
|
bitfld.long 0x00 6. "B1510,B1510" "0,1"
|
|
bitfld.long 0x00 5. "B1509,B1509" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1508,B1508" "0,1"
|
|
bitfld.long 0x00 3. "B1507,B1507" "0,1"
|
|
bitfld.long 0x00 2. "B1506,B1506" "0,1"
|
|
bitfld.long 0x00 1. "B1505,B1505" "0,1"
|
|
bitfld.long 0x00 0. "B1504,B1504" "0,1"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "MPCBB1_VCTR48,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1567,B1567" "0,1"
|
|
bitfld.long 0x00 30. "B1566,B1566" "0,1"
|
|
bitfld.long 0x00 29. "B1565,B1565" "0,1"
|
|
bitfld.long 0x00 28. "B1564,B1564" "0,1"
|
|
bitfld.long 0x00 27. "B1563,B1563" "0,1"
|
|
bitfld.long 0x00 26. "B1562,B1562" "0,1"
|
|
bitfld.long 0x00 25. "B1561,B1561" "0,1"
|
|
bitfld.long 0x00 24. "B1560,B1560" "0,1"
|
|
bitfld.long 0x00 23. "B1559,B1559" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1558,B1558" "0,1"
|
|
bitfld.long 0x00 21. "B1557,B1557" "0,1"
|
|
bitfld.long 0x00 20. "B1556,B1556" "0,1"
|
|
bitfld.long 0x00 19. "B1555,B1555" "0,1"
|
|
bitfld.long 0x00 18. "B1554,B1554" "0,1"
|
|
bitfld.long 0x00 17. "B1553,B1553" "0,1"
|
|
bitfld.long 0x00 16. "B1552,B1552" "0,1"
|
|
bitfld.long 0x00 15. "B1551,B1551" "0,1"
|
|
bitfld.long 0x00 14. "B1550,B1550" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1549,B1549" "0,1"
|
|
bitfld.long 0x00 12. "B1548,B1548" "0,1"
|
|
bitfld.long 0x00 11. "B1547,B1547" "0,1"
|
|
bitfld.long 0x00 10. "B1546,B1546" "0,1"
|
|
bitfld.long 0x00 9. "B1545,B1545" "0,1"
|
|
bitfld.long 0x00 8. "B1544,B1544" "0,1"
|
|
bitfld.long 0x00 7. "B1543,B1543" "0,1"
|
|
bitfld.long 0x00 6. "B1542,B1542" "0,1"
|
|
bitfld.long 0x00 5. "B1541,B1541" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1540,B1540" "0,1"
|
|
bitfld.long 0x00 3. "B1539,B1539" "0,1"
|
|
bitfld.long 0x00 2. "B1538,B1538" "0,1"
|
|
bitfld.long 0x00 1. "B1537,B1537" "0,1"
|
|
bitfld.long 0x00 0. "B1536,B1536" "0,1"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "MPCBB1_VCTR49,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1599,B1599" "0,1"
|
|
bitfld.long 0x00 30. "B1598,B1598" "0,1"
|
|
bitfld.long 0x00 29. "B1597,B1597" "0,1"
|
|
bitfld.long 0x00 28. "B1596,B1596" "0,1"
|
|
bitfld.long 0x00 27. "B1595,B1595" "0,1"
|
|
bitfld.long 0x00 26. "B1594,B1594" "0,1"
|
|
bitfld.long 0x00 25. "B1593,B1593" "0,1"
|
|
bitfld.long 0x00 24. "B1592,B1592" "0,1"
|
|
bitfld.long 0x00 23. "B1591,B1591" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1590,B1590" "0,1"
|
|
bitfld.long 0x00 21. "B1589,B1589" "0,1"
|
|
bitfld.long 0x00 20. "B1588,B1588" "0,1"
|
|
bitfld.long 0x00 19. "B1587,B1587" "0,1"
|
|
bitfld.long 0x00 18. "B1586,B1586" "0,1"
|
|
bitfld.long 0x00 17. "B1585,B1585" "0,1"
|
|
bitfld.long 0x00 16. "B1584,B1584" "0,1"
|
|
bitfld.long 0x00 15. "B1583,B1583" "0,1"
|
|
bitfld.long 0x00 14. "B1582,B1582" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1581,B1581" "0,1"
|
|
bitfld.long 0x00 12. "B1580,B1580" "0,1"
|
|
bitfld.long 0x00 11. "B1579,B1579" "0,1"
|
|
bitfld.long 0x00 10. "B1578,B1578" "0,1"
|
|
bitfld.long 0x00 9. "B1577,B1577" "0,1"
|
|
bitfld.long 0x00 8. "B1576,B1576" "0,1"
|
|
bitfld.long 0x00 7. "B1575,B1575" "0,1"
|
|
bitfld.long 0x00 6. "B1574,B1574" "0,1"
|
|
bitfld.long 0x00 5. "B1573,B1573" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1572,B1572" "0,1"
|
|
bitfld.long 0x00 3. "B1571,B1571" "0,1"
|
|
bitfld.long 0x00 2. "B1570,B1570" "0,1"
|
|
bitfld.long 0x00 1. "B1569,B1569" "0,1"
|
|
bitfld.long 0x00 0. "B1568,B1568" "0,1"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "MPCBB1_VCTR50,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1631,B1631" "0,1"
|
|
bitfld.long 0x00 30. "B1630,B1630" "0,1"
|
|
bitfld.long 0x00 29. "B1629,B1629" "0,1"
|
|
bitfld.long 0x00 28. "B1628,B1628" "0,1"
|
|
bitfld.long 0x00 27. "B1627,B1627" "0,1"
|
|
bitfld.long 0x00 26. "B1626,B1626" "0,1"
|
|
bitfld.long 0x00 25. "B1625,B1625" "0,1"
|
|
bitfld.long 0x00 24. "B1624,B1624" "0,1"
|
|
bitfld.long 0x00 23. "B1623,B1623" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1622,B1622" "0,1"
|
|
bitfld.long 0x00 21. "B1621,B1621" "0,1"
|
|
bitfld.long 0x00 20. "B1620,B1620" "0,1"
|
|
bitfld.long 0x00 19. "B1619,B1619" "0,1"
|
|
bitfld.long 0x00 18. "B1618,B1618" "0,1"
|
|
bitfld.long 0x00 17. "B1617,B1617" "0,1"
|
|
bitfld.long 0x00 16. "B1616,B1616" "0,1"
|
|
bitfld.long 0x00 15. "B1615,B1615" "0,1"
|
|
bitfld.long 0x00 14. "B1614,B1614" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1613,B1613" "0,1"
|
|
bitfld.long 0x00 12. "B1612,B1612" "0,1"
|
|
bitfld.long 0x00 11. "B1611,B1611" "0,1"
|
|
bitfld.long 0x00 10. "B1610,B1610" "0,1"
|
|
bitfld.long 0x00 9. "B1609,B1609" "0,1"
|
|
bitfld.long 0x00 8. "B1608,B1608" "0,1"
|
|
bitfld.long 0x00 7. "B1607,B1607" "0,1"
|
|
bitfld.long 0x00 6. "B1606,B1606" "0,1"
|
|
bitfld.long 0x00 5. "B1605,B1605" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1604,B1604" "0,1"
|
|
bitfld.long 0x00 3. "B1603,B1603" "0,1"
|
|
bitfld.long 0x00 2. "B1602,B1602" "0,1"
|
|
bitfld.long 0x00 1. "B1601,B1601" "0,1"
|
|
bitfld.long 0x00 0. "B1600,B1600" "0,1"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "MPCBB1_VCTR51,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1663,B1663" "0,1"
|
|
bitfld.long 0x00 30. "B1662,B1662" "0,1"
|
|
bitfld.long 0x00 29. "B1661,B1661" "0,1"
|
|
bitfld.long 0x00 28. "B1660,B1660" "0,1"
|
|
bitfld.long 0x00 27. "B1659,B1659" "0,1"
|
|
bitfld.long 0x00 26. "B1658,B1658" "0,1"
|
|
bitfld.long 0x00 25. "B1657,B1657" "0,1"
|
|
bitfld.long 0x00 24. "B1656,B1656" "0,1"
|
|
bitfld.long 0x00 23. "B1655,B1655" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1654,B1654" "0,1"
|
|
bitfld.long 0x00 21. "B1653,B1653" "0,1"
|
|
bitfld.long 0x00 20. "B1652,B1652" "0,1"
|
|
bitfld.long 0x00 19. "B1651,B1651" "0,1"
|
|
bitfld.long 0x00 18. "B1650,B1650" "0,1"
|
|
bitfld.long 0x00 17. "B1649,B1649" "0,1"
|
|
bitfld.long 0x00 16. "B1648,B1648" "0,1"
|
|
bitfld.long 0x00 15. "B1647,B1647" "0,1"
|
|
bitfld.long 0x00 14. "B1646,B1646" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1645,B1645" "0,1"
|
|
bitfld.long 0x00 12. "B1644,B1644" "0,1"
|
|
bitfld.long 0x00 11. "B1643,B1643" "0,1"
|
|
bitfld.long 0x00 10. "B1642,B1642" "0,1"
|
|
bitfld.long 0x00 9. "B1641,B1641" "0,1"
|
|
bitfld.long 0x00 8. "B1640,B1640" "0,1"
|
|
bitfld.long 0x00 7. "B1639,B1639" "0,1"
|
|
bitfld.long 0x00 6. "B1638,B1638" "0,1"
|
|
bitfld.long 0x00 5. "B1637,B1637" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1636,B1636" "0,1"
|
|
bitfld.long 0x00 3. "B1635,B1635" "0,1"
|
|
bitfld.long 0x00 2. "B1634,B1634" "0,1"
|
|
bitfld.long 0x00 1. "B1633,B1633" "0,1"
|
|
bitfld.long 0x00 0. "B1632,B1632" "0,1"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "MPCBB1_VCTR52,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1695,B1695" "0,1"
|
|
bitfld.long 0x00 30. "B1694,B1694" "0,1"
|
|
bitfld.long 0x00 29. "B1693,B1693" "0,1"
|
|
bitfld.long 0x00 28. "B1692,B1692" "0,1"
|
|
bitfld.long 0x00 27. "B1691,B1691" "0,1"
|
|
bitfld.long 0x00 26. "B1690,B1690" "0,1"
|
|
bitfld.long 0x00 25. "B1689,B1689" "0,1"
|
|
bitfld.long 0x00 24. "B1688,B1688" "0,1"
|
|
bitfld.long 0x00 23. "B1687,B1687" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1686,B1686" "0,1"
|
|
bitfld.long 0x00 21. "B1685,B1685" "0,1"
|
|
bitfld.long 0x00 20. "B1684,B1684" "0,1"
|
|
bitfld.long 0x00 19. "B1683,B1683" "0,1"
|
|
bitfld.long 0x00 18. "B1682,B1682" "0,1"
|
|
bitfld.long 0x00 17. "B1681,B1681" "0,1"
|
|
bitfld.long 0x00 16. "B1680,B1680" "0,1"
|
|
bitfld.long 0x00 15. "B1679,B1679" "0,1"
|
|
bitfld.long 0x00 14. "B1678,B1678" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1677,B1677" "0,1"
|
|
bitfld.long 0x00 12. "B1676,B1676" "0,1"
|
|
bitfld.long 0x00 11. "B1675,B1675" "0,1"
|
|
bitfld.long 0x00 10. "B1674,B1674" "0,1"
|
|
bitfld.long 0x00 9. "B1673,B1673" "0,1"
|
|
bitfld.long 0x00 8. "B1672,B1672" "0,1"
|
|
bitfld.long 0x00 7. "B1671,B1671" "0,1"
|
|
bitfld.long 0x00 6. "B1670,B1670" "0,1"
|
|
bitfld.long 0x00 5. "B1669,B1669" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1668,B1668" "0,1"
|
|
bitfld.long 0x00 3. "B1667,B1667" "0,1"
|
|
bitfld.long 0x00 2. "B1666,B1666" "0,1"
|
|
bitfld.long 0x00 1. "B1665,B1665" "0,1"
|
|
bitfld.long 0x00 0. "B1664,B1664" "0,1"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "MPCBB1_VCTR53,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1727,B1727" "0,1"
|
|
bitfld.long 0x00 30. "B1726,B1726" "0,1"
|
|
bitfld.long 0x00 29. "B1725,B1725" "0,1"
|
|
bitfld.long 0x00 28. "B1724,B1724" "0,1"
|
|
bitfld.long 0x00 27. "B1723,B1723" "0,1"
|
|
bitfld.long 0x00 26. "B1722,B1722" "0,1"
|
|
bitfld.long 0x00 25. "B1721,B1721" "0,1"
|
|
bitfld.long 0x00 24. "B1720,B1720" "0,1"
|
|
bitfld.long 0x00 23. "B1719,B1719" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1718,B1718" "0,1"
|
|
bitfld.long 0x00 21. "B1717,B1717" "0,1"
|
|
bitfld.long 0x00 20. "B1716,B1716" "0,1"
|
|
bitfld.long 0x00 19. "B1715,B1715" "0,1"
|
|
bitfld.long 0x00 18. "B1714,B1714" "0,1"
|
|
bitfld.long 0x00 17. "B1713,B1713" "0,1"
|
|
bitfld.long 0x00 16. "B1712,B1712" "0,1"
|
|
bitfld.long 0x00 15. "B1711,B1711" "0,1"
|
|
bitfld.long 0x00 14. "B1710,B1710" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1709,B1709" "0,1"
|
|
bitfld.long 0x00 12. "B1708,B1708" "0,1"
|
|
bitfld.long 0x00 11. "B1707,B1707" "0,1"
|
|
bitfld.long 0x00 10. "B1706,B1706" "0,1"
|
|
bitfld.long 0x00 9. "B1705,B1705" "0,1"
|
|
bitfld.long 0x00 8. "B1704,B1704" "0,1"
|
|
bitfld.long 0x00 7. "B1703,B1703" "0,1"
|
|
bitfld.long 0x00 6. "B1702,B1702" "0,1"
|
|
bitfld.long 0x00 5. "B1701,B1701" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1700,B1700" "0,1"
|
|
bitfld.long 0x00 3. "B1699,B1699" "0,1"
|
|
bitfld.long 0x00 2. "B1698,B1698" "0,1"
|
|
bitfld.long 0x00 1. "B1697,B1697" "0,1"
|
|
bitfld.long 0x00 0. "B1696,B1696" "0,1"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "MPCBB1_VCTR54,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1759,B1759" "0,1"
|
|
bitfld.long 0x00 30. "B1758,B1758" "0,1"
|
|
bitfld.long 0x00 29. "B1757,B1757" "0,1"
|
|
bitfld.long 0x00 28. "B1756,B1756" "0,1"
|
|
bitfld.long 0x00 27. "B1755,B1755" "0,1"
|
|
bitfld.long 0x00 26. "B1754,B1754" "0,1"
|
|
bitfld.long 0x00 25. "B1753,B1753" "0,1"
|
|
bitfld.long 0x00 24. "B1752,B1752" "0,1"
|
|
bitfld.long 0x00 23. "B1751,B1751" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1750,B1750" "0,1"
|
|
bitfld.long 0x00 21. "B1749,B1749" "0,1"
|
|
bitfld.long 0x00 20. "B1748,B1748" "0,1"
|
|
bitfld.long 0x00 19. "B1747,B1747" "0,1"
|
|
bitfld.long 0x00 18. "B1746,B1746" "0,1"
|
|
bitfld.long 0x00 17. "B1745,B1745" "0,1"
|
|
bitfld.long 0x00 16. "B1744,B1744" "0,1"
|
|
bitfld.long 0x00 15. "B1743,B1743" "0,1"
|
|
bitfld.long 0x00 14. "B1742,B1742" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1741,B1741" "0,1"
|
|
bitfld.long 0x00 12. "B1740,B1740" "0,1"
|
|
bitfld.long 0x00 11. "B1739,B1739" "0,1"
|
|
bitfld.long 0x00 10. "B1738,B1738" "0,1"
|
|
bitfld.long 0x00 9. "B1737,B1737" "0,1"
|
|
bitfld.long 0x00 8. "B1736,B1736" "0,1"
|
|
bitfld.long 0x00 7. "B1735,B1735" "0,1"
|
|
bitfld.long 0x00 6. "B1734,B1734" "0,1"
|
|
bitfld.long 0x00 5. "B1733,B1733" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1732,B1732" "0,1"
|
|
bitfld.long 0x00 3. "B1731,B1731" "0,1"
|
|
bitfld.long 0x00 2. "B1730,B1730" "0,1"
|
|
bitfld.long 0x00 1. "B1729,B1729" "0,1"
|
|
bitfld.long 0x00 0. "B1728,B1728" "0,1"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "MPCBB1_VCTR55,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1791,B1791" "0,1"
|
|
bitfld.long 0x00 30. "B1790,B1790" "0,1"
|
|
bitfld.long 0x00 29. "B1789,B1789" "0,1"
|
|
bitfld.long 0x00 28. "B1788,B1788" "0,1"
|
|
bitfld.long 0x00 27. "B1787,B1787" "0,1"
|
|
bitfld.long 0x00 26. "B1786,B1786" "0,1"
|
|
bitfld.long 0x00 25. "B1785,B1785" "0,1"
|
|
bitfld.long 0x00 24. "B1784,B1784" "0,1"
|
|
bitfld.long 0x00 23. "B1783,B1783" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1782,B1782" "0,1"
|
|
bitfld.long 0x00 21. "B1781,B1781" "0,1"
|
|
bitfld.long 0x00 20. "B1780,B1780" "0,1"
|
|
bitfld.long 0x00 19. "B1779,B1779" "0,1"
|
|
bitfld.long 0x00 18. "B1778,B1778" "0,1"
|
|
bitfld.long 0x00 17. "B1777,B1777" "0,1"
|
|
bitfld.long 0x00 16. "B1776,B1776" "0,1"
|
|
bitfld.long 0x00 15. "B1775,B1775" "0,1"
|
|
bitfld.long 0x00 14. "B1774,B1774" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1773,B1773" "0,1"
|
|
bitfld.long 0x00 12. "B1772,B1772" "0,1"
|
|
bitfld.long 0x00 11. "B1771,B1771" "0,1"
|
|
bitfld.long 0x00 10. "B1770,B1770" "0,1"
|
|
bitfld.long 0x00 9. "B1769,B1769" "0,1"
|
|
bitfld.long 0x00 8. "B1768,B1768" "0,1"
|
|
bitfld.long 0x00 7. "B1767,B1767" "0,1"
|
|
bitfld.long 0x00 6. "B1766,B1766" "0,1"
|
|
bitfld.long 0x00 5. "B1765,B1765" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1764,B1764" "0,1"
|
|
bitfld.long 0x00 3. "B1763,B1763" "0,1"
|
|
bitfld.long 0x00 2. "B1762,B1762" "0,1"
|
|
bitfld.long 0x00 1. "B1761,B1761" "0,1"
|
|
bitfld.long 0x00 0. "B1760,B1760" "0,1"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "MPCBB1_VCTR56,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1823,B1823" "0,1"
|
|
bitfld.long 0x00 30. "B1822,B1822" "0,1"
|
|
bitfld.long 0x00 29. "B1821,B1821" "0,1"
|
|
bitfld.long 0x00 28. "B1820,B1820" "0,1"
|
|
bitfld.long 0x00 27. "B1819,B1819" "0,1"
|
|
bitfld.long 0x00 26. "B1818,B1818" "0,1"
|
|
bitfld.long 0x00 25. "B1817,B1817" "0,1"
|
|
bitfld.long 0x00 24. "B1816,B1816" "0,1"
|
|
bitfld.long 0x00 23. "B1815,B1815" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1814,B1814" "0,1"
|
|
bitfld.long 0x00 21. "B1813,B1813" "0,1"
|
|
bitfld.long 0x00 20. "B1812,B1812" "0,1"
|
|
bitfld.long 0x00 19. "B1811,B1811" "0,1"
|
|
bitfld.long 0x00 18. "B1810,B1810" "0,1"
|
|
bitfld.long 0x00 17. "B1809,B1809" "0,1"
|
|
bitfld.long 0x00 16. "B1808,B1808" "0,1"
|
|
bitfld.long 0x00 15. "B1807,B1807" "0,1"
|
|
bitfld.long 0x00 14. "B1806,B1806" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1805,B1805" "0,1"
|
|
bitfld.long 0x00 12. "B1804,B1804" "0,1"
|
|
bitfld.long 0x00 11. "B1803,B1803" "0,1"
|
|
bitfld.long 0x00 10. "B1802,B1802" "0,1"
|
|
bitfld.long 0x00 9. "B1801,B1801" "0,1"
|
|
bitfld.long 0x00 8. "B1800,B1800" "0,1"
|
|
bitfld.long 0x00 7. "B1799,B1799" "0,1"
|
|
bitfld.long 0x00 6. "B1798,B1798" "0,1"
|
|
bitfld.long 0x00 5. "B1797,B1797" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1796,B1796" "0,1"
|
|
bitfld.long 0x00 3. "B1795,B1795" "0,1"
|
|
bitfld.long 0x00 2. "B1794,B1794" "0,1"
|
|
bitfld.long 0x00 1. "B1793,B1793" "0,1"
|
|
bitfld.long 0x00 0. "B1792,B1792" "0,1"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "MPCBB1_VCTR57,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1855,B1855" "0,1"
|
|
bitfld.long 0x00 30. "B1854,B1854" "0,1"
|
|
bitfld.long 0x00 29. "B1853,B1853" "0,1"
|
|
bitfld.long 0x00 28. "B1852,B1852" "0,1"
|
|
bitfld.long 0x00 27. "B1851,B1851" "0,1"
|
|
bitfld.long 0x00 26. "B1850,B1850" "0,1"
|
|
bitfld.long 0x00 25. "B1849,B1849" "0,1"
|
|
bitfld.long 0x00 24. "B1848,B1848" "0,1"
|
|
bitfld.long 0x00 23. "B1847,B1847" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1846,B1846" "0,1"
|
|
bitfld.long 0x00 21. "B1845,B1845" "0,1"
|
|
bitfld.long 0x00 20. "B1844,B1844" "0,1"
|
|
bitfld.long 0x00 19. "B1843,B1843" "0,1"
|
|
bitfld.long 0x00 18. "B1842,B1842" "0,1"
|
|
bitfld.long 0x00 17. "B1841,B1841" "0,1"
|
|
bitfld.long 0x00 16. "B1840,B1840" "0,1"
|
|
bitfld.long 0x00 15. "B1839,B1839" "0,1"
|
|
bitfld.long 0x00 14. "B1838,B1838" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1837,B1837" "0,1"
|
|
bitfld.long 0x00 12. "B1836,B1836" "0,1"
|
|
bitfld.long 0x00 11. "B1835,B1835" "0,1"
|
|
bitfld.long 0x00 10. "B1834,B1834" "0,1"
|
|
bitfld.long 0x00 9. "B1833,B1833" "0,1"
|
|
bitfld.long 0x00 8. "B1832,B1832" "0,1"
|
|
bitfld.long 0x00 7. "B1831,B1831" "0,1"
|
|
bitfld.long 0x00 6. "B1830,B1830" "0,1"
|
|
bitfld.long 0x00 5. "B1829,B1829" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1828,B1828" "0,1"
|
|
bitfld.long 0x00 3. "B1827,B1827" "0,1"
|
|
bitfld.long 0x00 2. "B1826,B1826" "0,1"
|
|
bitfld.long 0x00 1. "B1825,B1825" "0,1"
|
|
bitfld.long 0x00 0. "B1824,B1824" "0,1"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "MPCBB1_VCTR58,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1887,B1887" "0,1"
|
|
bitfld.long 0x00 30. "B1886,B1886" "0,1"
|
|
bitfld.long 0x00 29. "B1885,B1885" "0,1"
|
|
bitfld.long 0x00 28. "B1884,B1884" "0,1"
|
|
bitfld.long 0x00 27. "B1883,B1883" "0,1"
|
|
bitfld.long 0x00 26. "B1882,B1882" "0,1"
|
|
bitfld.long 0x00 25. "B1881,B1881" "0,1"
|
|
bitfld.long 0x00 24. "B1880,B1880" "0,1"
|
|
bitfld.long 0x00 23. "B1879,B1879" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1878,B1878" "0,1"
|
|
bitfld.long 0x00 21. "B1877,B1877" "0,1"
|
|
bitfld.long 0x00 20. "B1876,B1876" "0,1"
|
|
bitfld.long 0x00 19. "B1875,B1875" "0,1"
|
|
bitfld.long 0x00 18. "B1874,B1874" "0,1"
|
|
bitfld.long 0x00 17. "B1873,B1873" "0,1"
|
|
bitfld.long 0x00 16. "B1872,B1872" "0,1"
|
|
bitfld.long 0x00 15. "B1871,B1871" "0,1"
|
|
bitfld.long 0x00 14. "B1870,B1870" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1869,B1869" "0,1"
|
|
bitfld.long 0x00 12. "B1868,B1868" "0,1"
|
|
bitfld.long 0x00 11. "B1867,B1867" "0,1"
|
|
bitfld.long 0x00 10. "B1866,B1866" "0,1"
|
|
bitfld.long 0x00 9. "B1865,B1865" "0,1"
|
|
bitfld.long 0x00 8. "B1864,B1864" "0,1"
|
|
bitfld.long 0x00 7. "B1863,B1863" "0,1"
|
|
bitfld.long 0x00 6. "B1862,B1862" "0,1"
|
|
bitfld.long 0x00 5. "B1861,B1861" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1860,B1860" "0,1"
|
|
bitfld.long 0x00 3. "B1859,B1859" "0,1"
|
|
bitfld.long 0x00 2. "B1858,B1858" "0,1"
|
|
bitfld.long 0x00 1. "B1857,B1857" "0,1"
|
|
bitfld.long 0x00 0. "B1856,B1856" "0,1"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "MPCBB1_VCTR59,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1919,B1919" "0,1"
|
|
bitfld.long 0x00 30. "B1918,B1918" "0,1"
|
|
bitfld.long 0x00 29. "B1917,B1917" "0,1"
|
|
bitfld.long 0x00 28. "B1916,B1916" "0,1"
|
|
bitfld.long 0x00 27. "B1915,B1915" "0,1"
|
|
bitfld.long 0x00 26. "B1914,B1914" "0,1"
|
|
bitfld.long 0x00 25. "B1913,B1913" "0,1"
|
|
bitfld.long 0x00 24. "B1912,B1912" "0,1"
|
|
bitfld.long 0x00 23. "B1911,B1911" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1910,B1910" "0,1"
|
|
bitfld.long 0x00 21. "B1909,B1909" "0,1"
|
|
bitfld.long 0x00 20. "B1908,B1908" "0,1"
|
|
bitfld.long 0x00 19. "B1907,B1907" "0,1"
|
|
bitfld.long 0x00 18. "B1906,B1906" "0,1"
|
|
bitfld.long 0x00 17. "B1905,B1905" "0,1"
|
|
bitfld.long 0x00 16. "B1904,B1904" "0,1"
|
|
bitfld.long 0x00 15. "B1903,B1903" "0,1"
|
|
bitfld.long 0x00 14. "B1902,B1902" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1901,B1901" "0,1"
|
|
bitfld.long 0x00 12. "B1900,B1900" "0,1"
|
|
bitfld.long 0x00 11. "B1899,B1899" "0,1"
|
|
bitfld.long 0x00 10. "B1898,B1898" "0,1"
|
|
bitfld.long 0x00 9. "B1897,B1897" "0,1"
|
|
bitfld.long 0x00 8. "B1896,B1896" "0,1"
|
|
bitfld.long 0x00 7. "B1895,B1895" "0,1"
|
|
bitfld.long 0x00 6. "B1894,B1894" "0,1"
|
|
bitfld.long 0x00 5. "B1893,B1893" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1892,B1892" "0,1"
|
|
bitfld.long 0x00 3. "B1891,B1891" "0,1"
|
|
bitfld.long 0x00 2. "B1890,B1890" "0,1"
|
|
bitfld.long 0x00 1. "B1889,B1889" "0,1"
|
|
bitfld.long 0x00 0. "B1888,B1888" "0,1"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "MPCBB1_VCTR60,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1951,B1951" "0,1"
|
|
bitfld.long 0x00 30. "B1950,B1950" "0,1"
|
|
bitfld.long 0x00 29. "B1949,B1949" "0,1"
|
|
bitfld.long 0x00 28. "B1948,B1948" "0,1"
|
|
bitfld.long 0x00 27. "B1947,B1947" "0,1"
|
|
bitfld.long 0x00 26. "B1946,B1946" "0,1"
|
|
bitfld.long 0x00 25. "B1945,B1945" "0,1"
|
|
bitfld.long 0x00 24. "B1944,B1944" "0,1"
|
|
bitfld.long 0x00 23. "B1943,B1943" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1942,B1942" "0,1"
|
|
bitfld.long 0x00 21. "B1941,B1941" "0,1"
|
|
bitfld.long 0x00 20. "B1940,B1940" "0,1"
|
|
bitfld.long 0x00 19. "B1939,B1939" "0,1"
|
|
bitfld.long 0x00 18. "B1938,B1938" "0,1"
|
|
bitfld.long 0x00 17. "B1937,B1937" "0,1"
|
|
bitfld.long 0x00 16. "B1936,B1936" "0,1"
|
|
bitfld.long 0x00 15. "B1935,B1935" "0,1"
|
|
bitfld.long 0x00 14. "B1934,B1934" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1933,B1933" "0,1"
|
|
bitfld.long 0x00 12. "B1932,B1932" "0,1"
|
|
bitfld.long 0x00 11. "B1931,B1931" "0,1"
|
|
bitfld.long 0x00 10. "B1930,B1930" "0,1"
|
|
bitfld.long 0x00 9. "B1929,B1929" "0,1"
|
|
bitfld.long 0x00 8. "B1928,B1928" "0,1"
|
|
bitfld.long 0x00 7. "B1927,B1927" "0,1"
|
|
bitfld.long 0x00 6. "B1926,B1926" "0,1"
|
|
bitfld.long 0x00 5. "B1925,B1925" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1924,B1924" "0,1"
|
|
bitfld.long 0x00 3. "B1923,B1923" "0,1"
|
|
bitfld.long 0x00 2. "B1922,B1922" "0,1"
|
|
bitfld.long 0x00 1. "B1921,B1921" "0,1"
|
|
bitfld.long 0x00 0. "B1920,B1920" "0,1"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "MPCBB1_VCTR61,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1983,B1983" "0,1"
|
|
bitfld.long 0x00 30. "B1982,B1982" "0,1"
|
|
bitfld.long 0x00 29. "B1981,B1981" "0,1"
|
|
bitfld.long 0x00 28. "B1980,B1980" "0,1"
|
|
bitfld.long 0x00 27. "B1979,B1979" "0,1"
|
|
bitfld.long 0x00 26. "B1978,B1978" "0,1"
|
|
bitfld.long 0x00 25. "B1977,B1977" "0,1"
|
|
bitfld.long 0x00 24. "B1976,B1976" "0,1"
|
|
bitfld.long 0x00 23. "B1975,B1975" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1974,B1974" "0,1"
|
|
bitfld.long 0x00 21. "B1973,B1973" "0,1"
|
|
bitfld.long 0x00 20. "B1972,B1972" "0,1"
|
|
bitfld.long 0x00 19. "B1971,B1971" "0,1"
|
|
bitfld.long 0x00 18. "B1970,B1970" "0,1"
|
|
bitfld.long 0x00 17. "B1969,B1969" "0,1"
|
|
bitfld.long 0x00 16. "B1968,B1968" "0,1"
|
|
bitfld.long 0x00 15. "B1967,B1967" "0,1"
|
|
bitfld.long 0x00 14. "B1966,B1966" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1965,B1965" "0,1"
|
|
bitfld.long 0x00 12. "B1964,B1964" "0,1"
|
|
bitfld.long 0x00 11. "B1963,B1963" "0,1"
|
|
bitfld.long 0x00 10. "B1962,B1962" "0,1"
|
|
bitfld.long 0x00 9. "B1961,B1961" "0,1"
|
|
bitfld.long 0x00 8. "B1960,B1960" "0,1"
|
|
bitfld.long 0x00 7. "B1959,B1959" "0,1"
|
|
bitfld.long 0x00 6. "B1958,B1958" "0,1"
|
|
bitfld.long 0x00 5. "B1957,B1957" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1956,B1956" "0,1"
|
|
bitfld.long 0x00 3. "B1955,B1955" "0,1"
|
|
bitfld.long 0x00 2. "B1954,B1954" "0,1"
|
|
bitfld.long 0x00 1. "B1953,B1953" "0,1"
|
|
bitfld.long 0x00 0. "B1952,B1952" "0,1"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "MPCBB1_VCTR62,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B2015,B2015" "0,1"
|
|
bitfld.long 0x00 30. "B2014,B2014" "0,1"
|
|
bitfld.long 0x00 29. "B2013,B2013" "0,1"
|
|
bitfld.long 0x00 28. "B2012,B2012" "0,1"
|
|
bitfld.long 0x00 27. "B2011,B2011" "0,1"
|
|
bitfld.long 0x00 26. "B2010,B2010" "0,1"
|
|
bitfld.long 0x00 25. "B2009,B2009" "0,1"
|
|
bitfld.long 0x00 24. "B2008,B2008" "0,1"
|
|
bitfld.long 0x00 23. "B2007,B2007" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B2006,B2006" "0,1"
|
|
bitfld.long 0x00 21. "B2005,B2005" "0,1"
|
|
bitfld.long 0x00 20. "B2004,B2004" "0,1"
|
|
bitfld.long 0x00 19. "B2003,B2003" "0,1"
|
|
bitfld.long 0x00 18. "B2002,B2002" "0,1"
|
|
bitfld.long 0x00 17. "B2001,B2001" "0,1"
|
|
bitfld.long 0x00 16. "B2000,B2000" "0,1"
|
|
bitfld.long 0x00 15. "B1999,B1999" "0,1"
|
|
bitfld.long 0x00 14. "B1998,B1998" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1997,B1997" "0,1"
|
|
bitfld.long 0x00 12. "B1996,B1996" "0,1"
|
|
bitfld.long 0x00 11. "B1995,B1995" "0,1"
|
|
bitfld.long 0x00 10. "B1994,B1994" "0,1"
|
|
bitfld.long 0x00 9. "B1993,B1993" "0,1"
|
|
bitfld.long 0x00 8. "B1992,B1992" "0,1"
|
|
bitfld.long 0x00 7. "B1991,B1991" "0,1"
|
|
bitfld.long 0x00 6. "B1990,B1990" "0,1"
|
|
bitfld.long 0x00 5. "B1989,B1989" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1988,B1988" "0,1"
|
|
bitfld.long 0x00 3. "B1987,B1987" "0,1"
|
|
bitfld.long 0x00 2. "B1986,B1986" "0,1"
|
|
bitfld.long 0x00 1. "B1985,B1985" "0,1"
|
|
bitfld.long 0x00 0. "B1984,B1984" "0,1"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "MPCBB1_VCTR63,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B2047,B2047" "0,1"
|
|
bitfld.long 0x00 30. "B2046,B2046" "0,1"
|
|
bitfld.long 0x00 29. "B2045,B2045" "0,1"
|
|
bitfld.long 0x00 28. "B2044,B2044" "0,1"
|
|
bitfld.long 0x00 27. "B2043,B2043" "0,1"
|
|
bitfld.long 0x00 26. "B2042,B2042" "0,1"
|
|
bitfld.long 0x00 25. "B2041,B2041" "0,1"
|
|
bitfld.long 0x00 24. "B2040,B2040" "0,1"
|
|
bitfld.long 0x00 23. "B2039,B2039" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B2038,B2038" "0,1"
|
|
bitfld.long 0x00 21. "B2037,B2037" "0,1"
|
|
bitfld.long 0x00 20. "B2036,B2036" "0,1"
|
|
bitfld.long 0x00 19. "B2035,B2035" "0,1"
|
|
bitfld.long 0x00 18. "B2034,B2034" "0,1"
|
|
bitfld.long 0x00 17. "B2033,B2033" "0,1"
|
|
bitfld.long 0x00 16. "B2032,B2032" "0,1"
|
|
bitfld.long 0x00 15. "B2031,B2031" "0,1"
|
|
bitfld.long 0x00 14. "B2030,B2030" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B2029,B2029" "0,1"
|
|
bitfld.long 0x00 12. "B2028,B2028" "0,1"
|
|
bitfld.long 0x00 11. "B2027,B2027" "0,1"
|
|
bitfld.long 0x00 10. "B2026,B2026" "0,1"
|
|
bitfld.long 0x00 9. "B2025,B2025" "0,1"
|
|
bitfld.long 0x00 8. "B2024,B2024" "0,1"
|
|
bitfld.long 0x00 7. "B2023,B2023" "0,1"
|
|
bitfld.long 0x00 6. "B2022,B2022" "0,1"
|
|
bitfld.long 0x00 5. "B2021,B2021" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B2020,B2020" "0,1"
|
|
bitfld.long 0x00 3. "B2019,B2019" "0,1"
|
|
bitfld.long 0x00 2. "B2018,B2018" "0,1"
|
|
bitfld.long 0x00 1. "B2017,B2017" "0,1"
|
|
bitfld.long 0x00 0. "B2016,B2016" "0,1"
|
|
tree.end
|
|
tree "SEC_MPCBB2"
|
|
base ad:0x50033000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MPCBB2_CR,MPCBB control register"
|
|
bitfld.long 0x00 31. "SRWILADIS,SRWILADIS" "0,1"
|
|
bitfld.long 0x00 30. "INVSECSTATE,INVSECSTATE" "0,1"
|
|
bitfld.long 0x00 0. "LCK,LCK" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MPCBB2_LCKVTR1,MPCBB control register"
|
|
bitfld.long 0x00 31. "LCKSB31,LCKSB31" "0,1"
|
|
bitfld.long 0x00 30. "LCKSB30,LCKSB30" "0,1"
|
|
bitfld.long 0x00 29. "LCKSB29,LCKSB29" "0,1"
|
|
bitfld.long 0x00 28. "LCKSB28,LCKSB28" "0,1"
|
|
bitfld.long 0x00 27. "LCKSB27,LCKSB27" "0,1"
|
|
bitfld.long 0x00 26. "LCKSB26,LCKSB26" "0,1"
|
|
bitfld.long 0x00 25. "LCKSB25,LCKSB25" "0,1"
|
|
bitfld.long 0x00 24. "LCKSB24,LCKSB24" "0,1"
|
|
bitfld.long 0x00 23. "LCKSB23,LCKSB23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "LCKSB22,LCKSB22" "0,1"
|
|
bitfld.long 0x00 21. "LCKSB21,LCKSB21" "0,1"
|
|
bitfld.long 0x00 20. "LCKSB20,LCKSB20" "0,1"
|
|
bitfld.long 0x00 19. "LCKSB19,LCKSB19" "0,1"
|
|
bitfld.long 0x00 18. "LCKSB18,LCKSB18" "0,1"
|
|
bitfld.long 0x00 17. "LCKSB17,LCKSB17" "0,1"
|
|
bitfld.long 0x00 16. "LCKSB16,LCKSB16" "0,1"
|
|
bitfld.long 0x00 15. "LCKSB15,LCKSB15" "0,1"
|
|
bitfld.long 0x00 14. "LCKSB14,LCKSB14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "LCKSB13,LCKSB13" "0,1"
|
|
bitfld.long 0x00 12. "LCKSB12,LCKSB12" "0,1"
|
|
bitfld.long 0x00 11. "LCKSB11,LCKSB11" "0,1"
|
|
bitfld.long 0x00 10. "LCKSB10,LCKSB10" "0,1"
|
|
bitfld.long 0x00 9. "LCKSB9,LCKSB9" "0,1"
|
|
bitfld.long 0x00 8. "LCKSB8,LCKSB8" "0,1"
|
|
bitfld.long 0x00 7. "LCKSB7,LCKSB7" "0,1"
|
|
bitfld.long 0x00 6. "LCKSB6,LCKSB6" "0,1"
|
|
bitfld.long 0x00 5. "LCKSB5,LCKSB5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LCKSB4,LCKSB4" "0,1"
|
|
bitfld.long 0x00 3. "LCKSB3,LCKSB3" "0,1"
|
|
bitfld.long 0x00 2. "LCKSB2,LCKSB2" "0,1"
|
|
bitfld.long 0x00 1. "LCKSB1,LCKSB1" "0,1"
|
|
bitfld.long 0x00 0. "LCKSB0,LCKSB0" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MPCBB2_LCKVTR2,MPCBB control register"
|
|
bitfld.long 0x00 31. "LCKSB63,LCKSB63" "0,1"
|
|
bitfld.long 0x00 30. "LCKSB62,LCKSB62" "0,1"
|
|
bitfld.long 0x00 29. "LCKSB61,LCKSB61" "0,1"
|
|
bitfld.long 0x00 28. "LCKSB60,LCKSB60" "0,1"
|
|
bitfld.long 0x00 27. "LCKSB59,LCKSB59" "0,1"
|
|
bitfld.long 0x00 26. "LCKSB58,LCKSB58" "0,1"
|
|
bitfld.long 0x00 25. "LCKSB57,LCKSB57" "0,1"
|
|
bitfld.long 0x00 24. "LCKSB56,LCKSB56" "0,1"
|
|
bitfld.long 0x00 23. "LCKSB55,LCKSB55" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "LCKSB54,LCKSB54" "0,1"
|
|
bitfld.long 0x00 21. "LCKSB53,LCKSB53" "0,1"
|
|
bitfld.long 0x00 20. "LCKSB52,LCKSB52" "0,1"
|
|
bitfld.long 0x00 19. "LCKSB51,LCKSB51" "0,1"
|
|
bitfld.long 0x00 18. "LCKSB50,LCKSB50" "0,1"
|
|
bitfld.long 0x00 17. "LCKSB49,LCKSB49" "0,1"
|
|
bitfld.long 0x00 16. "LCKSB48,LCKSB48" "0,1"
|
|
bitfld.long 0x00 15. "LCKSB47,LCKSB47" "0,1"
|
|
bitfld.long 0x00 14. "LCKSB46,LCKSB46" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "LCKSB45,LCKSB45" "0,1"
|
|
bitfld.long 0x00 12. "LCKSB44,LCKSB44" "0,1"
|
|
bitfld.long 0x00 11. "LCKSB43,LCKSB43" "0,1"
|
|
bitfld.long 0x00 10. "LCKSB42,LCKSB42" "0,1"
|
|
bitfld.long 0x00 9. "LCKSB41,LCKSB41" "0,1"
|
|
bitfld.long 0x00 8. "LCKSB40,LCKSB40" "0,1"
|
|
bitfld.long 0x00 7. "LCKSB39,LCKSB39" "0,1"
|
|
bitfld.long 0x00 6. "LCKSB38,LCKSB38" "0,1"
|
|
bitfld.long 0x00 5. "LCKSB37,LCKSB37" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "LCKSB36,LCKSB36" "0,1"
|
|
bitfld.long 0x00 3. "LCKSB35,LCKSB35" "0,1"
|
|
bitfld.long 0x00 2. "LCKSB34,LCKSB34" "0,1"
|
|
bitfld.long 0x00 1. "LCKSB33,LCKSB33" "0,1"
|
|
bitfld.long 0x00 0. "LCKSB32,LCKSB32" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MPCBB2_VCTR0,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B31,B31" "0,1"
|
|
bitfld.long 0x00 30. "B30,B30" "0,1"
|
|
bitfld.long 0x00 29. "B29,B29" "0,1"
|
|
bitfld.long 0x00 28. "B28,B28" "0,1"
|
|
bitfld.long 0x00 27. "B27,B27" "0,1"
|
|
bitfld.long 0x00 26. "B26,B26" "0,1"
|
|
bitfld.long 0x00 25. "B25,B25" "0,1"
|
|
bitfld.long 0x00 24. "B24,B24" "0,1"
|
|
bitfld.long 0x00 23. "B23,B23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B22,B22" "0,1"
|
|
bitfld.long 0x00 21. "B21,B21" "0,1"
|
|
bitfld.long 0x00 20. "B20,B20" "0,1"
|
|
bitfld.long 0x00 19. "B19,B19" "0,1"
|
|
bitfld.long 0x00 18. "B18,B18" "0,1"
|
|
bitfld.long 0x00 17. "B17,B17" "0,1"
|
|
bitfld.long 0x00 16. "B16,B16" "0,1"
|
|
bitfld.long 0x00 15. "B15,B15" "0,1"
|
|
bitfld.long 0x00 14. "B14,B14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B13,B13" "0,1"
|
|
bitfld.long 0x00 12. "B12,B12" "0,1"
|
|
bitfld.long 0x00 11. "B11,B11" "0,1"
|
|
bitfld.long 0x00 10. "B10,B10" "0,1"
|
|
bitfld.long 0x00 9. "B9,B9" "0,1"
|
|
bitfld.long 0x00 8. "B8,B8" "0,1"
|
|
bitfld.long 0x00 7. "B7,B7" "0,1"
|
|
bitfld.long 0x00 6. "B6,B6" "0,1"
|
|
bitfld.long 0x00 5. "B5,B5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B4,B4" "0,1"
|
|
bitfld.long 0x00 3. "B3,B3" "0,1"
|
|
bitfld.long 0x00 2. "B2,B2" "0,1"
|
|
bitfld.long 0x00 1. "B1,B1" "0,1"
|
|
bitfld.long 0x00 0. "B0,B0" "0,1"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "MPCBB2_VCTR1,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B63,B63" "0,1"
|
|
bitfld.long 0x00 30. "B62,B62" "0,1"
|
|
bitfld.long 0x00 29. "B61,B61" "0,1"
|
|
bitfld.long 0x00 28. "B60,B60" "0,1"
|
|
bitfld.long 0x00 27. "B59,B59" "0,1"
|
|
bitfld.long 0x00 26. "B58,B58" "0,1"
|
|
bitfld.long 0x00 25. "B57,B57" "0,1"
|
|
bitfld.long 0x00 24. "B56,B56" "0,1"
|
|
bitfld.long 0x00 23. "B55,B55" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B54,B54" "0,1"
|
|
bitfld.long 0x00 21. "B53,B53" "0,1"
|
|
bitfld.long 0x00 20. "B52,B52" "0,1"
|
|
bitfld.long 0x00 19. "B51,B51" "0,1"
|
|
bitfld.long 0x00 18. "B50,B50" "0,1"
|
|
bitfld.long 0x00 17. "B49,B49" "0,1"
|
|
bitfld.long 0x00 16. "B48,B48" "0,1"
|
|
bitfld.long 0x00 15. "B47,B47" "0,1"
|
|
bitfld.long 0x00 14. "B46,B46" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B45,B45" "0,1"
|
|
bitfld.long 0x00 12. "B44,B44" "0,1"
|
|
bitfld.long 0x00 11. "B43,B43" "0,1"
|
|
bitfld.long 0x00 10. "B42,B42" "0,1"
|
|
bitfld.long 0x00 9. "B41,B41" "0,1"
|
|
bitfld.long 0x00 8. "B40,B40" "0,1"
|
|
bitfld.long 0x00 7. "B39,B39" "0,1"
|
|
bitfld.long 0x00 6. "B38,B38" "0,1"
|
|
bitfld.long 0x00 5. "B37,B37" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B36,B36" "0,1"
|
|
bitfld.long 0x00 3. "B35,B35" "0,1"
|
|
bitfld.long 0x00 2. "B34,B34" "0,1"
|
|
bitfld.long 0x00 1. "B33,B33" "0,1"
|
|
bitfld.long 0x00 0. "B32,B32" "0,1"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "MPCBB2_VCTR2,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B95,B95" "0,1"
|
|
bitfld.long 0x00 30. "B94,B94" "0,1"
|
|
bitfld.long 0x00 29. "B93,B93" "0,1"
|
|
bitfld.long 0x00 28. "B92,B92" "0,1"
|
|
bitfld.long 0x00 27. "B91,B91" "0,1"
|
|
bitfld.long 0x00 26. "B90,B90" "0,1"
|
|
bitfld.long 0x00 25. "B89,B89" "0,1"
|
|
bitfld.long 0x00 24. "B88,B88" "0,1"
|
|
bitfld.long 0x00 23. "B87,B87" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B86,B86" "0,1"
|
|
bitfld.long 0x00 21. "B85,B85" "0,1"
|
|
bitfld.long 0x00 20. "B84,B84" "0,1"
|
|
bitfld.long 0x00 19. "B83,B83" "0,1"
|
|
bitfld.long 0x00 18. "B82,B82" "0,1"
|
|
bitfld.long 0x00 17. "B81,B81" "0,1"
|
|
bitfld.long 0x00 16. "B80,B80" "0,1"
|
|
bitfld.long 0x00 15. "B79,B79" "0,1"
|
|
bitfld.long 0x00 14. "B78,B78" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B77,B77" "0,1"
|
|
bitfld.long 0x00 12. "B76,B76" "0,1"
|
|
bitfld.long 0x00 11. "B75,B75" "0,1"
|
|
bitfld.long 0x00 10. "B74,B74" "0,1"
|
|
bitfld.long 0x00 9. "B73,B73" "0,1"
|
|
bitfld.long 0x00 8. "B72,B72" "0,1"
|
|
bitfld.long 0x00 7. "B71,B71" "0,1"
|
|
bitfld.long 0x00 6. "B70,B70" "0,1"
|
|
bitfld.long 0x00 5. "B69,B69" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B68,B68" "0,1"
|
|
bitfld.long 0x00 3. "B67,B67" "0,1"
|
|
bitfld.long 0x00 2. "B66,B66" "0,1"
|
|
bitfld.long 0x00 1. "B65,B65" "0,1"
|
|
bitfld.long 0x00 0. "B64,B64" "0,1"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR3,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B127,B127" "0,1"
|
|
bitfld.long 0x00 30. "B126,B126" "0,1"
|
|
bitfld.long 0x00 29. "B125,B125" "0,1"
|
|
bitfld.long 0x00 28. "B124,B124" "0,1"
|
|
bitfld.long 0x00 27. "B123,B123" "0,1"
|
|
bitfld.long 0x00 26. "B122,B122" "0,1"
|
|
bitfld.long 0x00 25. "B121,B121" "0,1"
|
|
bitfld.long 0x00 24. "B120,B120" "0,1"
|
|
bitfld.long 0x00 23. "B119,B119" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B118,B118" "0,1"
|
|
bitfld.long 0x00 21. "B117,B117" "0,1"
|
|
bitfld.long 0x00 20. "B116,B116" "0,1"
|
|
bitfld.long 0x00 19. "B115,B115" "0,1"
|
|
bitfld.long 0x00 18. "B114,B114" "0,1"
|
|
bitfld.long 0x00 17. "B113,B113" "0,1"
|
|
bitfld.long 0x00 16. "B112,B112" "0,1"
|
|
bitfld.long 0x00 15. "B111,B111" "0,1"
|
|
bitfld.long 0x00 14. "B110,B110" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B109,B109" "0,1"
|
|
bitfld.long 0x00 12. "B108,B108" "0,1"
|
|
bitfld.long 0x00 11. "B107,B107" "0,1"
|
|
bitfld.long 0x00 10. "B106,B106" "0,1"
|
|
bitfld.long 0x00 9. "B105,B105" "0,1"
|
|
bitfld.long 0x00 8. "B104,B104" "0,1"
|
|
bitfld.long 0x00 7. "B103,B103" "0,1"
|
|
bitfld.long 0x00 6. "B102,B102" "0,1"
|
|
bitfld.long 0x00 5. "B101,B101" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B100,B100" "0,1"
|
|
bitfld.long 0x00 3. "B99,B99" "0,1"
|
|
bitfld.long 0x00 2. "B98,B98" "0,1"
|
|
bitfld.long 0x00 1. "B97,B97" "0,1"
|
|
bitfld.long 0x00 0. "B96,B96" "0,1"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MPCBB2_VCTR4,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B159,B159" "0,1"
|
|
bitfld.long 0x00 30. "B158,B158" "0,1"
|
|
bitfld.long 0x00 29. "B157,B157" "0,1"
|
|
bitfld.long 0x00 28. "B156,B156" "0,1"
|
|
bitfld.long 0x00 27. "B155,B155" "0,1"
|
|
bitfld.long 0x00 26. "B154,B154" "0,1"
|
|
bitfld.long 0x00 25. "B153,B153" "0,1"
|
|
bitfld.long 0x00 24. "B152,B152" "0,1"
|
|
bitfld.long 0x00 23. "B151,B151" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B150,B150" "0,1"
|
|
bitfld.long 0x00 21. "B149,B149" "0,1"
|
|
bitfld.long 0x00 20. "B148,B148" "0,1"
|
|
bitfld.long 0x00 19. "B147,B147" "0,1"
|
|
bitfld.long 0x00 18. "B146,B146" "0,1"
|
|
bitfld.long 0x00 17. "B145,B145" "0,1"
|
|
bitfld.long 0x00 16. "B144,B144" "0,1"
|
|
bitfld.long 0x00 15. "B143,B143" "0,1"
|
|
bitfld.long 0x00 14. "B142,B142" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B141,B141" "0,1"
|
|
bitfld.long 0x00 12. "B140,B140" "0,1"
|
|
bitfld.long 0x00 11. "B139,B139" "0,1"
|
|
bitfld.long 0x00 10. "B138,B138" "0,1"
|
|
bitfld.long 0x00 9. "B137,B137" "0,1"
|
|
bitfld.long 0x00 8. "B136,B136" "0,1"
|
|
bitfld.long 0x00 7. "B135,B135" "0,1"
|
|
bitfld.long 0x00 6. "B134,B134" "0,1"
|
|
bitfld.long 0x00 5. "B133,B133" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B132,B132" "0,1"
|
|
bitfld.long 0x00 3. "B131,B131" "0,1"
|
|
bitfld.long 0x00 2. "B130,B130" "0,1"
|
|
bitfld.long 0x00 1. "B129,B129" "0,1"
|
|
bitfld.long 0x00 0. "B128,B128" "0,1"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MPCBB2_VCTR5,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B191,B191" "0,1"
|
|
bitfld.long 0x00 30. "B190,B190" "0,1"
|
|
bitfld.long 0x00 29. "B189,B189" "0,1"
|
|
bitfld.long 0x00 28. "B188,B188" "0,1"
|
|
bitfld.long 0x00 27. "B187,B187" "0,1"
|
|
bitfld.long 0x00 26. "B186,B186" "0,1"
|
|
bitfld.long 0x00 25. "B185,B185" "0,1"
|
|
bitfld.long 0x00 24. "B184,B184" "0,1"
|
|
bitfld.long 0x00 23. "B183,B183" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B182,B182" "0,1"
|
|
bitfld.long 0x00 21. "B181,B181" "0,1"
|
|
bitfld.long 0x00 20. "B180,B180" "0,1"
|
|
bitfld.long 0x00 19. "B179,B179" "0,1"
|
|
bitfld.long 0x00 18. "B178,B178" "0,1"
|
|
bitfld.long 0x00 17. "B177,B177" "0,1"
|
|
bitfld.long 0x00 16. "B176,B176" "0,1"
|
|
bitfld.long 0x00 15. "B175,B175" "0,1"
|
|
bitfld.long 0x00 14. "B174,B174" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B173,B173" "0,1"
|
|
bitfld.long 0x00 12. "B172,B172" "0,1"
|
|
bitfld.long 0x00 11. "B171,B171" "0,1"
|
|
bitfld.long 0x00 10. "B170,B170" "0,1"
|
|
bitfld.long 0x00 9. "B169,B169" "0,1"
|
|
bitfld.long 0x00 8. "B168,B168" "0,1"
|
|
bitfld.long 0x00 7. "B167,B167" "0,1"
|
|
bitfld.long 0x00 6. "B166,B166" "0,1"
|
|
bitfld.long 0x00 5. "B165,B165" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B164,B164" "0,1"
|
|
bitfld.long 0x00 3. "B163,B163" "0,1"
|
|
bitfld.long 0x00 2. "B162,B162" "0,1"
|
|
bitfld.long 0x00 1. "B161,B161" "0,1"
|
|
bitfld.long 0x00 0. "B160,B160" "0,1"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MPCBB2_VCTR6,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B223,B223" "0,1"
|
|
bitfld.long 0x00 30. "B222,B222" "0,1"
|
|
bitfld.long 0x00 29. "B221,B221" "0,1"
|
|
bitfld.long 0x00 28. "B220,B220" "0,1"
|
|
bitfld.long 0x00 27. "B219,B219" "0,1"
|
|
bitfld.long 0x00 26. "B218,B218" "0,1"
|
|
bitfld.long 0x00 25. "B217,B217" "0,1"
|
|
bitfld.long 0x00 24. "B216,B216" "0,1"
|
|
bitfld.long 0x00 23. "B215,B215" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B214,B214" "0,1"
|
|
bitfld.long 0x00 21. "B213,B213" "0,1"
|
|
bitfld.long 0x00 20. "B212,B212" "0,1"
|
|
bitfld.long 0x00 19. "B211,B211" "0,1"
|
|
bitfld.long 0x00 18. "B210,B210" "0,1"
|
|
bitfld.long 0x00 17. "B209,B209" "0,1"
|
|
bitfld.long 0x00 16. "B208,B208" "0,1"
|
|
bitfld.long 0x00 15. "B207,B207" "0,1"
|
|
bitfld.long 0x00 14. "B206,B206" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B205,B205" "0,1"
|
|
bitfld.long 0x00 12. "B204,B204" "0,1"
|
|
bitfld.long 0x00 11. "B203,B203" "0,1"
|
|
bitfld.long 0x00 10. "B202,B202" "0,1"
|
|
bitfld.long 0x00 9. "B201,B201" "0,1"
|
|
bitfld.long 0x00 8. "B200,B200" "0,1"
|
|
bitfld.long 0x00 7. "B199,B199" "0,1"
|
|
bitfld.long 0x00 6. "B198,B198" "0,1"
|
|
bitfld.long 0x00 5. "B197,B197" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B196,B196" "0,1"
|
|
bitfld.long 0x00 3. "B195,B195" "0,1"
|
|
bitfld.long 0x00 2. "B194,B194" "0,1"
|
|
bitfld.long 0x00 1. "B193,B193" "0,1"
|
|
bitfld.long 0x00 0. "B192,B192" "0,1"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR7,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B255,B255" "0,1"
|
|
bitfld.long 0x00 30. "B254,B254" "0,1"
|
|
bitfld.long 0x00 29. "B253,B253" "0,1"
|
|
bitfld.long 0x00 28. "B252,B252" "0,1"
|
|
bitfld.long 0x00 27. "B251,B251" "0,1"
|
|
bitfld.long 0x00 26. "B250,B250" "0,1"
|
|
bitfld.long 0x00 25. "B249,B249" "0,1"
|
|
bitfld.long 0x00 24. "B248,B248" "0,1"
|
|
bitfld.long 0x00 23. "B247,B247" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B246,B246" "0,1"
|
|
bitfld.long 0x00 21. "B245,B245" "0,1"
|
|
bitfld.long 0x00 20. "B244,B244" "0,1"
|
|
bitfld.long 0x00 19. "B243,B243" "0,1"
|
|
bitfld.long 0x00 18. "B242,B242" "0,1"
|
|
bitfld.long 0x00 17. "B241,B241" "0,1"
|
|
bitfld.long 0x00 16. "B240,B240" "0,1"
|
|
bitfld.long 0x00 15. "B239,B239" "0,1"
|
|
bitfld.long 0x00 14. "B238,B238" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B237,B237" "0,1"
|
|
bitfld.long 0x00 12. "B236,B236" "0,1"
|
|
bitfld.long 0x00 11. "B235,B235" "0,1"
|
|
bitfld.long 0x00 10. "B234,B234" "0,1"
|
|
bitfld.long 0x00 9. "B233,B233" "0,1"
|
|
bitfld.long 0x00 8. "B232,B232" "0,1"
|
|
bitfld.long 0x00 7. "B231,B231" "0,1"
|
|
bitfld.long 0x00 6. "B230,B230" "0,1"
|
|
bitfld.long 0x00 5. "B229,B229" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B228,B228" "0,1"
|
|
bitfld.long 0x00 3. "B227,B227" "0,1"
|
|
bitfld.long 0x00 2. "B226,B226" "0,1"
|
|
bitfld.long 0x00 1. "B225,B225" "0,1"
|
|
bitfld.long 0x00 0. "B224,B224" "0,1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "MPCBB2_VCTR8,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B287,B287" "0,1"
|
|
bitfld.long 0x00 30. "B286,B286" "0,1"
|
|
bitfld.long 0x00 29. "B285,B285" "0,1"
|
|
bitfld.long 0x00 28. "B284,B284" "0,1"
|
|
bitfld.long 0x00 27. "B283,B283" "0,1"
|
|
bitfld.long 0x00 26. "B282,B282" "0,1"
|
|
bitfld.long 0x00 25. "B281,B281" "0,1"
|
|
bitfld.long 0x00 24. "B280,B280" "0,1"
|
|
bitfld.long 0x00 23. "B279,B279" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B278,B278" "0,1"
|
|
bitfld.long 0x00 21. "B277,B277" "0,1"
|
|
bitfld.long 0x00 20. "B276,B276" "0,1"
|
|
bitfld.long 0x00 19. "B275,B275" "0,1"
|
|
bitfld.long 0x00 18. "B274,B274" "0,1"
|
|
bitfld.long 0x00 17. "B273,B273" "0,1"
|
|
bitfld.long 0x00 16. "B272,B272" "0,1"
|
|
bitfld.long 0x00 15. "B271,B271" "0,1"
|
|
bitfld.long 0x00 14. "B270,B270" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B269,B269" "0,1"
|
|
bitfld.long 0x00 12. "B268,B268" "0,1"
|
|
bitfld.long 0x00 11. "B267,B267" "0,1"
|
|
bitfld.long 0x00 10. "B266,B266" "0,1"
|
|
bitfld.long 0x00 9. "B265,B265" "0,1"
|
|
bitfld.long 0x00 8. "B264,B264" "0,1"
|
|
bitfld.long 0x00 7. "B263,B263" "0,1"
|
|
bitfld.long 0x00 6. "B262,B262" "0,1"
|
|
bitfld.long 0x00 5. "B261,B261" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B260,B260" "0,1"
|
|
bitfld.long 0x00 3. "B259,B259" "0,1"
|
|
bitfld.long 0x00 2. "B258,B258" "0,1"
|
|
bitfld.long 0x00 1. "B257,B257" "0,1"
|
|
bitfld.long 0x00 0. "B256,B256" "0,1"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MPCBB2_VCTR9,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B319,B319" "0,1"
|
|
bitfld.long 0x00 30. "B318,B318" "0,1"
|
|
bitfld.long 0x00 29. "B317,B317" "0,1"
|
|
bitfld.long 0x00 28. "B316,B316" "0,1"
|
|
bitfld.long 0x00 27. "B315,B315" "0,1"
|
|
bitfld.long 0x00 26. "B314,B314" "0,1"
|
|
bitfld.long 0x00 25. "B313,B313" "0,1"
|
|
bitfld.long 0x00 24. "B312,B312" "0,1"
|
|
bitfld.long 0x00 23. "B311,B311" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B310,B310" "0,1"
|
|
bitfld.long 0x00 21. "B309,B309" "0,1"
|
|
bitfld.long 0x00 20. "B308,B308" "0,1"
|
|
bitfld.long 0x00 19. "B307,B307" "0,1"
|
|
bitfld.long 0x00 18. "B306,B306" "0,1"
|
|
bitfld.long 0x00 17. "B305,B305" "0,1"
|
|
bitfld.long 0x00 16. "B304,B304" "0,1"
|
|
bitfld.long 0x00 15. "B303,B303" "0,1"
|
|
bitfld.long 0x00 14. "B302,B302" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B301,B301" "0,1"
|
|
bitfld.long 0x00 12. "B300,B300" "0,1"
|
|
bitfld.long 0x00 11. "B299,B299" "0,1"
|
|
bitfld.long 0x00 10. "B298,B298" "0,1"
|
|
bitfld.long 0x00 9. "B297,B297" "0,1"
|
|
bitfld.long 0x00 8. "B296,B296" "0,1"
|
|
bitfld.long 0x00 7. "B295,B295" "0,1"
|
|
bitfld.long 0x00 6. "B294,B294" "0,1"
|
|
bitfld.long 0x00 5. "B293,B293" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B292,B292" "0,1"
|
|
bitfld.long 0x00 3. "B291,B291" "0,1"
|
|
bitfld.long 0x00 2. "B290,B290" "0,1"
|
|
bitfld.long 0x00 1. "B289,B289" "0,1"
|
|
bitfld.long 0x00 0. "B288,B288" "0,1"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "MPCBB2_VCTR10,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B351,B351" "0,1"
|
|
bitfld.long 0x00 30. "B350,B350" "0,1"
|
|
bitfld.long 0x00 29. "B349,B349" "0,1"
|
|
bitfld.long 0x00 28. "B348,B348" "0,1"
|
|
bitfld.long 0x00 27. "B347,B347" "0,1"
|
|
bitfld.long 0x00 26. "B346,B346" "0,1"
|
|
bitfld.long 0x00 25. "B345,B345" "0,1"
|
|
bitfld.long 0x00 24. "B344,B344" "0,1"
|
|
bitfld.long 0x00 23. "B343,B343" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B342,B342" "0,1"
|
|
bitfld.long 0x00 21. "B341,B341" "0,1"
|
|
bitfld.long 0x00 20. "B340,B340" "0,1"
|
|
bitfld.long 0x00 19. "B339,B339" "0,1"
|
|
bitfld.long 0x00 18. "B338,B338" "0,1"
|
|
bitfld.long 0x00 17. "B337,B337" "0,1"
|
|
bitfld.long 0x00 16. "B336,B336" "0,1"
|
|
bitfld.long 0x00 15. "B335,B335" "0,1"
|
|
bitfld.long 0x00 14. "B334,B334" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B333,B333" "0,1"
|
|
bitfld.long 0x00 12. "B332,B332" "0,1"
|
|
bitfld.long 0x00 11. "B331,B331" "0,1"
|
|
bitfld.long 0x00 10. "B330,B330" "0,1"
|
|
bitfld.long 0x00 9. "B329,B329" "0,1"
|
|
bitfld.long 0x00 8. "B328,B328" "0,1"
|
|
bitfld.long 0x00 7. "B327,B327" "0,1"
|
|
bitfld.long 0x00 6. "B326,B326" "0,1"
|
|
bitfld.long 0x00 5. "B325,B325" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B324,B324" "0,1"
|
|
bitfld.long 0x00 3. "B323,B323" "0,1"
|
|
bitfld.long 0x00 2. "B322,B322" "0,1"
|
|
bitfld.long 0x00 1. "B321,B321" "0,1"
|
|
bitfld.long 0x00 0. "B320,B320" "0,1"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR11,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B383,B383" "0,1"
|
|
bitfld.long 0x00 30. "B382,B382" "0,1"
|
|
bitfld.long 0x00 29. "B381,B381" "0,1"
|
|
bitfld.long 0x00 28. "B380,B380" "0,1"
|
|
bitfld.long 0x00 27. "B379,B379" "0,1"
|
|
bitfld.long 0x00 26. "B378,B378" "0,1"
|
|
bitfld.long 0x00 25. "B377,B377" "0,1"
|
|
bitfld.long 0x00 24. "B376,B376" "0,1"
|
|
bitfld.long 0x00 23. "B375,B375" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B374,B374" "0,1"
|
|
bitfld.long 0x00 21. "B373,B373" "0,1"
|
|
bitfld.long 0x00 20. "B372,B372" "0,1"
|
|
bitfld.long 0x00 19. "B371,B371" "0,1"
|
|
bitfld.long 0x00 18. "B370,B370" "0,1"
|
|
bitfld.long 0x00 17. "B369,B369" "0,1"
|
|
bitfld.long 0x00 16. "B368,B368" "0,1"
|
|
bitfld.long 0x00 15. "B367,B367" "0,1"
|
|
bitfld.long 0x00 14. "B366,B366" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B365,B365" "0,1"
|
|
bitfld.long 0x00 12. "B364,B364" "0,1"
|
|
bitfld.long 0x00 11. "B363,B363" "0,1"
|
|
bitfld.long 0x00 10. "B362,B362" "0,1"
|
|
bitfld.long 0x00 9. "B361,B361" "0,1"
|
|
bitfld.long 0x00 8. "B360,B360" "0,1"
|
|
bitfld.long 0x00 7. "B359,B359" "0,1"
|
|
bitfld.long 0x00 6. "B358,B358" "0,1"
|
|
bitfld.long 0x00 5. "B357,B357" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B356,B356" "0,1"
|
|
bitfld.long 0x00 3. "B355,B355" "0,1"
|
|
bitfld.long 0x00 2. "B354,B354" "0,1"
|
|
bitfld.long 0x00 1. "B353,B353" "0,1"
|
|
bitfld.long 0x00 0. "B352,B352" "0,1"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "MPCBB2_VCTR12,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B415,B415" "0,1"
|
|
bitfld.long 0x00 30. "B414,B414" "0,1"
|
|
bitfld.long 0x00 29. "B413,B413" "0,1"
|
|
bitfld.long 0x00 28. "B412,B412" "0,1"
|
|
bitfld.long 0x00 27. "B411,B411" "0,1"
|
|
bitfld.long 0x00 26. "B410,B410" "0,1"
|
|
bitfld.long 0x00 25. "B409,B409" "0,1"
|
|
bitfld.long 0x00 24. "B408,B408" "0,1"
|
|
bitfld.long 0x00 23. "B407,B407" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B406,B406" "0,1"
|
|
bitfld.long 0x00 21. "B405,B405" "0,1"
|
|
bitfld.long 0x00 20. "B404,B404" "0,1"
|
|
bitfld.long 0x00 19. "B403,B403" "0,1"
|
|
bitfld.long 0x00 18. "B402,B402" "0,1"
|
|
bitfld.long 0x00 17. "B401,B401" "0,1"
|
|
bitfld.long 0x00 16. "B400,B400" "0,1"
|
|
bitfld.long 0x00 15. "B399,B399" "0,1"
|
|
bitfld.long 0x00 14. "B398,B398" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B397,B397" "0,1"
|
|
bitfld.long 0x00 12. "B396,B396" "0,1"
|
|
bitfld.long 0x00 11. "B395,B395" "0,1"
|
|
bitfld.long 0x00 10. "B394,B394" "0,1"
|
|
bitfld.long 0x00 9. "B393,B393" "0,1"
|
|
bitfld.long 0x00 8. "B392,B392" "0,1"
|
|
bitfld.long 0x00 7. "B391,B391" "0,1"
|
|
bitfld.long 0x00 6. "B390,B390" "0,1"
|
|
bitfld.long 0x00 5. "B389,B389" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B388,B388" "0,1"
|
|
bitfld.long 0x00 3. "B387,B387" "0,1"
|
|
bitfld.long 0x00 2. "B386,B386" "0,1"
|
|
bitfld.long 0x00 1. "B385,B385" "0,1"
|
|
bitfld.long 0x00 0. "B384,B384" "0,1"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "MPCBB2_VCTR13,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B447,B447" "0,1"
|
|
bitfld.long 0x00 30. "B446,B446" "0,1"
|
|
bitfld.long 0x00 29. "B445,B445" "0,1"
|
|
bitfld.long 0x00 28. "B444,B444" "0,1"
|
|
bitfld.long 0x00 27. "B443,B443" "0,1"
|
|
bitfld.long 0x00 26. "B442,B442" "0,1"
|
|
bitfld.long 0x00 25. "B441,B441" "0,1"
|
|
bitfld.long 0x00 24. "B440,B440" "0,1"
|
|
bitfld.long 0x00 23. "B439,B439" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B438,B438" "0,1"
|
|
bitfld.long 0x00 21. "B437,B437" "0,1"
|
|
bitfld.long 0x00 20. "B436,B436" "0,1"
|
|
bitfld.long 0x00 19. "B435,B435" "0,1"
|
|
bitfld.long 0x00 18. "B434,B434" "0,1"
|
|
bitfld.long 0x00 17. "B433,B433" "0,1"
|
|
bitfld.long 0x00 16. "B432,B432" "0,1"
|
|
bitfld.long 0x00 15. "B431,B431" "0,1"
|
|
bitfld.long 0x00 14. "B430,B430" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B429,B429" "0,1"
|
|
bitfld.long 0x00 12. "B428,B428" "0,1"
|
|
bitfld.long 0x00 11. "B427,B427" "0,1"
|
|
bitfld.long 0x00 10. "B426,B426" "0,1"
|
|
bitfld.long 0x00 9. "B425,B425" "0,1"
|
|
bitfld.long 0x00 8. "B424,B424" "0,1"
|
|
bitfld.long 0x00 7. "B423,B423" "0,1"
|
|
bitfld.long 0x00 6. "B422,B422" "0,1"
|
|
bitfld.long 0x00 5. "B421,B421" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B420,B420" "0,1"
|
|
bitfld.long 0x00 3. "B419,B419" "0,1"
|
|
bitfld.long 0x00 2. "B418,B418" "0,1"
|
|
bitfld.long 0x00 1. "B417,B417" "0,1"
|
|
bitfld.long 0x00 0. "B416,B416" "0,1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "MPCBB2_VCTR14,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B479,B479" "0,1"
|
|
bitfld.long 0x00 30. "B478,B478" "0,1"
|
|
bitfld.long 0x00 29. "B477,B477" "0,1"
|
|
bitfld.long 0x00 28. "B476,B476" "0,1"
|
|
bitfld.long 0x00 27. "B475,B475" "0,1"
|
|
bitfld.long 0x00 26. "B474,B474" "0,1"
|
|
bitfld.long 0x00 25. "B473,B473" "0,1"
|
|
bitfld.long 0x00 24. "B472,B472" "0,1"
|
|
bitfld.long 0x00 23. "B471,B471" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B470,B470" "0,1"
|
|
bitfld.long 0x00 21. "B469,B469" "0,1"
|
|
bitfld.long 0x00 20. "B468,B468" "0,1"
|
|
bitfld.long 0x00 19. "B467,B467" "0,1"
|
|
bitfld.long 0x00 18. "B466,B466" "0,1"
|
|
bitfld.long 0x00 17. "B465,B465" "0,1"
|
|
bitfld.long 0x00 16. "B464,B464" "0,1"
|
|
bitfld.long 0x00 15. "B463,B463" "0,1"
|
|
bitfld.long 0x00 14. "B462,B462" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B461,B461" "0,1"
|
|
bitfld.long 0x00 12. "B460,B460" "0,1"
|
|
bitfld.long 0x00 11. "B459,B459" "0,1"
|
|
bitfld.long 0x00 10. "B458,B458" "0,1"
|
|
bitfld.long 0x00 9. "B457,B457" "0,1"
|
|
bitfld.long 0x00 8. "B456,B456" "0,1"
|
|
bitfld.long 0x00 7. "B455,B455" "0,1"
|
|
bitfld.long 0x00 6. "B454,B454" "0,1"
|
|
bitfld.long 0x00 5. "B453,B453" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B452,B452" "0,1"
|
|
bitfld.long 0x00 3. "B451,B451" "0,1"
|
|
bitfld.long 0x00 2. "B450,B450" "0,1"
|
|
bitfld.long 0x00 1. "B449,B449" "0,1"
|
|
bitfld.long 0x00 0. "B448,B448" "0,1"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR15,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B511,B511" "0,1"
|
|
bitfld.long 0x00 30. "B510,B510" "0,1"
|
|
bitfld.long 0x00 29. "B509,B509" "0,1"
|
|
bitfld.long 0x00 28. "B508,B508" "0,1"
|
|
bitfld.long 0x00 27. "B507,B507" "0,1"
|
|
bitfld.long 0x00 26. "B506,B506" "0,1"
|
|
bitfld.long 0x00 25. "B505,B505" "0,1"
|
|
bitfld.long 0x00 24. "B504,B504" "0,1"
|
|
bitfld.long 0x00 23. "B503,B503" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B502,B502" "0,1"
|
|
bitfld.long 0x00 21. "B501,B501" "0,1"
|
|
bitfld.long 0x00 20. "B500,B500" "0,1"
|
|
bitfld.long 0x00 19. "B499,B499" "0,1"
|
|
bitfld.long 0x00 18. "B498,B498" "0,1"
|
|
bitfld.long 0x00 17. "B497,B497" "0,1"
|
|
bitfld.long 0x00 16. "B496,B496" "0,1"
|
|
bitfld.long 0x00 15. "B495,B495" "0,1"
|
|
bitfld.long 0x00 14. "B494,B494" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B493,B493" "0,1"
|
|
bitfld.long 0x00 12. "B492,B492" "0,1"
|
|
bitfld.long 0x00 11. "B491,B491" "0,1"
|
|
bitfld.long 0x00 10. "B490,B490" "0,1"
|
|
bitfld.long 0x00 9. "B489,B489" "0,1"
|
|
bitfld.long 0x00 8. "B488,B488" "0,1"
|
|
bitfld.long 0x00 7. "B487,B487" "0,1"
|
|
bitfld.long 0x00 6. "B486,B486" "0,1"
|
|
bitfld.long 0x00 5. "B485,B485" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B484,B484" "0,1"
|
|
bitfld.long 0x00 3. "B483,B483" "0,1"
|
|
bitfld.long 0x00 2. "B482,B482" "0,1"
|
|
bitfld.long 0x00 1. "B481,B481" "0,1"
|
|
bitfld.long 0x00 0. "B480,B480" "0,1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "MPCBB2_VCTR16,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B543,B543" "0,1"
|
|
bitfld.long 0x00 30. "B542,B542" "0,1"
|
|
bitfld.long 0x00 29. "B541,B541" "0,1"
|
|
bitfld.long 0x00 28. "B540,B540" "0,1"
|
|
bitfld.long 0x00 27. "B539,B539" "0,1"
|
|
bitfld.long 0x00 26. "B538,B538" "0,1"
|
|
bitfld.long 0x00 25. "B537,B537" "0,1"
|
|
bitfld.long 0x00 24. "B536,B536" "0,1"
|
|
bitfld.long 0x00 23. "B535,B535" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B534,B534" "0,1"
|
|
bitfld.long 0x00 21. "B533,B533" "0,1"
|
|
bitfld.long 0x00 20. "B532,B532" "0,1"
|
|
bitfld.long 0x00 19. "B531,B531" "0,1"
|
|
bitfld.long 0x00 18. "B530,B530" "0,1"
|
|
bitfld.long 0x00 17. "B529,B529" "0,1"
|
|
bitfld.long 0x00 16. "B528,B528" "0,1"
|
|
bitfld.long 0x00 15. "B527,B527" "0,1"
|
|
bitfld.long 0x00 14. "B526,B526" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B525,B525" "0,1"
|
|
bitfld.long 0x00 12. "B524,B524" "0,1"
|
|
bitfld.long 0x00 11. "B523,B523" "0,1"
|
|
bitfld.long 0x00 10. "B522,B522" "0,1"
|
|
bitfld.long 0x00 9. "B521,B521" "0,1"
|
|
bitfld.long 0x00 8. "B520,B520" "0,1"
|
|
bitfld.long 0x00 7. "B519,B519" "0,1"
|
|
bitfld.long 0x00 6. "B518,B518" "0,1"
|
|
bitfld.long 0x00 5. "B517,B517" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B516,B516" "0,1"
|
|
bitfld.long 0x00 3. "B515,B515" "0,1"
|
|
bitfld.long 0x00 2. "B514,B514" "0,1"
|
|
bitfld.long 0x00 1. "B513,B513" "0,1"
|
|
bitfld.long 0x00 0. "B512,B512" "0,1"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "MPCBB2_VCTR17,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B575,B575" "0,1"
|
|
bitfld.long 0x00 30. "B574,B574" "0,1"
|
|
bitfld.long 0x00 29. "B573,B573" "0,1"
|
|
bitfld.long 0x00 28. "B572,B572" "0,1"
|
|
bitfld.long 0x00 27. "B571,B571" "0,1"
|
|
bitfld.long 0x00 26. "B570,B570" "0,1"
|
|
bitfld.long 0x00 25. "B569,B569" "0,1"
|
|
bitfld.long 0x00 24. "B568,B568" "0,1"
|
|
bitfld.long 0x00 23. "B567,B567" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B566,B566" "0,1"
|
|
bitfld.long 0x00 21. "B565,B565" "0,1"
|
|
bitfld.long 0x00 20. "B564,B564" "0,1"
|
|
bitfld.long 0x00 19. "B563,B563" "0,1"
|
|
bitfld.long 0x00 18. "B562,B562" "0,1"
|
|
bitfld.long 0x00 17. "B561,B561" "0,1"
|
|
bitfld.long 0x00 16. "B560,B560" "0,1"
|
|
bitfld.long 0x00 15. "B559,B559" "0,1"
|
|
bitfld.long 0x00 14. "B558,B558" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B557,B557" "0,1"
|
|
bitfld.long 0x00 12. "B556,B556" "0,1"
|
|
bitfld.long 0x00 11. "B555,B555" "0,1"
|
|
bitfld.long 0x00 10. "B554,B554" "0,1"
|
|
bitfld.long 0x00 9. "B553,B553" "0,1"
|
|
bitfld.long 0x00 8. "B552,B552" "0,1"
|
|
bitfld.long 0x00 7. "B551,B551" "0,1"
|
|
bitfld.long 0x00 6. "B550,B550" "0,1"
|
|
bitfld.long 0x00 5. "B549,B549" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B548,B548" "0,1"
|
|
bitfld.long 0x00 3. "B547,B547" "0,1"
|
|
bitfld.long 0x00 2. "B546,B546" "0,1"
|
|
bitfld.long 0x00 1. "B545,B545" "0,1"
|
|
bitfld.long 0x00 0. "B544,B544" "0,1"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "MPCBB2_VCTR18,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B607,B607" "0,1"
|
|
bitfld.long 0x00 30. "B606,B606" "0,1"
|
|
bitfld.long 0x00 29. "B605,B605" "0,1"
|
|
bitfld.long 0x00 28. "B604,B604" "0,1"
|
|
bitfld.long 0x00 27. "B603,B603" "0,1"
|
|
bitfld.long 0x00 26. "B602,B602" "0,1"
|
|
bitfld.long 0x00 25. "B601,B601" "0,1"
|
|
bitfld.long 0x00 24. "B600,B600" "0,1"
|
|
bitfld.long 0x00 23. "B599,B599" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B598,B598" "0,1"
|
|
bitfld.long 0x00 21. "B597,B597" "0,1"
|
|
bitfld.long 0x00 20. "B596,B596" "0,1"
|
|
bitfld.long 0x00 19. "B595,B595" "0,1"
|
|
bitfld.long 0x00 18. "B594,B594" "0,1"
|
|
bitfld.long 0x00 17. "B593,B593" "0,1"
|
|
bitfld.long 0x00 16. "B592,B592" "0,1"
|
|
bitfld.long 0x00 15. "B591,B591" "0,1"
|
|
bitfld.long 0x00 14. "B590,B590" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B589,B589" "0,1"
|
|
bitfld.long 0x00 12. "B588,B588" "0,1"
|
|
bitfld.long 0x00 11. "B587,B587" "0,1"
|
|
bitfld.long 0x00 10. "B586,B586" "0,1"
|
|
bitfld.long 0x00 9. "B585,B585" "0,1"
|
|
bitfld.long 0x00 8. "B584,B584" "0,1"
|
|
bitfld.long 0x00 7. "B583,B583" "0,1"
|
|
bitfld.long 0x00 6. "B582,B582" "0,1"
|
|
bitfld.long 0x00 5. "B581,B581" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B580,B580" "0,1"
|
|
bitfld.long 0x00 3. "B579,B579" "0,1"
|
|
bitfld.long 0x00 2. "B578,B578" "0,1"
|
|
bitfld.long 0x00 1. "B577,B577" "0,1"
|
|
bitfld.long 0x00 0. "B576,B576" "0,1"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR19,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B639,B639" "0,1"
|
|
bitfld.long 0x00 30. "B638,B638" "0,1"
|
|
bitfld.long 0x00 29. "B637,B637" "0,1"
|
|
bitfld.long 0x00 28. "B636,B636" "0,1"
|
|
bitfld.long 0x00 27. "B635,B635" "0,1"
|
|
bitfld.long 0x00 26. "B634,B634" "0,1"
|
|
bitfld.long 0x00 25. "B633,B633" "0,1"
|
|
bitfld.long 0x00 24. "B632,B632" "0,1"
|
|
bitfld.long 0x00 23. "B631,B631" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B630,B630" "0,1"
|
|
bitfld.long 0x00 21. "B629,B629" "0,1"
|
|
bitfld.long 0x00 20. "B628,B628" "0,1"
|
|
bitfld.long 0x00 19. "B627,B627" "0,1"
|
|
bitfld.long 0x00 18. "B626,B626" "0,1"
|
|
bitfld.long 0x00 17. "B625,B625" "0,1"
|
|
bitfld.long 0x00 16. "B624,B624" "0,1"
|
|
bitfld.long 0x00 15. "B623,B623" "0,1"
|
|
bitfld.long 0x00 14. "B622,B622" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B621,B621" "0,1"
|
|
bitfld.long 0x00 12. "B620,B620" "0,1"
|
|
bitfld.long 0x00 11. "B619,B619" "0,1"
|
|
bitfld.long 0x00 10. "B618,B618" "0,1"
|
|
bitfld.long 0x00 9. "B617,B617" "0,1"
|
|
bitfld.long 0x00 8. "B616,B616" "0,1"
|
|
bitfld.long 0x00 7. "B615,B615" "0,1"
|
|
bitfld.long 0x00 6. "B614,B614" "0,1"
|
|
bitfld.long 0x00 5. "B613,B613" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B612,B612" "0,1"
|
|
bitfld.long 0x00 3. "B611,B611" "0,1"
|
|
bitfld.long 0x00 2. "B610,B610" "0,1"
|
|
bitfld.long 0x00 1. "B609,B609" "0,1"
|
|
bitfld.long 0x00 0. "B608,B608" "0,1"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "MPCBB2_VCTR20,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B671,B671" "0,1"
|
|
bitfld.long 0x00 30. "B670,B670" "0,1"
|
|
bitfld.long 0x00 29. "B669,B669" "0,1"
|
|
bitfld.long 0x00 28. "B668,B668" "0,1"
|
|
bitfld.long 0x00 27. "B667,B667" "0,1"
|
|
bitfld.long 0x00 26. "B666,B666" "0,1"
|
|
bitfld.long 0x00 25. "B665,B665" "0,1"
|
|
bitfld.long 0x00 24. "B664,B664" "0,1"
|
|
bitfld.long 0x00 23. "B663,B663" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B662,B662" "0,1"
|
|
bitfld.long 0x00 21. "B661,B661" "0,1"
|
|
bitfld.long 0x00 20. "B660,B660" "0,1"
|
|
bitfld.long 0x00 19. "B659,B659" "0,1"
|
|
bitfld.long 0x00 18. "B658,B658" "0,1"
|
|
bitfld.long 0x00 17. "B657,B657" "0,1"
|
|
bitfld.long 0x00 16. "B656,B656" "0,1"
|
|
bitfld.long 0x00 15. "B655,B655" "0,1"
|
|
bitfld.long 0x00 14. "B654,B654" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B653,B653" "0,1"
|
|
bitfld.long 0x00 12. "B652,B652" "0,1"
|
|
bitfld.long 0x00 11. "B651,B651" "0,1"
|
|
bitfld.long 0x00 10. "B650,B650" "0,1"
|
|
bitfld.long 0x00 9. "B649,B649" "0,1"
|
|
bitfld.long 0x00 8. "B648,B648" "0,1"
|
|
bitfld.long 0x00 7. "B647,B647" "0,1"
|
|
bitfld.long 0x00 6. "B646,B646" "0,1"
|
|
bitfld.long 0x00 5. "B645,B645" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B644,B644" "0,1"
|
|
bitfld.long 0x00 3. "B643,B643" "0,1"
|
|
bitfld.long 0x00 2. "B642,B642" "0,1"
|
|
bitfld.long 0x00 1. "B641,B641" "0,1"
|
|
bitfld.long 0x00 0. "B640,B640" "0,1"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "MPCBB2_VCTR21,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B703,B703" "0,1"
|
|
bitfld.long 0x00 30. "B702,B702" "0,1"
|
|
bitfld.long 0x00 29. "B701,B701" "0,1"
|
|
bitfld.long 0x00 28. "B700,B700" "0,1"
|
|
bitfld.long 0x00 27. "B699,B699" "0,1"
|
|
bitfld.long 0x00 26. "B698,B698" "0,1"
|
|
bitfld.long 0x00 25. "B697,B697" "0,1"
|
|
bitfld.long 0x00 24. "B696,B696" "0,1"
|
|
bitfld.long 0x00 23. "B695,B695" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B694,B694" "0,1"
|
|
bitfld.long 0x00 21. "B693,B693" "0,1"
|
|
bitfld.long 0x00 20. "B692,B692" "0,1"
|
|
bitfld.long 0x00 19. "B691,B691" "0,1"
|
|
bitfld.long 0x00 18. "B690,B690" "0,1"
|
|
bitfld.long 0x00 17. "B689,B689" "0,1"
|
|
bitfld.long 0x00 16. "B688,B688" "0,1"
|
|
bitfld.long 0x00 15. "B687,B687" "0,1"
|
|
bitfld.long 0x00 14. "B686,B686" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B685,B685" "0,1"
|
|
bitfld.long 0x00 12. "B684,B684" "0,1"
|
|
bitfld.long 0x00 11. "B683,B683" "0,1"
|
|
bitfld.long 0x00 10. "B682,B682" "0,1"
|
|
bitfld.long 0x00 9. "B681,B681" "0,1"
|
|
bitfld.long 0x00 8. "B680,B680" "0,1"
|
|
bitfld.long 0x00 7. "B679,B679" "0,1"
|
|
bitfld.long 0x00 6. "B678,B678" "0,1"
|
|
bitfld.long 0x00 5. "B677,B677" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B676,B676" "0,1"
|
|
bitfld.long 0x00 3. "B675,B675" "0,1"
|
|
bitfld.long 0x00 2. "B674,B674" "0,1"
|
|
bitfld.long 0x00 1. "B673,B673" "0,1"
|
|
bitfld.long 0x00 0. "B672,B672" "0,1"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "MPCBB2_VCTR22,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B735,B735" "0,1"
|
|
bitfld.long 0x00 30. "B734,B734" "0,1"
|
|
bitfld.long 0x00 29. "B733,B733" "0,1"
|
|
bitfld.long 0x00 28. "B732,B732" "0,1"
|
|
bitfld.long 0x00 27. "B731,B731" "0,1"
|
|
bitfld.long 0x00 26. "B730,B730" "0,1"
|
|
bitfld.long 0x00 25. "B729,B729" "0,1"
|
|
bitfld.long 0x00 24. "B728,B728" "0,1"
|
|
bitfld.long 0x00 23. "B727,B727" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B726,B726" "0,1"
|
|
bitfld.long 0x00 21. "B725,B725" "0,1"
|
|
bitfld.long 0x00 20. "B724,B724" "0,1"
|
|
bitfld.long 0x00 19. "B723,B723" "0,1"
|
|
bitfld.long 0x00 18. "B722,B722" "0,1"
|
|
bitfld.long 0x00 17. "B721,B721" "0,1"
|
|
bitfld.long 0x00 16. "B720,B720" "0,1"
|
|
bitfld.long 0x00 15. "B719,B719" "0,1"
|
|
bitfld.long 0x00 14. "B718,B718" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B717,B717" "0,1"
|
|
bitfld.long 0x00 12. "B716,B716" "0,1"
|
|
bitfld.long 0x00 11. "B715,B715" "0,1"
|
|
bitfld.long 0x00 10. "B714,B714" "0,1"
|
|
bitfld.long 0x00 9. "B713,B713" "0,1"
|
|
bitfld.long 0x00 8. "B712,B712" "0,1"
|
|
bitfld.long 0x00 7. "B711,B711" "0,1"
|
|
bitfld.long 0x00 6. "B710,B710" "0,1"
|
|
bitfld.long 0x00 5. "B709,B709" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B708,B708" "0,1"
|
|
bitfld.long 0x00 3. "B707,B707" "0,1"
|
|
bitfld.long 0x00 2. "B706,B706" "0,1"
|
|
bitfld.long 0x00 1. "B705,B705" "0,1"
|
|
bitfld.long 0x00 0. "B704,B704" "0,1"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR23,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B767,B767" "0,1"
|
|
bitfld.long 0x00 30. "B766,B766" "0,1"
|
|
bitfld.long 0x00 29. "B765,B765" "0,1"
|
|
bitfld.long 0x00 28. "B764,B764" "0,1"
|
|
bitfld.long 0x00 27. "B763,B763" "0,1"
|
|
bitfld.long 0x00 26. "B762,B762" "0,1"
|
|
bitfld.long 0x00 25. "B761,B761" "0,1"
|
|
bitfld.long 0x00 24. "B760,B760" "0,1"
|
|
bitfld.long 0x00 23. "B759,B759" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B758,B758" "0,1"
|
|
bitfld.long 0x00 21. "B757,B757" "0,1"
|
|
bitfld.long 0x00 20. "B756,B756" "0,1"
|
|
bitfld.long 0x00 19. "B755,B755" "0,1"
|
|
bitfld.long 0x00 18. "B754,B754" "0,1"
|
|
bitfld.long 0x00 17. "B753,B753" "0,1"
|
|
bitfld.long 0x00 16. "B752,B752" "0,1"
|
|
bitfld.long 0x00 15. "B751,B751" "0,1"
|
|
bitfld.long 0x00 14. "B750,B750" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B749,B749" "0,1"
|
|
bitfld.long 0x00 12. "B748,B748" "0,1"
|
|
bitfld.long 0x00 11. "B747,B747" "0,1"
|
|
bitfld.long 0x00 10. "B746,B746" "0,1"
|
|
bitfld.long 0x00 9. "B745,B745" "0,1"
|
|
bitfld.long 0x00 8. "B744,B744" "0,1"
|
|
bitfld.long 0x00 7. "B743,B743" "0,1"
|
|
bitfld.long 0x00 6. "B742,B742" "0,1"
|
|
bitfld.long 0x00 5. "B741,B741" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B740,B740" "0,1"
|
|
bitfld.long 0x00 3. "B739,B739" "0,1"
|
|
bitfld.long 0x00 2. "B738,B738" "0,1"
|
|
bitfld.long 0x00 1. "B737,B737" "0,1"
|
|
bitfld.long 0x00 0. "B736,B736" "0,1"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "MPCBB2_VCTR24,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B799,B799" "0,1"
|
|
bitfld.long 0x00 30. "B798,B798" "0,1"
|
|
bitfld.long 0x00 29. "B797,B797" "0,1"
|
|
bitfld.long 0x00 28. "B796,B796" "0,1"
|
|
bitfld.long 0x00 27. "B795,B795" "0,1"
|
|
bitfld.long 0x00 26. "B794,B794" "0,1"
|
|
bitfld.long 0x00 25. "B793,B793" "0,1"
|
|
bitfld.long 0x00 24. "B792,B792" "0,1"
|
|
bitfld.long 0x00 23. "B791,B791" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B790,B790" "0,1"
|
|
bitfld.long 0x00 21. "B789,B789" "0,1"
|
|
bitfld.long 0x00 20. "B788,B788" "0,1"
|
|
bitfld.long 0x00 19. "B787,B787" "0,1"
|
|
bitfld.long 0x00 18. "B786,B786" "0,1"
|
|
bitfld.long 0x00 17. "B785,B785" "0,1"
|
|
bitfld.long 0x00 16. "B784,B784" "0,1"
|
|
bitfld.long 0x00 15. "B783,B783" "0,1"
|
|
bitfld.long 0x00 14. "B782,B782" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B781,B781" "0,1"
|
|
bitfld.long 0x00 12. "B780,B780" "0,1"
|
|
bitfld.long 0x00 11. "B779,B779" "0,1"
|
|
bitfld.long 0x00 10. "B778,B778" "0,1"
|
|
bitfld.long 0x00 9. "B777,B777" "0,1"
|
|
bitfld.long 0x00 8. "B776,B776" "0,1"
|
|
bitfld.long 0x00 7. "B775,B775" "0,1"
|
|
bitfld.long 0x00 6. "B774,B774" "0,1"
|
|
bitfld.long 0x00 5. "B773,B773" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B772,B772" "0,1"
|
|
bitfld.long 0x00 3. "B771,B771" "0,1"
|
|
bitfld.long 0x00 2. "B770,B770" "0,1"
|
|
bitfld.long 0x00 1. "B769,B769" "0,1"
|
|
bitfld.long 0x00 0. "B768,B768" "0,1"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "MPCBB2_VCTR25,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B831,B831" "0,1"
|
|
bitfld.long 0x00 30. "B830,B830" "0,1"
|
|
bitfld.long 0x00 29. "B829,B829" "0,1"
|
|
bitfld.long 0x00 28. "B828,B828" "0,1"
|
|
bitfld.long 0x00 27. "B827,B827" "0,1"
|
|
bitfld.long 0x00 26. "B826,B826" "0,1"
|
|
bitfld.long 0x00 25. "B825,B825" "0,1"
|
|
bitfld.long 0x00 24. "B824,B824" "0,1"
|
|
bitfld.long 0x00 23. "B823,B823" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B822,B822" "0,1"
|
|
bitfld.long 0x00 21. "B821,B821" "0,1"
|
|
bitfld.long 0x00 20. "B820,B820" "0,1"
|
|
bitfld.long 0x00 19. "B819,B819" "0,1"
|
|
bitfld.long 0x00 18. "B818,B818" "0,1"
|
|
bitfld.long 0x00 17. "B817,B817" "0,1"
|
|
bitfld.long 0x00 16. "B816,B816" "0,1"
|
|
bitfld.long 0x00 15. "B815,B815" "0,1"
|
|
bitfld.long 0x00 14. "B814,B814" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B813,B813" "0,1"
|
|
bitfld.long 0x00 12. "B812,B812" "0,1"
|
|
bitfld.long 0x00 11. "B811,B811" "0,1"
|
|
bitfld.long 0x00 10. "B810,B810" "0,1"
|
|
bitfld.long 0x00 9. "B809,B809" "0,1"
|
|
bitfld.long 0x00 8. "B808,B808" "0,1"
|
|
bitfld.long 0x00 7. "B807,B807" "0,1"
|
|
bitfld.long 0x00 6. "B806,B806" "0,1"
|
|
bitfld.long 0x00 5. "B805,B805" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B804,B804" "0,1"
|
|
bitfld.long 0x00 3. "B803,B803" "0,1"
|
|
bitfld.long 0x00 2. "B802,B802" "0,1"
|
|
bitfld.long 0x00 1. "B801,B801" "0,1"
|
|
bitfld.long 0x00 0. "B800,B800" "0,1"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "MPCBB2_VCTR26,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B863,B863" "0,1"
|
|
bitfld.long 0x00 30. "B862,B862" "0,1"
|
|
bitfld.long 0x00 29. "B861,B861" "0,1"
|
|
bitfld.long 0x00 28. "B860,B860" "0,1"
|
|
bitfld.long 0x00 27. "B859,B859" "0,1"
|
|
bitfld.long 0x00 26. "B858,B858" "0,1"
|
|
bitfld.long 0x00 25. "B857,B857" "0,1"
|
|
bitfld.long 0x00 24. "B856,B856" "0,1"
|
|
bitfld.long 0x00 23. "B855,B855" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B854,B854" "0,1"
|
|
bitfld.long 0x00 21. "B853,B853" "0,1"
|
|
bitfld.long 0x00 20. "B852,B852" "0,1"
|
|
bitfld.long 0x00 19. "B851,B851" "0,1"
|
|
bitfld.long 0x00 18. "B850,B850" "0,1"
|
|
bitfld.long 0x00 17. "B849,B849" "0,1"
|
|
bitfld.long 0x00 16. "B848,B848" "0,1"
|
|
bitfld.long 0x00 15. "B847,B847" "0,1"
|
|
bitfld.long 0x00 14. "B846,B846" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B845,B845" "0,1"
|
|
bitfld.long 0x00 12. "B844,B844" "0,1"
|
|
bitfld.long 0x00 11. "B843,B843" "0,1"
|
|
bitfld.long 0x00 10. "B842,B842" "0,1"
|
|
bitfld.long 0x00 9. "B841,B841" "0,1"
|
|
bitfld.long 0x00 8. "B840,B840" "0,1"
|
|
bitfld.long 0x00 7. "B839,B839" "0,1"
|
|
bitfld.long 0x00 6. "B838,B838" "0,1"
|
|
bitfld.long 0x00 5. "B837,B837" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B836,B836" "0,1"
|
|
bitfld.long 0x00 3. "B835,B835" "0,1"
|
|
bitfld.long 0x00 2. "B834,B834" "0,1"
|
|
bitfld.long 0x00 1. "B833,B833" "0,1"
|
|
bitfld.long 0x00 0. "B832,B832" "0,1"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR27,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B895,B895" "0,1"
|
|
bitfld.long 0x00 30. "B894,B894" "0,1"
|
|
bitfld.long 0x00 29. "B893,B893" "0,1"
|
|
bitfld.long 0x00 28. "B892,B892" "0,1"
|
|
bitfld.long 0x00 27. "B891,B891" "0,1"
|
|
bitfld.long 0x00 26. "B890,B890" "0,1"
|
|
bitfld.long 0x00 25. "B889,B889" "0,1"
|
|
bitfld.long 0x00 24. "B888,B888" "0,1"
|
|
bitfld.long 0x00 23. "B887,B887" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B886,B886" "0,1"
|
|
bitfld.long 0x00 21. "B885,B885" "0,1"
|
|
bitfld.long 0x00 20. "B884,B884" "0,1"
|
|
bitfld.long 0x00 19. "B883,B883" "0,1"
|
|
bitfld.long 0x00 18. "B882,B882" "0,1"
|
|
bitfld.long 0x00 17. "B881,B881" "0,1"
|
|
bitfld.long 0x00 16. "B880,B880" "0,1"
|
|
bitfld.long 0x00 15. "B879,B879" "0,1"
|
|
bitfld.long 0x00 14. "B878,B878" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B877,B877" "0,1"
|
|
bitfld.long 0x00 12. "B876,B876" "0,1"
|
|
bitfld.long 0x00 11. "B875,B875" "0,1"
|
|
bitfld.long 0x00 10. "B874,B874" "0,1"
|
|
bitfld.long 0x00 9. "B873,B873" "0,1"
|
|
bitfld.long 0x00 8. "B872,B872" "0,1"
|
|
bitfld.long 0x00 7. "B871,B871" "0,1"
|
|
bitfld.long 0x00 6. "B870,B870" "0,1"
|
|
bitfld.long 0x00 5. "B869,B869" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B868,B868" "0,1"
|
|
bitfld.long 0x00 3. "B867,B867" "0,1"
|
|
bitfld.long 0x00 2. "B866,B866" "0,1"
|
|
bitfld.long 0x00 1. "B865,B865" "0,1"
|
|
bitfld.long 0x00 0. "B864,B864" "0,1"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "MPCBB2_VCTR28,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B927,B927" "0,1"
|
|
bitfld.long 0x00 30. "B926,B926" "0,1"
|
|
bitfld.long 0x00 29. "B925,B925" "0,1"
|
|
bitfld.long 0x00 28. "B924,B924" "0,1"
|
|
bitfld.long 0x00 27. "B923,B923" "0,1"
|
|
bitfld.long 0x00 26. "B922,B922" "0,1"
|
|
bitfld.long 0x00 25. "B921,B921" "0,1"
|
|
bitfld.long 0x00 24. "B920,B920" "0,1"
|
|
bitfld.long 0x00 23. "B919,B919" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B918,B918" "0,1"
|
|
bitfld.long 0x00 21. "B917,B917" "0,1"
|
|
bitfld.long 0x00 20. "B916,B916" "0,1"
|
|
bitfld.long 0x00 19. "B915,B915" "0,1"
|
|
bitfld.long 0x00 18. "B914,B914" "0,1"
|
|
bitfld.long 0x00 17. "B913,B913" "0,1"
|
|
bitfld.long 0x00 16. "B912,B912" "0,1"
|
|
bitfld.long 0x00 15. "B911,B911" "0,1"
|
|
bitfld.long 0x00 14. "B910,B910" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B909,B909" "0,1"
|
|
bitfld.long 0x00 12. "B908,B908" "0,1"
|
|
bitfld.long 0x00 11. "B907,B907" "0,1"
|
|
bitfld.long 0x00 10. "B906,B906" "0,1"
|
|
bitfld.long 0x00 9. "B905,B905" "0,1"
|
|
bitfld.long 0x00 8. "B904,B904" "0,1"
|
|
bitfld.long 0x00 7. "B903,B903" "0,1"
|
|
bitfld.long 0x00 6. "B902,B902" "0,1"
|
|
bitfld.long 0x00 5. "B901,B901" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B900,B900" "0,1"
|
|
bitfld.long 0x00 3. "B899,B899" "0,1"
|
|
bitfld.long 0x00 2. "B898,B898" "0,1"
|
|
bitfld.long 0x00 1. "B897,B897" "0,1"
|
|
bitfld.long 0x00 0. "B896,B896" "0,1"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "MPCBB2_VCTR29,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B959,B959" "0,1"
|
|
bitfld.long 0x00 30. "B958,B958" "0,1"
|
|
bitfld.long 0x00 29. "B957,B957" "0,1"
|
|
bitfld.long 0x00 28. "B956,B956" "0,1"
|
|
bitfld.long 0x00 27. "B955,B955" "0,1"
|
|
bitfld.long 0x00 26. "B954,B954" "0,1"
|
|
bitfld.long 0x00 25. "B953,B953" "0,1"
|
|
bitfld.long 0x00 24. "B952,B952" "0,1"
|
|
bitfld.long 0x00 23. "B951,B951" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B950,B950" "0,1"
|
|
bitfld.long 0x00 21. "B949,B949" "0,1"
|
|
bitfld.long 0x00 20. "B948,B948" "0,1"
|
|
bitfld.long 0x00 19. "B947,B947" "0,1"
|
|
bitfld.long 0x00 18. "B946,B946" "0,1"
|
|
bitfld.long 0x00 17. "B945,B945" "0,1"
|
|
bitfld.long 0x00 16. "B944,B944" "0,1"
|
|
bitfld.long 0x00 15. "B943,B943" "0,1"
|
|
bitfld.long 0x00 14. "B942,B942" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B941,B941" "0,1"
|
|
bitfld.long 0x00 12. "B940,B940" "0,1"
|
|
bitfld.long 0x00 11. "B939,B939" "0,1"
|
|
bitfld.long 0x00 10. "B938,B938" "0,1"
|
|
bitfld.long 0x00 9. "B937,B937" "0,1"
|
|
bitfld.long 0x00 8. "B936,B936" "0,1"
|
|
bitfld.long 0x00 7. "B935,B935" "0,1"
|
|
bitfld.long 0x00 6. "B934,B934" "0,1"
|
|
bitfld.long 0x00 5. "B933,B933" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B932,B932" "0,1"
|
|
bitfld.long 0x00 3. "B931,B931" "0,1"
|
|
bitfld.long 0x00 2. "B930,B930" "0,1"
|
|
bitfld.long 0x00 1. "B929,B929" "0,1"
|
|
bitfld.long 0x00 0. "B928,B928" "0,1"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "MPCBB2_VCTR30,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B991,B991" "0,1"
|
|
bitfld.long 0x00 30. "B990,B990" "0,1"
|
|
bitfld.long 0x00 29. "B989,B989" "0,1"
|
|
bitfld.long 0x00 28. "B988,B988" "0,1"
|
|
bitfld.long 0x00 27. "B987,B987" "0,1"
|
|
bitfld.long 0x00 26. "B986,B986" "0,1"
|
|
bitfld.long 0x00 25. "B985,B985" "0,1"
|
|
bitfld.long 0x00 24. "B984,B984" "0,1"
|
|
bitfld.long 0x00 23. "B983,B983" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B982,B982" "0,1"
|
|
bitfld.long 0x00 21. "B981,B981" "0,1"
|
|
bitfld.long 0x00 20. "B980,B980" "0,1"
|
|
bitfld.long 0x00 19. "B979,B979" "0,1"
|
|
bitfld.long 0x00 18. "B978,B978" "0,1"
|
|
bitfld.long 0x00 17. "B977,B977" "0,1"
|
|
bitfld.long 0x00 16. "B976,B976" "0,1"
|
|
bitfld.long 0x00 15. "B975,B975" "0,1"
|
|
bitfld.long 0x00 14. "B974,B974" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B973,B973" "0,1"
|
|
bitfld.long 0x00 12. "B972,B972" "0,1"
|
|
bitfld.long 0x00 11. "B971,B971" "0,1"
|
|
bitfld.long 0x00 10. "B970,B970" "0,1"
|
|
bitfld.long 0x00 9. "B969,B969" "0,1"
|
|
bitfld.long 0x00 8. "B968,B968" "0,1"
|
|
bitfld.long 0x00 7. "B967,B967" "0,1"
|
|
bitfld.long 0x00 6. "B966,B966" "0,1"
|
|
bitfld.long 0x00 5. "B965,B965" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B964,B964" "0,1"
|
|
bitfld.long 0x00 3. "B963,B963" "0,1"
|
|
bitfld.long 0x00 2. "B962,B962" "0,1"
|
|
bitfld.long 0x00 1. "B961,B961" "0,1"
|
|
bitfld.long 0x00 0. "B960,B960" "0,1"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR31,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1023,B1023" "0,1"
|
|
bitfld.long 0x00 30. "B1022,B1022" "0,1"
|
|
bitfld.long 0x00 29. "B1021,B1021" "0,1"
|
|
bitfld.long 0x00 28. "B1020,B1020" "0,1"
|
|
bitfld.long 0x00 27. "B1019,B1019" "0,1"
|
|
bitfld.long 0x00 26. "B1018,B1018" "0,1"
|
|
bitfld.long 0x00 25. "B1017,B1017" "0,1"
|
|
bitfld.long 0x00 24. "B1016,B1016" "0,1"
|
|
bitfld.long 0x00 23. "B1015,B1015" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1014,B1014" "0,1"
|
|
bitfld.long 0x00 21. "B1013,B1013" "0,1"
|
|
bitfld.long 0x00 20. "B1012,B1012" "0,1"
|
|
bitfld.long 0x00 19. "B1011,B1011" "0,1"
|
|
bitfld.long 0x00 18. "B1010,B1010" "0,1"
|
|
bitfld.long 0x00 17. "B1009,B1009" "0,1"
|
|
bitfld.long 0x00 16. "B1008,B1008" "0,1"
|
|
bitfld.long 0x00 15. "B1007,B1007" "0,1"
|
|
bitfld.long 0x00 14. "B1006,B1006" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1005,B1005" "0,1"
|
|
bitfld.long 0x00 12. "B1004,B1004" "0,1"
|
|
bitfld.long 0x00 11. "B1003,B1003" "0,1"
|
|
bitfld.long 0x00 10. "B1002,B1002" "0,1"
|
|
bitfld.long 0x00 9. "B1001,B1001" "0,1"
|
|
bitfld.long 0x00 8. "B1000,B1000" "0,1"
|
|
bitfld.long 0x00 7. "B999,B999" "0,1"
|
|
bitfld.long 0x00 6. "B998,B998" "0,1"
|
|
bitfld.long 0x00 5. "B997,B997" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B996,B996" "0,1"
|
|
bitfld.long 0x00 3. "B995,B995" "0,1"
|
|
bitfld.long 0x00 2. "B994,B994" "0,1"
|
|
bitfld.long 0x00 1. "B993,B993" "0,1"
|
|
bitfld.long 0x00 0. "B992,B992" "0,1"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "MPCBB2_VCTR32,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1055,B1055" "0,1"
|
|
bitfld.long 0x00 30. "B1054,B1054" "0,1"
|
|
bitfld.long 0x00 29. "B1053,B1053" "0,1"
|
|
bitfld.long 0x00 28. "B1052,B1052" "0,1"
|
|
bitfld.long 0x00 27. "B1051,B1051" "0,1"
|
|
bitfld.long 0x00 26. "B1050,B1050" "0,1"
|
|
bitfld.long 0x00 25. "B1049,B1049" "0,1"
|
|
bitfld.long 0x00 24. "B1048,B1048" "0,1"
|
|
bitfld.long 0x00 23. "B1047,B1047" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1046,B1046" "0,1"
|
|
bitfld.long 0x00 21. "B1045,B1045" "0,1"
|
|
bitfld.long 0x00 20. "B1044,B1044" "0,1"
|
|
bitfld.long 0x00 19. "B1043,B1043" "0,1"
|
|
bitfld.long 0x00 18. "B1042,B1042" "0,1"
|
|
bitfld.long 0x00 17. "B1041,B1041" "0,1"
|
|
bitfld.long 0x00 16. "B1040,B1040" "0,1"
|
|
bitfld.long 0x00 15. "B1039,B1039" "0,1"
|
|
bitfld.long 0x00 14. "B1038,B1038" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1037,B1037" "0,1"
|
|
bitfld.long 0x00 12. "B1036,B1036" "0,1"
|
|
bitfld.long 0x00 11. "B1035,B1035" "0,1"
|
|
bitfld.long 0x00 10. "B1034,B1034" "0,1"
|
|
bitfld.long 0x00 9. "B1033,B1033" "0,1"
|
|
bitfld.long 0x00 8. "B1032,B1032" "0,1"
|
|
bitfld.long 0x00 7. "B1031,B1031" "0,1"
|
|
bitfld.long 0x00 6. "B1030,B1030" "0,1"
|
|
bitfld.long 0x00 5. "B1029,B1029" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1028,B1028" "0,1"
|
|
bitfld.long 0x00 3. "B1027,B1027" "0,1"
|
|
bitfld.long 0x00 2. "B1026,B1026" "0,1"
|
|
bitfld.long 0x00 1. "B1025,B1025" "0,1"
|
|
bitfld.long 0x00 0. "B1024,B1024" "0,1"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "MPCBB2_VCTR33,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1087,B1087" "0,1"
|
|
bitfld.long 0x00 30. "B1086,B1086" "0,1"
|
|
bitfld.long 0x00 29. "B1085,B1085" "0,1"
|
|
bitfld.long 0x00 28. "B1084,B1084" "0,1"
|
|
bitfld.long 0x00 27. "B1083,B1083" "0,1"
|
|
bitfld.long 0x00 26. "B1082,B1082" "0,1"
|
|
bitfld.long 0x00 25. "B1081,B1081" "0,1"
|
|
bitfld.long 0x00 24. "B1080,B1080" "0,1"
|
|
bitfld.long 0x00 23. "B1079,B1079" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1078,B1078" "0,1"
|
|
bitfld.long 0x00 21. "B1077,B1077" "0,1"
|
|
bitfld.long 0x00 20. "B1076,B1076" "0,1"
|
|
bitfld.long 0x00 19. "B1075,B1075" "0,1"
|
|
bitfld.long 0x00 18. "B1074,B1074" "0,1"
|
|
bitfld.long 0x00 17. "B1073,B1073" "0,1"
|
|
bitfld.long 0x00 16. "B1072,B1072" "0,1"
|
|
bitfld.long 0x00 15. "B1071,B1071" "0,1"
|
|
bitfld.long 0x00 14. "B1070,B1070" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1069,B1069" "0,1"
|
|
bitfld.long 0x00 12. "B1068,B1068" "0,1"
|
|
bitfld.long 0x00 11. "B1067,B1067" "0,1"
|
|
bitfld.long 0x00 10. "B1066,B1066" "0,1"
|
|
bitfld.long 0x00 9. "B1065,B1065" "0,1"
|
|
bitfld.long 0x00 8. "B1064,B1064" "0,1"
|
|
bitfld.long 0x00 7. "B1063,B1063" "0,1"
|
|
bitfld.long 0x00 6. "B1062,B1062" "0,1"
|
|
bitfld.long 0x00 5. "B1061,B1061" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1060,B1060" "0,1"
|
|
bitfld.long 0x00 3. "B1059,B1059" "0,1"
|
|
bitfld.long 0x00 2. "B1058,B1058" "0,1"
|
|
bitfld.long 0x00 1. "B1057,B1057" "0,1"
|
|
bitfld.long 0x00 0. "B1056,B1056" "0,1"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "MPCBB2_VCTR34,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1119,B1119" "0,1"
|
|
bitfld.long 0x00 30. "B1118,B1118" "0,1"
|
|
bitfld.long 0x00 29. "B1117,B1117" "0,1"
|
|
bitfld.long 0x00 28. "B1116,B1116" "0,1"
|
|
bitfld.long 0x00 27. "B1115,B1115" "0,1"
|
|
bitfld.long 0x00 26. "B1114,B1114" "0,1"
|
|
bitfld.long 0x00 25. "B1113,B1113" "0,1"
|
|
bitfld.long 0x00 24. "B1112,B1112" "0,1"
|
|
bitfld.long 0x00 23. "B1111,B1111" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1110,B1110" "0,1"
|
|
bitfld.long 0x00 21. "B1109,B1109" "0,1"
|
|
bitfld.long 0x00 20. "B1108,B1108" "0,1"
|
|
bitfld.long 0x00 19. "B1107,B1107" "0,1"
|
|
bitfld.long 0x00 18. "B1106,B1106" "0,1"
|
|
bitfld.long 0x00 17. "B1105,B1105" "0,1"
|
|
bitfld.long 0x00 16. "B1104,B1104" "0,1"
|
|
bitfld.long 0x00 15. "B1103,B1103" "0,1"
|
|
bitfld.long 0x00 14. "B1102,B1102" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1101,B1101" "0,1"
|
|
bitfld.long 0x00 12. "B1100,B1100" "0,1"
|
|
bitfld.long 0x00 11. "B1099,B1099" "0,1"
|
|
bitfld.long 0x00 10. "B1098,B1098" "0,1"
|
|
bitfld.long 0x00 9. "B1097,B1097" "0,1"
|
|
bitfld.long 0x00 8. "B1096,B1096" "0,1"
|
|
bitfld.long 0x00 7. "B1095,B1095" "0,1"
|
|
bitfld.long 0x00 6. "B1094,B1094" "0,1"
|
|
bitfld.long 0x00 5. "B1093,B1093" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1092,B1092" "0,1"
|
|
bitfld.long 0x00 3. "B1091,B1091" "0,1"
|
|
bitfld.long 0x00 2. "B1090,B1090" "0,1"
|
|
bitfld.long 0x00 1. "B1089,B1089" "0,1"
|
|
bitfld.long 0x00 0. "B1088,B1088" "0,1"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR35,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1151,B1151" "0,1"
|
|
bitfld.long 0x00 30. "B1150,B1150" "0,1"
|
|
bitfld.long 0x00 29. "B1149,B1149" "0,1"
|
|
bitfld.long 0x00 28. "B1148,B1148" "0,1"
|
|
bitfld.long 0x00 27. "B1147,B1147" "0,1"
|
|
bitfld.long 0x00 26. "B1146,B1146" "0,1"
|
|
bitfld.long 0x00 25. "B1145,B1145" "0,1"
|
|
bitfld.long 0x00 24. "B1144,B1144" "0,1"
|
|
bitfld.long 0x00 23. "B1143,B1143" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1142,B1142" "0,1"
|
|
bitfld.long 0x00 21. "B1141,B1141" "0,1"
|
|
bitfld.long 0x00 20. "B1140,B1140" "0,1"
|
|
bitfld.long 0x00 19. "B1139,B1139" "0,1"
|
|
bitfld.long 0x00 18. "B1138,B1138" "0,1"
|
|
bitfld.long 0x00 17. "B1137,B1137" "0,1"
|
|
bitfld.long 0x00 16. "B1136,B1136" "0,1"
|
|
bitfld.long 0x00 15. "B1135,B1135" "0,1"
|
|
bitfld.long 0x00 14. "B1134,B1134" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1133,B1133" "0,1"
|
|
bitfld.long 0x00 12. "B1132,B1132" "0,1"
|
|
bitfld.long 0x00 11. "B1131,B1131" "0,1"
|
|
bitfld.long 0x00 10. "B1130,B1130" "0,1"
|
|
bitfld.long 0x00 9. "B1129,B1129" "0,1"
|
|
bitfld.long 0x00 8. "B1128,B1128" "0,1"
|
|
bitfld.long 0x00 7. "B1127,B1127" "0,1"
|
|
bitfld.long 0x00 6. "B1126,B1126" "0,1"
|
|
bitfld.long 0x00 5. "B1125,B1125" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1124,B1124" "0,1"
|
|
bitfld.long 0x00 3. "B1123,B1123" "0,1"
|
|
bitfld.long 0x00 2. "B1122,B1122" "0,1"
|
|
bitfld.long 0x00 1. "B1121,B1121" "0,1"
|
|
bitfld.long 0x00 0. "B1120,B1120" "0,1"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "MPCBB2_VCTR36,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1183,B1183" "0,1"
|
|
bitfld.long 0x00 30. "B1182,B1182" "0,1"
|
|
bitfld.long 0x00 29. "B1181,B1181" "0,1"
|
|
bitfld.long 0x00 28. "B1180,B1180" "0,1"
|
|
bitfld.long 0x00 27. "B1179,B1179" "0,1"
|
|
bitfld.long 0x00 26. "B1178,B1178" "0,1"
|
|
bitfld.long 0x00 25. "B1177,B1177" "0,1"
|
|
bitfld.long 0x00 24. "B1176,B1176" "0,1"
|
|
bitfld.long 0x00 23. "B1175,B1175" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1174,B1174" "0,1"
|
|
bitfld.long 0x00 21. "B1173,B1173" "0,1"
|
|
bitfld.long 0x00 20. "B1172,B1172" "0,1"
|
|
bitfld.long 0x00 19. "B1171,B1171" "0,1"
|
|
bitfld.long 0x00 18. "B1170,B1170" "0,1"
|
|
bitfld.long 0x00 17. "B1169,B1169" "0,1"
|
|
bitfld.long 0x00 16. "B1168,B1168" "0,1"
|
|
bitfld.long 0x00 15. "B1167,B1167" "0,1"
|
|
bitfld.long 0x00 14. "B1166,B1166" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1165,B1165" "0,1"
|
|
bitfld.long 0x00 12. "B1164,B1164" "0,1"
|
|
bitfld.long 0x00 11. "B1163,B1163" "0,1"
|
|
bitfld.long 0x00 10. "B1162,B1162" "0,1"
|
|
bitfld.long 0x00 9. "B1161,B1161" "0,1"
|
|
bitfld.long 0x00 8. "B1160,B1160" "0,1"
|
|
bitfld.long 0x00 7. "B1159,B1159" "0,1"
|
|
bitfld.long 0x00 6. "B1158,B1158" "0,1"
|
|
bitfld.long 0x00 5. "B1157,B1157" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1156,B1156" "0,1"
|
|
bitfld.long 0x00 3. "B1155,B1155" "0,1"
|
|
bitfld.long 0x00 2. "B1154,B1154" "0,1"
|
|
bitfld.long 0x00 1. "B1153,B1153" "0,1"
|
|
bitfld.long 0x00 0. "B1152,B1152" "0,1"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "MPCBB2_VCTR37,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1215,B1215" "0,1"
|
|
bitfld.long 0x00 30. "B1214,B1214" "0,1"
|
|
bitfld.long 0x00 29. "B1213,B1213" "0,1"
|
|
bitfld.long 0x00 28. "B1212,B1212" "0,1"
|
|
bitfld.long 0x00 27. "B1211,B1211" "0,1"
|
|
bitfld.long 0x00 26. "B1210,B1210" "0,1"
|
|
bitfld.long 0x00 25. "B1209,B1209" "0,1"
|
|
bitfld.long 0x00 24. "B1208,B1208" "0,1"
|
|
bitfld.long 0x00 23. "B1207,B1207" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1206,B1206" "0,1"
|
|
bitfld.long 0x00 21. "B1205,B1205" "0,1"
|
|
bitfld.long 0x00 20. "B1204,B1204" "0,1"
|
|
bitfld.long 0x00 19. "B1203,B1203" "0,1"
|
|
bitfld.long 0x00 18. "B1202,B1202" "0,1"
|
|
bitfld.long 0x00 17. "B1201,B1201" "0,1"
|
|
bitfld.long 0x00 16. "B1200,B1200" "0,1"
|
|
bitfld.long 0x00 15. "B1199,B1199" "0,1"
|
|
bitfld.long 0x00 14. "B1198,B1198" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1197,B1197" "0,1"
|
|
bitfld.long 0x00 12. "B1196,B1196" "0,1"
|
|
bitfld.long 0x00 11. "B1195,B1195" "0,1"
|
|
bitfld.long 0x00 10. "B1194,B1194" "0,1"
|
|
bitfld.long 0x00 9. "B1193,B1193" "0,1"
|
|
bitfld.long 0x00 8. "B1192,B1192" "0,1"
|
|
bitfld.long 0x00 7. "B1191,B1191" "0,1"
|
|
bitfld.long 0x00 6. "B1190,B1190" "0,1"
|
|
bitfld.long 0x00 5. "B1189,B1189" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1188,B1188" "0,1"
|
|
bitfld.long 0x00 3. "B1187,B1187" "0,1"
|
|
bitfld.long 0x00 2. "B1186,B1186" "0,1"
|
|
bitfld.long 0x00 1. "B1185,B1185" "0,1"
|
|
bitfld.long 0x00 0. "B1184,B1184" "0,1"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "MPCBB2_VCTR38,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1247,B1247" "0,1"
|
|
bitfld.long 0x00 30. "B1246,B1246" "0,1"
|
|
bitfld.long 0x00 29. "B1245,B1245" "0,1"
|
|
bitfld.long 0x00 28. "B1244,B1244" "0,1"
|
|
bitfld.long 0x00 27. "B1243,B1243" "0,1"
|
|
bitfld.long 0x00 26. "B1242,B1242" "0,1"
|
|
bitfld.long 0x00 25. "B1241,B1241" "0,1"
|
|
bitfld.long 0x00 24. "B1240,B1240" "0,1"
|
|
bitfld.long 0x00 23. "B1239,B1239" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1238,B1238" "0,1"
|
|
bitfld.long 0x00 21. "B1237,B1237" "0,1"
|
|
bitfld.long 0x00 20. "B1236,B1236" "0,1"
|
|
bitfld.long 0x00 19. "B1235,B1235" "0,1"
|
|
bitfld.long 0x00 18. "B1234,B1234" "0,1"
|
|
bitfld.long 0x00 17. "B1233,B1233" "0,1"
|
|
bitfld.long 0x00 16. "B1232,B1232" "0,1"
|
|
bitfld.long 0x00 15. "B1231,B1231" "0,1"
|
|
bitfld.long 0x00 14. "B1230,B1230" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1229,B1229" "0,1"
|
|
bitfld.long 0x00 12. "B1228,B1228" "0,1"
|
|
bitfld.long 0x00 11. "B1227,B1227" "0,1"
|
|
bitfld.long 0x00 10. "B1226,B1226" "0,1"
|
|
bitfld.long 0x00 9. "B1225,B1225" "0,1"
|
|
bitfld.long 0x00 8. "B1224,B1224" "0,1"
|
|
bitfld.long 0x00 7. "B1223,B1223" "0,1"
|
|
bitfld.long 0x00 6. "B1222,B1222" "0,1"
|
|
bitfld.long 0x00 5. "B1221,B1221" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1220,B1220" "0,1"
|
|
bitfld.long 0x00 3. "B1219,B1219" "0,1"
|
|
bitfld.long 0x00 2. "B1218,B1218" "0,1"
|
|
bitfld.long 0x00 1. "B1217,B1217" "0,1"
|
|
bitfld.long 0x00 0. "B1216,B1216" "0,1"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "MPCBB2_VCTR39,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1279,B1279" "0,1"
|
|
bitfld.long 0x00 30. "B1278,B1278" "0,1"
|
|
bitfld.long 0x00 29. "B1277,B1277" "0,1"
|
|
bitfld.long 0x00 28. "B1276,B1276" "0,1"
|
|
bitfld.long 0x00 27. "B1275,B1275" "0,1"
|
|
bitfld.long 0x00 26. "B1274,B1274" "0,1"
|
|
bitfld.long 0x00 25. "B1273,B1273" "0,1"
|
|
bitfld.long 0x00 24. "B1272,B1272" "0,1"
|
|
bitfld.long 0x00 23. "B1271,B1271" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1270,B1270" "0,1"
|
|
bitfld.long 0x00 21. "B1269,B1269" "0,1"
|
|
bitfld.long 0x00 20. "B1268,B1268" "0,1"
|
|
bitfld.long 0x00 19. "B1267,B1267" "0,1"
|
|
bitfld.long 0x00 18. "B1266,B1266" "0,1"
|
|
bitfld.long 0x00 17. "B1265,B1265" "0,1"
|
|
bitfld.long 0x00 16. "B1264,B1264" "0,1"
|
|
bitfld.long 0x00 15. "B1263,B1263" "0,1"
|
|
bitfld.long 0x00 14. "B1262,B1262" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1261,B1261" "0,1"
|
|
bitfld.long 0x00 12. "B1260,B1260" "0,1"
|
|
bitfld.long 0x00 11. "B1259,B1259" "0,1"
|
|
bitfld.long 0x00 10. "B1258,B1258" "0,1"
|
|
bitfld.long 0x00 9. "B1257,B1257" "0,1"
|
|
bitfld.long 0x00 8. "B1256,B1256" "0,1"
|
|
bitfld.long 0x00 7. "B1255,B1255" "0,1"
|
|
bitfld.long 0x00 6. "B1254,B1254" "0,1"
|
|
bitfld.long 0x00 5. "B1253,B1253" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1252,B1252" "0,1"
|
|
bitfld.long 0x00 3. "B1251,B1251" "0,1"
|
|
bitfld.long 0x00 2. "B1250,B1250" "0,1"
|
|
bitfld.long 0x00 1. "B1249,B1249" "0,1"
|
|
bitfld.long 0x00 0. "B1248,B1248" "0,1"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "MPCBB2_VCTR40,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1311,B1311" "0,1"
|
|
bitfld.long 0x00 30. "B1310,B1310" "0,1"
|
|
bitfld.long 0x00 29. "B1309,B1309" "0,1"
|
|
bitfld.long 0x00 28. "B1308,B1308" "0,1"
|
|
bitfld.long 0x00 27. "B1307,B1307" "0,1"
|
|
bitfld.long 0x00 26. "B1306,B1306" "0,1"
|
|
bitfld.long 0x00 25. "B1305,B1305" "0,1"
|
|
bitfld.long 0x00 24. "B1304,B1304" "0,1"
|
|
bitfld.long 0x00 23. "B1303,B1303" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1302,B1302" "0,1"
|
|
bitfld.long 0x00 21. "B1301,B1301" "0,1"
|
|
bitfld.long 0x00 20. "B1300,B1300" "0,1"
|
|
bitfld.long 0x00 19. "B1299,B1299" "0,1"
|
|
bitfld.long 0x00 18. "B1298,B1298" "0,1"
|
|
bitfld.long 0x00 17. "B1297,B1297" "0,1"
|
|
bitfld.long 0x00 16. "B1296,B1296" "0,1"
|
|
bitfld.long 0x00 15. "B1295,B1295" "0,1"
|
|
bitfld.long 0x00 14. "B1294,B1294" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1293,B1293" "0,1"
|
|
bitfld.long 0x00 12. "B1292,B1292" "0,1"
|
|
bitfld.long 0x00 11. "B1291,B1291" "0,1"
|
|
bitfld.long 0x00 10. "B1290,B1290" "0,1"
|
|
bitfld.long 0x00 9. "B1289,B1289" "0,1"
|
|
bitfld.long 0x00 8. "B1288,B1288" "0,1"
|
|
bitfld.long 0x00 7. "B1287,B1287" "0,1"
|
|
bitfld.long 0x00 6. "B1286,B1286" "0,1"
|
|
bitfld.long 0x00 5. "B1285,B1285" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1284,B1284" "0,1"
|
|
bitfld.long 0x00 3. "B1283,B1283" "0,1"
|
|
bitfld.long 0x00 2. "B1282,B1282" "0,1"
|
|
bitfld.long 0x00 1. "B1281,B1281" "0,1"
|
|
bitfld.long 0x00 0. "B1280,B1280" "0,1"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "MPCBB2_VCTR41,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1343,B1343" "0,1"
|
|
bitfld.long 0x00 30. "B1342,B1342" "0,1"
|
|
bitfld.long 0x00 29. "B1341,B1341" "0,1"
|
|
bitfld.long 0x00 28. "B1340,B1340" "0,1"
|
|
bitfld.long 0x00 27. "B1339,B1339" "0,1"
|
|
bitfld.long 0x00 26. "B1338,B1338" "0,1"
|
|
bitfld.long 0x00 25. "B1337,B1337" "0,1"
|
|
bitfld.long 0x00 24. "B1336,B1336" "0,1"
|
|
bitfld.long 0x00 23. "B1335,B1335" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1334,B1334" "0,1"
|
|
bitfld.long 0x00 21. "B1333,B1333" "0,1"
|
|
bitfld.long 0x00 20. "B1332,B1332" "0,1"
|
|
bitfld.long 0x00 19. "B1331,B1331" "0,1"
|
|
bitfld.long 0x00 18. "B1330,B1330" "0,1"
|
|
bitfld.long 0x00 17. "B1329,B1329" "0,1"
|
|
bitfld.long 0x00 16. "B1328,B1328" "0,1"
|
|
bitfld.long 0x00 15. "B1327,B1327" "0,1"
|
|
bitfld.long 0x00 14. "B1326,B1326" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1325,B1325" "0,1"
|
|
bitfld.long 0x00 12. "B1324,B1324" "0,1"
|
|
bitfld.long 0x00 11. "B1323,B1323" "0,1"
|
|
bitfld.long 0x00 10. "B1322,B1322" "0,1"
|
|
bitfld.long 0x00 9. "B1321,B1321" "0,1"
|
|
bitfld.long 0x00 8. "B1320,B1320" "0,1"
|
|
bitfld.long 0x00 7. "B1319,B1319" "0,1"
|
|
bitfld.long 0x00 6. "B1318,B1318" "0,1"
|
|
bitfld.long 0x00 5. "B1317,B1317" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1316,B1316" "0,1"
|
|
bitfld.long 0x00 3. "B1315,B1315" "0,1"
|
|
bitfld.long 0x00 2. "B1314,B1314" "0,1"
|
|
bitfld.long 0x00 1. "B1313,B1313" "0,1"
|
|
bitfld.long 0x00 0. "B1312,B1312" "0,1"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "MPCBB2_VCTR42,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1375,B1375" "0,1"
|
|
bitfld.long 0x00 30. "B1374,B1374" "0,1"
|
|
bitfld.long 0x00 29. "B1373,B1373" "0,1"
|
|
bitfld.long 0x00 28. "B1372,B1372" "0,1"
|
|
bitfld.long 0x00 27. "B1371,B1371" "0,1"
|
|
bitfld.long 0x00 26. "B1370,B1370" "0,1"
|
|
bitfld.long 0x00 25. "B1369,B1369" "0,1"
|
|
bitfld.long 0x00 24. "B1368,B1368" "0,1"
|
|
bitfld.long 0x00 23. "B1367,B1367" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1366,B1366" "0,1"
|
|
bitfld.long 0x00 21. "B1365,B1365" "0,1"
|
|
bitfld.long 0x00 20. "B1364,B1364" "0,1"
|
|
bitfld.long 0x00 19. "B1363,B1363" "0,1"
|
|
bitfld.long 0x00 18. "B1362,B1362" "0,1"
|
|
bitfld.long 0x00 17. "B1361,B1361" "0,1"
|
|
bitfld.long 0x00 16. "B1360,B1360" "0,1"
|
|
bitfld.long 0x00 15. "B1359,B1359" "0,1"
|
|
bitfld.long 0x00 14. "B1358,B1358" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1357,B1357" "0,1"
|
|
bitfld.long 0x00 12. "B1356,B1356" "0,1"
|
|
bitfld.long 0x00 11. "B1355,B1355" "0,1"
|
|
bitfld.long 0x00 10. "B1354,B1354" "0,1"
|
|
bitfld.long 0x00 9. "B1353,B1353" "0,1"
|
|
bitfld.long 0x00 8. "B1352,B1352" "0,1"
|
|
bitfld.long 0x00 7. "B1351,B1351" "0,1"
|
|
bitfld.long 0x00 6. "B1350,B1350" "0,1"
|
|
bitfld.long 0x00 5. "B1349,B1349" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1348,B1348" "0,1"
|
|
bitfld.long 0x00 3. "B1347,B1347" "0,1"
|
|
bitfld.long 0x00 2. "B1346,B1346" "0,1"
|
|
bitfld.long 0x00 1. "B1345,B1345" "0,1"
|
|
bitfld.long 0x00 0. "B1344,B1344" "0,1"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "MPCBB2_VCTR43,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1407,B1407" "0,1"
|
|
bitfld.long 0x00 30. "B1406,B1406" "0,1"
|
|
bitfld.long 0x00 29. "B1405,B1405" "0,1"
|
|
bitfld.long 0x00 28. "B1404,B1404" "0,1"
|
|
bitfld.long 0x00 27. "B1403,B1403" "0,1"
|
|
bitfld.long 0x00 26. "B1402,B1402" "0,1"
|
|
bitfld.long 0x00 25. "B1401,B1401" "0,1"
|
|
bitfld.long 0x00 24. "B1400,B1400" "0,1"
|
|
bitfld.long 0x00 23. "B1399,B1399" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1398,B1398" "0,1"
|
|
bitfld.long 0x00 21. "B1397,B1397" "0,1"
|
|
bitfld.long 0x00 20. "B1396,B1396" "0,1"
|
|
bitfld.long 0x00 19. "B1395,B1395" "0,1"
|
|
bitfld.long 0x00 18. "B1394,B1394" "0,1"
|
|
bitfld.long 0x00 17. "B1393,B1393" "0,1"
|
|
bitfld.long 0x00 16. "B1392,B1392" "0,1"
|
|
bitfld.long 0x00 15. "B1391,B1391" "0,1"
|
|
bitfld.long 0x00 14. "B1390,B1390" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1389,B1389" "0,1"
|
|
bitfld.long 0x00 12. "B1388,B1388" "0,1"
|
|
bitfld.long 0x00 11. "B1387,B1387" "0,1"
|
|
bitfld.long 0x00 10. "B1386,B1386" "0,1"
|
|
bitfld.long 0x00 9. "B1385,B1385" "0,1"
|
|
bitfld.long 0x00 8. "B1384,B1384" "0,1"
|
|
bitfld.long 0x00 7. "B1383,B1383" "0,1"
|
|
bitfld.long 0x00 6. "B1382,B1382" "0,1"
|
|
bitfld.long 0x00 5. "B1381,B1381" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1380,B1380" "0,1"
|
|
bitfld.long 0x00 3. "B1379,B1379" "0,1"
|
|
bitfld.long 0x00 2. "B1378,B1378" "0,1"
|
|
bitfld.long 0x00 1. "B1377,B1377" "0,1"
|
|
bitfld.long 0x00 0. "B1376,B1376" "0,1"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "MPCBB2_VCTR44,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1439,B1439" "0,1"
|
|
bitfld.long 0x00 30. "B1438,B1438" "0,1"
|
|
bitfld.long 0x00 29. "B1437,B1437" "0,1"
|
|
bitfld.long 0x00 28. "B1436,B1436" "0,1"
|
|
bitfld.long 0x00 27. "B1435,B1435" "0,1"
|
|
bitfld.long 0x00 26. "B1434,B1434" "0,1"
|
|
bitfld.long 0x00 25. "B1433,B1433" "0,1"
|
|
bitfld.long 0x00 24. "B1432,B1432" "0,1"
|
|
bitfld.long 0x00 23. "B1431,B1431" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1430,B1430" "0,1"
|
|
bitfld.long 0x00 21. "B1429,B1429" "0,1"
|
|
bitfld.long 0x00 20. "B1428,B1428" "0,1"
|
|
bitfld.long 0x00 19. "B1427,B1427" "0,1"
|
|
bitfld.long 0x00 18. "B1426,B1426" "0,1"
|
|
bitfld.long 0x00 17. "B1425,B1425" "0,1"
|
|
bitfld.long 0x00 16. "B1424,B1424" "0,1"
|
|
bitfld.long 0x00 15. "B1423,B1423" "0,1"
|
|
bitfld.long 0x00 14. "B1422,B1422" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1421,B1421" "0,1"
|
|
bitfld.long 0x00 12. "B1420,B1420" "0,1"
|
|
bitfld.long 0x00 11. "B1419,B1419" "0,1"
|
|
bitfld.long 0x00 10. "B1418,B1418" "0,1"
|
|
bitfld.long 0x00 9. "B1417,B1417" "0,1"
|
|
bitfld.long 0x00 8. "B1416,B1416" "0,1"
|
|
bitfld.long 0x00 7. "B1415,B1415" "0,1"
|
|
bitfld.long 0x00 6. "B1414,B1414" "0,1"
|
|
bitfld.long 0x00 5. "B1413,B1413" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1412,B1412" "0,1"
|
|
bitfld.long 0x00 3. "B1411,B1411" "0,1"
|
|
bitfld.long 0x00 2. "B1410,B1410" "0,1"
|
|
bitfld.long 0x00 1. "B1409,B1409" "0,1"
|
|
bitfld.long 0x00 0. "B1408,B1408" "0,1"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "MPCBB2_VCTR45,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1471,B1471" "0,1"
|
|
bitfld.long 0x00 30. "B1470,B1470" "0,1"
|
|
bitfld.long 0x00 29. "B1469,B1469" "0,1"
|
|
bitfld.long 0x00 28. "B1468,B1468" "0,1"
|
|
bitfld.long 0x00 27. "B1467,B1467" "0,1"
|
|
bitfld.long 0x00 26. "B1466,B1466" "0,1"
|
|
bitfld.long 0x00 25. "B1465,B1465" "0,1"
|
|
bitfld.long 0x00 24. "B1464,B1464" "0,1"
|
|
bitfld.long 0x00 23. "B1463,B1463" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1462,B1462" "0,1"
|
|
bitfld.long 0x00 21. "B1461,B1461" "0,1"
|
|
bitfld.long 0x00 20. "B1460,B1460" "0,1"
|
|
bitfld.long 0x00 19. "B1459,B1459" "0,1"
|
|
bitfld.long 0x00 18. "B1458,B1458" "0,1"
|
|
bitfld.long 0x00 17. "B1457,B1457" "0,1"
|
|
bitfld.long 0x00 16. "B1456,B1456" "0,1"
|
|
bitfld.long 0x00 15. "B1455,B1455" "0,1"
|
|
bitfld.long 0x00 14. "B1454,B1454" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1453,B1453" "0,1"
|
|
bitfld.long 0x00 12. "B1452,B1452" "0,1"
|
|
bitfld.long 0x00 11. "B1451,B1451" "0,1"
|
|
bitfld.long 0x00 10. "B1450,B1450" "0,1"
|
|
bitfld.long 0x00 9. "B1449,B1449" "0,1"
|
|
bitfld.long 0x00 8. "B1448,B1448" "0,1"
|
|
bitfld.long 0x00 7. "B1447,B1447" "0,1"
|
|
bitfld.long 0x00 6. "B1446,B1446" "0,1"
|
|
bitfld.long 0x00 5. "B1445,B1445" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1444,B1444" "0,1"
|
|
bitfld.long 0x00 3. "B1443,B1443" "0,1"
|
|
bitfld.long 0x00 2. "B1442,B1442" "0,1"
|
|
bitfld.long 0x00 1. "B1441,B1441" "0,1"
|
|
bitfld.long 0x00 0. "B1440,B1440" "0,1"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "MPCBB2_VCTR46,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1503,B1503" "0,1"
|
|
bitfld.long 0x00 30. "B1502,B1502" "0,1"
|
|
bitfld.long 0x00 29. "B1501,B1501" "0,1"
|
|
bitfld.long 0x00 28. "B1500,B1500" "0,1"
|
|
bitfld.long 0x00 27. "B1499,B1499" "0,1"
|
|
bitfld.long 0x00 26. "B1498,B1498" "0,1"
|
|
bitfld.long 0x00 25. "B1497,B1497" "0,1"
|
|
bitfld.long 0x00 24. "B1496,B1496" "0,1"
|
|
bitfld.long 0x00 23. "B1495,B1495" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1494,B1494" "0,1"
|
|
bitfld.long 0x00 21. "B1493,B1493" "0,1"
|
|
bitfld.long 0x00 20. "B1492,B1492" "0,1"
|
|
bitfld.long 0x00 19. "B1491,B1491" "0,1"
|
|
bitfld.long 0x00 18. "B1490,B1490" "0,1"
|
|
bitfld.long 0x00 17. "B1489,B1489" "0,1"
|
|
bitfld.long 0x00 16. "B1488,B1488" "0,1"
|
|
bitfld.long 0x00 15. "B1487,B1487" "0,1"
|
|
bitfld.long 0x00 14. "B1486,B1486" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1485,B1485" "0,1"
|
|
bitfld.long 0x00 12. "B1484,B1484" "0,1"
|
|
bitfld.long 0x00 11. "B1483,B1483" "0,1"
|
|
bitfld.long 0x00 10. "B1482,B1482" "0,1"
|
|
bitfld.long 0x00 9. "B1481,B1481" "0,1"
|
|
bitfld.long 0x00 8. "B1480,B1480" "0,1"
|
|
bitfld.long 0x00 7. "B1479,B1479" "0,1"
|
|
bitfld.long 0x00 6. "B1478,B1478" "0,1"
|
|
bitfld.long 0x00 5. "B1477,B1477" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1476,B1476" "0,1"
|
|
bitfld.long 0x00 3. "B1475,B1475" "0,1"
|
|
bitfld.long 0x00 2. "B1474,B1474" "0,1"
|
|
bitfld.long 0x00 1. "B1473,B1473" "0,1"
|
|
bitfld.long 0x00 0. "B1472,B1472" "0,1"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "MPCBB2_VCTR47,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1535,B1535" "0,1"
|
|
bitfld.long 0x00 30. "B1534,B1534" "0,1"
|
|
bitfld.long 0x00 29. "B1533,B1533" "0,1"
|
|
bitfld.long 0x00 28. "B1532,B1532" "0,1"
|
|
bitfld.long 0x00 27. "B1531,B1531" "0,1"
|
|
bitfld.long 0x00 26. "B1530,B1530" "0,1"
|
|
bitfld.long 0x00 25. "B1529,B1529" "0,1"
|
|
bitfld.long 0x00 24. "B1528,B1528" "0,1"
|
|
bitfld.long 0x00 23. "B1527,B1527" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1526,B1526" "0,1"
|
|
bitfld.long 0x00 21. "B1525,B1525" "0,1"
|
|
bitfld.long 0x00 20. "B1524,B1524" "0,1"
|
|
bitfld.long 0x00 19. "B1523,B1523" "0,1"
|
|
bitfld.long 0x00 18. "B1522,B1522" "0,1"
|
|
bitfld.long 0x00 17. "B1521,B1521" "0,1"
|
|
bitfld.long 0x00 16. "B1520,B1520" "0,1"
|
|
bitfld.long 0x00 15. "B1519,B1519" "0,1"
|
|
bitfld.long 0x00 14. "B1518,B1518" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1517,B1517" "0,1"
|
|
bitfld.long 0x00 12. "B1516,B1516" "0,1"
|
|
bitfld.long 0x00 11. "B1515,B1515" "0,1"
|
|
bitfld.long 0x00 10. "B1514,B1514" "0,1"
|
|
bitfld.long 0x00 9. "B1513,B1513" "0,1"
|
|
bitfld.long 0x00 8. "B1512,B1512" "0,1"
|
|
bitfld.long 0x00 7. "B1511,B1511" "0,1"
|
|
bitfld.long 0x00 6. "B1510,B1510" "0,1"
|
|
bitfld.long 0x00 5. "B1509,B1509" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1508,B1508" "0,1"
|
|
bitfld.long 0x00 3. "B1507,B1507" "0,1"
|
|
bitfld.long 0x00 2. "B1506,B1506" "0,1"
|
|
bitfld.long 0x00 1. "B1505,B1505" "0,1"
|
|
bitfld.long 0x00 0. "B1504,B1504" "0,1"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "MPCBB2_VCTR48,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1567,B1567" "0,1"
|
|
bitfld.long 0x00 30. "B1566,B1566" "0,1"
|
|
bitfld.long 0x00 29. "B1565,B1565" "0,1"
|
|
bitfld.long 0x00 28. "B1564,B1564" "0,1"
|
|
bitfld.long 0x00 27. "B1563,B1563" "0,1"
|
|
bitfld.long 0x00 26. "B1562,B1562" "0,1"
|
|
bitfld.long 0x00 25. "B1561,B1561" "0,1"
|
|
bitfld.long 0x00 24. "B1560,B1560" "0,1"
|
|
bitfld.long 0x00 23. "B1559,B1559" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1558,B1558" "0,1"
|
|
bitfld.long 0x00 21. "B1557,B1557" "0,1"
|
|
bitfld.long 0x00 20. "B1556,B1556" "0,1"
|
|
bitfld.long 0x00 19. "B1555,B1555" "0,1"
|
|
bitfld.long 0x00 18. "B1554,B1554" "0,1"
|
|
bitfld.long 0x00 17. "B1553,B1553" "0,1"
|
|
bitfld.long 0x00 16. "B1552,B1552" "0,1"
|
|
bitfld.long 0x00 15. "B1551,B1551" "0,1"
|
|
bitfld.long 0x00 14. "B1550,B1550" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1549,B1549" "0,1"
|
|
bitfld.long 0x00 12. "B1548,B1548" "0,1"
|
|
bitfld.long 0x00 11. "B1547,B1547" "0,1"
|
|
bitfld.long 0x00 10. "B1546,B1546" "0,1"
|
|
bitfld.long 0x00 9. "B1545,B1545" "0,1"
|
|
bitfld.long 0x00 8. "B1544,B1544" "0,1"
|
|
bitfld.long 0x00 7. "B1543,B1543" "0,1"
|
|
bitfld.long 0x00 6. "B1542,B1542" "0,1"
|
|
bitfld.long 0x00 5. "B1541,B1541" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1540,B1540" "0,1"
|
|
bitfld.long 0x00 3. "B1539,B1539" "0,1"
|
|
bitfld.long 0x00 2. "B1538,B1538" "0,1"
|
|
bitfld.long 0x00 1. "B1537,B1537" "0,1"
|
|
bitfld.long 0x00 0. "B1536,B1536" "0,1"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "MPCBB2_VCTR49,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1599,B1599" "0,1"
|
|
bitfld.long 0x00 30. "B1598,B1598" "0,1"
|
|
bitfld.long 0x00 29. "B1597,B1597" "0,1"
|
|
bitfld.long 0x00 28. "B1596,B1596" "0,1"
|
|
bitfld.long 0x00 27. "B1595,B1595" "0,1"
|
|
bitfld.long 0x00 26. "B1594,B1594" "0,1"
|
|
bitfld.long 0x00 25. "B1593,B1593" "0,1"
|
|
bitfld.long 0x00 24. "B1592,B1592" "0,1"
|
|
bitfld.long 0x00 23. "B1591,B1591" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1590,B1590" "0,1"
|
|
bitfld.long 0x00 21. "B1589,B1589" "0,1"
|
|
bitfld.long 0x00 20. "B1588,B1588" "0,1"
|
|
bitfld.long 0x00 19. "B1587,B1587" "0,1"
|
|
bitfld.long 0x00 18. "B1586,B1586" "0,1"
|
|
bitfld.long 0x00 17. "B1585,B1585" "0,1"
|
|
bitfld.long 0x00 16. "B1584,B1584" "0,1"
|
|
bitfld.long 0x00 15. "B1583,B1583" "0,1"
|
|
bitfld.long 0x00 14. "B1582,B1582" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1581,B1581" "0,1"
|
|
bitfld.long 0x00 12. "B1580,B1580" "0,1"
|
|
bitfld.long 0x00 11. "B1579,B1579" "0,1"
|
|
bitfld.long 0x00 10. "B1578,B1578" "0,1"
|
|
bitfld.long 0x00 9. "B1577,B1577" "0,1"
|
|
bitfld.long 0x00 8. "B1576,B1576" "0,1"
|
|
bitfld.long 0x00 7. "B1575,B1575" "0,1"
|
|
bitfld.long 0x00 6. "B1574,B1574" "0,1"
|
|
bitfld.long 0x00 5. "B1573,B1573" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1572,B1572" "0,1"
|
|
bitfld.long 0x00 3. "B1571,B1571" "0,1"
|
|
bitfld.long 0x00 2. "B1570,B1570" "0,1"
|
|
bitfld.long 0x00 1. "B1569,B1569" "0,1"
|
|
bitfld.long 0x00 0. "B1568,B1568" "0,1"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "MPCBB2_VCTR50,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1631,B1631" "0,1"
|
|
bitfld.long 0x00 30. "B1630,B1630" "0,1"
|
|
bitfld.long 0x00 29. "B1629,B1629" "0,1"
|
|
bitfld.long 0x00 28. "B1628,B1628" "0,1"
|
|
bitfld.long 0x00 27. "B1627,B1627" "0,1"
|
|
bitfld.long 0x00 26. "B1626,B1626" "0,1"
|
|
bitfld.long 0x00 25. "B1625,B1625" "0,1"
|
|
bitfld.long 0x00 24. "B1624,B1624" "0,1"
|
|
bitfld.long 0x00 23. "B1623,B1623" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1622,B1622" "0,1"
|
|
bitfld.long 0x00 21. "B1621,B1621" "0,1"
|
|
bitfld.long 0x00 20. "B1620,B1620" "0,1"
|
|
bitfld.long 0x00 19. "B1619,B1619" "0,1"
|
|
bitfld.long 0x00 18. "B1618,B1618" "0,1"
|
|
bitfld.long 0x00 17. "B1617,B1617" "0,1"
|
|
bitfld.long 0x00 16. "B1616,B1616" "0,1"
|
|
bitfld.long 0x00 15. "B1615,B1615" "0,1"
|
|
bitfld.long 0x00 14. "B1614,B1614" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1613,B1613" "0,1"
|
|
bitfld.long 0x00 12. "B1612,B1612" "0,1"
|
|
bitfld.long 0x00 11. "B1611,B1611" "0,1"
|
|
bitfld.long 0x00 10. "B1610,B1610" "0,1"
|
|
bitfld.long 0x00 9. "B1609,B1609" "0,1"
|
|
bitfld.long 0x00 8. "B1608,B1608" "0,1"
|
|
bitfld.long 0x00 7. "B1607,B1607" "0,1"
|
|
bitfld.long 0x00 6. "B1606,B1606" "0,1"
|
|
bitfld.long 0x00 5. "B1605,B1605" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1604,B1604" "0,1"
|
|
bitfld.long 0x00 3. "B1603,B1603" "0,1"
|
|
bitfld.long 0x00 2. "B1602,B1602" "0,1"
|
|
bitfld.long 0x00 1. "B1601,B1601" "0,1"
|
|
bitfld.long 0x00 0. "B1600,B1600" "0,1"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "MPCBB2_VCTR51,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1663,B1663" "0,1"
|
|
bitfld.long 0x00 30. "B1662,B1662" "0,1"
|
|
bitfld.long 0x00 29. "B1661,B1661" "0,1"
|
|
bitfld.long 0x00 28. "B1660,B1660" "0,1"
|
|
bitfld.long 0x00 27. "B1659,B1659" "0,1"
|
|
bitfld.long 0x00 26. "B1658,B1658" "0,1"
|
|
bitfld.long 0x00 25. "B1657,B1657" "0,1"
|
|
bitfld.long 0x00 24. "B1656,B1656" "0,1"
|
|
bitfld.long 0x00 23. "B1655,B1655" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1654,B1654" "0,1"
|
|
bitfld.long 0x00 21. "B1653,B1653" "0,1"
|
|
bitfld.long 0x00 20. "B1652,B1652" "0,1"
|
|
bitfld.long 0x00 19. "B1651,B1651" "0,1"
|
|
bitfld.long 0x00 18. "B1650,B1650" "0,1"
|
|
bitfld.long 0x00 17. "B1649,B1649" "0,1"
|
|
bitfld.long 0x00 16. "B1648,B1648" "0,1"
|
|
bitfld.long 0x00 15. "B1647,B1647" "0,1"
|
|
bitfld.long 0x00 14. "B1646,B1646" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1645,B1645" "0,1"
|
|
bitfld.long 0x00 12. "B1644,B1644" "0,1"
|
|
bitfld.long 0x00 11. "B1643,B1643" "0,1"
|
|
bitfld.long 0x00 10. "B1642,B1642" "0,1"
|
|
bitfld.long 0x00 9. "B1641,B1641" "0,1"
|
|
bitfld.long 0x00 8. "B1640,B1640" "0,1"
|
|
bitfld.long 0x00 7. "B1639,B1639" "0,1"
|
|
bitfld.long 0x00 6. "B1638,B1638" "0,1"
|
|
bitfld.long 0x00 5. "B1637,B1637" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1636,B1636" "0,1"
|
|
bitfld.long 0x00 3. "B1635,B1635" "0,1"
|
|
bitfld.long 0x00 2. "B1634,B1634" "0,1"
|
|
bitfld.long 0x00 1. "B1633,B1633" "0,1"
|
|
bitfld.long 0x00 0. "B1632,B1632" "0,1"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "MPCBB2_VCTR52,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1695,B1695" "0,1"
|
|
bitfld.long 0x00 30. "B1694,B1694" "0,1"
|
|
bitfld.long 0x00 29. "B1693,B1693" "0,1"
|
|
bitfld.long 0x00 28. "B1692,B1692" "0,1"
|
|
bitfld.long 0x00 27. "B1691,B1691" "0,1"
|
|
bitfld.long 0x00 26. "B1690,B1690" "0,1"
|
|
bitfld.long 0x00 25. "B1689,B1689" "0,1"
|
|
bitfld.long 0x00 24. "B1688,B1688" "0,1"
|
|
bitfld.long 0x00 23. "B1687,B1687" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1686,B1686" "0,1"
|
|
bitfld.long 0x00 21. "B1685,B1685" "0,1"
|
|
bitfld.long 0x00 20. "B1684,B1684" "0,1"
|
|
bitfld.long 0x00 19. "B1683,B1683" "0,1"
|
|
bitfld.long 0x00 18. "B1682,B1682" "0,1"
|
|
bitfld.long 0x00 17. "B1681,B1681" "0,1"
|
|
bitfld.long 0x00 16. "B1680,B1680" "0,1"
|
|
bitfld.long 0x00 15. "B1679,B1679" "0,1"
|
|
bitfld.long 0x00 14. "B1678,B1678" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1677,B1677" "0,1"
|
|
bitfld.long 0x00 12. "B1676,B1676" "0,1"
|
|
bitfld.long 0x00 11. "B1675,B1675" "0,1"
|
|
bitfld.long 0x00 10. "B1674,B1674" "0,1"
|
|
bitfld.long 0x00 9. "B1673,B1673" "0,1"
|
|
bitfld.long 0x00 8. "B1672,B1672" "0,1"
|
|
bitfld.long 0x00 7. "B1671,B1671" "0,1"
|
|
bitfld.long 0x00 6. "B1670,B1670" "0,1"
|
|
bitfld.long 0x00 5. "B1669,B1669" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1668,B1668" "0,1"
|
|
bitfld.long 0x00 3. "B1667,B1667" "0,1"
|
|
bitfld.long 0x00 2. "B1666,B1666" "0,1"
|
|
bitfld.long 0x00 1. "B1665,B1665" "0,1"
|
|
bitfld.long 0x00 0. "B1664,B1664" "0,1"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "MPCBB2_VCTR53,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1727,B1727" "0,1"
|
|
bitfld.long 0x00 30. "B1726,B1726" "0,1"
|
|
bitfld.long 0x00 29. "B1725,B1725" "0,1"
|
|
bitfld.long 0x00 28. "B1724,B1724" "0,1"
|
|
bitfld.long 0x00 27. "B1723,B1723" "0,1"
|
|
bitfld.long 0x00 26. "B1722,B1722" "0,1"
|
|
bitfld.long 0x00 25. "B1721,B1721" "0,1"
|
|
bitfld.long 0x00 24. "B1720,B1720" "0,1"
|
|
bitfld.long 0x00 23. "B1719,B1719" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1718,B1718" "0,1"
|
|
bitfld.long 0x00 21. "B1717,B1717" "0,1"
|
|
bitfld.long 0x00 20. "B1716,B1716" "0,1"
|
|
bitfld.long 0x00 19. "B1715,B1715" "0,1"
|
|
bitfld.long 0x00 18. "B1714,B1714" "0,1"
|
|
bitfld.long 0x00 17. "B1713,B1713" "0,1"
|
|
bitfld.long 0x00 16. "B1712,B1712" "0,1"
|
|
bitfld.long 0x00 15. "B1711,B1711" "0,1"
|
|
bitfld.long 0x00 14. "B1710,B1710" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1709,B1709" "0,1"
|
|
bitfld.long 0x00 12. "B1708,B1708" "0,1"
|
|
bitfld.long 0x00 11. "B1707,B1707" "0,1"
|
|
bitfld.long 0x00 10. "B1706,B1706" "0,1"
|
|
bitfld.long 0x00 9. "B1705,B1705" "0,1"
|
|
bitfld.long 0x00 8. "B1704,B1704" "0,1"
|
|
bitfld.long 0x00 7. "B1703,B1703" "0,1"
|
|
bitfld.long 0x00 6. "B1702,B1702" "0,1"
|
|
bitfld.long 0x00 5. "B1701,B1701" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1700,B1700" "0,1"
|
|
bitfld.long 0x00 3. "B1699,B1699" "0,1"
|
|
bitfld.long 0x00 2. "B1698,B1698" "0,1"
|
|
bitfld.long 0x00 1. "B1697,B1697" "0,1"
|
|
bitfld.long 0x00 0. "B1696,B1696" "0,1"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "MPCBB2_VCTR54,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1759,B1759" "0,1"
|
|
bitfld.long 0x00 30. "B1758,B1758" "0,1"
|
|
bitfld.long 0x00 29. "B1757,B1757" "0,1"
|
|
bitfld.long 0x00 28. "B1756,B1756" "0,1"
|
|
bitfld.long 0x00 27. "B1755,B1755" "0,1"
|
|
bitfld.long 0x00 26. "B1754,B1754" "0,1"
|
|
bitfld.long 0x00 25. "B1753,B1753" "0,1"
|
|
bitfld.long 0x00 24. "B1752,B1752" "0,1"
|
|
bitfld.long 0x00 23. "B1751,B1751" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1750,B1750" "0,1"
|
|
bitfld.long 0x00 21. "B1749,B1749" "0,1"
|
|
bitfld.long 0x00 20. "B1748,B1748" "0,1"
|
|
bitfld.long 0x00 19. "B1747,B1747" "0,1"
|
|
bitfld.long 0x00 18. "B1746,B1746" "0,1"
|
|
bitfld.long 0x00 17. "B1745,B1745" "0,1"
|
|
bitfld.long 0x00 16. "B1744,B1744" "0,1"
|
|
bitfld.long 0x00 15. "B1743,B1743" "0,1"
|
|
bitfld.long 0x00 14. "B1742,B1742" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1741,B1741" "0,1"
|
|
bitfld.long 0x00 12. "B1740,B1740" "0,1"
|
|
bitfld.long 0x00 11. "B1739,B1739" "0,1"
|
|
bitfld.long 0x00 10. "B1738,B1738" "0,1"
|
|
bitfld.long 0x00 9. "B1737,B1737" "0,1"
|
|
bitfld.long 0x00 8. "B1736,B1736" "0,1"
|
|
bitfld.long 0x00 7. "B1735,B1735" "0,1"
|
|
bitfld.long 0x00 6. "B1734,B1734" "0,1"
|
|
bitfld.long 0x00 5. "B1733,B1733" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1732,B1732" "0,1"
|
|
bitfld.long 0x00 3. "B1731,B1731" "0,1"
|
|
bitfld.long 0x00 2. "B1730,B1730" "0,1"
|
|
bitfld.long 0x00 1. "B1729,B1729" "0,1"
|
|
bitfld.long 0x00 0. "B1728,B1728" "0,1"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "MPCBB2_VCTR55,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1791,B1791" "0,1"
|
|
bitfld.long 0x00 30. "B1790,B1790" "0,1"
|
|
bitfld.long 0x00 29. "B1789,B1789" "0,1"
|
|
bitfld.long 0x00 28. "B1788,B1788" "0,1"
|
|
bitfld.long 0x00 27. "B1787,B1787" "0,1"
|
|
bitfld.long 0x00 26. "B1786,B1786" "0,1"
|
|
bitfld.long 0x00 25. "B1785,B1785" "0,1"
|
|
bitfld.long 0x00 24. "B1784,B1784" "0,1"
|
|
bitfld.long 0x00 23. "B1783,B1783" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1782,B1782" "0,1"
|
|
bitfld.long 0x00 21. "B1781,B1781" "0,1"
|
|
bitfld.long 0x00 20. "B1780,B1780" "0,1"
|
|
bitfld.long 0x00 19. "B1779,B1779" "0,1"
|
|
bitfld.long 0x00 18. "B1778,B1778" "0,1"
|
|
bitfld.long 0x00 17. "B1777,B1777" "0,1"
|
|
bitfld.long 0x00 16. "B1776,B1776" "0,1"
|
|
bitfld.long 0x00 15. "B1775,B1775" "0,1"
|
|
bitfld.long 0x00 14. "B1774,B1774" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1773,B1773" "0,1"
|
|
bitfld.long 0x00 12. "B1772,B1772" "0,1"
|
|
bitfld.long 0x00 11. "B1771,B1771" "0,1"
|
|
bitfld.long 0x00 10. "B1770,B1770" "0,1"
|
|
bitfld.long 0x00 9. "B1769,B1769" "0,1"
|
|
bitfld.long 0x00 8. "B1768,B1768" "0,1"
|
|
bitfld.long 0x00 7. "B1767,B1767" "0,1"
|
|
bitfld.long 0x00 6. "B1766,B1766" "0,1"
|
|
bitfld.long 0x00 5. "B1765,B1765" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1764,B1764" "0,1"
|
|
bitfld.long 0x00 3. "B1763,B1763" "0,1"
|
|
bitfld.long 0x00 2. "B1762,B1762" "0,1"
|
|
bitfld.long 0x00 1. "B1761,B1761" "0,1"
|
|
bitfld.long 0x00 0. "B1760,B1760" "0,1"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "MPCBB2_VCTR56,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1823,B1823" "0,1"
|
|
bitfld.long 0x00 30. "B1822,B1822" "0,1"
|
|
bitfld.long 0x00 29. "B1821,B1821" "0,1"
|
|
bitfld.long 0x00 28. "B1820,B1820" "0,1"
|
|
bitfld.long 0x00 27. "B1819,B1819" "0,1"
|
|
bitfld.long 0x00 26. "B1818,B1818" "0,1"
|
|
bitfld.long 0x00 25. "B1817,B1817" "0,1"
|
|
bitfld.long 0x00 24. "B1816,B1816" "0,1"
|
|
bitfld.long 0x00 23. "B1815,B1815" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1814,B1814" "0,1"
|
|
bitfld.long 0x00 21. "B1813,B1813" "0,1"
|
|
bitfld.long 0x00 20. "B1812,B1812" "0,1"
|
|
bitfld.long 0x00 19. "B1811,B1811" "0,1"
|
|
bitfld.long 0x00 18. "B1810,B1810" "0,1"
|
|
bitfld.long 0x00 17. "B1809,B1809" "0,1"
|
|
bitfld.long 0x00 16. "B1808,B1808" "0,1"
|
|
bitfld.long 0x00 15. "B1807,B1807" "0,1"
|
|
bitfld.long 0x00 14. "B1806,B1806" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1805,B1805" "0,1"
|
|
bitfld.long 0x00 12. "B1804,B1804" "0,1"
|
|
bitfld.long 0x00 11. "B1803,B1803" "0,1"
|
|
bitfld.long 0x00 10. "B1802,B1802" "0,1"
|
|
bitfld.long 0x00 9. "B1801,B1801" "0,1"
|
|
bitfld.long 0x00 8. "B1800,B1800" "0,1"
|
|
bitfld.long 0x00 7. "B1799,B1799" "0,1"
|
|
bitfld.long 0x00 6. "B1798,B1798" "0,1"
|
|
bitfld.long 0x00 5. "B1797,B1797" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1796,B1796" "0,1"
|
|
bitfld.long 0x00 3. "B1795,B1795" "0,1"
|
|
bitfld.long 0x00 2. "B1794,B1794" "0,1"
|
|
bitfld.long 0x00 1. "B1793,B1793" "0,1"
|
|
bitfld.long 0x00 0. "B1792,B1792" "0,1"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "MPCBB2_VCTR57,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1855,B1855" "0,1"
|
|
bitfld.long 0x00 30. "B1854,B1854" "0,1"
|
|
bitfld.long 0x00 29. "B1853,B1853" "0,1"
|
|
bitfld.long 0x00 28. "B1852,B1852" "0,1"
|
|
bitfld.long 0x00 27. "B1851,B1851" "0,1"
|
|
bitfld.long 0x00 26. "B1850,B1850" "0,1"
|
|
bitfld.long 0x00 25. "B1849,B1849" "0,1"
|
|
bitfld.long 0x00 24. "B1848,B1848" "0,1"
|
|
bitfld.long 0x00 23. "B1847,B1847" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1846,B1846" "0,1"
|
|
bitfld.long 0x00 21. "B1845,B1845" "0,1"
|
|
bitfld.long 0x00 20. "B1844,B1844" "0,1"
|
|
bitfld.long 0x00 19. "B1843,B1843" "0,1"
|
|
bitfld.long 0x00 18. "B1842,B1842" "0,1"
|
|
bitfld.long 0x00 17. "B1841,B1841" "0,1"
|
|
bitfld.long 0x00 16. "B1840,B1840" "0,1"
|
|
bitfld.long 0x00 15. "B1839,B1839" "0,1"
|
|
bitfld.long 0x00 14. "B1838,B1838" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1837,B1837" "0,1"
|
|
bitfld.long 0x00 12. "B1836,B1836" "0,1"
|
|
bitfld.long 0x00 11. "B1835,B1835" "0,1"
|
|
bitfld.long 0x00 10. "B1834,B1834" "0,1"
|
|
bitfld.long 0x00 9. "B1833,B1833" "0,1"
|
|
bitfld.long 0x00 8. "B1832,B1832" "0,1"
|
|
bitfld.long 0x00 7. "B1831,B1831" "0,1"
|
|
bitfld.long 0x00 6. "B1830,B1830" "0,1"
|
|
bitfld.long 0x00 5. "B1829,B1829" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1828,B1828" "0,1"
|
|
bitfld.long 0x00 3. "B1827,B1827" "0,1"
|
|
bitfld.long 0x00 2. "B1826,B1826" "0,1"
|
|
bitfld.long 0x00 1. "B1825,B1825" "0,1"
|
|
bitfld.long 0x00 0. "B1824,B1824" "0,1"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "MPCBB2_VCTR58,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1887,B1887" "0,1"
|
|
bitfld.long 0x00 30. "B1886,B1886" "0,1"
|
|
bitfld.long 0x00 29. "B1885,B1885" "0,1"
|
|
bitfld.long 0x00 28. "B1884,B1884" "0,1"
|
|
bitfld.long 0x00 27. "B1883,B1883" "0,1"
|
|
bitfld.long 0x00 26. "B1882,B1882" "0,1"
|
|
bitfld.long 0x00 25. "B1881,B1881" "0,1"
|
|
bitfld.long 0x00 24. "B1880,B1880" "0,1"
|
|
bitfld.long 0x00 23. "B1879,B1879" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1878,B1878" "0,1"
|
|
bitfld.long 0x00 21. "B1877,B1877" "0,1"
|
|
bitfld.long 0x00 20. "B1876,B1876" "0,1"
|
|
bitfld.long 0x00 19. "B1875,B1875" "0,1"
|
|
bitfld.long 0x00 18. "B1874,B1874" "0,1"
|
|
bitfld.long 0x00 17. "B1873,B1873" "0,1"
|
|
bitfld.long 0x00 16. "B1872,B1872" "0,1"
|
|
bitfld.long 0x00 15. "B1871,B1871" "0,1"
|
|
bitfld.long 0x00 14. "B1870,B1870" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1869,B1869" "0,1"
|
|
bitfld.long 0x00 12. "B1868,B1868" "0,1"
|
|
bitfld.long 0x00 11. "B1867,B1867" "0,1"
|
|
bitfld.long 0x00 10. "B1866,B1866" "0,1"
|
|
bitfld.long 0x00 9. "B1865,B1865" "0,1"
|
|
bitfld.long 0x00 8. "B1864,B1864" "0,1"
|
|
bitfld.long 0x00 7. "B1863,B1863" "0,1"
|
|
bitfld.long 0x00 6. "B1862,B1862" "0,1"
|
|
bitfld.long 0x00 5. "B1861,B1861" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1860,B1860" "0,1"
|
|
bitfld.long 0x00 3. "B1859,B1859" "0,1"
|
|
bitfld.long 0x00 2. "B1858,B1858" "0,1"
|
|
bitfld.long 0x00 1. "B1857,B1857" "0,1"
|
|
bitfld.long 0x00 0. "B1856,B1856" "0,1"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "MPCBB2_VCTR59,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1919,B1919" "0,1"
|
|
bitfld.long 0x00 30. "B1918,B1918" "0,1"
|
|
bitfld.long 0x00 29. "B1917,B1917" "0,1"
|
|
bitfld.long 0x00 28. "B1916,B1916" "0,1"
|
|
bitfld.long 0x00 27. "B1915,B1915" "0,1"
|
|
bitfld.long 0x00 26. "B1914,B1914" "0,1"
|
|
bitfld.long 0x00 25. "B1913,B1913" "0,1"
|
|
bitfld.long 0x00 24. "B1912,B1912" "0,1"
|
|
bitfld.long 0x00 23. "B1911,B1911" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1910,B1910" "0,1"
|
|
bitfld.long 0x00 21. "B1909,B1909" "0,1"
|
|
bitfld.long 0x00 20. "B1908,B1908" "0,1"
|
|
bitfld.long 0x00 19. "B1907,B1907" "0,1"
|
|
bitfld.long 0x00 18. "B1906,B1906" "0,1"
|
|
bitfld.long 0x00 17. "B1905,B1905" "0,1"
|
|
bitfld.long 0x00 16. "B1904,B1904" "0,1"
|
|
bitfld.long 0x00 15. "B1903,B1903" "0,1"
|
|
bitfld.long 0x00 14. "B1902,B1902" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1901,B1901" "0,1"
|
|
bitfld.long 0x00 12. "B1900,B1900" "0,1"
|
|
bitfld.long 0x00 11. "B1899,B1899" "0,1"
|
|
bitfld.long 0x00 10. "B1898,B1898" "0,1"
|
|
bitfld.long 0x00 9. "B1897,B1897" "0,1"
|
|
bitfld.long 0x00 8. "B1896,B1896" "0,1"
|
|
bitfld.long 0x00 7. "B1895,B1895" "0,1"
|
|
bitfld.long 0x00 6. "B1894,B1894" "0,1"
|
|
bitfld.long 0x00 5. "B1893,B1893" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1892,B1892" "0,1"
|
|
bitfld.long 0x00 3. "B1891,B1891" "0,1"
|
|
bitfld.long 0x00 2. "B1890,B1890" "0,1"
|
|
bitfld.long 0x00 1. "B1889,B1889" "0,1"
|
|
bitfld.long 0x00 0. "B1888,B1888" "0,1"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "MPCBB2_VCTR60,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1951,B1951" "0,1"
|
|
bitfld.long 0x00 30. "B1950,B1950" "0,1"
|
|
bitfld.long 0x00 29. "B1949,B1949" "0,1"
|
|
bitfld.long 0x00 28. "B1948,B1948" "0,1"
|
|
bitfld.long 0x00 27. "B1947,B1947" "0,1"
|
|
bitfld.long 0x00 26. "B1946,B1946" "0,1"
|
|
bitfld.long 0x00 25. "B1945,B1945" "0,1"
|
|
bitfld.long 0x00 24. "B1944,B1944" "0,1"
|
|
bitfld.long 0x00 23. "B1943,B1943" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1942,B1942" "0,1"
|
|
bitfld.long 0x00 21. "B1941,B1941" "0,1"
|
|
bitfld.long 0x00 20. "B1940,B1940" "0,1"
|
|
bitfld.long 0x00 19. "B1939,B1939" "0,1"
|
|
bitfld.long 0x00 18. "B1938,B1938" "0,1"
|
|
bitfld.long 0x00 17. "B1937,B1937" "0,1"
|
|
bitfld.long 0x00 16. "B1936,B1936" "0,1"
|
|
bitfld.long 0x00 15. "B1935,B1935" "0,1"
|
|
bitfld.long 0x00 14. "B1934,B1934" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1933,B1933" "0,1"
|
|
bitfld.long 0x00 12. "B1932,B1932" "0,1"
|
|
bitfld.long 0x00 11. "B1931,B1931" "0,1"
|
|
bitfld.long 0x00 10. "B1930,B1930" "0,1"
|
|
bitfld.long 0x00 9. "B1929,B1929" "0,1"
|
|
bitfld.long 0x00 8. "B1928,B1928" "0,1"
|
|
bitfld.long 0x00 7. "B1927,B1927" "0,1"
|
|
bitfld.long 0x00 6. "B1926,B1926" "0,1"
|
|
bitfld.long 0x00 5. "B1925,B1925" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1924,B1924" "0,1"
|
|
bitfld.long 0x00 3. "B1923,B1923" "0,1"
|
|
bitfld.long 0x00 2. "B1922,B1922" "0,1"
|
|
bitfld.long 0x00 1. "B1921,B1921" "0,1"
|
|
bitfld.long 0x00 0. "B1920,B1920" "0,1"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "MPCBB2_VCTR61,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B1983,B1983" "0,1"
|
|
bitfld.long 0x00 30. "B1982,B1982" "0,1"
|
|
bitfld.long 0x00 29. "B1981,B1981" "0,1"
|
|
bitfld.long 0x00 28. "B1980,B1980" "0,1"
|
|
bitfld.long 0x00 27. "B1979,B1979" "0,1"
|
|
bitfld.long 0x00 26. "B1978,B1978" "0,1"
|
|
bitfld.long 0x00 25. "B1977,B1977" "0,1"
|
|
bitfld.long 0x00 24. "B1976,B1976" "0,1"
|
|
bitfld.long 0x00 23. "B1975,B1975" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B1974,B1974" "0,1"
|
|
bitfld.long 0x00 21. "B1973,B1973" "0,1"
|
|
bitfld.long 0x00 20. "B1972,B1972" "0,1"
|
|
bitfld.long 0x00 19. "B1971,B1971" "0,1"
|
|
bitfld.long 0x00 18. "B1970,B1970" "0,1"
|
|
bitfld.long 0x00 17. "B1969,B1969" "0,1"
|
|
bitfld.long 0x00 16. "B1968,B1968" "0,1"
|
|
bitfld.long 0x00 15. "B1967,B1967" "0,1"
|
|
bitfld.long 0x00 14. "B1966,B1966" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1965,B1965" "0,1"
|
|
bitfld.long 0x00 12. "B1964,B1964" "0,1"
|
|
bitfld.long 0x00 11. "B1963,B1963" "0,1"
|
|
bitfld.long 0x00 10. "B1962,B1962" "0,1"
|
|
bitfld.long 0x00 9. "B1961,B1961" "0,1"
|
|
bitfld.long 0x00 8. "B1960,B1960" "0,1"
|
|
bitfld.long 0x00 7. "B1959,B1959" "0,1"
|
|
bitfld.long 0x00 6. "B1958,B1958" "0,1"
|
|
bitfld.long 0x00 5. "B1957,B1957" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1956,B1956" "0,1"
|
|
bitfld.long 0x00 3. "B1955,B1955" "0,1"
|
|
bitfld.long 0x00 2. "B1954,B1954" "0,1"
|
|
bitfld.long 0x00 1. "B1953,B1953" "0,1"
|
|
bitfld.long 0x00 0. "B1952,B1952" "0,1"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "MPCBB2_VCTR62,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B2015,B2015" "0,1"
|
|
bitfld.long 0x00 30. "B2014,B2014" "0,1"
|
|
bitfld.long 0x00 29. "B2013,B2013" "0,1"
|
|
bitfld.long 0x00 28. "B2012,B2012" "0,1"
|
|
bitfld.long 0x00 27. "B2011,B2011" "0,1"
|
|
bitfld.long 0x00 26. "B2010,B2010" "0,1"
|
|
bitfld.long 0x00 25. "B2009,B2009" "0,1"
|
|
bitfld.long 0x00 24. "B2008,B2008" "0,1"
|
|
bitfld.long 0x00 23. "B2007,B2007" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B2006,B2006" "0,1"
|
|
bitfld.long 0x00 21. "B2005,B2005" "0,1"
|
|
bitfld.long 0x00 20. "B2004,B2004" "0,1"
|
|
bitfld.long 0x00 19. "B2003,B2003" "0,1"
|
|
bitfld.long 0x00 18. "B2002,B2002" "0,1"
|
|
bitfld.long 0x00 17. "B2001,B2001" "0,1"
|
|
bitfld.long 0x00 16. "B2000,B2000" "0,1"
|
|
bitfld.long 0x00 15. "B1999,B1999" "0,1"
|
|
bitfld.long 0x00 14. "B1998,B1998" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B1997,B1997" "0,1"
|
|
bitfld.long 0x00 12. "B1996,B1996" "0,1"
|
|
bitfld.long 0x00 11. "B1995,B1995" "0,1"
|
|
bitfld.long 0x00 10. "B1994,B1994" "0,1"
|
|
bitfld.long 0x00 9. "B1993,B1993" "0,1"
|
|
bitfld.long 0x00 8. "B1992,B1992" "0,1"
|
|
bitfld.long 0x00 7. "B1991,B1991" "0,1"
|
|
bitfld.long 0x00 6. "B1990,B1990" "0,1"
|
|
bitfld.long 0x00 5. "B1989,B1989" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B1988,B1988" "0,1"
|
|
bitfld.long 0x00 3. "B1987,B1987" "0,1"
|
|
bitfld.long 0x00 2. "B1986,B1986" "0,1"
|
|
bitfld.long 0x00 1. "B1985,B1985" "0,1"
|
|
bitfld.long 0x00 0. "B1984,B1984" "0,1"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "MPCBB2_VCTR63,MPCBBx vector register"
|
|
bitfld.long 0x00 31. "B2047,B2047" "0,1"
|
|
bitfld.long 0x00 30. "B2046,B2046" "0,1"
|
|
bitfld.long 0x00 29. "B2045,B2045" "0,1"
|
|
bitfld.long 0x00 28. "B2044,B2044" "0,1"
|
|
bitfld.long 0x00 27. "B2043,B2043" "0,1"
|
|
bitfld.long 0x00 26. "B2042,B2042" "0,1"
|
|
bitfld.long 0x00 25. "B2041,B2041" "0,1"
|
|
bitfld.long 0x00 24. "B2040,B2040" "0,1"
|
|
bitfld.long 0x00 23. "B2039,B2039" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "B2038,B2038" "0,1"
|
|
bitfld.long 0x00 21. "B2037,B2037" "0,1"
|
|
bitfld.long 0x00 20. "B2036,B2036" "0,1"
|
|
bitfld.long 0x00 19. "B2035,B2035" "0,1"
|
|
bitfld.long 0x00 18. "B2034,B2034" "0,1"
|
|
bitfld.long 0x00 17. "B2033,B2033" "0,1"
|
|
bitfld.long 0x00 16. "B2032,B2032" "0,1"
|
|
bitfld.long 0x00 15. "B2031,B2031" "0,1"
|
|
bitfld.long 0x00 14. "B2030,B2030" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "B2029,B2029" "0,1"
|
|
bitfld.long 0x00 12. "B2028,B2028" "0,1"
|
|
bitfld.long 0x00 11. "B2027,B2027" "0,1"
|
|
bitfld.long 0x00 10. "B2026,B2026" "0,1"
|
|
bitfld.long 0x00 9. "B2025,B2025" "0,1"
|
|
bitfld.long 0x00 8. "B2024,B2024" "0,1"
|
|
bitfld.long 0x00 7. "B2023,B2023" "0,1"
|
|
bitfld.long 0x00 6. "B2022,B2022" "0,1"
|
|
bitfld.long 0x00 5. "B2021,B2021" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "B2020,B2020" "0,1"
|
|
bitfld.long 0x00 3. "B2019,B2019" "0,1"
|
|
bitfld.long 0x00 2. "B2018,B2018" "0,1"
|
|
bitfld.long 0x00 1. "B2017,B2017" "0,1"
|
|
bitfld.long 0x00 0. "B2016,B2016" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "SPI (Serial peripheral interface)"
|
|
repeat 3. (list 1. 2. 3.) (list ad:0x50013000 ad:0x50003800 ad:0x50003C00)
|
|
tree "SEC_SPI$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x00 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x00 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x00 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x00 11. "CRCL,CRC length" "0,1"
|
|
bitfld.long 0x00 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x00 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x00 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x00 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x00 6. "SPE,SPI enable" "0,1"
|
|
bitfld.long 0x00 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x00 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x00 0. "CPHA,Clock phase" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x00 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x00 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
bitfld.long 0x00 8.--11. "DS,Data size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x00 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x00 2. "SSOE,SS output enable" "0,1"
|
|
bitfld.long 0x00 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR,status register"
|
|
rbitfld.long 0x00 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x00 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x00 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x00 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x00 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x00 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x00 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x00 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x00 0. "RXNE,Receive buffer not empty" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DR,data register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DR,Data register"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RxCRC,Rx CRC register"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TxCRC,Tx CRC register"
|
|
tree.end
|
|
repeat.end
|
|
repeat 3. (list 1. 2. 3.) (list ad:0x40013000 ad:0x40003800 ad:0x40003C00)
|
|
tree "SPI$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 15. "BIDIMODE,Bidirectional data mode enable" "0,1"
|
|
bitfld.long 0x00 14. "BIDIOE,Output enable in bidirectional mode" "0,1"
|
|
bitfld.long 0x00 13. "CRCEN,Hardware CRC calculation enable" "0,1"
|
|
bitfld.long 0x00 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x00 11. "CRCL,CRC length" "0,1"
|
|
bitfld.long 0x00 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x00 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x00 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x00 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x00 6. "SPE,SPI enable" "0,1"
|
|
bitfld.long 0x00 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x00 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x00 0. "CPHA,Clock phase" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 14. "LDMA_TX,Last DMA transfer for transmission" "0,1"
|
|
bitfld.long 0x00 13. "LDMA_RX,Last DMA transfer for reception" "0,1"
|
|
bitfld.long 0x00 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
bitfld.long 0x00 8.--11. "DS,Data size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "TXEIE,Tx buffer empty interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "RXNEIE,RX buffer not empty interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x00 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x00 2. "SSOE,SS output enable" "0,1"
|
|
bitfld.long 0x00 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR,status register"
|
|
rbitfld.long 0x00 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x00 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x00 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x00 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x00 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x00 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x00 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x00 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x00 0. "RXNE,Receive buffer not empty" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DR,data register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DR,Data register"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RxCRC,Rx CRC register"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TxCRC,Tx CRC register"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SYSCFG (System configuration controller)"
|
|
tree "SEC_SYSCFG"
|
|
base ad:0x50010000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SECCFGR,SYSCFG secure configuration register"
|
|
bitfld.long 0x00 3. "FPUSEC,FPUSEC" "0,1"
|
|
bitfld.long 0x00 2. "SRAM2SEC,SRAM2 security" "0,1"
|
|
bitfld.long 0x00 1. "CLASSBSEC,ClassB security" "0,1"
|
|
bitfld.long 0x00 0. "SYSCFGSEC,SYSCFG clock control security" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFGR1,configuration register 1"
|
|
bitfld.long 0x00 23. "I2C4_FMP,I2C4_FMP" "0,1"
|
|
bitfld.long 0x00 22. "I2C3_FMP,I2C3 Fast-mode Plus driving capability activation" "0,1"
|
|
bitfld.long 0x00 21. "I2C2_FMP,I2C2 Fast-mode Plus driving capability activation" "0,1"
|
|
bitfld.long 0x00 20. "I2C1_FMP,I2C1 Fast-mode Plus driving capability activation" "0,1"
|
|
bitfld.long 0x00 19. "I2C_PB9_FMP,Fast-mode Plus (Fm+) driving capability activation on PB9" "0,1"
|
|
bitfld.long 0x00 18. "I2C_PB8_FMP,Fast-mode Plus (Fm+) driving capability activation on PB8" "0,1"
|
|
bitfld.long 0x00 17. "I2C_PB7_FMP,Fast-mode Plus (Fm+) driving capability activation on PB7" "0,1"
|
|
bitfld.long 0x00 16. "I2C_PB6_FMP,Fast-mode Plus (Fm+) driving capability activation on PB6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ANASWVDD,GPIO analog switch control voltage selection" "0,1"
|
|
bitfld.long 0x00 8. "BOOSTEN,I/O analog switch voltage booster enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FPUIMR,FPU interrupt mask register"
|
|
bitfld.long 0x00 0.--5. "FPU_IE,Floating point unit interrupts enable bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNSLCKR,SYSCFG CPU non-secure lock register"
|
|
bitfld.long 0x00 1. "LOCKNSMPU,Non-secure MPU registers lock" "0,1"
|
|
bitfld.long 0x00 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CSLOCKR,SYSCFG CPU secure lock register"
|
|
bitfld.long 0x00 2. "LOCKSAU,LOCKSAU" "0,1"
|
|
bitfld.long 0x00 1. "LOCKSMPU,LOCKSMPU" "0,1"
|
|
bitfld.long 0x00 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SCSR,SCSR"
|
|
rbitfld.long 0x00 1. "SRAM2BSY,SRAM2 busy by erase operation" "0,1"
|
|
bitfld.long 0x00 0. "SRAM2ER,SRAM2 Erase" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CFGR2,CFGR2"
|
|
bitfld.long 0x00 8. "SPF,SRAM2 parity error flag" "0,1"
|
|
bitfld.long 0x00 3. "ECCL,ECC Lock" "0,1"
|
|
bitfld.long 0x00 2. "PVDL,PVD lock enable bit" "0,1"
|
|
bitfld.long 0x00 1. "SPL,SRAM2 parity lock bit" "0,1"
|
|
bitfld.long 0x00 0. "CLL,LOCKUP (hardfault) output enable bit" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "SWPR,SWPR"
|
|
bitfld.long 0x00 31. "P31WP,SRAM2 page 31 write protection" "0,1"
|
|
bitfld.long 0x00 30. "P30WP,P30WP" "0,1"
|
|
bitfld.long 0x00 29. "P29WP,P29WP" "0,1"
|
|
bitfld.long 0x00 28. "P28WP,P28WP" "0,1"
|
|
bitfld.long 0x00 27. "P27WP,P27WP" "0,1"
|
|
bitfld.long 0x00 26. "P26WP,P26WP" "0,1"
|
|
bitfld.long 0x00 25. "P25WP,P25WP" "0,1"
|
|
bitfld.long 0x00 24. "P24WP,P24WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "P23WP,P23WP" "0,1"
|
|
bitfld.long 0x00 22. "P22WP,P22WP" "0,1"
|
|
bitfld.long 0x00 21. "P21WP,P21WP" "0,1"
|
|
bitfld.long 0x00 20. "P20WP,P20WP" "0,1"
|
|
bitfld.long 0x00 19. "P19WP,P19WP" "0,1"
|
|
bitfld.long 0x00 18. "P18WP,P18WP" "0,1"
|
|
bitfld.long 0x00 17. "P17WP,P17WP" "0,1"
|
|
bitfld.long 0x00 16. "P16WP,P16WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "P15WP,P15WP" "0,1"
|
|
bitfld.long 0x00 14. "P14WP,P14WP" "0,1"
|
|
bitfld.long 0x00 13. "P13WP,P13WP" "0,1"
|
|
bitfld.long 0x00 12. "P12WP,P12WP" "0,1"
|
|
bitfld.long 0x00 11. "P11WP,P11WP" "0,1"
|
|
bitfld.long 0x00 10. "P10WP,P10WP" "0,1"
|
|
bitfld.long 0x00 9. "P9WP,P9WP" "0,1"
|
|
bitfld.long 0x00 8. "P8WP,P8WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "P7WP,P7WP" "0,1"
|
|
bitfld.long 0x00 6. "P6WP,P6WP" "0,1"
|
|
bitfld.long 0x00 5. "P5WP,P5WP" "0,1"
|
|
bitfld.long 0x00 4. "P4WP,P4WP" "0,1"
|
|
bitfld.long 0x00 3. "P3WP,P3WP" "0,1"
|
|
bitfld.long 0x00 2. "P2WP,P2WP" "0,1"
|
|
bitfld.long 0x00 1. "P1WP,P1WP" "0,1"
|
|
bitfld.long 0x00 0. "P0WP,P0WP" "0,1"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "SKR,SKR"
|
|
hexmask.long.byte 0x00 0.--7. 1. "KEY,SRAM2 write protection key for software erase"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SWPR2,SWPR2"
|
|
bitfld.long 0x00 31. "P63WP,P63WP" "0,1"
|
|
bitfld.long 0x00 30. "P62WP,P62WP" "0,1"
|
|
bitfld.long 0x00 29. "P61WP,P61WP" "0,1"
|
|
bitfld.long 0x00 28. "P60WP,P60WP" "0,1"
|
|
bitfld.long 0x00 27. "P59WP,P59WP" "0,1"
|
|
bitfld.long 0x00 26. "P58WP,P58WP" "0,1"
|
|
bitfld.long 0x00 25. "P57WP,P57WP" "0,1"
|
|
bitfld.long 0x00 24. "P56WP,P56WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "P55WP,P55WP" "0,1"
|
|
bitfld.long 0x00 22. "P54WP,P54WP" "0,1"
|
|
bitfld.long 0x00 21. "P53WP,P53WP" "0,1"
|
|
bitfld.long 0x00 20. "P52WP,P52WP" "0,1"
|
|
bitfld.long 0x00 19. "P51WP,P51WP" "0,1"
|
|
bitfld.long 0x00 18. "P50WP,P50WP" "0,1"
|
|
bitfld.long 0x00 17. "P49WP,P49WP" "0,1"
|
|
bitfld.long 0x00 16. "P48WP,P48WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "P47WP,P47WP" "0,1"
|
|
bitfld.long 0x00 14. "P46WP,P46WP" "0,1"
|
|
bitfld.long 0x00 13. "P45WP,P45WP" "0,1"
|
|
bitfld.long 0x00 12. "P44WP,P44WP" "0,1"
|
|
bitfld.long 0x00 11. "P43WP,P43WP" "0,1"
|
|
bitfld.long 0x00 10. "P42WP,P42WP" "0,1"
|
|
bitfld.long 0x00 9. "P41WP,P41WP" "0,1"
|
|
bitfld.long 0x00 8. "P40WP,P40WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "P39WP,P39WP" "0,1"
|
|
bitfld.long 0x00 6. "P38WP,P38WP" "0,1"
|
|
bitfld.long 0x00 5. "P37WP,P37WP" "0,1"
|
|
bitfld.long 0x00 4. "P36WP,P36WP" "0,1"
|
|
bitfld.long 0x00 3. "P35WP,P35WP" "0,1"
|
|
bitfld.long 0x00 2. "P34WP,P34WP" "0,1"
|
|
bitfld.long 0x00 1. "P33WP,P33WP" "0,1"
|
|
bitfld.long 0x00 0. "P32WP,P32WP" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RSSCMDR,RSSCMDR"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSSCMD,RSS commands"
|
|
tree.end
|
|
tree "SYSCFG"
|
|
base ad:0x40010000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SECCFGR,SYSCFG secure configuration register"
|
|
bitfld.long 0x00 3. "FPUSEC,FPUSEC" "0,1"
|
|
bitfld.long 0x00 2. "SRAM2SEC,SRAM2 security" "0,1"
|
|
bitfld.long 0x00 1. "CLASSBSEC,ClassB security" "0,1"
|
|
bitfld.long 0x00 0. "SYSCFGSEC,SYSCFG clock control security" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFGR1,configuration register 1"
|
|
bitfld.long 0x00 23. "I2C4_FMP,I2C4_FMP" "0,1"
|
|
bitfld.long 0x00 22. "I2C3_FMP,I2C3 Fast-mode Plus driving capability activation" "0,1"
|
|
bitfld.long 0x00 21. "I2C2_FMP,I2C2 Fast-mode Plus driving capability activation" "0,1"
|
|
bitfld.long 0x00 20. "I2C1_FMP,I2C1 Fast-mode Plus driving capability activation" "0,1"
|
|
bitfld.long 0x00 19. "I2C_PB9_FMP,Fast-mode Plus (Fm+) driving capability activation on PB9" "0,1"
|
|
bitfld.long 0x00 18. "I2C_PB8_FMP,Fast-mode Plus (Fm+) driving capability activation on PB8" "0,1"
|
|
bitfld.long 0x00 17. "I2C_PB7_FMP,Fast-mode Plus (Fm+) driving capability activation on PB7" "0,1"
|
|
bitfld.long 0x00 16. "I2C_PB6_FMP,Fast-mode Plus (Fm+) driving capability activation on PB6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ANASWVDD,GPIO analog switch control voltage selection" "0,1"
|
|
bitfld.long 0x00 8. "BOOSTEN,I/O analog switch voltage booster enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FPUIMR,FPU interrupt mask register"
|
|
bitfld.long 0x00 0.--5. "FPU_IE,Floating point unit interrupts enable bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNSLCKR,SYSCFG CPU non-secure lock register"
|
|
bitfld.long 0x00 1. "LOCKNSMPU,Non-secure MPU registers lock" "0,1"
|
|
bitfld.long 0x00 0. "LOCKNSVTOR,VTOR_NS register lock" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CSLOCKR,SYSCFG CPU secure lock register"
|
|
bitfld.long 0x00 2. "LOCKSAU,LOCKSAU" "0,1"
|
|
bitfld.long 0x00 1. "LOCKSMPU,LOCKSMPU" "0,1"
|
|
bitfld.long 0x00 0. "LOCKSVTAIRCR,LOCKSVTAIRCR" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SCSR,SCSR"
|
|
rbitfld.long 0x00 1. "SRAM2BSY,SRAM2 busy by erase operation" "0,1"
|
|
bitfld.long 0x00 0. "SRAM2ER,SRAM2 Erase" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CFGR2,CFGR2"
|
|
bitfld.long 0x00 8. "SPF,SRAM2 parity error flag" "0,1"
|
|
bitfld.long 0x00 3. "ECCL,ECC Lock" "0,1"
|
|
bitfld.long 0x00 2. "PVDL,PVD lock enable bit" "0,1"
|
|
bitfld.long 0x00 1. "SPL,SRAM2 parity lock bit" "0,1"
|
|
bitfld.long 0x00 0. "CLL,LOCKUP (hardfault) output enable bit" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "SWPR,SWPR"
|
|
bitfld.long 0x00 31. "P31WP,SRAM2 page 31 write protection" "0,1"
|
|
bitfld.long 0x00 30. "P30WP,P30WP" "0,1"
|
|
bitfld.long 0x00 29. "P29WP,P29WP" "0,1"
|
|
bitfld.long 0x00 28. "P28WP,P28WP" "0,1"
|
|
bitfld.long 0x00 27. "P27WP,P27WP" "0,1"
|
|
bitfld.long 0x00 26. "P26WP,P26WP" "0,1"
|
|
bitfld.long 0x00 25. "P25WP,P25WP" "0,1"
|
|
bitfld.long 0x00 24. "P24WP,P24WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "P23WP,P23WP" "0,1"
|
|
bitfld.long 0x00 22. "P22WP,P22WP" "0,1"
|
|
bitfld.long 0x00 21. "P21WP,P21WP" "0,1"
|
|
bitfld.long 0x00 20. "P20WP,P20WP" "0,1"
|
|
bitfld.long 0x00 19. "P19WP,P19WP" "0,1"
|
|
bitfld.long 0x00 18. "P18WP,P18WP" "0,1"
|
|
bitfld.long 0x00 17. "P17WP,P17WP" "0,1"
|
|
bitfld.long 0x00 16. "P16WP,P16WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "P15WP,P15WP" "0,1"
|
|
bitfld.long 0x00 14. "P14WP,P14WP" "0,1"
|
|
bitfld.long 0x00 13. "P13WP,P13WP" "0,1"
|
|
bitfld.long 0x00 12. "P12WP,P12WP" "0,1"
|
|
bitfld.long 0x00 11. "P11WP,P11WP" "0,1"
|
|
bitfld.long 0x00 10. "P10WP,P10WP" "0,1"
|
|
bitfld.long 0x00 9. "P9WP,P9WP" "0,1"
|
|
bitfld.long 0x00 8. "P8WP,P8WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "P7WP,P7WP" "0,1"
|
|
bitfld.long 0x00 6. "P6WP,P6WP" "0,1"
|
|
bitfld.long 0x00 5. "P5WP,P5WP" "0,1"
|
|
bitfld.long 0x00 4. "P4WP,P4WP" "0,1"
|
|
bitfld.long 0x00 3. "P3WP,P3WP" "0,1"
|
|
bitfld.long 0x00 2. "P2WP,P2WP" "0,1"
|
|
bitfld.long 0x00 1. "P1WP,P1WP" "0,1"
|
|
bitfld.long 0x00 0. "P0WP,P0WP" "0,1"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "SKR,SKR"
|
|
hexmask.long.byte 0x00 0.--7. 1. "KEY,SRAM2 write protection key for software erase"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SWPR2,SWPR2"
|
|
bitfld.long 0x00 31. "P63WP,P63WP" "0,1"
|
|
bitfld.long 0x00 30. "P62WP,P62WP" "0,1"
|
|
bitfld.long 0x00 29. "P61WP,P61WP" "0,1"
|
|
bitfld.long 0x00 28. "P60WP,P60WP" "0,1"
|
|
bitfld.long 0x00 27. "P59WP,P59WP" "0,1"
|
|
bitfld.long 0x00 26. "P58WP,P58WP" "0,1"
|
|
bitfld.long 0x00 25. "P57WP,P57WP" "0,1"
|
|
bitfld.long 0x00 24. "P56WP,P56WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "P55WP,P55WP" "0,1"
|
|
bitfld.long 0x00 22. "P54WP,P54WP" "0,1"
|
|
bitfld.long 0x00 21. "P53WP,P53WP" "0,1"
|
|
bitfld.long 0x00 20. "P52WP,P52WP" "0,1"
|
|
bitfld.long 0x00 19. "P51WP,P51WP" "0,1"
|
|
bitfld.long 0x00 18. "P50WP,P50WP" "0,1"
|
|
bitfld.long 0x00 17. "P49WP,P49WP" "0,1"
|
|
bitfld.long 0x00 16. "P48WP,P48WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "P47WP,P47WP" "0,1"
|
|
bitfld.long 0x00 14. "P46WP,P46WP" "0,1"
|
|
bitfld.long 0x00 13. "P45WP,P45WP" "0,1"
|
|
bitfld.long 0x00 12. "P44WP,P44WP" "0,1"
|
|
bitfld.long 0x00 11. "P43WP,P43WP" "0,1"
|
|
bitfld.long 0x00 10. "P42WP,P42WP" "0,1"
|
|
bitfld.long 0x00 9. "P41WP,P41WP" "0,1"
|
|
bitfld.long 0x00 8. "P40WP,P40WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "P39WP,P39WP" "0,1"
|
|
bitfld.long 0x00 6. "P38WP,P38WP" "0,1"
|
|
bitfld.long 0x00 5. "P37WP,P37WP" "0,1"
|
|
bitfld.long 0x00 4. "P36WP,P36WP" "0,1"
|
|
bitfld.long 0x00 3. "P35WP,P35WP" "0,1"
|
|
bitfld.long 0x00 2. "P34WP,P34WP" "0,1"
|
|
bitfld.long 0x00 1. "P33WP,P33WP" "0,1"
|
|
bitfld.long 0x00 0. "P32WP,P32WP" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RSSCMDR,RSSCMDR"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSSCMD,RSS commands"
|
|
tree.end
|
|
tree.end
|
|
tree "TAMP (Tamper and backup registers)"
|
|
tree "SEC_TAMP"
|
|
base ad:0x50003400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 23. "ITAMP8E,ITAMP5E" "0,1"
|
|
bitfld.long 0x00 20. "ITAMP5E,ITAMP5E" "0,1"
|
|
bitfld.long 0x00 18. "ITAMP3E,ITAMP3E" "0,1"
|
|
bitfld.long 0x00 17. "ITAMP2E,ITAMP2E" "0,1"
|
|
bitfld.long 0x00 16. "ITAMP1E,ITAMP1E" "0,1"
|
|
bitfld.long 0x00 7. "TAMP8E,TAMP8E" "0,1"
|
|
bitfld.long 0x00 6. "TAMP7E,TAMP7E" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6E,TAMP6E" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5E,TAMP5E" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TAMP4E,TAMP4E" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3E,TAMP3E" "0,1"
|
|
bitfld.long 0x00 1. "TAMP2E,TAMP2E" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1E,TAMP1E" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 31. "TAMP8TRG,TAMP8TRG" "0,1"
|
|
bitfld.long 0x00 30. "TAMP7TRG,TAMP7TRG" "0,1"
|
|
bitfld.long 0x00 29. "TAMP6TRG,TAMP6TRG" "0,1"
|
|
bitfld.long 0x00 28. "TAMP5TRG,TAMP5TRG" "0,1"
|
|
bitfld.long 0x00 27. "TAMP4TRG,TAMP4TRG" "0,1"
|
|
bitfld.long 0x00 26. "TAMP3TRG,TAMP3TRG" "0,1"
|
|
bitfld.long 0x00 25. "TAMP2TRG,TAMP2TRG" "0,1"
|
|
bitfld.long 0x00 24. "TAMP1TRG,TAMP1TRG" "0,1"
|
|
bitfld.long 0x00 23. "BKERASE,BKERASE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TAMP3MSK,TAMP3MSK" "0,1"
|
|
bitfld.long 0x00 17. "TAMP2MSK,TAMP2MSK" "0,1"
|
|
bitfld.long 0x00 16. "TAMP1MSK,TAMP1MSK" "0,1"
|
|
bitfld.long 0x00 7. "TAMP8NOER,TAMP8NOER" "0,1"
|
|
bitfld.long 0x00 6. "TAMP7NOER,TAMP7NOER" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6NOER,TAMP6NOER" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5NOER,TAMP5NOER" "0,1"
|
|
bitfld.long 0x00 3. "TAMP4NOER,TAMP4NOER" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3NOER,TAMP3NOER" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TAMP2NOER,TAMP2NOER" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1NOER,TAMP1NOER" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,control register 3"
|
|
bitfld.long 0x00 7. "ITAMP8NOER,ITAMP8NOER" "0,1"
|
|
bitfld.long 0x00 4. "ITAMP5NOER,ITAMP5NOER" "0,1"
|
|
bitfld.long 0x00 2. "ITAMP3NOER,ITAMP3NOER" "0,1"
|
|
bitfld.long 0x00 1. "ITAMP2NOER,ITAMP2NOER" "0,1"
|
|
bitfld.long 0x00 0. "ITAMP1NOER,ITAMP1NOER" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FLTCR,TAMP filter control register"
|
|
bitfld.long 0x00 7. "TAMPPUDIS,TAMPPUDIS" "0,1"
|
|
bitfld.long 0x00 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ATCR1,TAMP active tamper control register 1"
|
|
bitfld.long 0x00 31. "FLTEN,FLTEN" "0,1"
|
|
bitfld.long 0x00 30. "ATOSHARE,ATOSHARE" "0,1"
|
|
bitfld.long 0x00 24.--25. "ATPER,ATPER" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "ATCKSEL,ATCKSEL" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3"
|
|
bitfld.long 0x00 7. "TAMP8AM,TAMP8AM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TAMP7AM,TAMP7AM" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6AM,TAMP6AM" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5AM,TAMP5AM" "0,1"
|
|
bitfld.long 0x00 3. "TAMP4AM,TAMP4AM" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3AM,TAMP3AM" "0,1"
|
|
bitfld.long 0x00 1. "TAMP2AM,TAMP2AM" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1AM,TAMP1AM" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "ATSEEDR,TAMP active tamper seed register"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,Pseudo-random generator seed value"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ATOR,TAMP active tamper output register"
|
|
bitfld.long 0x00 15. "INITS,Active tamper initialization status" "0,1"
|
|
bitfld.long 0x00 14. "SEEDF,Seed running flag" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRNG,Pseudo-random generator value"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ATCR2,TAMP active tamper control register 2"
|
|
bitfld.long 0x00 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17.--19. "ATOSEL4,ATOSEL4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SMCR,TAMP secure mode register"
|
|
bitfld.long 0x00 31. "TAMPDPROT,Tamper protection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BKPWDPROT,Backup registers write protection offset"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BKPRWDPROT,Backup registers read/write protection offset"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PRIVCR,TAMP privilege mode control register"
|
|
bitfld.long 0x00 31. "TAMPPRIV,Tamper privilege protection" "0,1"
|
|
bitfld.long 0x00 30. "BKPWPRIV,Backup registers zone 2 privilege protection" "0,1"
|
|
bitfld.long 0x00 29. "BKPRWPRIV,Backup registers zone 1 privilege protection" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IER,TAMP interrupt enable register"
|
|
bitfld.long 0x00 23. "ITAMP8IE,ITAMP8IE" "0,1"
|
|
bitfld.long 0x00 20. "ITAMP5IE,ITAMP5IE" "0,1"
|
|
bitfld.long 0x00 18. "ITAMP3IE,ITAMP3IE" "0,1"
|
|
bitfld.long 0x00 17. "ITAMP2IE,ITAMP2IE" "0,1"
|
|
bitfld.long 0x00 16. "ITAMP1IE,ITAMP1IE" "0,1"
|
|
bitfld.long 0x00 7. "TAMP8IE,TAMP8IE" "0,1"
|
|
bitfld.long 0x00 6. "TAMP7IE,TAMP7IE" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6IE,TAMP6IE" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5IE,TAMP5IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TAMP4IE,TAMP4IE" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3IE,TAMP3IE" "0,1"
|
|
bitfld.long 0x00 1. "TAMP2IE,TAMP2IE" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1IE,TAMP1IE" "0,1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SR,TAMP status register"
|
|
bitfld.long 0x00 23. "ITAMP8F,ITAMP8F" "0,1"
|
|
bitfld.long 0x00 20. "ITAMP5F,ITAMP5F" "0,1"
|
|
bitfld.long 0x00 18. "ITAMP3F,ITAMP3F" "0,1"
|
|
bitfld.long 0x00 17. "ITAMP2F,ITAMP2F" "0,1"
|
|
bitfld.long 0x00 16. "ITAMP1F,ITAMP1F" "0,1"
|
|
bitfld.long 0x00 7. "TAMP8F,TAMP8F" "0,1"
|
|
bitfld.long 0x00 6. "TAMP7F,TAMP7F" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6F,TAMP6F" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5F,TAMP5F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TAMP4F,TAMP4F" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3F,TAMP3F" "0,1"
|
|
bitfld.long 0x00 1. "TAMP2F,TAMP2F" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1F,TAMP1F" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "MISR,TAMP masked interrupt status register"
|
|
bitfld.long 0x00 23. "ITAMP8MF,ITAMP8MF" "0,1"
|
|
bitfld.long 0x00 20. "ITAMP5MF,ITAMP5MF" "0,1"
|
|
bitfld.long 0x00 18. "ITAMP3MF,ITAMP3MF" "0,1"
|
|
bitfld.long 0x00 17. "ITAMP2MF,ITAMP2MF" "0,1"
|
|
bitfld.long 0x00 16. "ITAMP1MF,ITAMP1MF" "0,1"
|
|
bitfld.long 0x00 7. "TAMP8MF,TAMP8MF" "0,1"
|
|
bitfld.long 0x00 6. "TAMP7MF,TAMP7MF" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6MF,TAMP6MF" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5MF,TAMP5MF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TAMP4MF,TAMP4MF" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3MF,TAMP3MF" "0,1"
|
|
bitfld.long 0x00 1. "TAMP2MF,TAMP2MF" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1MF,TAMP1MF" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SMISR,TAMP secure masked interrupt status register"
|
|
bitfld.long 0x00 23. "ITAMP8MF,ITAMP8MF" "0,1"
|
|
bitfld.long 0x00 20. "ITAMP5MF,ITAMP5MF" "0,1"
|
|
bitfld.long 0x00 18. "ITAMP3MF,ITAMP3MF" "0,1"
|
|
bitfld.long 0x00 17. "ITAMP2MF,ITAMP2MF" "0,1"
|
|
bitfld.long 0x00 16. "ITAMP1MF,ITAMP1MF" "0,1"
|
|
bitfld.long 0x00 7. "TAMP8MF,TAMP8MF" "0,1"
|
|
bitfld.long 0x00 6. "TAMP7MF,TAMP7MF" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6MF,TAMP6MF" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5MF,TAMP5MF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TAMP4MF,TAMP4MF" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3MF,TAMP3MF" "0,1"
|
|
bitfld.long 0x00 1. "TAMP2MF,TAMP2MF" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1MF,TAMP1MF" "0,1"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "SCR,TAMP status clear register"
|
|
bitfld.long 0x00 23. "CITAMP8F,CITAMP8F" "0,1"
|
|
bitfld.long 0x00 20. "CITAMP5F,CITAMP5F" "0,1"
|
|
bitfld.long 0x00 18. "CITAMP3F,CITAMP3F" "0,1"
|
|
bitfld.long 0x00 17. "CITAMP2F,CITAMP2F" "0,1"
|
|
bitfld.long 0x00 16. "CITAMP1F,CITAMP1F" "0,1"
|
|
bitfld.long 0x00 7. "CTAMP8F,CTAMP8F" "0,1"
|
|
bitfld.long 0x00 6. "CTAMP7F,CTAMP7F" "0,1"
|
|
bitfld.long 0x00 5. "CTAMP6F,CTAMP6F" "0,1"
|
|
bitfld.long 0x00 4. "CTAMP5F,CTAMP5F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CTAMP4F,CTAMP4F" "0,1"
|
|
bitfld.long 0x00 2. "CTAMP3F,CTAMP3F" "0,1"
|
|
bitfld.long 0x00 1. "CTAMP2F,CTAMP2F" "0,1"
|
|
bitfld.long 0x00 0. "CTAMP1F,CTAMP1F" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "COUNTR,TAMP monotonic counter register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,COUNT"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CFGR,TAMP configuration register"
|
|
bitfld.long 0x00 3. "WUTMONEN,WUTMONEN" "0,1"
|
|
bitfld.long 0x00 2. "VMONEN,VMONEN" "0,1"
|
|
bitfld.long 0x00 1. "TMONEN,TMONEN" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "BKP0R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "BKP1R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "BKP2R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "BKP3R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "BKP4R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "BKP5R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "BKP6R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "BKP7R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "BKP8R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "BKP9R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "BKP10R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "BKP11R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "BKP12R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "BKP13R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "BKP14R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "BKP15R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "BKP16R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "BKP17R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "BKP18R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "BKP19R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "BKP20R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "BKP21R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "BKP22R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "BKP23R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "BKP24R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "BKP25R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "BKP26R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "BKP27R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "BKP28R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "BKP29R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "BKP30R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "BKP31R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
tree.end
|
|
tree "TAMP"
|
|
base ad:0x40003400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 23. "ITAMP8E,ITAMP5E" "0,1"
|
|
bitfld.long 0x00 20. "ITAMP5E,ITAMP5E" "0,1"
|
|
bitfld.long 0x00 18. "ITAMP3E,ITAMP3E" "0,1"
|
|
bitfld.long 0x00 17. "ITAMP2E,ITAMP2E" "0,1"
|
|
bitfld.long 0x00 16. "ITAMP1E,ITAMP1E" "0,1"
|
|
bitfld.long 0x00 7. "TAMP8E,TAMP8E" "0,1"
|
|
bitfld.long 0x00 6. "TAMP7E,TAMP7E" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6E,TAMP6E" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5E,TAMP5E" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TAMP4E,TAMP4E" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3E,TAMP3E" "0,1"
|
|
bitfld.long 0x00 1. "TAMP2E,TAMP2E" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1E,TAMP1E" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 31. "TAMP8TRG,TAMP8TRG" "0,1"
|
|
bitfld.long 0x00 30. "TAMP7TRG,TAMP7TRG" "0,1"
|
|
bitfld.long 0x00 29. "TAMP6TRG,TAMP6TRG" "0,1"
|
|
bitfld.long 0x00 28. "TAMP5TRG,TAMP5TRG" "0,1"
|
|
bitfld.long 0x00 27. "TAMP4TRG,TAMP4TRG" "0,1"
|
|
bitfld.long 0x00 26. "TAMP3TRG,TAMP3TRG" "0,1"
|
|
bitfld.long 0x00 25. "TAMP2TRG,TAMP2TRG" "0,1"
|
|
bitfld.long 0x00 24. "TAMP1TRG,TAMP1TRG" "0,1"
|
|
bitfld.long 0x00 23. "BKERASE,BKERASE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TAMP3MSK,TAMP3MSK" "0,1"
|
|
bitfld.long 0x00 17. "TAMP2MSK,TAMP2MSK" "0,1"
|
|
bitfld.long 0x00 16. "TAMP1MSK,TAMP1MSK" "0,1"
|
|
bitfld.long 0x00 7. "TAMP8NOER,TAMP8NOER" "0,1"
|
|
bitfld.long 0x00 6. "TAMP7NOER,TAMP7NOER" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6NOER,TAMP6NOER" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5NOER,TAMP5NOER" "0,1"
|
|
bitfld.long 0x00 3. "TAMP4NOER,TAMP4NOER" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3NOER,TAMP3NOER" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TAMP2NOER,TAMP2NOER" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1NOER,TAMP1NOER" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,control register 3"
|
|
bitfld.long 0x00 7. "ITAMP8NOER,ITAMP8NOER" "0,1"
|
|
bitfld.long 0x00 4. "ITAMP5NOER,ITAMP5NOER" "0,1"
|
|
bitfld.long 0x00 2. "ITAMP3NOER,ITAMP3NOER" "0,1"
|
|
bitfld.long 0x00 1. "ITAMP2NOER,ITAMP2NOER" "0,1"
|
|
bitfld.long 0x00 0. "ITAMP1NOER,ITAMP1NOER" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FLTCR,TAMP filter control register"
|
|
bitfld.long 0x00 7. "TAMPPUDIS,TAMPPUDIS" "0,1"
|
|
bitfld.long 0x00 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3"
|
|
bitfld.long 0x00 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ATCR1,TAMP active tamper control register 1"
|
|
bitfld.long 0x00 31. "FLTEN,FLTEN" "0,1"
|
|
bitfld.long 0x00 30. "ATOSHARE,ATOSHARE" "0,1"
|
|
bitfld.long 0x00 24.--25. "ATPER,ATPER" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "ATCKSEL,ATCKSEL" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "ATOSEL4,ATOSEL4" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3"
|
|
bitfld.long 0x00 7. "TAMP8AM,TAMP8AM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TAMP7AM,TAMP7AM" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6AM,TAMP6AM" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5AM,TAMP5AM" "0,1"
|
|
bitfld.long 0x00 3. "TAMP4AM,TAMP4AM" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3AM,TAMP3AM" "0,1"
|
|
bitfld.long 0x00 1. "TAMP2AM,TAMP2AM" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1AM,TAMP1AM" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "ATSEEDR,TAMP active tamper seed register"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,Pseudo-random generator seed value"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ATOR,TAMP active tamper output register"
|
|
bitfld.long 0x00 15. "INITS,Active tamper initialization status" "0,1"
|
|
bitfld.long 0x00 14. "SEEDF,Seed running flag" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRNG,Pseudo-random generator value"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ATCR2,TAMP active tamper control register 2"
|
|
bitfld.long 0x00 29.--31. "ATOSEL8,ATOSEL8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26.--28. "ATOSEL7,ATOSEL7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23.--25. "ATOSEL6,ATOSEL6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. "ATOSEL5,ATOSEL5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17.--19. "ATOSEL4,ATOSEL4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 14.--16. "ATOSEL3,ATOSEL3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11.--13. "ATOSEL2,ATOSEL2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "ATOSEL1,ATOSEL1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SMCR,TAMP secure mode register"
|
|
bitfld.long 0x00 31. "TAMPDPROT,Tamper protection" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BKPWDPROT,Backup registers write protection offset"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BKPRWDPROT,Backup registers read/write protection offset"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PRIVCR,TAMP privilege mode control register"
|
|
bitfld.long 0x00 31. "TAMPPRIV,Tamper privilege protection" "0,1"
|
|
bitfld.long 0x00 30. "BKPWPRIV,Backup registers zone 2 privilege protection" "0,1"
|
|
bitfld.long 0x00 29. "BKPRWPRIV,Backup registers zone 1 privilege protection" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IER,TAMP interrupt enable register"
|
|
bitfld.long 0x00 23. "ITAMP8IE,ITAMP8IE" "0,1"
|
|
bitfld.long 0x00 20. "ITAMP5IE,ITAMP5IE" "0,1"
|
|
bitfld.long 0x00 18. "ITAMP3IE,ITAMP3IE" "0,1"
|
|
bitfld.long 0x00 17. "ITAMP2IE,ITAMP2IE" "0,1"
|
|
bitfld.long 0x00 16. "ITAMP1IE,ITAMP1IE" "0,1"
|
|
bitfld.long 0x00 7. "TAMP8IE,TAMP8IE" "0,1"
|
|
bitfld.long 0x00 6. "TAMP7IE,TAMP7IE" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6IE,TAMP6IE" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5IE,TAMP5IE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TAMP4IE,TAMP4IE" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3IE,TAMP3IE" "0,1"
|
|
bitfld.long 0x00 1. "TAMP2IE,TAMP2IE" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1IE,TAMP1IE" "0,1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SR,TAMP status register"
|
|
bitfld.long 0x00 23. "ITAMP8F,ITAMP8F" "0,1"
|
|
bitfld.long 0x00 20. "ITAMP5F,ITAMP5F" "0,1"
|
|
bitfld.long 0x00 18. "ITAMP3F,ITAMP3F" "0,1"
|
|
bitfld.long 0x00 17. "ITAMP2F,ITAMP2F" "0,1"
|
|
bitfld.long 0x00 16. "ITAMP1F,ITAMP1F" "0,1"
|
|
bitfld.long 0x00 7. "TAMP8F,TAMP8F" "0,1"
|
|
bitfld.long 0x00 6. "TAMP7F,TAMP7F" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6F,TAMP6F" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5F,TAMP5F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TAMP4F,TAMP4F" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3F,TAMP3F" "0,1"
|
|
bitfld.long 0x00 1. "TAMP2F,TAMP2F" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1F,TAMP1F" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "MISR,TAMP masked interrupt status register"
|
|
bitfld.long 0x00 23. "ITAMP8MF,ITAMP8MF" "0,1"
|
|
bitfld.long 0x00 20. "ITAMP5MF,ITAMP5MF" "0,1"
|
|
bitfld.long 0x00 18. "ITAMP3MF,ITAMP3MF" "0,1"
|
|
bitfld.long 0x00 17. "ITAMP2MF,ITAMP2MF" "0,1"
|
|
bitfld.long 0x00 16. "ITAMP1MF,ITAMP1MF" "0,1"
|
|
bitfld.long 0x00 7. "TAMP8MF,TAMP8MF" "0,1"
|
|
bitfld.long 0x00 6. "TAMP7MF,TAMP7MF" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6MF,TAMP6MF" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5MF,TAMP5MF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TAMP4MF,TAMP4MF" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3MF,TAMP3MF" "0,1"
|
|
bitfld.long 0x00 1. "TAMP2MF,TAMP2MF" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1MF,TAMP1MF" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SMISR,TAMP secure masked interrupt status register"
|
|
bitfld.long 0x00 23. "ITAMP8MF,ITAMP8MF" "0,1"
|
|
bitfld.long 0x00 20. "ITAMP5MF,ITAMP5MF" "0,1"
|
|
bitfld.long 0x00 18. "ITAMP3MF,ITAMP3MF" "0,1"
|
|
bitfld.long 0x00 17. "ITAMP2MF,ITAMP2MF" "0,1"
|
|
bitfld.long 0x00 16. "ITAMP1MF,ITAMP1MF" "0,1"
|
|
bitfld.long 0x00 7. "TAMP8MF,TAMP8MF" "0,1"
|
|
bitfld.long 0x00 6. "TAMP7MF,TAMP7MF" "0,1"
|
|
bitfld.long 0x00 5. "TAMP6MF,TAMP6MF" "0,1"
|
|
bitfld.long 0x00 4. "TAMP5MF,TAMP5MF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TAMP4MF,TAMP4MF" "0,1"
|
|
bitfld.long 0x00 2. "TAMP3MF,TAMP3MF" "0,1"
|
|
bitfld.long 0x00 1. "TAMP2MF,TAMP2MF" "0,1"
|
|
bitfld.long 0x00 0. "TAMP1MF,TAMP1MF" "0,1"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "SCR,TAMP status clear register"
|
|
bitfld.long 0x00 23. "CITAMP8F,CITAMP8F" "0,1"
|
|
bitfld.long 0x00 20. "CITAMP5F,CITAMP5F" "0,1"
|
|
bitfld.long 0x00 18. "CITAMP3F,CITAMP3F" "0,1"
|
|
bitfld.long 0x00 17. "CITAMP2F,CITAMP2F" "0,1"
|
|
bitfld.long 0x00 16. "CITAMP1F,CITAMP1F" "0,1"
|
|
bitfld.long 0x00 7. "CTAMP8F,CTAMP8F" "0,1"
|
|
bitfld.long 0x00 6. "CTAMP7F,CTAMP7F" "0,1"
|
|
bitfld.long 0x00 5. "CTAMP6F,CTAMP6F" "0,1"
|
|
bitfld.long 0x00 4. "CTAMP5F,CTAMP5F" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CTAMP4F,CTAMP4F" "0,1"
|
|
bitfld.long 0x00 2. "CTAMP3F,CTAMP3F" "0,1"
|
|
bitfld.long 0x00 1. "CTAMP2F,CTAMP2F" "0,1"
|
|
bitfld.long 0x00 0. "CTAMP1F,CTAMP1F" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "COUNTR,TAMP monotonic counter register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,COUNT"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CFGR,TAMP configuration register"
|
|
bitfld.long 0x00 3. "WUTMONEN,WUTMONEN" "0,1"
|
|
bitfld.long 0x00 2. "VMONEN,VMONEN" "0,1"
|
|
bitfld.long 0x00 1. "TMONEN,TMONEN" "0,1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "BKP0R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "BKP1R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "BKP2R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "BKP3R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "BKP4R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "BKP5R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "BKP6R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "BKP7R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "BKP8R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "BKP9R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "BKP10R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "BKP11R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "BKP12R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "BKP13R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "BKP14R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "BKP15R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "BKP16R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "BKP17R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "BKP18R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "BKP19R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "BKP20R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "BKP21R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "BKP22R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "BKP23R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "BKP24R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "BKP25R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "BKP26R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "BKP27R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "BKP28R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "BKP29R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "BKP30R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "BKP31R,TAMP backup register"
|
|
hexmask.long 0x00 0.--31. 1. "BKP,BKP"
|
|
tree.end
|
|
tree.end
|
|
tree "TIM (Advanced-timers)"
|
|
tree "SEC_TIM1"
|
|
base ad:0x50012C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 20.--23. "MMS2,Master mode selection 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. "OIS6,Output Idle state 6" "0,1"
|
|
bitfld.long 0x00 15. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x00 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x00 13. "OIS3N,Output Idle state 3" "0,1"
|
|
bitfld.long 0x00 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x00 11. "OIS2N,Output Idle state 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x00 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x00 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,slave mode control register"
|
|
bitfld.long 0x00 16. "SMS_bit3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x00 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "ETF,External trigger filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x00 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x00 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x00 13. "SBIF,System Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x00 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x00 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x00 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x00 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x00 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x00 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x00 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x00 24. "OC2M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC1M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC2F,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC4M_bit3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC3M_bit3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC4F,Input capture 4 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC3F,Input capture 3 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x00 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x00 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x00 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x00 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x00 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x00 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x00 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x00 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
rbitfld.long 0x00 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR,Auto-reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR3,Capture/Compare value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR4,Capture/Compare value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,break and dead-time register"
|
|
bitfld.long 0x00 29. "BK2BID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x00 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x00 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x00 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x00 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x00 24. "BK2E,Break 2 enable" "0,1"
|
|
bitfld.long 0x00 20.--23. "BK2F,Break 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "BKF,Break filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x00 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x00 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,DMA address for full transfer"
|
|
bitfld.long 0x00 4. "TI1_RMP,Input Capture 1 remap" "0,1"
|
|
bitfld.long 0x00 0.--1. "ETR_ADC1_RMP,External trigger remap on ADC1 analog watchdog" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x00 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x00 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CCR5,capture/compare register 4"
|
|
bitfld.long 0x00 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x00 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x00 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR5,Capture/Compare value"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR6,Capture/Compare value"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,DMA address for full transfer"
|
|
bitfld.long 0x00 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x00 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BKDFBK0E,BRK DFSDM_BREAK0 enable" "0,1"
|
|
bitfld.long 0x00 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "OR3,DMA address for full transfer"
|
|
bitfld.long 0x00 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x00 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BK2DFBK0E,BRK2 DFSDM_BREAK0 enable" "0,1"
|
|
bitfld.long 0x00 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x00 0. "BK2INE,BRK2 BKIN input enable" "0,1"
|
|
tree.end
|
|
tree "SEC_TIM2"
|
|
base ad:0x50000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,slave mode control register"
|
|
bitfld.long 0x00 16. "SMS_bit3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x00 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "ETF,External trigger filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x00 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x00 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x00 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x00 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x00 24. "OC2M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC1M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC1CE,Output compare 1 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC1PE,Output compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC2F,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC4M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC3M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC4F,Input capture 4 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC3F,Input capture 3 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 15. "CC4NP,Capture/Compare 4 output Polarity" "0,1"
|
|
bitfld.long 0x00 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x00 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
bitfld.long 0x00 31. "CNT_bit31,Most significant bit of counter value (on TIM2 and TIM5)" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "CNT_H,Most significant part counter value (on TIM2 and TIM5)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT_L,Least significant part of counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 16.--31. 1. "ARR_H,High Auto-reload value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1_L,Low Capture/Compare 1 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR2_L,Low Capture/Compare 2 value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMAB,Low Capture/Compare 2 value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,TIM2 option register"
|
|
bitfld.long 0x00 2.--3. "TI4_RMP,Input Capture 4 remap" "0,1,2,3"
|
|
bitfld.long 0x00 1. "ETR1_RMP,External trigger remap" "0,1"
|
|
bitfld.long 0x00 0. "ITR1_RMP,Internal trigger 1 remap" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,TIM3 option register 2"
|
|
bitfld.long 0x00 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "SEC_TIM3"
|
|
base ad:0x50000400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,slave mode control register"
|
|
bitfld.long 0x00 16. "SMS_bit3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x00 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "ETF,External trigger filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x00 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x00 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x00 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x00 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x00 24. "OC2M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC1M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC1CE,Output compare 1 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC1PE,Output compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC2F,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC4M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC3M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC4F,Input capture 4 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC3F,Input capture 3 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 15. "CC4NP,Capture/Compare 4 output Polarity" "0,1"
|
|
bitfld.long 0x00 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x00 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
bitfld.long 0x00 31. "CNT_bit31,Most significant bit of counter value (on TIM2 and TIM5)" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "CNT_H,Most significant part counter value (on TIM2 and TIM5)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT_L,Least significant part of counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 16.--31. 1. "ARR_H,High Auto-reload value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1_L,Low Capture/Compare 1 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR2_L,Low Capture/Compare 2 value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMAB,Low Capture/Compare 2 value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,TIM2 option register"
|
|
bitfld.long 0x00 0. "ITR1_RMP,Internal trigger 1 remap" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,TIM3 option register 2"
|
|
bitfld.long 0x00 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
repeat 2. (list 4. 5.) (list ad:0x50000800 ad:0x50000C00)
|
|
tree "SEC_TIM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,slave mode control register"
|
|
bitfld.long 0x00 16. "SMS_bit3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x00 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "ETF,External trigger filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x00 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x00 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x00 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x00 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x00 24. "OC2M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC1M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC1CE,Output compare 1 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC1PE,Output compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC2F,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC4M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC3M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC4F,Input capture 4 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC3F,Input capture 3 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 15. "CC4NP,Capture/Compare 4 output Polarity" "0,1"
|
|
bitfld.long 0x00 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x00 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
bitfld.long 0x00 31. "CNT_bit31,Most significant bit of counter value (on TIM2 and TIM5)" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "CNT_H,Most significant part counter value (on TIM2 and TIM5)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT_L,Least significant part of counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 16.--31. 1. "ARR_H,High Auto-reload value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1_L,Low Capture/Compare 1 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR2_L,Low Capture/Compare 2 value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMAB,Low Capture/Compare 2 value"
|
|
tree.end
|
|
repeat.end
|
|
repeat 2. (list 6. 7.) (list ad:0x50001000 ad:0x50001400)
|
|
tree "SEC_TIM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMA,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
bitfld.long 0x00 31. "UIFCPY,UIFCPY or Res" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT_bit0,CNT"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR_bit0,ARR_bit0"
|
|
tree.end
|
|
repeat.end
|
|
tree "SEC_TIM8"
|
|
base ad:0x50013400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 20.--23. "MMS2,Master mode selection 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. "OIS6,Output Idle state 6" "0,1"
|
|
bitfld.long 0x00 15. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x00 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x00 13. "OIS3N,Output Idle state 3" "0,1"
|
|
bitfld.long 0x00 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x00 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x00 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x00 9. "OIS1N,Output Idle state 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x00 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x00 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,slave mode control register"
|
|
bitfld.long 0x00 16. "SMS_bit3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x00 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "ETF,External trigger filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x00 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TIE,Trigger interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x00 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x00 13. "SBIF,System Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x00 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x00 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x00 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x00 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x00 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x00 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x00 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x00 24. "OC2M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC1M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC2F,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC4M_bit3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC3M_bit3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC4F,Input capture 4 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC3F,Input capture 3 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x00 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x00 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x00 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x00 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x00 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x00 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x00 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
rbitfld.long 0x00 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR,Auto-reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR3,Capture/Compare value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR4,Capture/Compare value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,break and dead-time register"
|
|
bitfld.long 0x00 29. "BK2BID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x00 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x00 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x00 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x00 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x00 24. "BK2E,Break 2 enable" "0,1"
|
|
bitfld.long 0x00 20.--23. "BK2F,Break 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "BKF,Break filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "MOE,Main output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x00 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x00 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,DMA address for full transfer"
|
|
bitfld.long 0x00 4. "TI1_RMP,Input Capture 1 remap" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x00 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x00 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CCR5,capture/compare register 4"
|
|
bitfld.long 0x00 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x00 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x00 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR5,Capture/Compare value"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR6,Capture/Compare value"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,DMA address for full transfer"
|
|
bitfld.long 0x00 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x00 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BKDF1BK2E,BRK dfsdm1_break[2] enable" "0,1"
|
|
bitfld.long 0x00 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x00 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "OR3,DMA address for full transfer"
|
|
bitfld.long 0x00 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x00 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BK2DFBK3E,BRK2 DFSDM_BREAK0 enable" "0,1"
|
|
bitfld.long 0x00 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x00 0. "BK2INE,BRK2 BKIN input enable" "0,1"
|
|
tree.end
|
|
tree "SEC_TIM15"
|
|
base ad:0x50014000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 10. "OIS2,Output idle state 2 (OC2 output)" "0,1"
|
|
bitfld.long 0x00 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x00 4.--5. "MMS,Master mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x00 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x00 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x00 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x00 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x00 24. "OC2M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC1M_bit3,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC2F,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
bitfld.long 0x00 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
bitfld.long 0x00 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
rbitfld.long 0x00 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR,Auto-reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,break and dead-time register"
|
|
bitfld.long 0x00 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x00 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x00 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x00 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,TIM15 slave mode control register"
|
|
bitfld.long 0x00 16. "SMS_bit3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x00 7. "MSM,Master/slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,TIM15 option register 1"
|
|
bitfld.long 0x00 1.--2. "ENCODER_MODE,Encoder mode" "0,1,2,3"
|
|
bitfld.long 0x00 0. "TI1_RMP,Input capture 1 remap" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,TIM15 option register 2"
|
|
bitfld.long 0x00 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x00 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1"
|
|
bitfld.long 0x00 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x00 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CCR2,TIM15 capture/compare register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
tree.end
|
|
tree "SEC_TIM16"
|
|
base ad:0x50014400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x00 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x00 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x00 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x00 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
rbitfld.long 0x00 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR,Auto-reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,break and dead-time register"
|
|
bitfld.long 0x00 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x00 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x00 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x00 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x00 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,TIM16 option register 1"
|
|
bitfld.long 0x00 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,TIM17 option register 1"
|
|
bitfld.long 0x00 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x00 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BKDF1BK1E,BRK dfsdm1_break[1] enable" "0,1"
|
|
bitfld.long 0x00 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x00 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
tree.end
|
|
tree "SEC_TIM17"
|
|
base ad:0x50014800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x00 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x00 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x00 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x00 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
rbitfld.long 0x00 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR,Auto-reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,break and dead-time register"
|
|
bitfld.long 0x00 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x00 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x00 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x00 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x00 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,TIM16 option register 1"
|
|
bitfld.long 0x00 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,TIM17 option register 1"
|
|
bitfld.long 0x00 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x00 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BKDF1BK2E,BRK dfsdm1_break[2] enable" "0,1"
|
|
bitfld.long 0x00 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x00 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
tree.end
|
|
tree "TIM1"
|
|
base ad:0x40012C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 20.--23. "MMS2,Master mode selection 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. "OIS6,Output Idle state 6" "0,1"
|
|
bitfld.long 0x00 15. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x00 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x00 13. "OIS3N,Output Idle state 3" "0,1"
|
|
bitfld.long 0x00 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x00 11. "OIS2N,Output Idle state 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x00 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x00 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,slave mode control register"
|
|
bitfld.long 0x00 16. "SMS_bit3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x00 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "ETF,External trigger filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x00 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x00 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x00 13. "SBIF,System Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x00 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x00 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x00 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x00 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x00 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x00 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x00 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x00 24. "OC2M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC1M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC2F,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC4M_bit3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC3M_bit3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC4F,Input capture 4 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC3F,Input capture 3 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x00 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x00 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x00 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x00 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x00 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x00 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x00 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x00 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
rbitfld.long 0x00 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR,Auto-reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR3,Capture/Compare value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR4,Capture/Compare value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,break and dead-time register"
|
|
bitfld.long 0x00 29. "BK2BID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x00 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x00 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x00 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x00 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x00 24. "BK2E,Break 2 enable" "0,1"
|
|
bitfld.long 0x00 20.--23. "BK2F,Break 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "BKF,Break filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x00 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x00 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,DMA address for full transfer"
|
|
bitfld.long 0x00 4. "TI1_RMP,Input Capture 1 remap" "0,1"
|
|
bitfld.long 0x00 0.--1. "ETR_ADC1_RMP,External trigger remap on ADC1 analog watchdog" "0,1,2,3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x00 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x00 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CCR5,capture/compare register 4"
|
|
bitfld.long 0x00 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x00 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x00 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR5,Capture/Compare value"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR6,Capture/Compare value"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,DMA address for full transfer"
|
|
bitfld.long 0x00 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x00 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BKDFBK0E,BRK DFSDM_BREAK0 enable" "0,1"
|
|
bitfld.long 0x00 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "OR3,DMA address for full transfer"
|
|
bitfld.long 0x00 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x00 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BK2DFBK0E,BRK2 DFSDM_BREAK0 enable" "0,1"
|
|
bitfld.long 0x00 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x00 0. "BK2INE,BRK2 BKIN input enable" "0,1"
|
|
tree.end
|
|
tree "TIM2"
|
|
base ad:0x40000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,slave mode control register"
|
|
bitfld.long 0x00 16. "SMS_bit3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x00 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "ETF,External trigger filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x00 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x00 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x00 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x00 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x00 24. "OC2M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC1M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC1CE,Output compare 1 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC1PE,Output compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC2F,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC4M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC3M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC4F,Input capture 4 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC3F,Input capture 3 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 15. "CC4NP,Capture/Compare 4 output Polarity" "0,1"
|
|
bitfld.long 0x00 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x00 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
bitfld.long 0x00 31. "CNT_bit31,Most significant bit of counter value (on TIM2 and TIM5)" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "CNT_H,Most significant part counter value (on TIM2 and TIM5)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT_L,Least significant part of counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 16.--31. 1. "ARR_H,High Auto-reload value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1_L,Low Capture/Compare 1 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR2_L,Low Capture/Compare 2 value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMAB,Low Capture/Compare 2 value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,TIM2 option register"
|
|
bitfld.long 0x00 2.--3. "TI4_RMP,Input Capture 4 remap" "0,1,2,3"
|
|
bitfld.long 0x00 1. "ETR1_RMP,External trigger remap" "0,1"
|
|
bitfld.long 0x00 0. "ITR1_RMP,Internal trigger 1 remap" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,TIM3 option register 2"
|
|
bitfld.long 0x00 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "TIM3"
|
|
base ad:0x40000400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,slave mode control register"
|
|
bitfld.long 0x00 16. "SMS_bit3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x00 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "ETF,External trigger filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x00 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x00 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x00 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x00 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x00 24. "OC2M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC1M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC1CE,Output compare 1 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC1PE,Output compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC2F,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC4M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC3M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC4F,Input capture 4 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC3F,Input capture 3 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 15. "CC4NP,Capture/Compare 4 output Polarity" "0,1"
|
|
bitfld.long 0x00 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x00 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
bitfld.long 0x00 31. "CNT_bit31,Most significant bit of counter value (on TIM2 and TIM5)" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "CNT_H,Most significant part counter value (on TIM2 and TIM5)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT_L,Least significant part of counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 16.--31. 1. "ARR_H,High Auto-reload value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1_L,Low Capture/Compare 1 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR2_L,Low Capture/Compare 2 value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMAB,Low Capture/Compare 2 value"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,TIM2 option register"
|
|
bitfld.long 0x00 0. "ITR1_RMP,Internal trigger 1 remap" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,TIM3 option register 2"
|
|
bitfld.long 0x00 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
repeat 2. (list 4. 5.) (list ad:0x40000800 ad:0x40000C00)
|
|
tree "TIM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,slave mode control register"
|
|
bitfld.long 0x00 16. "SMS_bit3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x00 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "ETF,External trigger filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x00 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x00 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x00 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x00 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x00 24. "OC2M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC1M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC1CE,Output compare 1 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC1PE,Output compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC2F,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC4M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC3M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC4F,Input capture 4 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC3F,Input capture 3 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 15. "CC4NP,Capture/Compare 4 output Polarity" "0,1"
|
|
bitfld.long 0x00 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x00 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
bitfld.long 0x00 31. "CNT_bit31,Most significant bit of counter value (on TIM2 and TIM5)" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "CNT_H,Most significant part counter value (on TIM2 and TIM5)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT_L,Least significant part of counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 16.--31. 1. "ARR_H,High Auto-reload value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1_L,Low Capture/Compare 1 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR2_L,Low Capture/Compare 2 value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2 only)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMAB,Low Capture/Compare 2 value"
|
|
tree.end
|
|
repeat.end
|
|
repeat 2. (list 6. 7.) (list ad:0x40001000 ad:0x40001400)
|
|
tree "TIM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMA,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
bitfld.long 0x00 31. "UIFCPY,UIFCPY or Res" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT_bit0,CNT"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR_bit0,ARR_bit0"
|
|
tree.end
|
|
repeat.end
|
|
tree "TIM8"
|
|
base ad:0x40013400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 5.--6. "CMS,Center-aligned mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 20.--23. "MMS2,Master mode selection 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. "OIS6,Output Idle state 6" "0,1"
|
|
bitfld.long 0x00 15. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x00 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x00 13. "OIS3N,Output Idle state 3" "0,1"
|
|
bitfld.long 0x00 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x00 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x00 10. "OIS2,Output Idle state 2" "0,1"
|
|
bitfld.long 0x00 9. "OIS1N,Output Idle state 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x00 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x00 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x00 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,slave mode control register"
|
|
bitfld.long 0x00 16. "SMS_bit3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x00 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "ETF,External trigger filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x00 12. "CC4DE,Capture/Compare 4 DMA request enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3DE,Capture/Compare 3 DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TIE,Trigger interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "CC4IE,Capture/Compare 4 interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "CC3IE,Capture/Compare 3 interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x00 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x00 13. "SBIF,System Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x00 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x00 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
bitfld.long 0x00 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x00 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x00 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x00 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
bitfld.long 0x00 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x00 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register 1 (output mode)"
|
|
bitfld.long 0x00 24. "OC2M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC1M_bit3,Output Compare 1 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC1CE,Output Compare 1 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC2F,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC4M_bit3,Output Compare 4 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC3M_bit3,Output Compare 3 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/Compare 3 selection" "0,1,2,3"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2_Input,capture/compare mode register 2 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC4F,Input capture 4 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC4S,Capture/Compare 4 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC3F,Input capture 3 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC3S,Capture/compare 3 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x00 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
bitfld.long 0x00 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x00 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
bitfld.long 0x00 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x00 13. "CC4P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x00 11. "CC3NP,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CC3P,Capture/Compare 3 output Polarity" "0,1"
|
|
bitfld.long 0x00 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x00 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x00 5. "CC2P,Capture/Compare 2 output Polarity" "0,1"
|
|
bitfld.long 0x00 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
rbitfld.long 0x00 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR,Auto-reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR3,Capture/Compare value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR4,Capture/Compare value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,break and dead-time register"
|
|
bitfld.long 0x00 29. "BK2BID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x00 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x00 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x00 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x00 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x00 24. "BK2E,Break 2 enable" "0,1"
|
|
bitfld.long 0x00 20.--23. "BK2F,Break 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "BKF,Break filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "MOE,Main output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x00 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long 0x00 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,DMA address for full transfer"
|
|
bitfld.long 0x00 4. "TI1_RMP,Input Capture 1 remap" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CCMR3_Output,capture/compare mode register 2 (output mode)"
|
|
bitfld.long 0x00 24. "OC6M_bit3,Output Compare 6 mode bit 3" "0,1"
|
|
bitfld.long 0x00 16.--18. "OC5M_bit3,Output Compare 5 mode bit 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x00 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
bitfld.long 0x00 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CCR5,capture/compare register 4"
|
|
bitfld.long 0x00 31. "GC5C3,Group Channel 5 and Channel 3" "0,1"
|
|
bitfld.long 0x00 30. "GC5C2,Group Channel 5 and Channel 2" "0,1"
|
|
bitfld.long 0x00 29. "GC5C1,Group Channel 5 and Channel 1" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR5,Capture/Compare value"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR6,Capture/Compare value"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,DMA address for full transfer"
|
|
bitfld.long 0x00 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x00 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BKDF1BK2E,BRK dfsdm1_break[2] enable" "0,1"
|
|
bitfld.long 0x00 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x00 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "OR3,DMA address for full transfer"
|
|
bitfld.long 0x00 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x00 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BK2DFBK3E,BRK2 DFSDM_BREAK0 enable" "0,1"
|
|
bitfld.long 0x00 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x00 0. "BK2INE,BRK2 BKIN input enable" "0,1"
|
|
tree.end
|
|
tree "TIM15"
|
|
base ad:0x40014000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 10. "OIS2,Output idle state 2 (OC2 output)" "0,1"
|
|
bitfld.long 0x00 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x00 4.--5. "MMS,Master mode selection" "0,1,2,3"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x00 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x00 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0x00 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x00 10. "CC2DE,Capture/Compare 2 DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CC2IE,Capture/Compare 2 interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x00 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x00 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x00 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x00 24. "OC2M_bit3,Output Compare 2 mode - bit 3" "0,1"
|
|
bitfld.long 0x00 16. "OC1M_bit3,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x00 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 12.--15. "IC2F,Input capture 2 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "CC2S,Capture/Compare 2 selection" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
bitfld.long 0x00 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
bitfld.long 0x00 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
rbitfld.long 0x00 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR,Auto-reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,break and dead-time register"
|
|
bitfld.long 0x00 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x00 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x00 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x00 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,TIM15 slave mode control register"
|
|
bitfld.long 0x00 16. "SMS_bit3,Slave mode selection - bit 3" "0,1"
|
|
bitfld.long 0x00 7. "MSM,Master/slave mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,TIM15 option register 1"
|
|
bitfld.long 0x00 1.--2. "ENCODER_MODE,Encoder mode" "0,1,2,3"
|
|
bitfld.long 0x00 0. "TI1_RMP,Input capture 1 remap" "0,1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,TIM15 option register 2"
|
|
bitfld.long 0x00 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x00 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1"
|
|
bitfld.long 0x00 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x00 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CCR2,TIM15 capture/compare register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
tree.end
|
|
tree "TIM16"
|
|
base ad:0x40014400
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x00 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x00 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x00 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x00 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
rbitfld.long 0x00 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR,Auto-reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,break and dead-time register"
|
|
bitfld.long 0x00 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x00 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x00 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x00 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x00 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,TIM16 option register 1"
|
|
bitfld.long 0x00 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,TIM17 option register 1"
|
|
bitfld.long 0x00 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x00 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BKDF1BK1E,BRK dfsdm1_break[1] enable" "0,1"
|
|
bitfld.long 0x00 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x00 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
tree.end
|
|
tree "TIM17"
|
|
base ad:0x40014800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,control register 1"
|
|
bitfld.long 0x00 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x00 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x00 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x00 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x00 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x00 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x00 0. "CEN,Counter enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,control register 2"
|
|
bitfld.long 0x00 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x00 3. "CCDS,Capture/compare DMA selection" "0,1"
|
|
bitfld.long 0x00 2. "CCUS,Capture/compare control update selection" "0,1"
|
|
bitfld.long 0x00 0. "CCPC,Capture/compare preloaded control" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x00 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x00 9. "CC1DE,Capture/Compare 1 DMA request enable" "0,1"
|
|
bitfld.long 0x00 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x00 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1IE,Capture/Compare 1 interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "UIE,Update interrupt enable" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,status register"
|
|
bitfld.long 0x00 9. "CC1OF,Capture/Compare 1 overcapture flag" "0,1"
|
|
bitfld.long 0x00 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x00 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x00 1. "CC1IF,Capture/compare 1 interrupt flag" "0,1"
|
|
bitfld.long 0x00 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "EGR,event generation register"
|
|
bitfld.long 0x00 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x00 5. "COMG,Capture/Compare control update generation" "0,1"
|
|
bitfld.long 0x00 1. "CC1G,Capture/compare 1 generation" "0,1"
|
|
bitfld.long 0x00 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Output,capture/compare mode register (output mode)"
|
|
bitfld.long 0x00 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x00 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "OC1PE,Output Compare 1 preload enable" "0,1"
|
|
bitfld.long 0x00 2. "OC1FE,Output Compare 1 fast enable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1_Input,capture/compare mode register 1 (input mode)"
|
|
bitfld.long 0x00 4.--7. "IC1F,Input capture 1 filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "CC1S,Capture/Compare 1 selection" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,capture/compare enable register"
|
|
bitfld.long 0x00 3. "CC1NP,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 2. "CC1NE,Capture/Compare 1 complementary output enable" "0,1"
|
|
bitfld.long 0x00 1. "CC1P,Capture/Compare 1 output Polarity" "0,1"
|
|
bitfld.long 0x00 0. "CC1E,Capture/Compare 1 output enable" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,counter"
|
|
rbitfld.long 0x00 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,counter value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PSC,prescaler"
|
|
hexmask.long.word 0x00 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARR,Auto-reload value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REP,Repetition counter value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,break and dead-time register"
|
|
bitfld.long 0x00 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x00 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x00 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x00 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x00 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x00 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x00 11. "OSSR,Off-state selection for Run mode" "0,1"
|
|
bitfld.long 0x00 10. "OSSI,Off-state selection for Idle mode" "0,1"
|
|
bitfld.long 0x00 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DCR,DMA control register"
|
|
bitfld.long 0x00 8.--12. "DBL,DMA burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "DBA,DMA base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OR1,TIM16 option register 1"
|
|
bitfld.long 0x00 0.--1. "TI1_RMP,Input capture 1 remap" "0,1,2,3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OR2,TIM17 option register 1"
|
|
bitfld.long 0x00 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x00 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x00 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x00 8. "BKDF1BK2E,BRK dfsdm1_break[2] enable" "0,1"
|
|
bitfld.long 0x00 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x00 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x00 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "TSC (Touch sensing controller)"
|
|
tree "SEC_TSC"
|
|
base ad:0x50024000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,control register"
|
|
bitfld.long 0x00 28.--31. "CTPH,Charge transfer pulse high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "CTPL,Charge transfer pulse low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 17.--23. 1. "SSD,Spread spectrum deviation"
|
|
bitfld.long 0x00 16. "SSE,Spread spectrum enable" "0,1"
|
|
bitfld.long 0x00 15. "SSPSC,Spread spectrum prescaler" "0,1"
|
|
bitfld.long 0x00 12.--14. "PGPSC,pulse generator prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. "MCV,Max count value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "IODEF,I/O Default mode" "0,1"
|
|
bitfld.long 0x00 3. "SYNCPOL,Synchronization pin polarity" "0,1"
|
|
bitfld.long 0x00 2. "AM,Acquisition mode" "0,1"
|
|
bitfld.long 0x00 1. "START,Start a new acquisition" "0,1"
|
|
bitfld.long 0x00 0. "TSCE,Touch sensing controller enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER,interrupt enable register"
|
|
bitfld.long 0x00 1. "MCEIE,Max count error interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EOAIE,End of acquisition interrupt enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICR,interrupt clear register"
|
|
bitfld.long 0x00 1. "MCEIC,Max count error interrupt clear" "0,1"
|
|
bitfld.long 0x00 0. "EOAIC,End of acquisition interrupt clear" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ISR,interrupt status register"
|
|
bitfld.long 0x00 1. "MCEF,Max count error flag" "0,1"
|
|
bitfld.long 0x00 0. "EOAF,End of acquisition flag" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IOHCR,I/O hysteresis control register"
|
|
bitfld.long 0x00 31. "G8_IO4,G8_IO4" "0,1"
|
|
bitfld.long 0x00 30. "G8_IO3,G8_IO3" "0,1"
|
|
bitfld.long 0x00 29. "G8_IO2,G8_IO2" "0,1"
|
|
bitfld.long 0x00 28. "G8_IO1,G8_IO1" "0,1"
|
|
bitfld.long 0x00 27. "G7_IO4,G7_IO4" "0,1"
|
|
bitfld.long 0x00 26. "G7_IO3,G7_IO3" "0,1"
|
|
bitfld.long 0x00 25. "G7_IO2,G7_IO2" "0,1"
|
|
bitfld.long 0x00 24. "G7_IO1,G7_IO1" "0,1"
|
|
bitfld.long 0x00 23. "G6_IO4,G6_IO4" "0,1"
|
|
bitfld.long 0x00 22. "G6_IO3,G6_IO3" "0,1"
|
|
bitfld.long 0x00 21. "G6_IO2,G6_IO2" "0,1"
|
|
bitfld.long 0x00 20. "G6_IO1,G6_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "G5_IO4,G5_IO4" "0,1"
|
|
bitfld.long 0x00 18. "G5_IO3,G5_IO3" "0,1"
|
|
bitfld.long 0x00 17. "G5_IO2,G5_IO2" "0,1"
|
|
bitfld.long 0x00 16. "G5_IO1,G5_IO1" "0,1"
|
|
bitfld.long 0x00 15. "G4_IO4,G4_IO4" "0,1"
|
|
bitfld.long 0x00 14. "G4_IO3,G4_IO3" "0,1"
|
|
bitfld.long 0x00 13. "G4_IO2,G4_IO2" "0,1"
|
|
bitfld.long 0x00 12. "G4_IO1,G4_IO1" "0,1"
|
|
bitfld.long 0x00 11. "G3_IO4,G3_IO4" "0,1"
|
|
bitfld.long 0x00 10. "G3_IO3,G3_IO3" "0,1"
|
|
bitfld.long 0x00 9. "G3_IO2,G3_IO2" "0,1"
|
|
bitfld.long 0x00 8. "G3_IO1,G3_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "G2_IO4,G2_IO4" "0,1"
|
|
bitfld.long 0x00 6. "G2_IO3,G2_IO3" "0,1"
|
|
bitfld.long 0x00 5. "G2_IO2,G2_IO2" "0,1"
|
|
bitfld.long 0x00 4. "G2_IO1,G2_IO1" "0,1"
|
|
bitfld.long 0x00 3. "G1_IO4,G1_IO4" "0,1"
|
|
bitfld.long 0x00 2. "G1_IO3,G1_IO3" "0,1"
|
|
bitfld.long 0x00 1. "G1_IO2,G1_IO2" "0,1"
|
|
bitfld.long 0x00 0. "G1_IO1,G1_IO1" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IOASCR,I/O analog switch control register"
|
|
bitfld.long 0x00 31. "G8_IO4,G8_IO4" "0,1"
|
|
bitfld.long 0x00 30. "G8_IO3,G8_IO3" "0,1"
|
|
bitfld.long 0x00 29. "G8_IO2,G8_IO2" "0,1"
|
|
bitfld.long 0x00 28. "G8_IO1,G8_IO1" "0,1"
|
|
bitfld.long 0x00 27. "G7_IO4,G7_IO4" "0,1"
|
|
bitfld.long 0x00 26. "G7_IO3,G7_IO3" "0,1"
|
|
bitfld.long 0x00 25. "G7_IO2,G7_IO2" "0,1"
|
|
bitfld.long 0x00 24. "G7_IO1,G7_IO1" "0,1"
|
|
bitfld.long 0x00 23. "G6_IO4,G6_IO4" "0,1"
|
|
bitfld.long 0x00 22. "G6_IO3,G6_IO3" "0,1"
|
|
bitfld.long 0x00 21. "G6_IO2,G6_IO2" "0,1"
|
|
bitfld.long 0x00 20. "G6_IO1,G6_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "G5_IO4,G5_IO4" "0,1"
|
|
bitfld.long 0x00 18. "G5_IO3,G5_IO3" "0,1"
|
|
bitfld.long 0x00 17. "G5_IO2,G5_IO2" "0,1"
|
|
bitfld.long 0x00 16. "G5_IO1,G5_IO1" "0,1"
|
|
bitfld.long 0x00 15. "G4_IO4,G4_IO4" "0,1"
|
|
bitfld.long 0x00 14. "G4_IO3,G4_IO3" "0,1"
|
|
bitfld.long 0x00 13. "G4_IO2,G4_IO2" "0,1"
|
|
bitfld.long 0x00 12. "G4_IO1,G4_IO1" "0,1"
|
|
bitfld.long 0x00 11. "G3_IO4,G3_IO4" "0,1"
|
|
bitfld.long 0x00 10. "G3_IO3,G3_IO3" "0,1"
|
|
bitfld.long 0x00 9. "G3_IO2,G3_IO2" "0,1"
|
|
bitfld.long 0x00 8. "G3_IO1,G3_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "G2_IO4,G2_IO4" "0,1"
|
|
bitfld.long 0x00 6. "G2_IO3,G2_IO3" "0,1"
|
|
bitfld.long 0x00 5. "G2_IO2,G2_IO2" "0,1"
|
|
bitfld.long 0x00 4. "G2_IO1,G2_IO1" "0,1"
|
|
bitfld.long 0x00 3. "G1_IO4,G1_IO4" "0,1"
|
|
bitfld.long 0x00 2. "G1_IO3,G1_IO3" "0,1"
|
|
bitfld.long 0x00 1. "G1_IO2,G1_IO2" "0,1"
|
|
bitfld.long 0x00 0. "G1_IO1,G1_IO1" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IOSCR,I/O sampling control register"
|
|
bitfld.long 0x00 31. "G8_IO4,G8_IO4" "0,1"
|
|
bitfld.long 0x00 30. "G8_IO3,G8_IO3" "0,1"
|
|
bitfld.long 0x00 29. "G8_IO2,G8_IO2" "0,1"
|
|
bitfld.long 0x00 28. "G8_IO1,G8_IO1" "0,1"
|
|
bitfld.long 0x00 27. "G7_IO4,G7_IO4" "0,1"
|
|
bitfld.long 0x00 26. "G7_IO3,G7_IO3" "0,1"
|
|
bitfld.long 0x00 25. "G7_IO2,G7_IO2" "0,1"
|
|
bitfld.long 0x00 24. "G7_IO1,G7_IO1" "0,1"
|
|
bitfld.long 0x00 23. "G6_IO4,G6_IO4" "0,1"
|
|
bitfld.long 0x00 22. "G6_IO3,G6_IO3" "0,1"
|
|
bitfld.long 0x00 21. "G6_IO2,G6_IO2" "0,1"
|
|
bitfld.long 0x00 20. "G6_IO1,G6_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "G5_IO4,G5_IO4" "0,1"
|
|
bitfld.long 0x00 18. "G5_IO3,G5_IO3" "0,1"
|
|
bitfld.long 0x00 17. "G5_IO2,G5_IO2" "0,1"
|
|
bitfld.long 0x00 16. "G5_IO1,G5_IO1" "0,1"
|
|
bitfld.long 0x00 15. "G4_IO4,G4_IO4" "0,1"
|
|
bitfld.long 0x00 14. "G4_IO3,G4_IO3" "0,1"
|
|
bitfld.long 0x00 13. "G4_IO2,G4_IO2" "0,1"
|
|
bitfld.long 0x00 12. "G4_IO1,G4_IO1" "0,1"
|
|
bitfld.long 0x00 11. "G3_IO4,G3_IO4" "0,1"
|
|
bitfld.long 0x00 10. "G3_IO3,G3_IO3" "0,1"
|
|
bitfld.long 0x00 9. "G3_IO2,G3_IO2" "0,1"
|
|
bitfld.long 0x00 8. "G3_IO1,G3_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "G2_IO4,G2_IO4" "0,1"
|
|
bitfld.long 0x00 6. "G2_IO3,G2_IO3" "0,1"
|
|
bitfld.long 0x00 5. "G2_IO2,G2_IO2" "0,1"
|
|
bitfld.long 0x00 4. "G2_IO1,G2_IO1" "0,1"
|
|
bitfld.long 0x00 3. "G1_IO4,G1_IO4" "0,1"
|
|
bitfld.long 0x00 2. "G1_IO3,G1_IO3" "0,1"
|
|
bitfld.long 0x00 1. "G1_IO2,G1_IO2" "0,1"
|
|
bitfld.long 0x00 0. "G1_IO1,G1_IO1" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IOCCR,I/O channel control register"
|
|
bitfld.long 0x00 31. "G8_IO4,G8_IO4" "0,1"
|
|
bitfld.long 0x00 30. "G8_IO3,G8_IO3" "0,1"
|
|
bitfld.long 0x00 29. "G8_IO2,G8_IO2" "0,1"
|
|
bitfld.long 0x00 28. "G8_IO1,G8_IO1" "0,1"
|
|
bitfld.long 0x00 27. "G7_IO4,G7_IO4" "0,1"
|
|
bitfld.long 0x00 26. "G7_IO3,G7_IO3" "0,1"
|
|
bitfld.long 0x00 25. "G7_IO2,G7_IO2" "0,1"
|
|
bitfld.long 0x00 24. "G7_IO1,G7_IO1" "0,1"
|
|
bitfld.long 0x00 23. "G6_IO4,G6_IO4" "0,1"
|
|
bitfld.long 0x00 22. "G6_IO3,G6_IO3" "0,1"
|
|
bitfld.long 0x00 21. "G6_IO2,G6_IO2" "0,1"
|
|
bitfld.long 0x00 20. "G6_IO1,G6_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "G5_IO4,G5_IO4" "0,1"
|
|
bitfld.long 0x00 18. "G5_IO3,G5_IO3" "0,1"
|
|
bitfld.long 0x00 17. "G5_IO2,G5_IO2" "0,1"
|
|
bitfld.long 0x00 16. "G5_IO1,G5_IO1" "0,1"
|
|
bitfld.long 0x00 15. "G4_IO4,G4_IO4" "0,1"
|
|
bitfld.long 0x00 14. "G4_IO3,G4_IO3" "0,1"
|
|
bitfld.long 0x00 13. "G4_IO2,G4_IO2" "0,1"
|
|
bitfld.long 0x00 12. "G4_IO1,G4_IO1" "0,1"
|
|
bitfld.long 0x00 11. "G3_IO4,G3_IO4" "0,1"
|
|
bitfld.long 0x00 10. "G3_IO3,G3_IO3" "0,1"
|
|
bitfld.long 0x00 9. "G3_IO2,G3_IO2" "0,1"
|
|
bitfld.long 0x00 8. "G3_IO1,G3_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "G2_IO4,G2_IO4" "0,1"
|
|
bitfld.long 0x00 6. "G2_IO3,G2_IO3" "0,1"
|
|
bitfld.long 0x00 5. "G2_IO2,G2_IO2" "0,1"
|
|
bitfld.long 0x00 4. "G2_IO1,G2_IO1" "0,1"
|
|
bitfld.long 0x00 3. "G1_IO4,G1_IO4" "0,1"
|
|
bitfld.long 0x00 2. "G1_IO3,G1_IO3" "0,1"
|
|
bitfld.long 0x00 1. "G1_IO2,G1_IO2" "0,1"
|
|
bitfld.long 0x00 0. "G1_IO1,G1_IO1" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IOGCSR,I/O group control status register"
|
|
rbitfld.long 0x00 23. "G8S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 22. "G7S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 21. "G6S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 20. "G5S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 19. "G4S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 18. "G3S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 17. "G2S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 16. "G1S,Analog I/O group x status" "0,1"
|
|
bitfld.long 0x00 7. "G8E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x00 6. "G7E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x00 5. "G6E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x00 4. "G5E,Analog I/O group x enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "G4E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x00 2. "G3E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x00 1. "G2E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x00 0. "G1E,Analog I/O group x enable" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "IOG1CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "IOG2CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "IOG3CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "IOG4CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "IOG5CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "IOG6CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "IOG7CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "IOG8CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
tree.end
|
|
tree "TSC"
|
|
base ad:0x40024000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,control register"
|
|
bitfld.long 0x00 28.--31. "CTPH,Charge transfer pulse high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "CTPL,Charge transfer pulse low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 17.--23. 1. "SSD,Spread spectrum deviation"
|
|
bitfld.long 0x00 16. "SSE,Spread spectrum enable" "0,1"
|
|
bitfld.long 0x00 15. "SSPSC,Spread spectrum prescaler" "0,1"
|
|
bitfld.long 0x00 12.--14. "PGPSC,pulse generator prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. "MCV,Max count value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "IODEF,I/O Default mode" "0,1"
|
|
bitfld.long 0x00 3. "SYNCPOL,Synchronization pin polarity" "0,1"
|
|
bitfld.long 0x00 2. "AM,Acquisition mode" "0,1"
|
|
bitfld.long 0x00 1. "START,Start a new acquisition" "0,1"
|
|
bitfld.long 0x00 0. "TSCE,Touch sensing controller enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER,interrupt enable register"
|
|
bitfld.long 0x00 1. "MCEIE,Max count error interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "EOAIE,End of acquisition interrupt enable" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICR,interrupt clear register"
|
|
bitfld.long 0x00 1. "MCEIC,Max count error interrupt clear" "0,1"
|
|
bitfld.long 0x00 0. "EOAIC,End of acquisition interrupt clear" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ISR,interrupt status register"
|
|
bitfld.long 0x00 1. "MCEF,Max count error flag" "0,1"
|
|
bitfld.long 0x00 0. "EOAF,End of acquisition flag" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IOHCR,I/O hysteresis control register"
|
|
bitfld.long 0x00 31. "G8_IO4,G8_IO4" "0,1"
|
|
bitfld.long 0x00 30. "G8_IO3,G8_IO3" "0,1"
|
|
bitfld.long 0x00 29. "G8_IO2,G8_IO2" "0,1"
|
|
bitfld.long 0x00 28. "G8_IO1,G8_IO1" "0,1"
|
|
bitfld.long 0x00 27. "G7_IO4,G7_IO4" "0,1"
|
|
bitfld.long 0x00 26. "G7_IO3,G7_IO3" "0,1"
|
|
bitfld.long 0x00 25. "G7_IO2,G7_IO2" "0,1"
|
|
bitfld.long 0x00 24. "G7_IO1,G7_IO1" "0,1"
|
|
bitfld.long 0x00 23. "G6_IO4,G6_IO4" "0,1"
|
|
bitfld.long 0x00 22. "G6_IO3,G6_IO3" "0,1"
|
|
bitfld.long 0x00 21. "G6_IO2,G6_IO2" "0,1"
|
|
bitfld.long 0x00 20. "G6_IO1,G6_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "G5_IO4,G5_IO4" "0,1"
|
|
bitfld.long 0x00 18. "G5_IO3,G5_IO3" "0,1"
|
|
bitfld.long 0x00 17. "G5_IO2,G5_IO2" "0,1"
|
|
bitfld.long 0x00 16. "G5_IO1,G5_IO1" "0,1"
|
|
bitfld.long 0x00 15. "G4_IO4,G4_IO4" "0,1"
|
|
bitfld.long 0x00 14. "G4_IO3,G4_IO3" "0,1"
|
|
bitfld.long 0x00 13. "G4_IO2,G4_IO2" "0,1"
|
|
bitfld.long 0x00 12. "G4_IO1,G4_IO1" "0,1"
|
|
bitfld.long 0x00 11. "G3_IO4,G3_IO4" "0,1"
|
|
bitfld.long 0x00 10. "G3_IO3,G3_IO3" "0,1"
|
|
bitfld.long 0x00 9. "G3_IO2,G3_IO2" "0,1"
|
|
bitfld.long 0x00 8. "G3_IO1,G3_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "G2_IO4,G2_IO4" "0,1"
|
|
bitfld.long 0x00 6. "G2_IO3,G2_IO3" "0,1"
|
|
bitfld.long 0x00 5. "G2_IO2,G2_IO2" "0,1"
|
|
bitfld.long 0x00 4. "G2_IO1,G2_IO1" "0,1"
|
|
bitfld.long 0x00 3. "G1_IO4,G1_IO4" "0,1"
|
|
bitfld.long 0x00 2. "G1_IO3,G1_IO3" "0,1"
|
|
bitfld.long 0x00 1. "G1_IO2,G1_IO2" "0,1"
|
|
bitfld.long 0x00 0. "G1_IO1,G1_IO1" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IOASCR,I/O analog switch control register"
|
|
bitfld.long 0x00 31. "G8_IO4,G8_IO4" "0,1"
|
|
bitfld.long 0x00 30. "G8_IO3,G8_IO3" "0,1"
|
|
bitfld.long 0x00 29. "G8_IO2,G8_IO2" "0,1"
|
|
bitfld.long 0x00 28. "G8_IO1,G8_IO1" "0,1"
|
|
bitfld.long 0x00 27. "G7_IO4,G7_IO4" "0,1"
|
|
bitfld.long 0x00 26. "G7_IO3,G7_IO3" "0,1"
|
|
bitfld.long 0x00 25. "G7_IO2,G7_IO2" "0,1"
|
|
bitfld.long 0x00 24. "G7_IO1,G7_IO1" "0,1"
|
|
bitfld.long 0x00 23. "G6_IO4,G6_IO4" "0,1"
|
|
bitfld.long 0x00 22. "G6_IO3,G6_IO3" "0,1"
|
|
bitfld.long 0x00 21. "G6_IO2,G6_IO2" "0,1"
|
|
bitfld.long 0x00 20. "G6_IO1,G6_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "G5_IO4,G5_IO4" "0,1"
|
|
bitfld.long 0x00 18. "G5_IO3,G5_IO3" "0,1"
|
|
bitfld.long 0x00 17. "G5_IO2,G5_IO2" "0,1"
|
|
bitfld.long 0x00 16. "G5_IO1,G5_IO1" "0,1"
|
|
bitfld.long 0x00 15. "G4_IO4,G4_IO4" "0,1"
|
|
bitfld.long 0x00 14. "G4_IO3,G4_IO3" "0,1"
|
|
bitfld.long 0x00 13. "G4_IO2,G4_IO2" "0,1"
|
|
bitfld.long 0x00 12. "G4_IO1,G4_IO1" "0,1"
|
|
bitfld.long 0x00 11. "G3_IO4,G3_IO4" "0,1"
|
|
bitfld.long 0x00 10. "G3_IO3,G3_IO3" "0,1"
|
|
bitfld.long 0x00 9. "G3_IO2,G3_IO2" "0,1"
|
|
bitfld.long 0x00 8. "G3_IO1,G3_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "G2_IO4,G2_IO4" "0,1"
|
|
bitfld.long 0x00 6. "G2_IO3,G2_IO3" "0,1"
|
|
bitfld.long 0x00 5. "G2_IO2,G2_IO2" "0,1"
|
|
bitfld.long 0x00 4. "G2_IO1,G2_IO1" "0,1"
|
|
bitfld.long 0x00 3. "G1_IO4,G1_IO4" "0,1"
|
|
bitfld.long 0x00 2. "G1_IO3,G1_IO3" "0,1"
|
|
bitfld.long 0x00 1. "G1_IO2,G1_IO2" "0,1"
|
|
bitfld.long 0x00 0. "G1_IO1,G1_IO1" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IOSCR,I/O sampling control register"
|
|
bitfld.long 0x00 31. "G8_IO4,G8_IO4" "0,1"
|
|
bitfld.long 0x00 30. "G8_IO3,G8_IO3" "0,1"
|
|
bitfld.long 0x00 29. "G8_IO2,G8_IO2" "0,1"
|
|
bitfld.long 0x00 28. "G8_IO1,G8_IO1" "0,1"
|
|
bitfld.long 0x00 27. "G7_IO4,G7_IO4" "0,1"
|
|
bitfld.long 0x00 26. "G7_IO3,G7_IO3" "0,1"
|
|
bitfld.long 0x00 25. "G7_IO2,G7_IO2" "0,1"
|
|
bitfld.long 0x00 24. "G7_IO1,G7_IO1" "0,1"
|
|
bitfld.long 0x00 23. "G6_IO4,G6_IO4" "0,1"
|
|
bitfld.long 0x00 22. "G6_IO3,G6_IO3" "0,1"
|
|
bitfld.long 0x00 21. "G6_IO2,G6_IO2" "0,1"
|
|
bitfld.long 0x00 20. "G6_IO1,G6_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "G5_IO4,G5_IO4" "0,1"
|
|
bitfld.long 0x00 18. "G5_IO3,G5_IO3" "0,1"
|
|
bitfld.long 0x00 17. "G5_IO2,G5_IO2" "0,1"
|
|
bitfld.long 0x00 16. "G5_IO1,G5_IO1" "0,1"
|
|
bitfld.long 0x00 15. "G4_IO4,G4_IO4" "0,1"
|
|
bitfld.long 0x00 14. "G4_IO3,G4_IO3" "0,1"
|
|
bitfld.long 0x00 13. "G4_IO2,G4_IO2" "0,1"
|
|
bitfld.long 0x00 12. "G4_IO1,G4_IO1" "0,1"
|
|
bitfld.long 0x00 11. "G3_IO4,G3_IO4" "0,1"
|
|
bitfld.long 0x00 10. "G3_IO3,G3_IO3" "0,1"
|
|
bitfld.long 0x00 9. "G3_IO2,G3_IO2" "0,1"
|
|
bitfld.long 0x00 8. "G3_IO1,G3_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "G2_IO4,G2_IO4" "0,1"
|
|
bitfld.long 0x00 6. "G2_IO3,G2_IO3" "0,1"
|
|
bitfld.long 0x00 5. "G2_IO2,G2_IO2" "0,1"
|
|
bitfld.long 0x00 4. "G2_IO1,G2_IO1" "0,1"
|
|
bitfld.long 0x00 3. "G1_IO4,G1_IO4" "0,1"
|
|
bitfld.long 0x00 2. "G1_IO3,G1_IO3" "0,1"
|
|
bitfld.long 0x00 1. "G1_IO2,G1_IO2" "0,1"
|
|
bitfld.long 0x00 0. "G1_IO1,G1_IO1" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IOCCR,I/O channel control register"
|
|
bitfld.long 0x00 31. "G8_IO4,G8_IO4" "0,1"
|
|
bitfld.long 0x00 30. "G8_IO3,G8_IO3" "0,1"
|
|
bitfld.long 0x00 29. "G8_IO2,G8_IO2" "0,1"
|
|
bitfld.long 0x00 28. "G8_IO1,G8_IO1" "0,1"
|
|
bitfld.long 0x00 27. "G7_IO4,G7_IO4" "0,1"
|
|
bitfld.long 0x00 26. "G7_IO3,G7_IO3" "0,1"
|
|
bitfld.long 0x00 25. "G7_IO2,G7_IO2" "0,1"
|
|
bitfld.long 0x00 24. "G7_IO1,G7_IO1" "0,1"
|
|
bitfld.long 0x00 23. "G6_IO4,G6_IO4" "0,1"
|
|
bitfld.long 0x00 22. "G6_IO3,G6_IO3" "0,1"
|
|
bitfld.long 0x00 21. "G6_IO2,G6_IO2" "0,1"
|
|
bitfld.long 0x00 20. "G6_IO1,G6_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "G5_IO4,G5_IO4" "0,1"
|
|
bitfld.long 0x00 18. "G5_IO3,G5_IO3" "0,1"
|
|
bitfld.long 0x00 17. "G5_IO2,G5_IO2" "0,1"
|
|
bitfld.long 0x00 16. "G5_IO1,G5_IO1" "0,1"
|
|
bitfld.long 0x00 15. "G4_IO4,G4_IO4" "0,1"
|
|
bitfld.long 0x00 14. "G4_IO3,G4_IO3" "0,1"
|
|
bitfld.long 0x00 13. "G4_IO2,G4_IO2" "0,1"
|
|
bitfld.long 0x00 12. "G4_IO1,G4_IO1" "0,1"
|
|
bitfld.long 0x00 11. "G3_IO4,G3_IO4" "0,1"
|
|
bitfld.long 0x00 10. "G3_IO3,G3_IO3" "0,1"
|
|
bitfld.long 0x00 9. "G3_IO2,G3_IO2" "0,1"
|
|
bitfld.long 0x00 8. "G3_IO1,G3_IO1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "G2_IO4,G2_IO4" "0,1"
|
|
bitfld.long 0x00 6. "G2_IO3,G2_IO3" "0,1"
|
|
bitfld.long 0x00 5. "G2_IO2,G2_IO2" "0,1"
|
|
bitfld.long 0x00 4. "G2_IO1,G2_IO1" "0,1"
|
|
bitfld.long 0x00 3. "G1_IO4,G1_IO4" "0,1"
|
|
bitfld.long 0x00 2. "G1_IO3,G1_IO3" "0,1"
|
|
bitfld.long 0x00 1. "G1_IO2,G1_IO2" "0,1"
|
|
bitfld.long 0x00 0. "G1_IO1,G1_IO1" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IOGCSR,I/O group control status register"
|
|
rbitfld.long 0x00 23. "G8S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 22. "G7S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 21. "G6S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 20. "G5S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 19. "G4S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 18. "G3S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 17. "G2S,Analog I/O group x status" "0,1"
|
|
rbitfld.long 0x00 16. "G1S,Analog I/O group x status" "0,1"
|
|
bitfld.long 0x00 7. "G8E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x00 6. "G7E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x00 5. "G6E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x00 4. "G5E,Analog I/O group x enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "G4E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x00 2. "G3E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x00 1. "G2E,Analog I/O group x enable" "0,1"
|
|
bitfld.long 0x00 0. "G1E,Analog I/O group x enable" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "IOG1CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "IOG2CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "IOG3CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "IOG4CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "IOG5CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "IOG6CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "IOG7CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "IOG8CR,I/O group x counter register"
|
|
hexmask.long.word 0x00 0.--13. 1. "CNT,Counter value"
|
|
tree.end
|
|
tree.end
|
|
tree "UCPD (USB Power Delivery interface)"
|
|
tree "SEC_UCPD1"
|
|
base ad:0x5000DC00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG1,UCPD configuration register"
|
|
bitfld.long 0x00 31. "UCPDEN,UCPDEN" "0,1"
|
|
bitfld.long 0x00 30. "RXDMAEN,RXDMAEN" "0,1"
|
|
bitfld.long 0x00 29. "TXDMAEN,TXDMAEN" "0,1"
|
|
hexmask.long.word 0x00 20.--28. 1. "RXORDSETEN,RXORDSETEN"
|
|
bitfld.long 0x00 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11.--15. "TRANSWIN,TRANSWIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 6.--10. "IFRGAP,IFRGAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. "HBITCLKDIV,HBITCLKDIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFG2,UCPD configuration register 2"
|
|
bitfld.long 0x00 3. "WUPEN,WUPEN" "0,1"
|
|
bitfld.long 0x00 2. "FORCECLK,FORCECLK" "0,1"
|
|
bitfld.long 0x00 1. "RXFILT2N3,RXFILT2N3" "0,1"
|
|
bitfld.long 0x00 0. "RXFILTDIS,RXFILTDIS" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CFG3,UCPD configuration register 3"
|
|
bitfld.long 0x00 25.--28. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--24. "TRIM2_NG_CC1A5,TRIM2_NG_CC1A5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--19. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--12. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--8. "TRIM1_NG_CC1A5,TRIM1_NG_CC1A5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR,UCPD control register"
|
|
bitfld.long 0x00 21. "CC2TCDIS,CC2TCDIS" "0,1"
|
|
bitfld.long 0x00 20. "CC1TCDIS,CC1TCDIS" "0,1"
|
|
bitfld.long 0x00 18. "RDCH,RDCH" "0,1"
|
|
bitfld.long 0x00 17. "FRSTX,FRSTX" "0,1"
|
|
bitfld.long 0x00 16. "FRSRXEN,FRSRXEN" "0,1"
|
|
bitfld.long 0x00 10.--11. "CCENABLE,CCENABLE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "ANAMODE,ANAMODE" "0,1"
|
|
bitfld.long 0x00 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3"
|
|
bitfld.long 0x00 6. "PHYCCSEL,PHYCCSEL" "0,1"
|
|
bitfld.long 0x00 5. "PHYRXEN,PHYRXEN" "0,1"
|
|
bitfld.long 0x00 4. "RXMODE,RXMODE" "0,1"
|
|
bitfld.long 0x00 3. "TXHRST,TXHRST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TXSEND,TXSEND" "0,1"
|
|
bitfld.long 0x00 0.--1. "TXMODE,TXMODE" "0,1,2,3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR,UCPD Interrupt Mask Register"
|
|
bitfld.long 0x00 20. "FRSEVTIE,FRSEVTIE" "0,1"
|
|
bitfld.long 0x00 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1"
|
|
bitfld.long 0x00 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1"
|
|
bitfld.long 0x00 12. "RXMSGENDIE,RXMSGENDIE" "0,1"
|
|
bitfld.long 0x00 11. "RXOVRIE,RXOVRIE" "0,1"
|
|
bitfld.long 0x00 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "RXORDDETIE,RXORDDETIE" "0,1"
|
|
bitfld.long 0x00 8. "RXNEIE,RXNEIE" "0,1"
|
|
bitfld.long 0x00 6. "TXUNDIE,TXUNDIE" "0,1"
|
|
bitfld.long 0x00 5. "HRSTSENTIE,HRSTSENTIE" "0,1"
|
|
bitfld.long 0x00 4. "HRSTDISCIE,HRSTDISCIE" "0,1"
|
|
bitfld.long 0x00 3. "TXMSGABTIE,TXMSGABTIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1"
|
|
bitfld.long 0x00 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1"
|
|
bitfld.long 0x00 0. "TXISIE,TXISIE" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SR,UCPD Status Register"
|
|
bitfld.long 0x00 20. "FRSEVT,FRSEVT" "0,1"
|
|
bitfld.long 0x00 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3"
|
|
bitfld.long 0x00 15. "TYPECEVT2,TYPECEVT2" "0,1"
|
|
bitfld.long 0x00 14. "TYPECEVT1,TYPECEVT1" "0,1"
|
|
bitfld.long 0x00 13. "RXERR,RXERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "RXMSGEND,RXMSGEND" "0,1"
|
|
bitfld.long 0x00 11. "RXOVR,RXOVR" "0,1"
|
|
bitfld.long 0x00 10. "RXHRSTDET,RXHRSTDET" "0,1"
|
|
bitfld.long 0x00 9. "RXORDDET,RXORDDET" "0,1"
|
|
bitfld.long 0x00 8. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x00 6. "TXUND,TXUND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "HRSTSENT,HRSTSENT" "0,1"
|
|
bitfld.long 0x00 4. "HRSTDISC,HRSTDISC" "0,1"
|
|
bitfld.long 0x00 3. "TXMSGABT,TXMSGABT" "0,1"
|
|
bitfld.long 0x00 2. "TXMSGSENT,TXMSGSENT" "0,1"
|
|
bitfld.long 0x00 1. "TXMSGDISC,TXMSGDISC" "0,1"
|
|
bitfld.long 0x00 0. "TXIS,TXIS" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ICR,UCPD Interrupt Clear Register"
|
|
bitfld.long 0x00 20. "FRSEVTCF,FRSEVTCF" "0,1"
|
|
bitfld.long 0x00 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1"
|
|
bitfld.long 0x00 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1"
|
|
bitfld.long 0x00 12. "RXMSGENDCF,RXMSGENDCF" "0,1"
|
|
bitfld.long 0x00 11. "RXOVRCF,RXOVRCF" "0,1"
|
|
bitfld.long 0x00 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "RXORDDETCF,RXORDDETCF" "0,1"
|
|
bitfld.long 0x00 6. "TXUNDCF,TXUNDCF" "0,1"
|
|
bitfld.long 0x00 5. "HRSTSENTCF,HRSTSENTCF" "0,1"
|
|
bitfld.long 0x00 4. "HRSTDISCCF,HRSTDISCCF" "0,1"
|
|
bitfld.long 0x00 3. "TXMSGABTCF,TXMSGABTCF" "0,1"
|
|
bitfld.long 0x00 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TX_ORDSET,UCPD Tx Ordered Set Type Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "TXORDSET,TXORDSET"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TX_PAYSZ,UCPD Tx Paysize Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "TXPAYSZ,TXPAYSZ"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TXDR,UCPD Tx Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXDATA,TXDATA"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RX_ORDSET,UCPD Rx Ordered Set Register"
|
|
bitfld.long 0x00 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "RXSOP3OF4,RXSOP3OF4" "0,1"
|
|
bitfld.long 0x00 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RX_PAYSZ,UCPD Rx Paysize Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "RXPAYSZ,RXPAYSZ"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "RXDR,UCPD Receive Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RXDATA,RXDATA"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "RX_ORDEXT1,UCPD Rx Ordered Set Extension Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "RXSOPX1,RXSOPX1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "RX_ORDEXT2,UCPD Rx Ordered Set Extension Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "RXSOPX2,RXSOPX2"
|
|
tree.end
|
|
tree "UCPD1"
|
|
base ad:0x4000DC00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG1,UCPD configuration register"
|
|
bitfld.long 0x00 31. "UCPDEN,UCPDEN" "0,1"
|
|
bitfld.long 0x00 30. "RXDMAEN,RXDMAEN" "0,1"
|
|
bitfld.long 0x00 29. "TXDMAEN,TXDMAEN" "0,1"
|
|
hexmask.long.word 0x00 20.--28. 1. "RXORDSETEN,RXORDSETEN"
|
|
bitfld.long 0x00 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11.--15. "TRANSWIN,TRANSWIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 6.--10. "IFRGAP,IFRGAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. "HBITCLKDIV,HBITCLKDIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFG2,UCPD configuration register 2"
|
|
bitfld.long 0x00 3. "WUPEN,WUPEN" "0,1"
|
|
bitfld.long 0x00 2. "FORCECLK,FORCECLK" "0,1"
|
|
bitfld.long 0x00 1. "RXFILT2N3,RXFILT2N3" "0,1"
|
|
bitfld.long 0x00 0. "RXFILTDIS,RXFILTDIS" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CFG3,UCPD configuration register 3"
|
|
bitfld.long 0x00 25.--28. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--24. "TRIM2_NG_CC1A5,TRIM2_NG_CC1A5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--19. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9.--12. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--8. "TRIM1_NG_CC1A5,TRIM1_NG_CC1A5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CR,UCPD control register"
|
|
bitfld.long 0x00 21. "CC2TCDIS,CC2TCDIS" "0,1"
|
|
bitfld.long 0x00 20. "CC1TCDIS,CC1TCDIS" "0,1"
|
|
bitfld.long 0x00 18. "RDCH,RDCH" "0,1"
|
|
bitfld.long 0x00 17. "FRSTX,FRSTX" "0,1"
|
|
bitfld.long 0x00 16. "FRSRXEN,FRSRXEN" "0,1"
|
|
bitfld.long 0x00 10.--11. "CCENABLE,CCENABLE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "ANAMODE,ANAMODE" "0,1"
|
|
bitfld.long 0x00 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3"
|
|
bitfld.long 0x00 6. "PHYCCSEL,PHYCCSEL" "0,1"
|
|
bitfld.long 0x00 5. "PHYRXEN,PHYRXEN" "0,1"
|
|
bitfld.long 0x00 4. "RXMODE,RXMODE" "0,1"
|
|
bitfld.long 0x00 3. "TXHRST,TXHRST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TXSEND,TXSEND" "0,1"
|
|
bitfld.long 0x00 0.--1. "TXMODE,TXMODE" "0,1,2,3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR,UCPD Interrupt Mask Register"
|
|
bitfld.long 0x00 20. "FRSEVTIE,FRSEVTIE" "0,1"
|
|
bitfld.long 0x00 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1"
|
|
bitfld.long 0x00 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1"
|
|
bitfld.long 0x00 12. "RXMSGENDIE,RXMSGENDIE" "0,1"
|
|
bitfld.long 0x00 11. "RXOVRIE,RXOVRIE" "0,1"
|
|
bitfld.long 0x00 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "RXORDDETIE,RXORDDETIE" "0,1"
|
|
bitfld.long 0x00 8. "RXNEIE,RXNEIE" "0,1"
|
|
bitfld.long 0x00 6. "TXUNDIE,TXUNDIE" "0,1"
|
|
bitfld.long 0x00 5. "HRSTSENTIE,HRSTSENTIE" "0,1"
|
|
bitfld.long 0x00 4. "HRSTDISCIE,HRSTDISCIE" "0,1"
|
|
bitfld.long 0x00 3. "TXMSGABTIE,TXMSGABTIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1"
|
|
bitfld.long 0x00 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1"
|
|
bitfld.long 0x00 0. "TXISIE,TXISIE" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SR,UCPD Status Register"
|
|
bitfld.long 0x00 20. "FRSEVT,FRSEVT" "0,1"
|
|
bitfld.long 0x00 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3"
|
|
bitfld.long 0x00 15. "TYPECEVT2,TYPECEVT2" "0,1"
|
|
bitfld.long 0x00 14. "TYPECEVT1,TYPECEVT1" "0,1"
|
|
bitfld.long 0x00 13. "RXERR,RXERR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "RXMSGEND,RXMSGEND" "0,1"
|
|
bitfld.long 0x00 11. "RXOVR,RXOVR" "0,1"
|
|
bitfld.long 0x00 10. "RXHRSTDET,RXHRSTDET" "0,1"
|
|
bitfld.long 0x00 9. "RXORDDET,RXORDDET" "0,1"
|
|
bitfld.long 0x00 8. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x00 6. "TXUND,TXUND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "HRSTSENT,HRSTSENT" "0,1"
|
|
bitfld.long 0x00 4. "HRSTDISC,HRSTDISC" "0,1"
|
|
bitfld.long 0x00 3. "TXMSGABT,TXMSGABT" "0,1"
|
|
bitfld.long 0x00 2. "TXMSGSENT,TXMSGSENT" "0,1"
|
|
bitfld.long 0x00 1. "TXMSGDISC,TXMSGDISC" "0,1"
|
|
bitfld.long 0x00 0. "TXIS,TXIS" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ICR,UCPD Interrupt Clear Register"
|
|
bitfld.long 0x00 20. "FRSEVTCF,FRSEVTCF" "0,1"
|
|
bitfld.long 0x00 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1"
|
|
bitfld.long 0x00 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1"
|
|
bitfld.long 0x00 12. "RXMSGENDCF,RXMSGENDCF" "0,1"
|
|
bitfld.long 0x00 11. "RXOVRCF,RXOVRCF" "0,1"
|
|
bitfld.long 0x00 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "RXORDDETCF,RXORDDETCF" "0,1"
|
|
bitfld.long 0x00 6. "TXUNDCF,TXUNDCF" "0,1"
|
|
bitfld.long 0x00 5. "HRSTSENTCF,HRSTSENTCF" "0,1"
|
|
bitfld.long 0x00 4. "HRSTDISCCF,HRSTDISCCF" "0,1"
|
|
bitfld.long 0x00 3. "TXMSGABTCF,TXMSGABTCF" "0,1"
|
|
bitfld.long 0x00 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TX_ORDSET,UCPD Tx Ordered Set Type Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "TXORDSET,TXORDSET"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TX_PAYSZ,UCPD Tx Paysize Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "TXPAYSZ,TXPAYSZ"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TXDR,UCPD Tx Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXDATA,TXDATA"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RX_ORDSET,UCPD Rx Ordered Set Register"
|
|
bitfld.long 0x00 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. "RXSOP3OF4,RXSOP3OF4" "0,1"
|
|
bitfld.long 0x00 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RX_PAYSZ,UCPD Rx Paysize Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "RXPAYSZ,RXPAYSZ"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "RXDR,UCPD Receive Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RXDATA,RXDATA"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "RX_ORDEXT1,UCPD Rx Ordered Set Extension Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "RXSOPX1,RXSOPX1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "RX_ORDEXT2,UCPD Rx Ordered Set Extension Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "RXSOPX2,RXSOPX2"
|
|
tree.end
|
|
tree.end
|
|
tree "USART (Universal synchronous asynchronous receiver transmitter)"
|
|
tree "LPUART1"
|
|
base ad:0x40008000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control register 1"
|
|
bitfld.long 0x00 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x00 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x00 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x00 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x00 21.--25. "DEAT,DEAT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "DEDT,DEDT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x00 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x00 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x00 11. "WAKE,Receiver wakeup method" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x00 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x00 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x00 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x00 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x00 1. "UESM,USART enable in Stop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UE,USART enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. "ADD4_7,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "ADD0_3,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x00 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x00 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x00 16. "RXINV,RX pin active level inversion" "0,1"
|
|
bitfld.long 0x00 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x00 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x00 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control register 3"
|
|
bitfld.long 0x00 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x00 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x00 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x00 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x00 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x00 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x00 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x00 12. "OVRDIS,Overrun Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x00 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x00 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x00 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x00 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x00 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x00 0. "EIE,Error interrupt enable" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud rate register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "BRR,BRR"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RQR,Request register"
|
|
bitfld.long 0x00 4. "TXFRQ,TXFRQ" "0,1"
|
|
bitfld.long 0x00 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x00 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x00 1. "SBKRQ,Send break request" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt & status register"
|
|
bitfld.long 0x00 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x00 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x00 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x00 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x00 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x00 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x00 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x00 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x00 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x00 17. "CMF,CMF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x00 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x00 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x00 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 6. "TC,TC" "0,1"
|
|
bitfld.long 0x00 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x00 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x00 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x00 2. "NF,NF" "0,1"
|
|
bitfld.long 0x00 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x00 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x00 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x00 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x00 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x00 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x00 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x00 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x00 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x00 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RDR,Receive data register"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. "TDR,Transmit data value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PRESC,PRESC"
|
|
bitfld.long 0x00 0.--3. "PRESCALER,PRESCALER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "SEC_LPUART1"
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base ad:0x50008000
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group.long 0x00++0x03
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line.long 0x00 "CR1,Control register 1"
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bitfld.long 0x00 31. "RXFFIE,RXFFIE" "0,1"
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bitfld.long 0x00 30. "TXFEIE,TXFEIE" "0,1"
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bitfld.long 0x00 29. "FIFOEN,FIFOEN" "0,1"
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bitfld.long 0x00 28. "M1,Word length" "0,1"
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bitfld.long 0x00 21.--25. "DEAT,DEAT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. "DEDT,DEDT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14. "CMIE,Character match interrupt enable" "0,1"
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bitfld.long 0x00 13. "MME,Mute mode enable" "0,1"
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bitfld.long 0x00 12. "M0,Word length" "0,1"
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bitfld.long 0x00 11. "WAKE,Receiver wakeup method" "0,1"
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newline
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bitfld.long 0x00 10. "PCE,Parity control enable" "0,1"
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bitfld.long 0x00 9. "PS,Parity selection" "0,1"
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bitfld.long 0x00 8. "PEIE,PE interrupt enable" "0,1"
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bitfld.long 0x00 7. "TXEIE,interrupt enable" "0,1"
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bitfld.long 0x00 6. "TCIE,Transmission complete interrupt enable" "0,1"
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bitfld.long 0x00 5. "RXNEIE,RXNE interrupt enable" "0,1"
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bitfld.long 0x00 4. "IDLEIE,IDLE interrupt enable" "0,1"
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bitfld.long 0x00 3. "TE,Transmitter enable" "0,1"
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bitfld.long 0x00 2. "RE,Receiver enable" "0,1"
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bitfld.long 0x00 1. "UESM,USART enable in Stop mode" "0,1"
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newline
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bitfld.long 0x00 0. "UE,USART enable" "0,1"
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group.long 0x04++0x03
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line.long 0x00 "CR2,Control register 2"
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bitfld.long 0x00 28.--31. "ADD4_7,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "ADD0_3,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "MSBFIRST,Most significant bit first" "0,1"
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bitfld.long 0x00 18. "TAINV,Binary data inversion" "0,1"
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bitfld.long 0x00 17. "TXINV,TX pin active level inversion" "0,1"
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bitfld.long 0x00 16. "RXINV,RX pin active level inversion" "0,1"
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bitfld.long 0x00 15. "SWAP,Swap TX/RX pins" "0,1"
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bitfld.long 0x00 12.--13. "STOP,STOP bits" "0,1,2,3"
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bitfld.long 0x00 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
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group.long 0x08++0x03
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line.long 0x00 "CR3,Control register 3"
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bitfld.long 0x00 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 28. "RXFTIE,RXFTIE" "0,1"
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bitfld.long 0x00 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 23. "TXFTIE,TXFTIE" "0,1"
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bitfld.long 0x00 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
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bitfld.long 0x00 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
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bitfld.long 0x00 15. "DEP,Driver enable polarity selection" "0,1"
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bitfld.long 0x00 14. "DEM,Driver enable mode" "0,1"
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bitfld.long 0x00 13. "DDRE,DMA Disable on Reception Error" "0,1"
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bitfld.long 0x00 12. "OVRDIS,Overrun Disable" "0,1"
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newline
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bitfld.long 0x00 10. "CTSIE,CTS interrupt enable" "0,1"
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bitfld.long 0x00 9. "CTSE,CTS enable" "0,1"
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bitfld.long 0x00 8. "RTSE,RTS enable" "0,1"
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bitfld.long 0x00 7. "DMAT,DMA enable transmitter" "0,1"
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bitfld.long 0x00 6. "DMAR,DMA enable receiver" "0,1"
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bitfld.long 0x00 3. "HDSEL,Half-duplex selection" "0,1"
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bitfld.long 0x00 0. "EIE,Error interrupt enable" "0,1"
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group.long 0x0C++0x03
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line.long 0x00 "BRR,Baud rate register"
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hexmask.long.tbyte 0x00 0.--19. 1. "BRR,BRR"
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wgroup.long 0x18++0x03
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line.long 0x00 "RQR,Request register"
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bitfld.long 0x00 4. "TXFRQ,TXFRQ" "0,1"
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bitfld.long 0x00 3. "RXFRQ,Receive data flush request" "0,1"
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bitfld.long 0x00 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x00 1. "SBKRQ,Send break request" "0,1"
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rgroup.long 0x1C++0x03
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line.long 0x00 "ISR,Interrupt & status register"
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bitfld.long 0x00 27. "TXFT,TXFT" "0,1"
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bitfld.long 0x00 26. "RXFT,RXFT" "0,1"
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bitfld.long 0x00 24. "RXFF,RXFF" "0,1"
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bitfld.long 0x00 23. "TXFE,TXFE" "0,1"
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bitfld.long 0x00 22. "REACK,REACK" "0,1"
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bitfld.long 0x00 21. "TEACK,TEACK" "0,1"
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bitfld.long 0x00 20. "WUF,WUF" "0,1"
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bitfld.long 0x00 19. "RWU,RWU" "0,1"
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bitfld.long 0x00 18. "SBKF,SBKF" "0,1"
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bitfld.long 0x00 17. "CMF,CMF" "0,1"
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newline
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bitfld.long 0x00 16. "BUSY,BUSY" "0,1"
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bitfld.long 0x00 10. "CTS,CTS" "0,1"
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bitfld.long 0x00 9. "CTSIF,CTSIF" "0,1"
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bitfld.long 0x00 7. "TXE,TXE" "0,1"
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bitfld.long 0x00 6. "TC,TC" "0,1"
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bitfld.long 0x00 5. "RXNE,RXNE" "0,1"
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bitfld.long 0x00 4. "IDLE,IDLE" "0,1"
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bitfld.long 0x00 3. "ORE,ORE" "0,1"
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bitfld.long 0x00 2. "NF,NF" "0,1"
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bitfld.long 0x00 1. "FE,FE" "0,1"
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newline
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bitfld.long 0x00 0. "PE,PE" "0,1"
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wgroup.long 0x20++0x03
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line.long 0x00 "ICR,Interrupt flag clear register"
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bitfld.long 0x00 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
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bitfld.long 0x00 17. "CMCF,Character match clear flag" "0,1"
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bitfld.long 0x00 9. "CTSCF,CTS clear flag" "0,1"
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bitfld.long 0x00 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x00 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x00 3. "ORECF,Overrun error clear flag" "0,1"
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bitfld.long 0x00 2. "NCF,Noise detected clear flag" "0,1"
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bitfld.long 0x00 1. "FECF,Framing error clear flag" "0,1"
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bitfld.long 0x00 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x03
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line.long 0x00 "RDR,Receive data register"
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hexmask.long.word 0x00 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x03
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line.long 0x00 "TDR,Transmit data register"
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hexmask.long.word 0x00 0.--8. 1. "TDR,Transmit data value"
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group.long 0x2C++0x03
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line.long 0x00 "PRESC,PRESC"
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bitfld.long 0x00 0.--3. "PRESCALER,PRESCALER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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tree.end
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repeat 2. (list 4. 5.) (list ad:0x50004C00 ad:0x50005000)
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tree "SEC_UART$1"
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base $2
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group.long 0x00++0x03
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line.long 0x00 "CR1,Control register 1"
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bitfld.long 0x00 31. "RXFFIE,RXFFIE" "0,1"
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bitfld.long 0x00 30. "TXFEIE,TXFEIE" "0,1"
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bitfld.long 0x00 29. "FIFOEN,FIFOEN" "0,1"
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bitfld.long 0x00 28. "M1,Word length" "0,1"
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bitfld.long 0x00 27. "EOBIE,End of Block interrupt enable" "0,1"
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bitfld.long 0x00 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
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bitfld.long 0x00 25. "DEAT4,Driver Enable assertion time" "0,1"
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bitfld.long 0x00 24. "DEAT3,DEAT3" "0,1"
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bitfld.long 0x00 23. "DEAT2,DEAT2" "0,1"
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bitfld.long 0x00 22. "DEAT1,DEAT1" "0,1"
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newline
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bitfld.long 0x00 21. "DEAT0,DEAT0" "0,1"
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bitfld.long 0x00 20. "DEDT4,Driver Enable de-assertion time" "0,1"
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bitfld.long 0x00 19. "DEDT3,DEDT3" "0,1"
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bitfld.long 0x00 18. "DEDT2,DEDT2" "0,1"
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bitfld.long 0x00 17. "DEDT1,DEDT1" "0,1"
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bitfld.long 0x00 16. "DEDT0,DEDT0" "0,1"
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bitfld.long 0x00 15. "OVER8,Oversampling mode" "0,1"
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bitfld.long 0x00 14. "CMIE,Character match interrupt enable" "0,1"
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bitfld.long 0x00 13. "MME,Mute mode enable" "0,1"
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bitfld.long 0x00 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x00 11. "WAKE,Receiver wakeup method" "0,1"
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bitfld.long 0x00 10. "PCE,Parity control enable" "0,1"
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bitfld.long 0x00 9. "PS,Parity selection" "0,1"
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bitfld.long 0x00 8. "PEIE,PE interrupt enable" "0,1"
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bitfld.long 0x00 7. "TXEIE,interrupt enable" "0,1"
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bitfld.long 0x00 6. "TCIE,Transmission complete interrupt enable" "0,1"
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bitfld.long 0x00 5. "RXNEIE,RXNE interrupt enable" "0,1"
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bitfld.long 0x00 4. "IDLEIE,IDLE interrupt enable" "0,1"
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bitfld.long 0x00 3. "TE,Transmitter enable" "0,1"
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bitfld.long 0x00 2. "RE,Receiver enable" "0,1"
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newline
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bitfld.long 0x00 1. "UESM,USART enable in Stop mode" "0,1"
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bitfld.long 0x00 0. "UE,USART enable" "0,1"
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group.long 0x04++0x03
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line.long 0x00 "CR2,Control register 2"
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bitfld.long 0x00 28.--31. "ADD4_7,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "ADD0_3,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "RTOEN,Receiver timeout enable" "0,1"
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bitfld.long 0x00 22. "ABRMOD1,Auto baud rate mode" "0,1"
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bitfld.long 0x00 21. "ABRMOD0,ABRMOD0" "0,1"
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bitfld.long 0x00 20. "ABREN,Auto baud rate enable" "0,1"
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bitfld.long 0x00 19. "MSBFIRST,Most significant bit first" "0,1"
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bitfld.long 0x00 18. "DATAINV,Binary data inversion" "0,1"
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bitfld.long 0x00 17. "TXINV,TX pin active level inversion" "0,1"
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bitfld.long 0x00 16. "RXINV,RX pin active level inversion" "0,1"
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newline
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bitfld.long 0x00 15. "SWAP,Swap TX/RX pins" "0,1"
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bitfld.long 0x00 14. "LINEN,LIN mode enable" "0,1"
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bitfld.long 0x00 12.--13. "STOP,STOP bits" "0,1,2,3"
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bitfld.long 0x00 11. "CLKEN,Clock enable" "0,1"
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bitfld.long 0x00 10. "CPOL,Clock polarity" "0,1"
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bitfld.long 0x00 9. "CPHA,Clock phase" "0,1"
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bitfld.long 0x00 8. "LBCL,Last bit clock pulse" "0,1"
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bitfld.long 0x00 6. "LBDIE,LIN break detection interrupt enable" "0,1"
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bitfld.long 0x00 5. "LBDL,LIN break detection length" "0,1"
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bitfld.long 0x00 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
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newline
|
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bitfld.long 0x00 3. "DIS_NSS,DIS_NSS" "0,1"
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bitfld.long 0x00 0. "SLVEN,SLVEN" "0,1"
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group.long 0x08++0x03
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line.long 0x00 "CR3,Control register 3"
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bitfld.long 0x00 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 28. "RXFTIE,RXFTIE" "0,1"
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bitfld.long 0x00 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24. "TCBGTIE,TCBGTIE" "0,1"
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bitfld.long 0x00 23. "TXFTIE,TXFTIE" "0,1"
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bitfld.long 0x00 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
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bitfld.long 0x00 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
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bitfld.long 0x00 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "DEP,Driver enable polarity selection" "0,1"
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bitfld.long 0x00 14. "DEM,Driver enable mode" "0,1"
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newline
|
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bitfld.long 0x00 13. "DDRE,DMA Disable on Reception Error" "0,1"
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bitfld.long 0x00 12. "OVRDIS,Overrun Disable" "0,1"
|
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bitfld.long 0x00 11. "ONEBIT,One sample bit method enable" "0,1"
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bitfld.long 0x00 10. "CTSIE,CTS interrupt enable" "0,1"
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bitfld.long 0x00 9. "CTSE,CTS enable" "0,1"
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bitfld.long 0x00 8. "RTSE,RTS enable" "0,1"
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bitfld.long 0x00 7. "DMAT,DMA enable transmitter" "0,1"
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bitfld.long 0x00 6. "DMAR,DMA enable receiver" "0,1"
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bitfld.long 0x00 5. "SCEN,Smartcard mode enable" "0,1"
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bitfld.long 0x00 4. "NACK,Smartcard NACK enable" "0,1"
|
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newline
|
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bitfld.long 0x00 3. "HDSEL,Half-duplex selection" "0,1"
|
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bitfld.long 0x00 2. "IRLP,Ir low-power" "0,1"
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bitfld.long 0x00 1. "IREN,Ir mode enable" "0,1"
|
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bitfld.long 0x00 0. "EIE,Error interrupt enable" "0,1"
|
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group.long 0x0C++0x03
|
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line.long 0x00 "BRR,Baud rate register"
|
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hexmask.long.word 0x00 0.--15. 1. "BRR,BRR"
|
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group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescaler value"
|
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group.long 0x14++0x03
|
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line.long 0x00 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BLEN,Block Length"
|
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hexmask.long.tbyte 0x00 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
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line.long 0x00 "RQR,Request register"
|
|
bitfld.long 0x00 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x00 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x00 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x00 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x00 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt & status register"
|
|
bitfld.long 0x00 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x00 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x00 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x00 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x00 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x00 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x00 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x00 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x00 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x00 18. "SBKF,SBKF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x00 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x00 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x00 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x00 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x00 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x00 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x00 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x00 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x00 7. "TXE,TXE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TC,TC" "0,1"
|
|
bitfld.long 0x00 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x00 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x00 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x00 2. "NF,NF" "0,1"
|
|
bitfld.long 0x00 1. "FE,FE" "0,1"
|
|
bitfld.long 0x00 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x00 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x00 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x00 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x00 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x00 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x00 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x00 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x00 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
bitfld.long 0x00 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x00 5. "TXFECF,TXFECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x00 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x00 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x00 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x00 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RDR,Receive data register"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. "TDR,Transmit data value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PRESC,PRESC"
|
|
bitfld.long 0x00 0.--3. "PRESCALER,PRESCALER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
repeat.end
|
|
repeat 3. (list 1. 2. 3.) (list ad:0x50013800 ad:0x50004400 ad:0x50004800)
|
|
tree "SEC_USART$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control register 1"
|
|
bitfld.long 0x00 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x00 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x00 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x00 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x00 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x00 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x00 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x00 24. "DEAT3,DEAT3" "0,1"
|
|
bitfld.long 0x00 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x00 22. "DEAT1,DEAT1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x00 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x00 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x00 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x00 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x00 16. "DEDT0,DEDT0" "0,1"
|
|
bitfld.long 0x00 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x00 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x00 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x00 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x00 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x00 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x00 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x00 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x00 2. "RE,Receiver enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x00 0. "UE,USART enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. "ADD4_7,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "ADD0_3,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x00 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x00 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x00 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x00 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x00 18. "DATAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x00 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x00 16. "RXINV,RX pin active level inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x00 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x00 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x00 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x00 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x00 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x00 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x00 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x00 0. "SLVEN,SLVEN" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control register 3"
|
|
bitfld.long 0x00 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x00 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x00 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x00 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x00 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x00 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x00 14. "DEM,Driver enable mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x00 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x00 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x00 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x00 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x00 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x00 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x00 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x00 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x00 4. "NACK,Smartcard NACK enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x00 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x00 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x00 0. "EIE,Error interrupt enable" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud rate register"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRR,BRR"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescaler value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RQR,Request register"
|
|
bitfld.long 0x00 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x00 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x00 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x00 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x00 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt & status register"
|
|
bitfld.long 0x00 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x00 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x00 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x00 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x00 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x00 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x00 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x00 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x00 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x00 18. "SBKF,SBKF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x00 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x00 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x00 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x00 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x00 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x00 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x00 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x00 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x00 7. "TXE,TXE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TC,TC" "0,1"
|
|
bitfld.long 0x00 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x00 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x00 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x00 2. "NF,NF" "0,1"
|
|
bitfld.long 0x00 1. "FE,FE" "0,1"
|
|
bitfld.long 0x00 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x00 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x00 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x00 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x00 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x00 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x00 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x00 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x00 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
bitfld.long 0x00 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x00 5. "TXFECF,TXFECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x00 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x00 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x00 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x00 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RDR,Receive data register"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. "TDR,Transmit data value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PRESC,PRESC"
|
|
bitfld.long 0x00 0.--3. "PRESCALER,PRESCALER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
repeat.end
|
|
repeat 2. (list 4. 5.) (list ad:0x40004C00 ad:0x40005000)
|
|
tree "UART$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control register 1"
|
|
bitfld.long 0x00 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x00 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x00 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x00 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x00 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x00 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x00 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x00 24. "DEAT3,DEAT3" "0,1"
|
|
bitfld.long 0x00 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x00 22. "DEAT1,DEAT1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x00 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x00 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x00 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x00 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x00 16. "DEDT0,DEDT0" "0,1"
|
|
bitfld.long 0x00 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x00 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x00 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x00 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x00 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x00 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x00 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x00 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x00 2. "RE,Receiver enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x00 0. "UE,USART enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. "ADD4_7,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "ADD0_3,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x00 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x00 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x00 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x00 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x00 18. "DATAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x00 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x00 16. "RXINV,RX pin active level inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x00 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x00 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x00 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x00 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x00 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x00 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x00 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x00 0. "SLVEN,SLVEN" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control register 3"
|
|
bitfld.long 0x00 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x00 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x00 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x00 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x00 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x00 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x00 14. "DEM,Driver enable mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x00 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x00 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x00 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x00 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x00 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x00 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x00 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x00 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x00 4. "NACK,Smartcard NACK enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x00 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x00 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x00 0. "EIE,Error interrupt enable" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud rate register"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRR,BRR"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescaler value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RQR,Request register"
|
|
bitfld.long 0x00 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x00 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x00 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x00 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x00 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt & status register"
|
|
bitfld.long 0x00 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x00 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x00 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x00 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x00 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x00 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x00 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x00 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x00 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x00 18. "SBKF,SBKF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x00 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x00 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x00 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x00 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x00 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x00 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x00 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x00 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x00 7. "TXE,TXE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TC,TC" "0,1"
|
|
bitfld.long 0x00 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x00 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x00 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x00 2. "NF,NF" "0,1"
|
|
bitfld.long 0x00 1. "FE,FE" "0,1"
|
|
bitfld.long 0x00 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x00 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x00 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x00 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x00 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x00 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x00 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x00 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x00 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
bitfld.long 0x00 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x00 5. "TXFECF,TXFECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x00 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x00 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x00 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x00 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RDR,Receive data register"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. "TDR,Transmit data value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PRESC,PRESC"
|
|
bitfld.long 0x00 0.--3. "PRESCALER,PRESCALER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
repeat.end
|
|
repeat 3. (list 1. 2. 3.) (list ad:0x40013800 ad:0x40004400 ad:0x40004800)
|
|
tree "USART$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control register 1"
|
|
bitfld.long 0x00 31. "RXFFIE,RXFFIE" "0,1"
|
|
bitfld.long 0x00 30. "TXFEIE,TXFEIE" "0,1"
|
|
bitfld.long 0x00 29. "FIFOEN,FIFOEN" "0,1"
|
|
bitfld.long 0x00 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x00 27. "EOBIE,End of Block interrupt enable" "0,1"
|
|
bitfld.long 0x00 26. "RTOIE,Receiver timeout interrupt enable" "0,1"
|
|
bitfld.long 0x00 25. "DEAT4,Driver Enable assertion time" "0,1"
|
|
bitfld.long 0x00 24. "DEAT3,DEAT3" "0,1"
|
|
bitfld.long 0x00 23. "DEAT2,DEAT2" "0,1"
|
|
bitfld.long 0x00 22. "DEAT1,DEAT1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "DEAT0,DEAT0" "0,1"
|
|
bitfld.long 0x00 20. "DEDT4,Driver Enable de-assertion time" "0,1"
|
|
bitfld.long 0x00 19. "DEDT3,DEDT3" "0,1"
|
|
bitfld.long 0x00 18. "DEDT2,DEDT2" "0,1"
|
|
bitfld.long 0x00 17. "DEDT1,DEDT1" "0,1"
|
|
bitfld.long 0x00 16. "DEDT0,DEDT0" "0,1"
|
|
bitfld.long 0x00 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x00 14. "CMIE,Character match interrupt enable" "0,1"
|
|
bitfld.long 0x00 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x00 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x00 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x00 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x00 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x00 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "TCIE,Transmission complete interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x00 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x00 2. "RE,Receiver enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x00 0. "UE,USART enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. "ADD4_7,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "ADD0_3,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x00 22. "ABRMOD1,Auto baud rate mode" "0,1"
|
|
bitfld.long 0x00 21. "ABRMOD0,ABRMOD0" "0,1"
|
|
bitfld.long 0x00 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x00 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x00 18. "DATAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x00 17. "TXINV,TX pin active level inversion" "0,1"
|
|
bitfld.long 0x00 16. "RXINV,RX pin active level inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x00 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x00 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x00 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x00 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x00 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x00 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x00 6. "LBDIE,LIN break detection interrupt enable" "0,1"
|
|
bitfld.long 0x00 5. "LBDL,LIN break detection length" "0,1"
|
|
bitfld.long 0x00 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DIS_NSS,DIS_NSS" "0,1"
|
|
bitfld.long 0x00 0. "SLVEN,SLVEN" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control register 3"
|
|
bitfld.long 0x00 29.--31. "TXFTCFG,TXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "RXFTIE,RXFTIE" "0,1"
|
|
bitfld.long 0x00 25.--27. "RXFTCFG,RXFTCFG" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24. "TCBGTIE,TCBGTIE" "0,1"
|
|
bitfld.long 0x00 23. "TXFTIE,TXFTIE" "0,1"
|
|
bitfld.long 0x00 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1"
|
|
bitfld.long 0x00 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
|
|
bitfld.long 0x00 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "DEP,Driver enable polarity selection" "0,1"
|
|
bitfld.long 0x00 14. "DEM,Driver enable mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DDRE,DMA Disable on Reception Error" "0,1"
|
|
bitfld.long 0x00 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x00 11. "ONEBIT,One sample bit method enable" "0,1"
|
|
bitfld.long 0x00 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x00 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x00 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x00 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x00 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x00 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x00 4. "NACK,Smartcard NACK enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x00 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x00 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x00 0. "EIE,Error interrupt enable" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud rate register"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRR,BRR"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescaler value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RQR,Request register"
|
|
bitfld.long 0x00 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x00 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x00 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x00 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x00 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt & status register"
|
|
bitfld.long 0x00 27. "TXFT,TXFT" "0,1"
|
|
bitfld.long 0x00 26. "RXFT,RXFT" "0,1"
|
|
bitfld.long 0x00 25. "TCBGT,TCBGT" "0,1"
|
|
bitfld.long 0x00 24. "RXFF,RXFF" "0,1"
|
|
bitfld.long 0x00 23. "TXFE,TXFE" "0,1"
|
|
bitfld.long 0x00 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x00 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x00 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x00 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x00 18. "SBKF,SBKF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x00 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x00 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x00 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x00 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x00 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x00 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x00 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x00 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x00 7. "TXE,TXE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TC,TC" "0,1"
|
|
bitfld.long 0x00 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x00 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x00 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x00 2. "NF,NF" "0,1"
|
|
bitfld.long 0x00 1. "FE,FE" "0,1"
|
|
bitfld.long 0x00 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x00 20. "WUCF,Wakeup from Stop mode clear flag" "0,1"
|
|
bitfld.long 0x00 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x00 13. "UDRCF,UDRCF" "0,1"
|
|
bitfld.long 0x00 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x00 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x00 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x00 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x00 7. "TCBGTCF,TCBGTCF" "0,1"
|
|
bitfld.long 0x00 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x00 5. "TXFECF,TXFECF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x00 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x00 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x00 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x00 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RDR,Receive data register"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. "TDR,Transmit data value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PRESC,PRESC"
|
|
bitfld.long 0x00 0.--3. "PRESCALER,PRESCALER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "USB (Universal Serial Bus)"
|
|
tree "SEC_USB"
|
|
base ad:0x5000D400
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "EP0R,endpoint 0 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "EP1R,endpoint 1 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "EP2R,endpoint 2 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "EP3R,endpoint 3 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "EP4R,endpoint 4 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "EP5R,endpoint 5 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "EP6R,endpoint 6 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "EP7R,endpoint 7 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CNTR,control register"
|
|
bitfld.word 0x00 15. "CTRM,Correct transfer interrupt mask" "0,1"
|
|
bitfld.word 0x00 14. "PMAOVRM,Packet memory area over / underrun interrupt mask" "0,1"
|
|
bitfld.word 0x00 13. "ERRM,Error interrupt mask" "0,1"
|
|
bitfld.word 0x00 12. "WKUPM,Wakeup interrupt mask" "0,1"
|
|
bitfld.word 0x00 11. "SUSPM,Suspend mode interrupt mask" "0,1"
|
|
bitfld.word 0x00 10. "RESETM,USB reset interrupt mask" "0,1"
|
|
bitfld.word 0x00 9. "SOFM,Start of frame interrupt mask" "0,1"
|
|
bitfld.word 0x00 8. "ESOFM,Expected start of frame interrupt mask" "0,1"
|
|
bitfld.word 0x00 7. "L1REQM,LPM L1 state request interrupt mask" "0,1"
|
|
bitfld.word 0x00 5. "L1RESUME,LPM L1 Resume request" "0,1"
|
|
bitfld.word 0x00 4. "RESUME,Resume request" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. "FSUSP,Force suspend" "0,1"
|
|
bitfld.word 0x00 2. "LPMODE,Low-power mode" "0,1"
|
|
bitfld.word 0x00 1. "PDWN,Power down" "0,1"
|
|
bitfld.word 0x00 0. "FRES,Force USB Reset" "0,1"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "ISTR,interrupt status register"
|
|
rbitfld.word 0x00 15. "CTR,Correct transfer" "0,1"
|
|
bitfld.word 0x00 14. "PMAOVR,Packet memory area over / underrun" "0,1"
|
|
bitfld.word 0x00 13. "ERR,Error" "0,1"
|
|
bitfld.word 0x00 12. "WKUP,Wakeup" "0,1"
|
|
bitfld.word 0x00 11. "SUSP,Suspend mode request" "0,1"
|
|
bitfld.word 0x00 10. "RESET,reset request" "0,1"
|
|
bitfld.word 0x00 9. "SOF,start of frame" "0,1"
|
|
bitfld.word 0x00 8. "ESOF,Expected start frame" "0,1"
|
|
bitfld.word 0x00 7. "L1REQ,LPM L1 state request" "0,1"
|
|
rbitfld.word 0x00 4. "DIR,Direction of transaction" "0,1"
|
|
rbitfld.word 0x00 0.--3. "EP_ID,Endpoint Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "FNR,frame number register"
|
|
bitfld.word 0x00 15. "RXDP,Receive data + line status" "0,1"
|
|
bitfld.word 0x00 14. "RXDM,Receive data - line status" "0,1"
|
|
bitfld.word 0x00 13. "LCK,Locked" "0,1"
|
|
bitfld.word 0x00 11.--12. "LSOF,Lost SOF" "0,1,2,3"
|
|
hexmask.word 0x00 0.--10. 1. "FN,Frame number"
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "DADDR,device address"
|
|
bitfld.word 0x00 7. "EF,Enable function" "0,1"
|
|
hexmask.word.byte 0x00 0.--6. 1. "ADD,Device address"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "BTABLE,Buffer table address"
|
|
hexmask.word 0x00 3.--15. 1. "BTABLE,Buffer table"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "LPMCSR,LPM control and status register"
|
|
bitfld.word 0x00 4.--7. "BESL,BESL value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. "REMWAKE,RemoteWake value" "0,1"
|
|
bitfld.word 0x00 1. "LPMACK,LPM Token acknowledge enable" "0,1"
|
|
bitfld.word 0x00 0. "LPMEN,LPM support enable" "0,1"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "BCDR,Battery charging detector"
|
|
bitfld.word 0x00 15. "DPPU,DP pull-up control" "0,1"
|
|
bitfld.word 0x00 7. "PS2DET,DM pull-up detection status" "0,1"
|
|
bitfld.word 0x00 6. "SDET,Secondary detection (SD) status" "0,1"
|
|
bitfld.word 0x00 5. "PDET,Primary detection (PD) status" "0,1"
|
|
bitfld.word 0x00 4. "DCDET,Data contact detection (DCD) status" "0,1"
|
|
bitfld.word 0x00 3. "SDEN,Secondary detection (SD) mode enable" "0,1"
|
|
bitfld.word 0x00 2. "PDEN,Primary detection (PD) mode enable" "0,1"
|
|
bitfld.word 0x00 1. "DCDEN,Data contact detection (DCD) mode enable" "0,1"
|
|
bitfld.word 0x00 0. "BCDEN,Battery charging detector (BCD) enable" "0,1"
|
|
tree.end
|
|
tree "USB"
|
|
base ad:0x4000D400
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "EP0R,endpoint 0 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "EP1R,endpoint 1 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "EP2R,endpoint 2 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "EP3R,endpoint 3 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "EP4R,endpoint 4 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "EP5R,endpoint 5 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "EP6R,endpoint 6 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "EP7R,endpoint 7 register"
|
|
bitfld.word 0x00 15. "CTR_RX,Correct transfer for reception" "0,1"
|
|
bitfld.word 0x00 14. "DTOG_RX,Data Toggle for reception transfers" "0,1"
|
|
bitfld.word 0x00 12.--13. "STAT_RX,Status bits for reception transfers" "0,1,2,3"
|
|
bitfld.word 0x00 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.word 0x00 9.--10. "EP_TYPE,Endpoint type" "0,1,2,3"
|
|
bitfld.word 0x00 8. "EP_KIND,Endpoint kind" "0,1"
|
|
bitfld.word 0x00 7. "CTR_TX,Correct Transfer for transmission" "0,1"
|
|
bitfld.word 0x00 6. "DTOG_TX,Data Toggle for transmission transfers" "0,1"
|
|
bitfld.word 0x00 4.--5. "STAT_TX,Status bits for transmission transfers" "0,1,2,3"
|
|
bitfld.word 0x00 0.--3. "EA,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CNTR,control register"
|
|
bitfld.word 0x00 15. "CTRM,Correct transfer interrupt mask" "0,1"
|
|
bitfld.word 0x00 14. "PMAOVRM,Packet memory area over / underrun interrupt mask" "0,1"
|
|
bitfld.word 0x00 13. "ERRM,Error interrupt mask" "0,1"
|
|
bitfld.word 0x00 12. "WKUPM,Wakeup interrupt mask" "0,1"
|
|
bitfld.word 0x00 11. "SUSPM,Suspend mode interrupt mask" "0,1"
|
|
bitfld.word 0x00 10. "RESETM,USB reset interrupt mask" "0,1"
|
|
bitfld.word 0x00 9. "SOFM,Start of frame interrupt mask" "0,1"
|
|
bitfld.word 0x00 8. "ESOFM,Expected start of frame interrupt mask" "0,1"
|
|
bitfld.word 0x00 7. "L1REQM,LPM L1 state request interrupt mask" "0,1"
|
|
bitfld.word 0x00 5. "L1RESUME,LPM L1 Resume request" "0,1"
|
|
bitfld.word 0x00 4. "RESUME,Resume request" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. "FSUSP,Force suspend" "0,1"
|
|
bitfld.word 0x00 2. "LPMODE,Low-power mode" "0,1"
|
|
bitfld.word 0x00 1. "PDWN,Power down" "0,1"
|
|
bitfld.word 0x00 0. "FRES,Force USB Reset" "0,1"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "ISTR,interrupt status register"
|
|
rbitfld.word 0x00 15. "CTR,Correct transfer" "0,1"
|
|
bitfld.word 0x00 14. "PMAOVR,Packet memory area over / underrun" "0,1"
|
|
bitfld.word 0x00 13. "ERR,Error" "0,1"
|
|
bitfld.word 0x00 12. "WKUP,Wakeup" "0,1"
|
|
bitfld.word 0x00 11. "SUSP,Suspend mode request" "0,1"
|
|
bitfld.word 0x00 10. "RESET,reset request" "0,1"
|
|
bitfld.word 0x00 9. "SOF,start of frame" "0,1"
|
|
bitfld.word 0x00 8. "ESOF,Expected start frame" "0,1"
|
|
bitfld.word 0x00 7. "L1REQ,LPM L1 state request" "0,1"
|
|
rbitfld.word 0x00 4. "DIR,Direction of transaction" "0,1"
|
|
rbitfld.word 0x00 0.--3. "EP_ID,Endpoint Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "FNR,frame number register"
|
|
bitfld.word 0x00 15. "RXDP,Receive data + line status" "0,1"
|
|
bitfld.word 0x00 14. "RXDM,Receive data - line status" "0,1"
|
|
bitfld.word 0x00 13. "LCK,Locked" "0,1"
|
|
bitfld.word 0x00 11.--12. "LSOF,Lost SOF" "0,1,2,3"
|
|
hexmask.word 0x00 0.--10. 1. "FN,Frame number"
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "DADDR,device address"
|
|
bitfld.word 0x00 7. "EF,Enable function" "0,1"
|
|
hexmask.word.byte 0x00 0.--6. 1. "ADD,Device address"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "BTABLE,Buffer table address"
|
|
hexmask.word 0x00 3.--15. 1. "BTABLE,Buffer table"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "LPMCSR,LPM control and status register"
|
|
bitfld.word 0x00 4.--7. "BESL,BESL value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. "REMWAKE,RemoteWake value" "0,1"
|
|
bitfld.word 0x00 1. "LPMACK,LPM Token acknowledge enable" "0,1"
|
|
bitfld.word 0x00 0. "LPMEN,LPM support enable" "0,1"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "BCDR,Battery charging detector"
|
|
bitfld.word 0x00 15. "DPPU,DP pull-up control" "0,1"
|
|
bitfld.word 0x00 7. "PS2DET,DM pull-up detection status" "0,1"
|
|
bitfld.word 0x00 6. "SDET,Secondary detection (SD) status" "0,1"
|
|
bitfld.word 0x00 5. "PDET,Primary detection (PD) status" "0,1"
|
|
bitfld.word 0x00 4. "DCDET,Data contact detection (DCD) status" "0,1"
|
|
bitfld.word 0x00 3. "SDEN,Secondary detection (SD) mode enable" "0,1"
|
|
bitfld.word 0x00 2. "PDEN,Primary detection (PD) mode enable" "0,1"
|
|
bitfld.word 0x00 1. "DCDEN,Data contact detection (DCD) mode enable" "0,1"
|
|
bitfld.word 0x00 0. "BCDEN,Battery charging detector (BCD) enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "VREF (Voltage reference buffer)"
|
|
tree "SEC_VREFBUF"
|
|
base ad:0x50010030
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,VREF control and status register"
|
|
rbitfld.long 0x00 3. "VRR,Voltage reference buffer ready" "0,1"
|
|
bitfld.long 0x00 2. "VRS,Voltage reference scale" "0,1"
|
|
bitfld.long 0x00 1. "HIZ,High impedance mode" "0,1"
|
|
bitfld.long 0x00 0. "ENVR,Voltage reference buffer enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CCR,calibration control register"
|
|
bitfld.long 0x00 0.--5. "TRIM,Trimming code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree "VREFBUF"
|
|
base ad:0x40010030
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,VREF control and status register"
|
|
rbitfld.long 0x00 3. "VRR,Voltage reference buffer ready" "0,1"
|
|
bitfld.long 0x00 2. "VRS,Voltage reference scale" "0,1"
|
|
bitfld.long 0x00 1. "HIZ,High impedance mode" "0,1"
|
|
bitfld.long 0x00 0. "ENVR,Voltage reference buffer enable" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CCR,calibration control register"
|
|
bitfld.long 0x00 0.--5. "TRIM,Trimming code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree.end
|
|
tree "WWDG (System window watchdog)"
|
|
tree "SEC_WWDG"
|
|
base ad:0x50002C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control register"
|
|
bitfld.long 0x00 7. "WDGA,Activation bit" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFR,Configuration register"
|
|
bitfld.long 0x00 9. "EWI,Early wakeup interrupt" "0,1"
|
|
bitfld.long 0x00 7.--8. "WDGTB,Timer base" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--6. 1. "W,7-bit window value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR,Status register"
|
|
bitfld.long 0x00 0. "EWIF,Early wakeup interrupt flag" "0,1"
|
|
tree.end
|
|
tree "WWDG"
|
|
base ad:0x40002C00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control register"
|
|
bitfld.long 0x00 7. "WDGA,Activation bit" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFR,Configuration register"
|
|
bitfld.long 0x00 9. "EWI,Early wakeup interrupt" "0,1"
|
|
bitfld.long 0x00 7.--8. "WDGTB,Timer base" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--6. 1. "W,7-bit window value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR,Status register"
|
|
bitfld.long 0x00 0. "EWIF,Early wakeup interrupt flag" "0,1"
|
|
tree.end
|
|
tree.end
|
|
autoindent.off
|
|
newline
|